JP6034354B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a technique effective when applied to a layout technique in a power semiconductor device (or a semiconductor integrated circuit device).

  In Japanese Patent Laid-Open No. 2006-228882 (Patent Document 1), in forming a contact embedded polysilicon in a DRAM (Dynamic Random Access Memory) chip, an integral polysilicon band that intersects with a word line is provided. A technique for avoiding undesired etching from the side of the interlayer insulating film by embedding is disclosed.

  Japanese Unexamined Patent Publication No. 2006-54483 (Patent Document 2) discloses a gate electrode having a structure in which an internal region is removed for the purpose of reducing gate capacitance in a planar power MOSFET having a planar structure.

JP 2006-228882 A JP 2006-54483 A

  At present, an insulated gate power semiconductor active device such as a power MOSFET has a large number of linearly parallel gate electrodes, which are covered with an interlayer insulating film, and further relatively thin thereon. The barrier metal film and a relatively thick aluminum-based electrode film are stacked. As described above, when the space between the gate electrodes running in parallel is buried with a thick aluminum-based electrode film, in many cases, a void running along with the gate electrode is accompanied at the center of the buried portion. The present inventors have clarified that such a void does not cause a defect by itself, but may cause a defect in relation to a metal processing process.

  That is, when the aluminum-based electrode film has an elongated void, when the aluminum-based electrode film is patterned, for example, when wet etching is performed, the etching solution penetrates through the elongated void. Etching proceeds to the active cell portion.

  The present invention has been made to solve these problems.

  An object of the present invention is to provide a power semiconductor device with high reliability.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, one invention of the present application relates to a plurality of gate electrodes provided through a gate insulating film so as to protrude outside from the active cell region, and a gate connecting the plurality of gate electrodes outside the active cell region. The insulated gate power semiconductor device has an electrode connecting portion, and the gate electrode connecting portion is covered with a metal electrode that covers the active cell region.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, having a plurality of gate electrodes provided through the gate insulating film so as to protrude outside from the active cell region, and a gate electrode connecting portion for connecting the plurality of gate electrodes outside the active cell region, Since the gate electrode connection portion is an insulated gate power semiconductor device covered with a metal electrode that covers the active cell region, it is possible to prevent the introduction of defects due to the manufacturing process.

1 is a circuit diagram of a DC-DC down converter for explaining a typical application field such as a power MOSFET that is an example of a power semiconductor device according to an embodiment of the present application; FIG. Wide area plane of chip inner surface area for explaining outline of gate electrode layout corresponding to semiconductor device of one embodiment of the present application (cell neighboring gate electrode connecting portion is a plurality of connecting bars corresponding to the one embodiment) FIG. FIG. 5 is a plan view of a wide area of a chip upper surface inner region for explaining a modification 1 (single connection bar) of the gate electrode layout of FIG. 2. FIG. 10 is a wide-area plan view of a chip upper surface internal region for explaining a modification 2 (zigzag connection bar) of the gate electrode layout of FIG. 2. It is a whole chip top view for demonstrating the specific planar structure of the device in power MOSFET which is an example of the power type semiconductor device of the said one Embodiment of this application. FIG. 6 is a chip partial top view showing details of a layout of a gate electrode protruding direction cutout portion R1 in FIG. 5; FIG. 7 is a device schematic cross-sectional view corresponding to the Y-Y ′ cross section of FIG. 6. FIG. 6 is a chip partial top view showing details of a layout of a gate electrode side cutout portion R2 in FIG. 5; FIG. 9 is a device schematic cross-sectional view corresponding to the X-X ′ cross section of FIG. 8. FIG. 7 is a chip local top view showing a basic layout of a cell vicinity gate electrode connection portion periphery cutout portion R3 of FIG. 6; FIG. 8 is a chip local top view showing a layout corresponding to a modification of the dimensions of the cell vicinity gate electrode connection portion periphery cutout portion R3 of FIG. 6; It is a process block flowchart for demonstrating the principal part of the wafer process of the power MOSFET which is an example of the power type semiconductor device of the said one Embodiment of this application. FIG. 6 is a device sectional view (gate insulating film forming step) substantially corresponding to the section AA ′ of FIG. 6 for explaining the main part of the wafer process of the power MOSFET as an example of the power semiconductor device of the embodiment of the present application. To a silicon oxide hard mask film forming step). FIG. 6 is a device cross-sectional view substantially corresponding to the AA ′ cross section of FIG. 6 for explaining the main part of the wafer process of the power MOSFET which is an example of the power semiconductor device of the embodiment of the present application ). 6 is a device cross-sectional view (introduction of a P-type base region) substantially corresponding to the cross section AA ′ of FIG. 6 for explaining the main part of the wafer process of the power MOSFET which is an example of the power semiconductor device of the embodiment of the present application. Process). Device sectional view (N-type source extension region) substantially corresponding to the AA ′ section of FIG. 6 for explaining the main part of the wafer process of the power MOSFET which is an example of the power semiconductor device of the one embodiment of the present application. Introduction process). Device sectional view (side wall forming step) substantially corresponding to the AA ′ section of FIG. 6 for explaining the main part of the wafer process of the power MOSFET which is an example of the power semiconductor device of the one embodiment of the present application. It is. 6 is a device cross-sectional view (introduction of an N + type source region) substantially corresponding to the AA ′ cross section of FIG. 6 for explaining the main part of the wafer process of the power MOSFET which is an example of the power semiconductor device of the embodiment of the present application. Process). FIG. 6 is a device cross-sectional view (contact hole and the like forming step) substantially corresponding to the cross section AA ′ of FIG. 6 for explaining the main part of the wafer process of the power MOSFET which is an example of the power semiconductor device of the embodiment of the present application. ). Device sectional view (barrier metal film deposition) substantially corresponding to the AA ′ section of FIG. 6 for explaining the main part of the wafer process of the power MOSFET which is an example of the power semiconductor device of the one embodiment of the present application. Process). Device sectional view (aluminum-based metal electrode film) substantially corresponding to the AA ′ section of FIG. 6 for explaining the main part of the wafer process of the power MOSFET which is an example of the power-based semiconductor device of the one embodiment of the present application Wet etching process). Device sectional view (barrier metal film dry etching) substantially corresponding to the AA ′ section of FIG. 6 for explaining the main part of the wafer process of the power MOSFET which is an example of the power semiconductor device of the one embodiment of the present application. Process).

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. Power semiconductor devices including:
(A) a semiconductor chip having first and second main surfaces;
(B) a plurality of gate electrodes provided via a gate insulating film so as to protrude from the active cell region on the first main surface of the semiconductor chip to the outside;
(C) a gate electrode connecting portion that integrally connects intermediate portions of the plurality of gate electrodes outside the active cell region on the first main surface of the semiconductor chip;
(D) an interlayer insulating film that covers the plurality of gate electrodes and the gate electrode connecting portion on the first main surface of the semiconductor chip;
(E) a first metal electrode covering the active cell region and its peripheral portion on the interlayer insulating film;
Here, the gate electrode connection part between the plurality of gate electrodes is covered with the first metal electrode, and the first metal electrode includes the following:
(E1) barrier metal film;
(E2) A metal electrode film mainly composed of aluminum thicker than the barrier metal film provided on the barrier metal film.

  2. In the semiconductor device according to the item 1, a plurality of the gate electrode connecting portions are provided close to each other.

  3. In the semiconductor device according to the item 1 or 2, the gate electrode connecting portion is substantially linear.

  4). In the semiconductor device according to any one of items 1 to 3, the width of the gate electrode connecting portion is substantially the same as that of the plurality of gate electrodes.

  5. 4. In the semiconductor device according to items 1 to 3, a width of the gate electrode connecting portion is wider than a width of the plurality of gate electrodes.

  6). 6. In the semiconductor device as described above in any one of 1 to 5, the gate electrode connecting portion is formed of a member in the same layer as the plurality of gate electrodes.

  7). 7. In the semiconductor device as described above in any one of 1 to 6, the power semiconductor device is a power MISFET having a linear gate electrode structure.

  8). 8. The semiconductor device according to any one of 1 to 7, wherein the power semiconductor device is a power MISFET having a planar structure.

  9. 8. The semiconductor device according to any one of 1 to 7, wherein the power semiconductor device is a split gate type power MISFET having a planar structure.

  10. 10. In the semiconductor device as described above in any one of 1 to 9, there is no insulating film thicker than the gate insulating film between the first main surface of the semiconductor chip and the gate electrode connecting portion.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Further, in the present application, the term “transistor”, “semiconductor device” or “semiconductor integrated circuit device” mainly refers to various transistors (active elements) alone, and mainly a resistor, a capacitor, etc., as a semiconductor chip, etc. The one integrated on (for example, a single crystal silicon substrate). Here, as a representative of various transistors, a MISFET (Metal Insulator Semiconductor Effect Transistor) typified by a MOSFET (Metal Oxide Field Effect Transistor) can be exemplified. In the present application, the term “MOSFET” includes not only the gate insulating film that is an oxide film, but also those that use other insulating films as the gate insulating film.

  2. Similarly, in the description of the embodiment and the like, the material, composition, etc. may be referred to as “X consisting of A”, etc., except when clearly stated otherwise and clearly from the context, except for A It does not exclude what makes an element one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say. Similarly, “silicon oxide film”, “silicon oxide insulating film”, etc. are not only relatively pure undoped silicon oxide (FS), but also FSG (Fluorosilicate Glass), TEOS-based silicon oxide ( Thermal oxide films such as TEOS-based silicon oxide), SiOC (Silicon Oxicarbide) or carbon-doped silicon oxide or OSG (Organosilicate glass), PSG (Phosphorus Silicate Glass), BPSG (Borophosphosilicate Glass), CVD Oxide film, SOG (Spin ON Glass), nano-clustering silica (Nano-Clustering Silica: NCS) and other coating-type silicon oxide, silica-based low-k insulating film (porous insulating) Needless to say, a film) and a composite film with other silicon-based insulating films including these as main constituent elements are included.

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor device (same as a semiconductor integrated circuit device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate, and the like. Needless to say, a composite wafer such as a semiconductor layer is also included.

  6). In the present application, the term “power semiconductor” refers to a semiconductor device that can handle electric power of several watts or more. Among power semiconductors, power MOSFETs, power IGBTs (Insulated gate Bipolar Transistors), and the like belong to the category of “insulated gate power transistors”. Therefore, all normal power MOSFETs are included in this.

  Among power MOSFETs, a structure in which the front surface is a source and the back surface is a drain is called a vertical power MOSFET (Vertical Power MOSFET).

  Among the vertical power MOSFETs, the “trench gate power MOSFET” usually means that polysilicon or the like is formed in a trench (relatively long and thin groove) formed on the device surface (first main surface) of the semiconductor substrate. A gate electrode is provided, and a channel is formed in the thickness direction (longitudinal direction) of a semiconductor substrate. In this case, the device surface side of the semiconductor substrate is usually the source, and the back surface side (second main surface side) is the drain. A part of the main part of the gate electrode (a part other than the electrode lead part) may protrude from the trench.

  In addition, the IGBT has a pure structure in which a collector layer having a conductivity type different from that of the drain region is added to the drain side of the vertical power MOSFET, but the source of the constituent vertical power MOSFET is practical. Is referred to as the “emitter”, but in this application, the original vertical power MOSFET designation, ie, “source”, is used, unless specifically called “emitter”. These are called “region”, “source electrode”, and the like. Therefore, regarding the layout of the device surface, the IGBT and the vertical power MOSFET are almost the same. Therefore, what is described in the embodiment of the present application also applies to the IGBT as it is.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

1. Description of typical application fields such as a power MOSFET as an example of a power semiconductor device according to an embodiment of the present application (mainly FIG. 1)
In this section, in order to clarify the attributes of a power MOSFET that is an example of a power semiconductor device according to an embodiment of the present application, a typical application circuit will be described as an example. It goes without saying that power semiconductor devices such as MOSFETs (especially insulated gate power active elements) are not limited to such specific applications.

  FIG. 1 is a circuit diagram of a DC-DC down converter for explaining a typical application field such as a power MOSFET as an example of a power semiconductor device according to an embodiment of the present application. Based on this, typical application fields such as a power MOSFET which is an example of a power semiconductor device according to an embodiment of the present application will be described.

  As shown in FIG. 1, the DC-DC down converter (DC) uses a power source voltage (for example, 15 to 20 volts) supplied from a voltage source VS by an upper side MOSFET (Q1) controlled by a control circuit CC. The voltage is stepped down by ON / OFF control, and the output is passed through a smoothing circuit composed of an inductance element L and a capacitor C, and a low-voltage DC power supply (for example, about 1 volt, About 3 volts or about 5 volts). Here, the lower side MOSFET (Q2) is an active switch that takes the place of a freewheel diode.

  In this application example, the power MOSFET that is an example of the power semiconductor device according to the embodiment of the present application is mainly used as an upper side MOSFET (Q1).

2. Outline of gate electrode layout corresponding to semiconductor device of one embodiment of the present application (mainly FIG. 2)
In this section, an outline of the gate electrode layout corresponding to the semiconductor device of the embodiment will be described by taking the simplified layout of the power MOSFET described in section 1 as an example. The layout of the example of FIG. 2 below is basically the same as that of FIG. 5 to FIG. 9, but has a simpler form for convenience of explanation.

  FIG. 2 is a chip upper surface internal region for explaining the outline of the gate electrode layout corresponding to the semiconductor device of the one embodiment of the present application (cell vicinity gate electrode connecting portion is a plurality of connecting bars corresponding to the one embodiment). FIG. Based on this, the outline of the gate electrode layout corresponding to the semiconductor device of the one embodiment of the present application will be described.

  FIG. 2 shows an outline of the layout of the internal region 2i of the semiconductor chip surface 1a including the active cell region 7, the gate electrode end portion 17 and the like. As shown in FIG. 2, in this example, a large number of gate electrodes 9 extending in parallel at substantially equal intervals (not necessarily equal in the example of section 4) substantially cross the active cell region 7, It extends to the outside and is connected to each other by the lower gate wiring 14 at the end of the active cell region 7. However, it is not essential to be connected at this portion, and it is not essential to be connected to each other (this is because they are interconnected by the upper aluminum-based metal layer).

  Here, the cell vicinity gate electrode connecting portion 11 has a dam structure (cell vicinity dam structure) for preventing defects during processing of the metal source electrode 8 (first metal electrode) in the vicinity of the outside of the active cell region 7. For example, it is composed of two orthogonal cell neighboring gate electrode connection bars 11a and 11b (the upper part of these gate electrode connections must be covered by the metal source electrode 8). ). The cell vicinity gate electrode connection bars 11a and 11b are integrally formed from the same member layer as the gate electrode 9, for example. It is effective from the viewpoint of occupied area that the gate electrode connection bars 11a and 11b are provided close to each other.

  The number of the cell vicinity gate electrode connection bars constituting the cell vicinity gate electrode connection portion 11 may be other than two as will be described later. However, as the number increases, the dam characteristic improves, but on the other hand, the distance between the outer edge of the active cell region 7 and the outer edge of the metal source electrode 8 increases, and the area occupied by the metal source electrode 8 increases.

  Such a dam structure is effective not only in the vicinity of the outer edge portion of the active cell region 7 but also in the vicinity of the upper gate wiring 6 (aluminum-based gate wiring) in the vicinity of the gate electrode end portion 17, which is the gate end portion. This is the gate electrode connecting portion 12. Note that the number of gate electrode connection bars constituting the gate end gate electrode connection portion 12 may be other than one as in the cell vicinity gate electrode connection portion 11.

3. Outline description of modified examples 1 and 2 of the gate electrode layout corresponding to the semiconductor device of the embodiment of the present application (mainly FIGS. 3 and 4)
In this section, modifications of the cell vicinity dam structure and the gate end vicinity dam structure described in section 2 will be described. In the following, the cell vicinity dam structure will be described, but it can be similarly applied to the gate end vicinity dam structure.

  FIG. 3 is a wide area plan view of a chip upper surface inner region for explaining a modification 1 (single connection bar) of the gate electrode layout of FIG. FIG. 4 is a wide-area plan view of the chip upper surface inner region for explaining a modification 2 (zigzag connection bar) of the gate electrode layout of FIG. Based on these, the outlines of modified examples 1 and 2 of the gate electrode layout corresponding to the semiconductor device of the one embodiment of the present application will be described.

  Modification 1 is shown in FIG. As shown in FIG. 3, in this example, the number of cell vicinity gate electrode connection bars constituting the cell vicinity gate electrode connection portion 11 is one, and the outer edge of the active cell region 7 and the metal source are reduced by the small number. The distance between the outer edges of the electrodes 8 can be reduced, and the area occupied by the metal source electrode 8 is reduced.

  On the other hand, as shown in FIG. 4 with respect to the second modification, the cell vicinity gate electrode connection portion 11 can be formed in a zigzag structure instead of the straight cell vicinity gate electrode connection bar.

4). Description of device structure in power MOSFET which is an example of power semiconductor device of one embodiment of the present application (mainly FIGS. 5 to 9)
In this section, the device structure in the power MOSFET which is an example of the power semiconductor device of the embodiment is shown more specifically. In this section, cross-sectional views are shown relatively schematically, and a more detailed description is the process description.

  Here, for convenience, an N-type epitaxial layer is formed on an N-type silicon single crystal substrate portion, and an N-channel type device structure using the N-epitaxial layer as a drift region will be described. However, the present invention is not limited thereto. Needless to say.

  Here, a split gated vertical planar type power MOSFET in which voids are likely to occur in the metal electrode will be described. However, a normal vertical planar type power MOSFET, a trench gate type power MOSFET, and the like are described. Needless to say, the present invention can be similarly applied to a power MOSFET having a linear gate structure and an IGBT (Insulated Gate Bipolar Transistor).

  FIG. 5 is a top view of the entire chip for explaining a specific planar structure of a device in a power MOSFET which is an example of the power semiconductor device according to the embodiment of the present application. FIG. 6 is a chip partial top view showing details of the layout of the gate electrode protruding direction cutout portion R1 of FIG. FIG. 7 is a device schematic cross-sectional view corresponding to the Y-Y ′ cross section of FIG. 6. FIG. 8 is a chip partial top view showing details of the layout of the gate electrode side cutout portion R2 of FIG. FIG. 9 is a device schematic cross-sectional view corresponding to the X-X ′ cross section of FIG. 8. Based on these, the device structure in the power MOSFET which is an example of the power semiconductor device of the one embodiment of the present application will be described.

  As shown in FIG. 5, an annular guard ring (for example, a lower barrier metal film and an upper aluminum-based metal electrode film) is provided at the outer end of the upper surface 1a of the power MOSFET chip 2. An annular field limiting ring 4 (Field Limiting Ring) or a floating field ring (Floating Field Ring) is also provided in the inside. For example, a substantially U-shaped upper gate wiring 6 (for example, a lower barrier metal film and an upper aluminum metal electrode film) is provided inside the field limiting ring 4. A part of the gate pad portion 5 is formed.

  The active cell region 7 occupying a relatively large area in the region further inside the field limiting ring 4 and the upper layer gate wiring 6 includes, for example, a large number of linear gate electrode 9 having a mutually parallel repeating structure. Although at least one end extends to the lower layer of the upper-layer gate wiring 6, only a part of the so-called intrinsic gate electrode is shown in this figure (FIG. 5). Because it becomes more than a book and it becomes difficult to see the figure). Note that the metal source electrode 8 (for example, composed of a lower barrier metal film and an upper aluminum-based metal electrode film) generally covers the entire active cell region 7 and extends beyond the entire periphery of the active cell region 7. Is covered.

  Next, FIG. 6 shows details of the gate electrode protruding direction cutout portion R1 in FIG. As shown in FIG. 6, there is a P-type field limiting ring 4 on the left end, and on the right side, an N-type drift region 19 (N-epitaxial layer 1e) is sandwiched to surround the active cell region 7 in a ring shape. There is a P-type ring region 18 around the active cell region. Here, the gate electrode structure 9 (an integral network structure composed of the same member layer as the multilayer structure constituting the intrinsic gate electrode 9i) is the gate electrode 9 in the active cell region 7, that is, the intrinsic gate electrode. 9i, the gate electrode lead-out portion 9t outside the active cell region 7, the gate electrode end portion 17, and the cell-proximal gate electrode connection portion 11 that connects them perpendicularly to the gate electrode lead-out portion 9t, the gate end gate It is divided into parts such as an electrode connecting portion 12 and a lower layer gate wiring 14. A gate electrode-gate metal connection 15 is provided at the center of the gate electrode end 17 and is connected to the upper gate wiring 6 of the upper layer. As described above, the cell vicinity gate electrode connecting portion 11 and the gate end gate electrode connecting portion 12 are covered with the metal source electrode 8 and the upper gate wiring 6, respectively. Between the gate electrodes 9 in the active cell region 7, gate split regions 21 and P + type body contact regions 16 are alternately provided.

  An example of the dimensions of each part shown in FIG. 6 is as follows. That is, the width of the intrinsic gate electrode 9i and the gate electrode lead-out portion 9t is, for example, about 0.5 micrometers, the distance between the gate electrode connection bars 11a and 11b wound adjacent to each other, and the cell vicinity gate electrode connection portion. The distance between the inner end of 11 (the active cell side of the gate electrode connecting bar 11b) and the active cell 7 is about 0.5 to 2 micrometers. The distance between the gate electrodes (a pair of gate electrodes facing each other across the split gate and the P + type body contact region 16) is, for example, about 1.1 to 1.5 micrometers.

  Next, FIG. 7 shows a device structure corresponding to the Y-Y ′ cross section of FIG. 6. As shown in FIG. 7, the power MOSFET has its main structure on the upper surface side 1a of the N-epitaxial layer 1e (N-type drift region 19) on the N-type silicon single crystal substrate portion 1s. In the surface region of the N− epitaxial layer 1 e, an active cell region peripheral P-type ring region 18, a P + type body contact region 16, an N-type source region 22, etc. are provided. The gate electrode structure 9, that is, the cell vicinity gate electrode connecting portion 11, the gate end gate electrode connecting portion 12, and the lower layer are interposed through the gate insulating film 23 (or an insulating film formed simultaneously with the gate insulating film). A gate wiring 14, a gate electrode end 17 and the like are provided. These gate electrode structures are covered with a sidewall forming insulating film 32 and an interlayer insulating film 37. On the interlayer insulating film 37, a barrier metal film 20 (for example, a TiW film) and an aluminum-based metal electrode are formed. It is partially covered with a film 10 (aluminum as a main component, for example, containing an additive of about several percent or less). These constitute the metal source electrode 8 and the upper gate wiring 6 (or the gate pad portion 5) together with the upper aluminum metal electrode film 10 including the barrier metal film 20. Note that the gate electrode 9 (gate electrode structure) is formed of an integral laminated body. In this example, for example, a lower polysilicon film 24, a silicide film 25 such as an intermediate WSi film, and an upper oxide layer. The silicon cap film 26 is used.

  Next, FIG. 8 is an enlarged plan view of the gate electrode side cutout portion R2 of FIG. As shown in FIG. 8, there is a P-type field limiting ring 4 on the leftmost side, and a P-type ring region 18 around the active cell region is provided on the right side with an N-type drift region 19 interposed therebetween. It has been. The active cell region 7 is formed from the vicinity of the inner end to the inside of the P-ring region 18 around the active cell region, and is substantially equidistant (in this case, it is not exactly equidistant) and is substantially linear. A plurality of gate electrodes 9 (intrinsic gate electrodes 9i) to be presented are provided, and P + type body contact regions 16 and gate split regions 21 are alternately provided between these intrinsic gate electrodes 9i. A lower gate wiring 14 is provided on the P-ring region 18 around the active cell region via a gate insulating film 23 (FIG. 7), and the outer periphery (left side in FIG. 8) of the lower gate wiring 14 is active. Above the cell region peripheral P-type ring region 18, an upper gate wiring 6 (consisting of a lower barrier metal film 20 and an upper aluminum-based metal electrode film 10) is provided. Similarly to FIG. 5 or FIG. 6, the metal source electrode 8 covers the active cell region 7 and its outer periphery.

  Next, FIG. 9 shows an X-X ′ cross section of FIG. 8. As shown in FIG. 9, the power MOSFET has its main structure on the upper surface side 1a of the N-epitaxial layer 1e (N-type drift region 19) on the N-type silicon single crystal substrate portion 1s. In the surface region of the N− epitaxial layer 1 e, an active cell region peripheral P-type ring region 18, a P + type body contact region 16, an N-type source region 22, etc. are provided. The gate electrode structure 9, that is, the intrinsic gate electrode 9 i, the active cell region end gate electrode 9 p (operates as a MOSFET) via the gate insulating film 23 (or an insulating film formed simultaneously with the gate insulating film). Not a pseudo structure or an edge termination structure), a lower gate wiring 14 and the like. These gate electrode structures are covered with a sidewall forming insulating film 32 and an interlayer insulating film 37. (These composite insulating films are collectively referred to as active region gate electrode peripheral insulation in the active cell region 7. On the interlayer insulating film 37, the barrier metal film 20 (for example, TiW film) and the aluminum-based metal electrode film 10 (including aluminum as a main component, including, for example, an additive of about several percent or less) It is partially covered with. These constitute the metal source electrode 8 and the upper gate wiring 6 (or the gate pad portion 5) together with the upper aluminum metal electrode film 10 including the barrier metal film 20. The active cell region end gate electrode 9p constitutes a so-called dummy cell portion UCD, while the unit cell UC constituting the main part of the active cell region 7 is a plane object with respect to the symmetry plane corresponding to the unit cell center line LS. The unit cell UC has a repetitive structure of several hundred to several thousand or more.

5. Additional description regarding the width of the gate electrode and the like in the power MOSFET which is an example of the power semiconductor device according to the embodiment of the present application (mainly FIGS. 10 and 11)
In this section, the relationship between the widths of the portions of the gate electrode structure described so far will be described.

  FIG. 10 is a chip local top view showing a basic layout of the cell vicinity gate electrode connection portion periphery cutout portion R3 of FIG. FIG. 11 is a local chip top view showing a layout corresponding to a modified example related to the dimensions of the cell vicinity gate electrode connecting portion periphery cutout portion R3 of FIG. Based on these, an additional description will be given regarding the width of the gate electrode and the like in the power MOSFET which is an example of the power semiconductor device according to the embodiment of the present application.

  As shown in FIG. 10, in the gate electrode in the power MOSFET which is an example of the power semiconductor device according to the embodiment of the present application, the lead portion 9t of the gate electrode and the width T1 of the intrinsic gate electrode 9i are usually the same. The width T2 of the cell vicinity gate electrode connection portion 11 (the width of the portion other than the gate electrode lead portion 9t and the intrinsic gate electrode 9i in the gate electrode structure), more precisely, the cell vicinity gate electrode connection portion The widths of the individual cell vicinity gate electrode connection bars 11a, 11b, etc., constituting 11 are also substantially equal to the width T1. This also applies to the widths of the gate end gate electrode connecting portion 12, the lower layer gate wiring 14, and the like. Thus, the processing of the same layer can be facilitated by making the widths of the respective parts constituted by the same member layer substantially the same.

  FIG. 11 shows a modification to FIG. As shown in FIG. 11, in the modification, the relationship of width T2> width T1 is satisfied. This improves the dam effect in etching, but has a demerit that the distance between the end of the active cell region 7 and the end of the metal source electrode 8 increases. Further, with respect to the ease of processing, the one shown in FIG. 10 is more advantageous.

6). Description of the main part of a wafer process of a power MOSFET which is an example of a power semiconductor device according to an embodiment of the present application (mainly FIG. 12 and FIG. 13 to FIG. 22)
In this section, the source / drain withstand voltage of about several tens of volts or slightly lower than that will be described in detail by way of example, corresponding to sections 1 and 4. In the manufacturing process of a general planar type vertical MOSFET, an edge termination (Edge Termination) structure such as a field plate is formed so that a relatively thick field insulating film is provided below the gate electrode. However, in the process described below, In order to simplify the process, an insulating film thicker than the gate oxide film is not provided below such a gate electrode (hereinafter referred to as “non-field insulating film structure”). However, it goes without saying that the present invention is not limited to such a non-field insulating film structure. However, because of such a structure, in order to suppress unnecessary capacitance, there is a problem that the gate lead-out portion should be an integrated laminated body without an opening (the split gate structure also comes from the same reason). ing).

  FIG. 12 is a process block flow diagram for explaining the main part of the wafer process of the power MOSFET which is an example of the power semiconductor device according to the embodiment of the present application. FIG. 13 is a device sectional view (gate insulation) substantially corresponding to the section AA ′ of FIG. 6 for explaining the main part of the wafer process of the power MOSFET which is an example of the power semiconductor device according to the embodiment of the present application. Film formation process to silicon oxide hard mask film formation process). 14 is a device sectional view (gate electrode) substantially corresponding to the section AA ′ of FIG. 6 for explaining the main part of the wafer process of the power MOSFET which is an example of the power semiconductor device according to the embodiment of the present application. Equivalent processing step). 15 is a device cross-sectional view (P-type) substantially corresponding to the cross-section AA ′ of FIG. 6 for explaining the main part of the wafer process of the power MOSFET which is an example of the power semiconductor device according to the embodiment of the present application. Base region introduction step). FIG. 16 is a device sectional view (N-type) substantially corresponding to the section AA ′ of FIG. 6 for explaining the main part of the wafer process of the power MOSFET which is an example of the power semiconductor device according to the embodiment of the present application. Source extension region introduction process). FIG. 17 is a device sectional view (side wall) substantially corresponding to the section AA ′ of FIG. 6 for explaining the main part of the wafer process of the power MOSFET which is an example of the power semiconductor device according to the embodiment of the present application. Forming step). 18 is a device cross-sectional view (N + type) substantially corresponding to the cross section AA ′ of FIG. 6 for explaining the main part of the wafer process of the power MOSFET which is an example of the power semiconductor device of the embodiment of the present application. Source region introduction step). FIG. 19 is a device sectional view (contact hole) substantially corresponding to the section AA ′ of FIG. 6 for explaining the main part of the wafer process of the power MOSFET which is an example of the power semiconductor device of the embodiment of the present application. Isoformation step). FIG. 20 is a device sectional view (barrier metal) substantially corresponding to the section AA ′ of FIG. 6 for explaining the main part of the wafer process of the power MOSFET which is an example of the power semiconductor device according to the embodiment of the present application. Film forming step). 21 is a device cross-sectional view (aluminum-based) substantially corresponding to the AA ′ cross-section of FIG. 6 for explaining the main part of the wafer process of the power MOSFET which is an example of the power semiconductor device of the one embodiment of the present application. Metal electrode film wet etching step). 22 is a device sectional view (barrier metal) substantially corresponding to the section AA ′ of FIG. 6 for explaining the main part of the wafer process of the power MOSFET which is an example of the power semiconductor device according to the embodiment of the present application. Film dry etching step). Based on these, the main part of the wafer process of the power MOSFET which is an example of the power semiconductor device according to the embodiment of the present application will be described.

  As shown in FIG. 12, first, for example, a 200φ N-type silicon single crystal wafer 1s having a plane orientation of (100) (300 phi, 450 phi, or other diameter wafers may be used as necessary. The resistivity is, for example, about 1 to 2 mΩ · cm, and the N-type (for example, phosphorus doping, for example, the resistivity is about 0, for example, about 1.3 to 3.3 micrometers depending on the required breakdown voltage. (About 0.1 to 0.3 mΩ · cm) By depositing a silicon epitaxial layer, the wafer 1 with an epitaxial layer is obtained. Subsequently, a gate oxide film 23 (gate insulating film) is formed on the surface 1a (first main surface) of the wafer 1 with an epitaxial layer by, for example, thermal oxidation (thickness is, for example, about 20 to 40 nm). Subsequently, for example, a phosphorous doped polysilicon film 24 (having a thickness of about 200 to 400 nm, for example) is deposited on the gate oxide film 23 by CVD (Chemical Vapor Deposition) or the like.

  Further, a WSi film 25 (silicide film) having a thickness of about 100 to 200 nm is formed on the polysilicon film 24, for example. The film formation of the WSi film 25 can be performed by, for example, sputtering film formation using a WSi target.

  Subsequently, a silicon oxide insulating film by, for example, CVD is formed on the WSi film 25 as a gate cap film 26 (for example, a thickness of about 150 to 350 nm).

  Next, as shown in FIG. 14, the silicon oxide insulating film is patterned by dry etching or the like using the gate cap film 26 as a hard mask.

  Next, as shown in FIG. 15, a P-type base region introducing resist film 27 is formed on the surface 1 a side of the wafer 1, and this is used as a mask for ion implantation. Then, the P-type channel region 28 (P-type base region) and the active cell region peripheral P-type ring region 18 are introduced. Specific injection conditions are, for example, as follows.

That is,
(1) First step: Boron ion species, implantation energy is about 150 to 250 KeV, for example, and dose amount (total for four times) is about ² × 10 ¹² / cm ² to 2 × 10 ¹³ / cm ² , for example.
(2) Second step: The ion species is boron, the implantation energy is, for example, about 70 to 170 KeV, and the dose amount (total for four times) is, for example, about 3 × 10 ¹² / cm ² to 3 × 10 ¹³ / cm ²
(3) Third step: The ion species is boron, the implantation energy is, for example, about 30 to 130 KeV, and the dose amount (total for four times) is, for example, about 4 × 10 ¹² / cm ² to 4 × 10 ¹³ / cm ² .

  Thereafter, the P-type base region introduction resist film 27 that is no longer needed is removed.

Next, as shown in FIG. 16, an N-type source extension region introduction resist film 31 is formed on the surface 1a side of the wafer 1, and is used as a mask for ion implantation to perform normal ion implantation (for example, vertical implantation). Thus, the N-type source extension region 22b is introduced. As the ion implantation conditions, for example, the arsenic is an ionic species, the implantation energy is about 30 to 90 KeV, and the dose is about 7 × 10 ¹³ / cm ² to 7 × 10 ¹⁴ / cm ^2, for example. it can. After the ion implantation is completed, the resist film 31 for introducing the N-type source extension region that has become unnecessary is removed.

  Next, as shown in FIG. 17, for example, a silicon oxide insulating film (for example, a silicon oxide insulating film) is formed on the entire surface on the surface 1a side of the wafer 1 as a sidewall forming insulating film 32 by, for example, CVD using TEOS. And a thickness of about 150 to 350 nm). Subsequently, a side wall forming resist film 33 is formed, and by using this as a mask, anisotropic dry etching is performed to form side wall spacers 32w, connection prior holes 34, and the like. Thereafter, the side wall forming resist film 33 that is no longer needed is removed.

Next, as shown in FIG. 18, for example, a silicon oxide insulating film (for example, a thickness of 10) is formed on the entire surface on the surface 1 a side of the wafer 1 by, for example, CVD using TEOS, as the sidewall cap film 29. To about 30 nm). Subsequently, an N + type source region introduction resist film 35 is formed on the surface 1a side of the wafer 1, and the N + type source region 22a is introduced by performing vertical ion implantation, for example, using this as a mask. As the ion implantation conditions, arsenic is preferable as the ion species, the implantation energy is, for example, about 30 to 90 KeV, and the dose is, for example, about 8 × 10 ¹⁴ / cm ² to 8 × 10 ¹⁵ / cm ^2. . After the ion implantation is completed, the resist film 35 for introducing the N + type source region that is no longer needed is removed.

Next, as shown in FIG. 19, an interlayer insulating film 37 (for example, a thickness of about 150 to 450 nm) made of, for example, a silicon oxide insulating film is formed on the entire surface of the wafer 1 on the surface 1a side. As the structure of the interlayer insulating film 37, for example, a lower PSG (Phosphosilicate Glass) film (for example, about 150 to 350 nm thick) by CVD and a coating silicon oxide system such as an upper SOG (Spin ON Glass) film are used. What consists of an insulating film (for example, thickness about 50 to 150 nm) can be illustrated as a suitable thing. Subsequently, a contact hole forming resist film is applied and patterned by ordinary lithography. By performing anisotropic dry etching using the patterned contact hole forming resist film as a mask, the contact hole 36 reaching the silicon substrate and the connection hole 38 reaching the polysilicon film 24 at the gate electrode end 17 (FIG. 6). Form. Subsequently, silicon is dug down by, for example, about 0.1 to 0.3 micrometers by dry etching in the same state. Thereafter, the contact hole forming resist film that has become unnecessary is removed. Subsequently, by performing vertical ion implantation through the contact hole 36, the P + type body contact region 16 is introduced. As the ion implantation conditions, for example, the ion species is BF ₂ , the implantation energy is, for example, about 10 to 40 KeV, and the dose amount is, for example, about 8 × 10 ¹⁴ / cm ² to 8 × 10 ¹⁵ / cm ² as a preferable range. Can do.

  Next, as shown in FIG. 20, a TiW film (for example, a titanium composition of about 10% by weight and a thickness of about 100 to 300 nm) is formed as a barrier metal film 20 on the entire surface on the surface 1a side of the wafer 1 by sputtering. It forms with a film | membrane etc. (barrier sputtering process 101 of FIG. 12). Thereafter, by performing heat treatment (annealing step 102 in FIG. 12), a part of titanium of the TiW film reacts with the underlying silicon to form a titanium silicide film under the TiW film (this titanium silicide film). Is not displayed for the sake of illustration).

  Next, as shown in FIG. 21, for example, an aluminum-based metal electrode film 10 (for example, containing aluminum as a main component) is formed on the entire surface on the surface 1a side of the wafer 1 by sputtering film formation (aluminum sputtering step 103 in FIG. 12). For example, silicon is added to high-purity aluminum with a thickness of about 2500 to 6000 nm. Subsequently, a photoresist film is applied to the entire surface on the surface 1a side of the wafer 1 and patterned by ordinary lithography (aluminum photo process 104 in FIG. 12). Using the patterned resist film for processing such as an aluminum-based metal electrode film as a mask, patterning of the aluminum-based metal electrode film 10 is performed, for example, by wet etching (aluminum wet etching step 105 in FIG. 12). As a result, the portion corresponding to the upper gate wiring 6 of the aluminum-based metal electrode film 10 and the portion corresponding to the metal source electrode 8 are separated. As an etching solution used at this time, for example, a so-called mixed acid chemical solution, that is, a mixed solution of acetic acid, nitric acid, water and phosphoric acid (for example, about 70 to 80% by weight) can be exemplified as a suitable one. Note that cleaning is performed after the wet etching.

  Next, as shown in FIG. 22, the exposed portion of the barrier metal film 20 is removed by, for example, isotropic dry etching (barrier film etching step 106 in FIG. 12). Thereafter, the resist film for processing such as an aluminum metal electrode film that is no longer needed is removed (resist film removal step 107 in FIG. 12).

  Thereafter, if necessary, a final passivation film such as a polyimide film is formed on the surface 1 a side of the wafer 1.

7). Consideration of Embodiment and Supplementary Explanation Related to the Embodiment In the above embodiment, a metal made of a lower barrier metal film, an upper aluminum electrode film (the aluminum electrode film is sufficiently thicker than the barrier metal film), etc. The case where the electrode is patterned using a wet etching solution containing phosphoric acid as a main component and isotropic dry etching has been specifically described. In this case, if there is a void in the aluminum electrode film between the gate electrodes, when etching the aluminum electrode film, the wet etching solution penetrates through the void to the portion that should not be etched, and the aluminum system in that portion The electrode film is etched (abnormal side etching). Similarly, the same undesirable etching occurs when the barrier metal is etched. Further, when a wet etching solution (high viscosity due to high phosphoric acid concentration) remains in the void and moves to a portion to be etched during dry etching of the barrier metal film, an etching residue is generated. Such undesired etching and remaining etching problems may occur even when wet etching is changed to dry etching. In addition, there is a possibility of occurrence when isotropic dry etching is changed to anisotropic dry etching.

  Therefore, in the above embodiment, in order to prevent such abnormal side etching through the void, a gate electrode connecting portion (or gate electrode connecting bar) having a dam action is introduced into a part of the gate structure. Is. That is, in the laminated member of the same layer as the gate electrode, a large number of gate electrodes (gate electrode lead-out portions) are located near the outside of the active cell, and the upper portion is covered with the metal electrode film. By providing the connecting portion so as to be almost perpendicular to the extending direction, the dam effect that prevents the intrusion of the etching solution (etching gas) from the side is exhibited.

8). Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, the N-channel type device has been specifically described mainly in the above embodiment, but the present invention is not limited thereto, and it goes without saying that the present invention can be applied almost directly to a P-channel type device.

  In the above-described embodiments, the single device has been specifically described. However, the present invention is not limited thereto, and the composite semiconductor chip (semiconductor device) incorporating these insulated gate power transistors is used. However, it goes without saying that it can be applied almost as it is.

  Furthermore, in the above-described embodiment, the silicon-based device has been specifically described. However, the present invention is not limited to this, and a device using a substrate material belonging to another system such as SiC-based or SiN-based. Needless to say, it can be applied almost as it is.

  In the above embodiment, a device using an electrode (aluminum-based electrode) mainly including a metal layer mainly composed of aluminum as a main component is mainly described as a surface side metal. The invention is not limited thereto, and it goes without saying that the present invention can be applied almost as it is to devices using other electrode metals such as tungsten-based electrodes.

1 Semiconductor wafer (semiconductor substrate)
1a (Wafer or chip) surface (first main surface)
1b Back surface (second main surface) of wafer or chip
1e (wafer or chip) N-epitaxial layer 1s (wafer or chip) N-type silicon single crystal substrate 2 semiconductor chip (semiconductor substrate)
2i Internal area of semiconductor chip surface 3 Guard ring 4 (P-type) field limiting ring 5 Gate pad 6 Upper gate wiring 7 Active cell area 8 Metal source electrode (first metal electrode)
9 Gate electrode (gate electrode structure)
9i Intrinsic gate electrode 9p Active cell region end gate electrode 9t Gate electrode lead-out portion 10 Aluminum-based metal electrode film 11 Cell vicinity gate electrode connection portion 11a, 11b Cell vicinity gate electrode connection bar 12 Gate end portion gate electrode connection portion 14 Lower layer Gate wiring 15 Gate electrode-gate metal connection portion 16 P + type body contact region 17 Gate electrode end portion 18 Active cell region peripheral P type ring region 19 N− type drift region 20 Barrier metal film 21 Gate split region 22 N type source region 22a N + type source region 22b N type source extension region 23 Gate insulating film 24 Polysilicon film 25 Silicide film (WSi film)
26 Silicon oxide hard mask film 27 P-type base region introduction resist film 28 P-type channel region (P-type base region)
29 Cap film on side wall 30 Insulating film around gate electrode in active region 31 Resist film for introducing N-type source extension region 32 Insulating film for forming side wall 32w Side wall spacer 33 Resist film for forming side wall 34 Pre-connection hole 35 N + Resist film for introducing a source region 36 Contact hole 37 Interlayer insulating film 38 Connection hole 39 Gate electrode laminated film 101 Barrier metal sputtering film forming process 102 Annealing process 103 Aluminum-based metal sputtering film forming process 104 Metal electrode processing resist patterning process 105 Aluminum Metal film wet etching process 106 Barrier metal film dry etching process 107 Resist removal process C Capacitor CC Control circuit DC DC-DC down converter Gnd Ground terminal L Inductance element LS Unit cell center line corresponding to symmetry plane Q1 Upper side MOSFET
Q2 Lower side MOSFET
R1 Gate electrode protruding direction cutout portion R2 Gate electrode side cutout portion R3 Cell neighboring gate electrode connecting portion peripheral cutout portion T1 Width of intrinsic gate electrode and its extension T2 Width of cell neighboring gate electrode connecting portion UC Unit cell UCD Dummy cell portion Vdd Power supply output terminal VS Voltage source

Claims (9)

(A) A semiconductor substrate having a first main surface on which a gate electrode and a source electrode of a MOSFET are formed and a second main surface on the opposite side of the first main surface and on which the drain electrode of the MOSFET is formed. Preparation process,
(B) forming a gate insulating film of the MOSFET on an active cell region in which the channel of the MOSFET is formed;
(C) on said gate insulating film in plan view, are arranged at a predetermined distance from each other in a first direction and in a second direction crossing the first direction, a plurality of said gate electrodes extending in stripes Forming step,
(D) forming a first conductivity type first semiconductor region used as a source region of the MOSFET on the first main surface of the semiconductor substrate between the plurality of gate electrodes ;
(E) forming an interlayer insulating film that covers the plurality of gate electrodes and the first semiconductor region and has an opening that exposes the first semiconductor region;
(F) forming a barrier metal film electrically connected to the first semiconductor region through the opening on the interlayer insulating film;
(G) forming on the barrier metal film a metal electrode film mainly composed of aluminum thicker than the barrier metal film;
(H) by sequentially patterning the metal electrode film and the barrier metal film by selective wet etching, the gate electrode of the MOSFET including the laminated film of the barrier metal film and the metal electrode film; Forming the source electrode,
In the step (c), each of the previous SL plurality of gate electrodes,
A first portion located in the active cell region;
A second portion formed to extend to an outer region of the active cell region in the second direction;
The gate electrode is formed to extend in the first direction in the outer region, and to further include a third portion integrally formed so as to connect the second portions to each other,
The method of manufacturing a semiconductor device, wherein the selective wet etching in the step (h) is performed outside the active cell region and the third portion of the gate electrode .   The method of manufacturing a semiconductor device according to claim 1, wherein a plurality of the third portions are provided close to each other.   2. The method for manufacturing a semiconductor device according to claim 1, wherein the third portion is substantially linear. The method of manufacturing a semiconductor device according to claim 3, wherein the third part component, said plurality of gate electrodes, the width is substantially the same, a method of manufacturing a semiconductor device. 4. The method for manufacturing a semiconductor device according to claim 3, wherein the width of the third portion is wider than the width of the plurality of gate electrodes . 5. The method of manufacturing a semiconductor device according to claim 4, wherein the third portion is formed of a member in the same layer as the plurality of gate electrodes .   5. The method of manufacturing a semiconductor device according to claim 4, wherein the MOSFET is a power MOSFET.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the MOSFET is a power MOSFET having a planar structure.   9. The method of manufacturing a semiconductor device according to claim 8, wherein the MOSFET is a split gate type power MOSFET having a planar structure.

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