JP2014116680A - Clock phase adjustment circuit and receiving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a phase adjustment circuit capable of maintaining high linearity even when an operation frequency is switched.SOLUTION: A clock phase adjustment circuit for adjusting a phase of a fetch clock for fetching an input data signal by a fetch clock of a frequency CLKO N times the frequency of a reference clock CLKI includes: a code conversion circuit 21 for converting a fetch phase adjustment code indicating a phase shift quantity of a fetched input data signal into a reference clock phase adjustment code in accordance with a conversion table; a reference phase adjustment circuit 22 for adjusting the phase of the reference clock accordingly to the phase shift quantity by mixing the reference clock and the reference clock phase adjustment code; and a frequency conversion circuit 23 for converting an adjusted clock into a fetching clock with a frequency of N times.

Description

  The present invention relates to a clock phase adjusting circuit and a receiving circuit.

  As the performance of information processing devices such as communication backbone devices and servers increases, it is necessary to increase the data rate of signal transmission and reception inside and outside the device. A transceiver that operates at high speed is provided with an equalization circuit that restores the high-frequency attenuation of the transmission line to a level at which 0/1 determination is possible, and a CDR (Clock and Data Recovery) circuit that restores a clock having an optimal timing from the data signal. It is known that the same effect can be obtained when the equalization circuit is arranged in any of a transmitter, a transmission line, and a receiver when considered in terms of a transfer function. On the other hand, the function performed by the CDR circuit is a function performed on the receiver side, and is required to be performed in parallel with waveform equalization.

  There are a plurality of architectures for realizing a CDR circuit. Here, a receiving circuit having a tracking type digital CDR circuit in which a clock follows a data sampling point will be described. The tracking type reception circuit includes a determination circuit, a demultiplexing circuit (demultiplexer (DEMUX)), a digital CDR circuit including a phase detector (PD), and a phase adjustment circuit. The determination circuit captures the input data signal as a digital signal according to the capture clock. The demultiplexing circuit converts the serial data output from the determination circuit into parallel data and performs speed conversion. A phase detector (PD) detects phase information of a data signal. The digital CDR circuit generates a digital phase adjustment code based on the determination result of the phase detector. The phase adjustment circuit adjusts the phase of the reference clock by the digital phase adjustment code generated by the digital CDR circuit, and generates a capture clock. By generating an acquisition clock whose phase is adjusted at the center of the data, the eye opening at the time of sampling is maximized. As the transmission speed increases, phase interpolation using a high-frequency clock is performed with high resolution.

  In order to make the receiving circuit comply with various communication standards such as USB and PCI-Express, each element of the tracking type receiving circuit corresponds to different data rates defined by the standard. Circuits such as a decision circuit, a DEMUX, and a digital CDR including a phase detector can be adapted to a low-speed mode by optimizing the circuit at the highest data rate. However, since the optimum point is different for each data rate, the phase adjustment circuit performs adjustment.

  Next, the phase adjustment circuit will be described. The phase adjustment circuit is a delay circuit, and controls the phase to any one of 360 ° using a digital phase adjustment code. For this purpose, the phase adjustment circuit uses a circuit that performs an addition theorem of a trigonometric function and mounts it on an LSI (Large Scale Integrated Circuit). The addition theorem can be realized by adding a result obtained by multiplying cos θ and sin θ to a sine wave (sin) and a cosine wave (cos) shifted by 90 ° in accordance with the phase amount θ to be shifted. Although the sine wave is used in the arithmetic processing of the addition theorem, it is actually difficult to create a complete sine wave using a narrow-band filter. Yes. In a general phase adjustment circuit, a digital phase adjustment code is D / A converted to generate a triangular wave current, which is transmitted to a current source of a current-driven mixer circuit by a current mirror circuit. Then, arithmetic processing of the addition theorem is realized by mixing the clock and the triangular wave current, and a cross point with respect to the comparison threshold of the signal generated by the arithmetic processing of the addition theorem is detected as phase information.

  Similar to the AD converter and DA converter, the important performance index of the phase adjustment circuit is linear. The linearity is mainly expressed using a linear error (INL: Integer Non-Linearity) or a differential error (DNL: Differential Non-Linearity). Ideally, it is desirable to change the delay amount (phase shift) every time the digital phase adjustment code shifts by 1 LSB, but in reality there is a deviation from the ideal state, so performance evaluation is performed with linearity. ing.

  As described above, it is desirable that the receiving circuit operate at different data rates, and it is desirable that the phase adjustment circuit be kept constant without degrading linearity even when the operating frequency is switched. For example, the signal at the output node of the phase adjustment circuit becomes a triangular wave when cos θ = a = 0, and when ΔT corresponding to the reciprocal of the CLK cycle changes, the slew rate so that the amplitude (output voltage) V becomes constant. It is necessary to adjust the value of I / C. If such adjustment is not performed, the output voltage V is saturated, and the time information at which the threshold value of the determination circuit that determines the delay amount and the output voltage V intersect deviates from the ideal state. Therefore, in a general phase adjustment circuit, the value of the output capacitance or the current source bias of the phase adjustment circuit is adjusted according to the operating frequency. When such adjustment is performed, it is not easy to make the linearity uniform in each operation mode due to the influence of parasitic capacitance and current fluctuation due to the finite output impedance of the current source transistor.

Special table 2008-535387 Japanese Patent Application Laid-Open No. 06-062428 JP 2012-028935 A

  In the above general phase adjustment circuit, the linearity of the phase adjustment circuit does not become uniform when the operating frequency is switched due to the influence of parasitic capacitance and the gate bias fluctuation of the current source transistor, and the linearity deteriorates at a specific frequency. Resulting in.

  According to this embodiment, a phase adjustment circuit that maintains good linearity even when the operating frequency is switched is realized.

  According to the first aspect of the invention, the clock phase adjustment circuit captures the input data signal with a capture clock having a frequency N (N = integer or N = 1 / integer) times the frequency of the reference clock. Adjust the phase of the capture clock. The clock phase adjustment circuit includes a code conversion circuit, a reference phase adjustment circuit, and a frequency conversion circuit. The code conversion circuit converts an acquisition phase adjustment code indicating a phase shift amount of the input data signal acquired with respect to the acquisition clock into a reference clock phase adjustment code according to the conversion table. The reference phase adjustment circuit mixes the reference clock and the reference clock phase adjustment code, adjusts the phase of the reference clock according to the phase shift amount, and outputs the adjusted clock. The frequency conversion circuit converts the adjusted clock into an acquisition clock having a frequency N times.

  According to a second aspect of the invention, the receiving circuit includes a determination circuit, a demultiplexing circuit, a digital CDR circuit, and a phase adjustment circuit. The determination circuit captures an input data signal with a capture clock having a frequency N (N = integer or N = 1 / integer) times the frequency of the reference clock. The demultiplexing circuit converts the output of the determination circuit, which is serial data, into parallel data and performs speed conversion. The digital CDR circuit detects the phase information of the data signal from the output of the demultiplexing circuit and generates an acquisition phase adjustment code. The phase adjustment circuit adjusts the phase of the clock CLK using the fetch phase adjustment code generated by the digital CDR circuit. The phase adjustment circuit includes a code conversion circuit, a reference phase adjustment circuit, and a frequency conversion circuit. The code conversion circuit converts an acquisition phase adjustment code indicating a phase shift amount of the input data signal acquired with respect to the acquisition clock into a reference clock phase adjustment code according to the conversion table. The reference phase adjustment circuit mixes the reference clock and the reference clock phase adjustment code, adjusts the phase of the reference clock according to the phase shift amount, and outputs the adjusted clock. The frequency conversion circuit converts the adjusted clock into an acquisition clock having a frequency N times.

  According to the above aspect, the phase adjustment circuit corresponding to a plurality of operation modes having different clock frequencies can be realized without changing the current flowing through the transistor of the current source of the mixer amplifier for mixing or the capacitance of the output node. When the clock frequency input to the phase adjustment circuit is low, the influence of the clock duty and the power consumed by the clock distribution are reduced.

FIG. 1 is a diagram showing a configuration of a general receiving circuit having a tracking type CDR. FIG. 2 is a diagram illustrating generation of a phase shift signal by combining two triangular waves that are 90 ° phase shifted. FIG. 3 is a diagram illustrating a circuit example of a general phase adjustment circuit, in which (A) shows a circuit configuration and (B) shows an arithmetic expression of the circuit. FIG. 4 is a diagram showing a modification in which the linearity is maintained even when the operating frequency is changed to a different frequency in the phase adjustment circuit of FIG. FIG. 5 is a diagram showing another modification in which the linearity is maintained even when the operating frequency is changed to a different frequency in the phase adjustment circuit of FIG. FIG. 6 is a diagram showing the output voltage amplitude when the phase adjustment circuit of FIG. 4 is changed to a different operating frequency with a = 1. FIG. 7 is a block diagram showing the configuration of the phase adjustment circuit of the first embodiment. FIG. 8 is a block diagram showing the configuration of the phase adjustment circuit of the second embodiment. FIG. 9 is a diagram illustrating a configuration of the reference phase adjustment circuit. FIG. 10 is a diagram illustrating a configuration of the first phase adjustment unit or the second phase adjustment unit. FIG. 11 is a diagram illustrating a circuit example of the mixing circuit of FIG. FIG. 12 is a diagram illustrating a modification of the mixing circuit. FIG. 12 is a diagram illustrating another modification of the mixing circuit. FIG. 14 is a diagram for explaining the conversion process of the code conversion circuit, and shows an example of a 4-bit digital phase adjustment code. 15A and 15B are diagrams for explaining a code conversion table included in the code conversion circuit according to the second embodiment. FIG. 15A is a 4-bit digital phase adjustment code of 5 GHz before conversion, and FIG. A 2.5 GHz 4-bit digital phase adjustment code is shown. FIG. 16 is a block diagram showing the configuration of the phase adjustment circuit of the third embodiment. FIG. 17 is a diagram for explaining the conversion processing of the code conversion circuit in the third embodiment, and shows an example of a 4-bit digital phase adjustment code. 18A and 18B are diagrams illustrating a code conversion table included in the code conversion circuit according to the third embodiment. FIG. 18A illustrates a 7.5-GHz 4-bit digital phase adjustment code before conversion, and FIG. 18B illustrates conversion. The latter 2.5 GHz 4-bit digital phase adjustment code is shown. FIG. 19 is a block diagram showing the configuration of the phase adjustment circuit of the fourth embodiment. FIG. 20 is a diagram for explaining the conversion process of the code conversion circuit in the fourth embodiment, and shows an example of a 4-bit digital phase adjustment code. FIG. 21 is a diagram for explaining a code conversion table included in the code conversion circuit according to the fourth embodiment. FIG. 21A illustrates a 10-bit 4-bit digital phase adjustment code before conversion, and FIG. A 2.5 GHz 4-bit digital phase adjustment code is shown. FIG. 22 is a block diagram showing the configuration of the phase adjustment circuit of the fifth embodiment. FIG. 23 is a diagram for explaining the conversion processing of the code conversion circuit in the fifth embodiment, and shows an example of a 4-bit digital phase adjustment code. 24A and 24B are diagrams for explaining a code conversion table included in the code conversion circuit according to the fifth embodiment. FIG. 24A shows a 625 MHz 4-bit digital phase adjustment code before conversion, and FIG. A 2.5 GHz 4-bit digital phase adjustment code is shown. FIG. 25 is a circuit diagram in the case where the code conversion circuit of the fifth embodiment is realized by a gate circuit. FIG. 26 is a block diagram showing the configuration of the phase adjustment circuit of the sixth embodiment. FIG. 27 shows the reception circuit shown in FIG. 1 having the phase adjustment circuit of the sixth embodiment as a phase adjustment circuit. The frequency of the acquisition clock is set in accordance with the input data signal, and the phase adjustment is performed for reception. It is a flowchart which shows the setting operation | movement which enables it. FIG. 28 is a block diagram showing the configuration of the phase adjustment circuit of the seventh embodiment.

  Before describing the embodiment, a general receiving circuit and phase adjustment circuit will be described.

FIG. 1 is a diagram showing a configuration of a general receiving circuit having a tracking type CDR.
A general receiving circuit includes an equalization circuit 11, a determination circuit 12, a demultiplexing circuit (DEMUX) 13, a digital CDR (Clock Data Recovery) 14, and a phase adjustment circuit 15. The equalization circuit 11 is a circuit that receives the input data signal Din and corrects the influence on the subsequent UI based on the value of the data received in the previous unit interval (UI). The equalization circuit 11 produces the same effect regardless of where it is placed in the communication path. The determination circuit 12 takes in the input data signal Din that has been equalized by the take-in clock CLKO. The demultiplexing circuit 13 converts the output of the determination circuit 12 as serial data into parallel data and performs speed conversion. The digital CDR circuit 14 detects the phase information of the data signal from the output of the demultiplexing circuit 13 and generates an acquisition phase adjustment code. The phase adjustment circuit 15 adjusts the phase of the reference clock CLKI using the capture phase adjustment code generated by the digital CDR circuit 14 and generates the capture clock CLKO. The reference clock CLKI is generated by a PLL circuit or the like provided in the receiving circuit and supplied to the phase adjustment circuit 15. The reference clock CLKI has a period similar to the unit period (unit interval: UI) of the input data signal Din but does not match, and the phases of CLKI and Din change gradually.

  In other words, the phase adjustment circuit 15 is a delay device whose phase is controlled by 360 ° by a digital code. The general phase adjustment circuit 15 changes the phase by an addition theorem of trigonometric functions. In the addition theorem, a phase-shifted signal is generated by adding the result of multiplying cos θ and sin θ in accordance with the amount to be phase-shifted with respect to the sin wave and the cosine wave 90 ° phase-shifted with respect to the sin wave. .

A signal obtained by shifting the sin wave of the angular frequency ωt by the phase θ is represented by sin (ωt−θ) and is decomposed as the following equation.
sin (ωt−θ) = sin (ωt) cos θ−cos (ωt) sin θ
≒ CLK0 × a-CLK90 × (1-a)
Here, a is a value determined according to the phase shift amount.

However, since it is practically impossible to create a complete sine wave using a narrow-band filter, the sine wave is approximated to a triangular wave in practice.
FIG. 2 is a diagram illustrating generation of a phase shift signal by combining two triangular waves that are 90 ° phase shifted.

  In FIG. 2, CLK000 is the first triangular wave, CLK090 is the second triangular wave whose phase is shifted by 90 ° with respect to the first triangular wave, and the combined wave CLKS is synthesized with a = 0.6. The phase of CLKS is shifted with respect to CLK000.

FIG. 3 is a diagram illustrating a circuit example of a general phase adjustment circuit, in which (A) shows a circuit configuration and (B) shows an arithmetic expression of the circuit.
The phase adjustment circuit includes two capacitors PC connected to a node that combines two voltage-current conversion circuits VITA and VITB composed of differential amplifiers, a comparator CA, and outputs of positive and negative phases of VITA and VITB. And NC. VITA receives a reference clock CLKI000 having a phase of 0 ° and a reference clock CLKI180 having a phase of 180 °, and outputs a differential current signal corresponding to the difference signal. The amplification factor a of VITA is adjusted by adjusting the power supply current of the differential amplifier that forms VITA. The amplification factor a is adjusted according to the digital phase adjustment code. VITB has the same configuration as VITA, and a reference clock CLKI090 having a phase of 90 ° and a reference clock CLKI270 having a phase of 270 ° are input and adjusted to an amplification factor (1-a). VITA outputs positive and negative phase current signals that repeat charging and discharging, and generates a triangular wave voltage signal by charging and discharging the capacitors PC and NC. Similarly, VITB outputs positive and negative current signals that repeat charging and discharging, charges and discharges the capacitors PC and NC, and generates a triangular wave voltage signal if there is no charging or discharging from VITA. To do. The output of VITA and the output of VITB are combined. By adjusting the amplification factors a and (1-a) according to the digital phase adjustment code, the two triangular waves shifted by 90 ° shown in FIG. 2 are synthesized. Is done. A node to which the capacitors PC and NC are connected is connected to two input nodes of the comparator CA. Comparator CA determines the magnitude of the two inputs and outputs rectangular wave output clocks CLKO000 and CLKO180 having a phase difference of 180 °.

  Since the phase adjustment circuit for generating and calculating the triangular wave in FIG. 3 is widely known, further explanation is omitted.

  As described above, it is desirable that the phase adjustment circuit maintain linearity even at a plurality of different frequencies. In the phase adjustment circuit of FIG. 3, the reference clocks CLKI000 to CLKI270 also have a frequency corresponding to the operating frequency. However, when the operating frequency is a low frequency with a large period, the signal input to the comparator CA is saturated and the linearity is maintained. become unable.

FIG. 4 shows a modification in which the linearity is maintained even when the operating frequency is changed to a different frequency in the phase adjustment circuit of FIG.
In the phase adjustment circuit of FIG. 4, the capacitors PC and NC are replaced with variable capacitors APC and ANC having variable capacitance values, and the capacitance value of the variable capacitor is adjusted according to the operating frequency. Here, if the combined output current from VITA and VITB is I, the capacitance value of the variable capacitor APC or ANC is C, and the half period of the operating frequency is ΔT, the voltage V = I / C × at the input node of the comparator CA ΔT. C is a value including parasitic capacitance. When ΔT is large, that is, when the operating frequency is low, the variable capacitor is adjusted so as to increase C. However, due to the influence of the parasitic capacitance, the amplitude of the CA output voltage at each operating frequency is not the same, and it is difficult to make the linearity uniform.

FIG. 5 shows another modification in which the linearity is maintained even when the operating frequency is changed to a different frequency in the phase adjustment circuit of FIG.
In the phase adjustment circuit of FIG. 5, the gains of VITA and VITB are set to a × k and (1−a) × with the corrected digital phase adjustment code corrected so that the gain is increased to k (0 <k ≦ 1) times. Correct to k. In other words, the output current of VITA and VITB is reduced by k times to prevent saturation. However, when the current of the current source transistor is reduced, the transistor becomes a non-linear region, and fluctuation due to gate bias fluctuation increases, making it difficult to make the linearity uniform at each operating frequency.

  FIG. 6 is a diagram showing the output voltage amplitude when the phase adjustment circuit of FIG. 4 is changed to a different operating frequency with a = 1. It can be seen that the output voltage amplitude varies depending on the operating frequency.

The above is the configuration and problems of a general phase adjustment circuit.
Hereinafter, the phase adjustment circuit of the embodiment will be described.

FIG. 7 is a block diagram showing the configuration of the phase adjustment circuit of the first embodiment.
The phase adjustment circuit of the first embodiment is used, for example, as the phase adjustment circuit 15 of the reception circuit of FIG. The phase adjustment circuit of the first embodiment has a phase suitable for capturing the input data signal Din at a frequency N (N = integer or N = 1 / integer) times the frequency of the reference clock CLKI. The capture clock CLKO adjusted to the above is generated.

  The phase adjustment circuit of the first embodiment includes a code conversion circuit 21, a reference phase adjustment circuit 22, and a frequency conversion circuit 23. The code conversion circuit 21 converts the fetch phase adjustment code indicating the amount of phase shift from the fetch clock of the fetched input data signal into the reference clock phase adjustment code according to the conversion table. The reference phase adjustment circuit 22 mixes the reference clock CLKI with the frequency f = f0 and the phase adjustment code for the reference clock, adjusts the phase of the reference clock according to the phase shift amount, and adjusts the adjusted clock CLKT with the frequency f = f0. Is output. The frequency conversion circuit 23 converts the adjusted clock CLKT into an acquisition clock CLKO having an N-fold frequency f = f1.

  In the phase adjustment circuit according to the first embodiment, the code conversion circuit 21 uses the acquisition phase adjustment code indicating the phase shift amount with respect to the input data signal of the acquisition clock CLKO having the frequency f1 different from the reference clock CLKI as the reference clock phase adjustment. Convert to code. Thereafter, the phase adjustment is performed by the reference phase adjustment circuit 22. As a result, the reference clock phase adjustment code supplied to the reference phase adjustment circuit 22 has a frequency corresponding to the frequency f0 of the reference clock, and the phase adjustment with the reference clock CLKI in the reference phase adjustment circuit 22 is performed. Then, the adjusted clock CLKT is frequency-converted to generate the fetch clock CLKO. Therefore, even if the frequency f1 of the fetch clock CLKO is different from the frequency f0 of the reference clock CLKI, the reference phase adjustment circuit 22 can perform phase adjustment with the reference clock CLKI, so that linearity is maintained.

FIG. 8 is a block diagram showing the configuration of the phase adjustment circuit of the second embodiment.
The phase adjustment circuit according to the second embodiment includes a code conversion circuit 31, a reference phase adjustment circuit 32, a mixing circuit 33, and a band pass filter 34. The mixing circuit 33 and the band pass filter 34 correspond to the frequency conversion circuit 23 in FIG.

  The phase adjustment circuit of the second embodiment shown in FIG. 8 generates a capture clock CLKO having a frequency twice that of the reference clock CLKI. For example, the frequency of the reference clock CLKI is 2.5 GHz, and the frequency of the capture clock CLKO is 5 GHz. The code conversion circuit 31 converts the acquisition phase adjustment code indicating the phase shift amount with respect to the input data signal of the 5 GHz acquisition clock CLKO into the reference adjustment phase adjustment code for 2.5 GHz. The reference phase adjustment circuit 32 performs phase adjustment using a 2.5 GHz multiphase reference clock CLKI and a 2.5 GHz reference clock phase adjustment code, and generates a 2.5 GHz adjusted clock CLKT. The mixing circuit 33 mixes the adjusted clock CLKT of 2.5 GHz and the reference clock CLKI to generate a synthesized clock CLKS. Synthetic clock CLKS includes a frequency component of 5 GHz, a frequency component of 2.5 GHz, a direct current component, and the like. The BPF 34 is a bandpass filter that passes a frequency component of 5 GHz, and passes a frequency component of 5 GHz from the synthesized clock CLKS and outputs a 5 GHz capture clock CLKO.

FIG. 9 is a diagram illustrating a configuration of the reference phase adjustment circuit 32.
The phase adjustment circuit 32 includes a first phase adjustment unit 41 and a second phase adjustment unit 41. The first phase adjustment unit 41 generates differential adjusted clocks CLKT (0) to CLKT (π) whose phases are adjusted from CLKI000 to CLKI270 and the digital phase adjustment code. Similarly, the second phase adjustment unit 42 generates differential adjusted clocks CLKT (π / 2) to CLKT (3π / 2) that are phase-adjusted from CLKI270 to CLKI000 and the digital phase adjustment code. In other words, the phase adjustment circuit 32 generates a four-phase adjusted clock CLKT that is 90 ° out of phase. Note that when only the single-phase or two-phase adjusted clock CLKT is generated, the second phase adjustment unit 42 can be omitted.

  FIG. 10 is a diagram illustrating a configuration of the first phase adjustment unit 41 or the second phase adjustment unit 42. The first phase adjustment unit 41 and the second phase adjustment unit 42 have the same circuit configuration, and the input order of the four-phase reference clocks is different.

  Each phase adjustment unit includes four mixer amplifiers VIT0 to VIT3, four current D / A conversion circuits IDAC0 to IDAC3, four current mirror current sources W0 to W3, a coupling circuit CN, a comparator CAA, Have VIT0, IDAC0 and W0 form a first voltage-current conversion circuit in which the addition ratio is adjusted by the digital phase adjustment code. Similarly, VIT1, IDAC1, and W1 form a second voltage-current conversion circuit, VIT2, IDAC2, and W2 form a third voltage-current conversion circuit, and VIT3, IDAC3, and W3 form a fourth voltage-current conversion circuit. .

  Each mixer amplifier includes a differential pair in which two columns of PMOS transistors and NMOS transistors connected in series are connected in parallel, and a PMOS that operates as a current source connected between the differential pair and the high potential source and the low potential source. A transistor and an NMOS transistor; A differential reference clock is input to the gates of the PMOS transistor and the NMOS transistor in the opposite column of the differential pair. Each mixer amplifier supplies current to the positive phase output and draws current from the negative phase output in the first half cycle of the differential reference clock, and draws current from the positive phase output and feeds current to the negative phase output in the second half cycle To work. Further, by controlling the gate voltage of the PMOS transistor and NMOS transistor of the current source, the amount of current input to and output from the normal phase output and the negative phase output can be adjusted.

  In VIT0, a reference clock CLK000 (θ0) having a phase of 0 ° and a reference clock CLK180 having a phase of 180 ° (θ2) are input to the differential pair, and operates as a current source that generates a triangular wave of the first phase (0 °). VIT1 operates as a current source that generates a second phase (90 °) triangular wave by inputting a reference clock CLK90 having a phase of 90 ° (θ1) and a reference clock CLK270 having a phase of 270 ° (θ3) to the differential pair. VIT2 operates as a current source that generates a third phase (180 °) triangular wave by inputting a reference clock CLK180 (θ2) having a phase of 180 ° and a reference clock CLK000 having a phase of 0 ° (θ0) to the differential pair. In VIT3, a reference clock CLK270 having a phase of 270 ° (θ3) and a reference clock CLK090 having a phase of 90 ° (θ1) are input to the differential pair, and operates as a current source that generates a fourth (270 °) triangular wave. The positive phase output and the negative phase output of VIT0 to VIT3 are connected in common and input to the comparator CAA.

  Current D / A conversion circuits IDAC0 to IDAC3 are controlled in operation state and the number of connected PMOS transistors as current sources in accordance with the digital phase adjustment codes, respectively, and change the amount of current supplied to current mirror current sources W0 to W3. The high-order bits of the digital phase adjustment code set one to use among IDAC0 to IDAC3 in an operating state and put one not in use into a non-operating state according to the quadrant to be adjusted. Current mirror current sources W0 to W3 change the voltages applied to the gates of the PMOS transistors and NMOS transistors of the current sources VIT0 to VIT3 according to the amounts of current supplied from the current D / A conversion circuits IDAC0 to IDAC3, respectively. . In other words, the current source transistors VIT0 to VIT3 and the W0 to W3 transistors form a current mirror circuit, and the output currents of VIT0 to VIT3 are changed according to the amount of current supplied from IDAC0 to IDAC3.

  Comparator CAA compares the voltages of the positive and negative phase outputs of VIT0 to VIT3 connected in common, and outputs rectangular adjusted clocks CLKT (φ0) and CLKT (φ2) that change to 1 or 0. . CLKT (φ0) and CLKT (φ2) are opposite in phase and form a differential signal. The coupling circuit CN forms a capacitor that is the output destination of the currents VIT0 to VIT3, and is arranged to match the DC (direct current) level between the operating point of the current comparator CAA and the outputs of VIT0 to VIT3.

  The digital phase adjustment code represents a phase shift from 0 ° to 360 ° as a code, where 0 ° to 90 ° is the first quadrant, 90 ° to 180 ° is the second quadrant, and 180 ° to 270 °. Is the third quadrant, and 270 ° to 360 ° is the fourth quadrant. The upper bit of the digital phase adjustment code indicates a quadrant, and if it is four quadrants, the upper two bits are used to indicate the quadrant. In the first quadrant, IDAC0 and IDAC1 supply current and IDAC2 and IDAC3 do not supply current according to the digital phase adjustment code. As a result, in the first quadrant, the third voltage-current conversion circuit VIT2 and the fourth voltage-current conversion circuit VIT3 do not input and output current, and the first voltage-current conversion circuit VIT0 and the second voltage-current conversion circuit VIT1 inputs and outputs current according to the phase difference. In other words, a set of voltage-current conversion circuits to be used is determined according to the position of the quadrant. The lower bits of the digital phase adjustment code indicate the angular position in each quadrant, and indicate the weight when adding the triangular wave clock at a predetermined ratio based on the addition theorem. As a result, a circuit for executing the addition theorem shown in FIG. 3 is realized, and phase adjustment according to the digital phase adjustment code is performed. Similarly, in the second quadrant, the phase adjustment according to the digital phase adjustment code is performed by the second voltage-current conversion circuit VIT1 and the third voltage-current conversion circuit VIT2. In the third quadrant, the phase adjustment according to the digital phase adjustment code is performed by the third voltage-current conversion circuit VIT2 and the fourth voltage-current conversion circuit VIT3. In the fourth quadrant, the phase adjustment according to the digital phase adjustment code is performed by the fourth voltage-current conversion circuit VIT3 and the first voltage-current conversion circuit VIT0.

  The phase adjustment circuit shown in FIGS. 9 and 10 is described in, for example, Patent Document 3, and further detailed description thereof is omitted.

  FIG. 11 is a diagram illustrating a circuit example of the mixing circuit 33 in FIG. 8. The differential reference (reference) clock CLKI is input to RF_IN and RF_INX, and the differential adjusted clock CLKT is input to LO_IN and LO_INX. The mixing circuit 33 in FIG. 11 is a circuit called a Gilbert mixer, and uses a resistor as a load to switch a current path through two differential pairs connected in parallel between the load and a current source using CLKT. It is a circuit that mixes with. Since the mixing circuit of FIG. 11 is widely known, detailed description thereof is omitted.

  FIG. 12 is a diagram illustrating a modification of the mixing circuit 33. The mixing circuit of FIG. 12 is the mixing circuit 33 of FIG. 11 and has a configuration in which an inductance element and a capacitive element are connected in parallel to a load resistor. In the circuit of FIG. 12, the inductance element and the capacitive element form a tank circuit that causes resonance, the impedance increases only at the time of resonance, and the function of adding a bandpass filter is achieved.

  FIG. 13 is a diagram illustrating another modification of the mixing circuit 33. The mixing circuit of FIG. 13 is the mixing circuit 33 of FIG. 11 and has a configuration in which a capacitor is added to the output node. These capacitors function as a high-pass filter that removes low-frequency components.

  The band pass filter (BPF) 34 in FIG. 8 is realized by a widely known filter circuit using a capacitor, an inductor, and a resistor. Further, as will be described later, the code conversion circuit 31 has a conversion table and converts the digital movement adjustment code into a predetermined conversion code.

FIG. 14 is a diagram for explaining the conversion process of the code conversion circuit 31 and shows an example of a 4-bit digital phase adjustment code.
As described above, the digital phase adjustment code represents a phase shift from 0 ° to 360 ° as a code. As shown in FIG. 14A, the digital phase adjustment code before code conversion indicates a phase position (angle) from 0 ° to 360 °. The phase position is divided into first to fourth quadrants, and as shown in FIG. 14C, the upper 2 bits of the code indicate the position of the quadrant. The lower 2 bits of the code indicate a phase position obtained by dividing each quadrant into four.

  In the second embodiment, the digital phase adjustment code before code conversion indicates the phase difference between the 5 GHz capture clock CLKO and the input data signal, but the phase adjustment in the phase adjustment circuit 32 is performed with the 2.5 GHz reference clock CLKI. Done in Therefore, the code conversion circuit 31 converts the digital phase adjustment code of 5 GHz into a digital phase adjustment code for 2.5 GHz. The displacement time from 0 ° of the phase position in the period of 5 GHz corresponds to the displacement time of the phase position of ½ in the period of 2.5 GHz. Therefore, the 5 GHz digital phase adjustment code indicating the phase position from 0 ° to 360 ° in FIG. 14A shows the phase position from 0 ° to 180 ° as shown in FIG. It is converted into a digital phase adjustment code for 5 GHz. Therefore, the phase position indicated by the digital phase adjustment code for 2.5 GHz is limited to the first quadrant from 0 ° to 90 ° and the second quadrant from 90 ° to 180 °. Therefore, as shown in FIG. 14D, it indicates whether the upper 1 bit of the digital phase adjustment code for 2.5 GHz is in the first quadrant or the second quadrant. The lower 3 bits indicate a phase position obtained by dividing each quadrant into 8 parts.

  FIG. 15 is a diagram for explaining a code conversion table included in the code conversion circuit 31. FIG. 15A shows a 5-GHz 4-bit digital phase adjustment code before conversion, and FIG. 15B shows a 2.5-GHz 4-bit digital phase adjustment code after conversion. The code conversion circuit 31 converts the code value of FIG. 15A to the code value of FIG. A 4-bit code can take values from 0 to 15. In the 5-GHz 4-bit digital phase adjustment code before conversion, the upper 2 bits indicate four quadrants and the lower 2 bits indicate a position in the quadrant. In FIG. 15A, the weight indicates the lower 2 bits and indicates the positions of 0 °, 22.5 °, 45 °, and 67.5 ° within the quadrant. In this example, when switching from the first quadrant (00) to the second quadrant (01) and from the third quadrant (10) to the fourth quadrant (11), the code of the lower 2 bits is folded back symmetrically. To change. This is because, for example, the phase 0 ° of the first quadrant is the first reference clock and the phase 90 ° is the second reference clock, and the phase 180 ° of the second quadrant is the first reference clock and the phase 90 ° is the second. This is because the group is switched to the reference clock group, and the same applies to other switching. In FIG. 15A, for example, when code value = 10, code = 1010, which indicates a 45 ° position in the third quadrant, that is, a 225 ° position.

  In the converted digital phase adjustment code for 2.5 GHz, the upper 1 bit indicates two quadrants (first or second quadrant), and the lower 3 bits indicate a position divided into 8 in the quadrant. In FIG. 15B, the weight indicates the lower 3 bits, and 0 °, 11.25 °, 22.5 °, 33.75 °, 45 °, 56.25 °, 67.5 ° within the quadrant. , 78.75 ° position. Also in FIG. 15B, when the first quadrant (0) is switched to the second quadrant (1), the lower 3 bits of the code are changed symmetrically. For example, when the code value is 10, the code is 1101 and indicates a 45 ° position in the second quadrant, that is, a 225 ° position.

  As described above, the 5 GHz digital phase adjustment code indicating the phase difference between the 5 GHz capture clock CLKO and the input data signal is converted into the 2.5 GHz digital phase adjustment code. Here, the digital phase adjustment code for 5 GHz and the digital phase adjustment code for 2.5 GHz are different in code, but the phase difference time indicated by the code is the same. As described above, the phase adjustment circuit 32 generates the adjusted clock CLKT using the 2.5 GHz reference clocks CLKI000 to CLKI270 and the converted digital phase adjustment code for 2.5 GHz. Then, the mixing circuit 33 and the BPF 34 generate a signal including a harmonic of 5 GHz from the reference (reference) clock CLKI and the adjusted clock CLKT, and output a 5 GHz acquisition clock CLKO. The fetch clock CLKO is a 5 GHz clock whose phase is adjusted by the amount of the phase difference indicated by the 5 GHz digital phase adjustment code.

  In the phase adjustment circuit of the second embodiment, the phase adjustment is performed only in the first and second quadrants, and therefore a set of VIT0 and VIT1 or a set of VIT1 and VIT2 is used. In other words, VIT3 is not used.

  Further, the phase adjustment circuit of the second embodiment uses the differential mixer amplifier shown in FIG. 10, but a single-phase mixer amplifier may be used, and each of the four single-phase mixer amplifiers includes: CLKI000 (θ0) to CLKI270 (Theta 3) are input. In this case, if only a single phase clock of 0 ° is required as the capture clock CLKO, a single phase type mixer amplifier corresponding to VIT3 is not used as described above, so the reference clock CLKI 270 of phase 270 ° is used. Not.

FIG. 16 is a block diagram showing the configuration of the phase adjustment circuit of the third embodiment.
The phase adjustment circuit according to the third embodiment includes a code conversion circuit 51, a reference phase adjustment circuit 52, a mixing circuit 53, and a band pass filter 54.

  The phase adjustment circuit according to the third embodiment generates a capture clock CLKO having a frequency three times that of the reference clock CLKI. For example, the frequency of the reference clock CLKI is 2.5 GHz, and the frequency of the capture clock CLKO is 7.5 GHz. The code conversion circuit 51 converts the acquisition phase adjustment code indicating the amount of phase shift with respect to the input data signal of the 7.5 GHz acquisition clock CLKO into the reference adjustment phase adjustment code for 2.5 GHz. The reference phase adjustment circuit 52 performs phase adjustment using a 2.5 GHz multi-phase reference clock CLKI and a 2.5 GHz reference clock phase adjustment code, and generates a 2.5 GHz adjusted clock CLKT. The mixing circuit 53 mixes the adjusted clock CLKT of 2.5 GHz and the reference clock CLKR of 5 GHz to generate a synthesized clock CLKS. Synthetic clock CLKS includes a frequency component of 7.5 GHz, a frequency component of 2.5 GHz, a direct current component, and the like. The BPF 54 is a band pass filter that passes a frequency component of 7.5 GHz, and passes a frequency component of 7.5 GHz from the synthesized clock CLKS and outputs a take-in clock CLKO of 7.5 GHz.

FIG. 17 is a diagram for explaining the conversion processing of the code conversion circuit 51 in the third embodiment, and shows an example of a 4-bit digital phase adjustment code.
As shown in FIG. 17A, the digital phase adjustment code before code conversion indicates a phase position (angle) from 0 ° to 360 °, and as shown in FIG. Two bits indicate the position of the quadrant. The 7.5 GHz digital phase adjustment code is converted into a 2.5 GHz digital phase adjustment code indicating a phase position of 0 ° to 120 ° as shown in FIG. Therefore, the phase position indicated by the digital phase adjustment code for 2.5 GHz is limited to the first quadrant and the second quadrant from 0 ° to 120 °.

  FIG. 18 is a diagram illustrating a code conversion table included in the code conversion circuit 31 according to the third embodiment. 18A shows a 7.5-GHz 4-bit digital phase adjustment code before conversion, and FIG. 18B shows a 2.5-GHz 4-bit digital phase adjustment code after conversion. In the third embodiment, the converted digital phase adjustment code has a code value from 0 to 11 in the first quadrant and a code value from 12 to 15 in the second quadrant.

  Also in the third embodiment, since the phase adjustment is performed only in the first and second quadrants, the set of VIT0 and VIT1 or the set of VIT1 and VIT2 in FIG. 8 is used, and VIT3 is not used. Also in the third embodiment, a single-phase mixer amplifier may be used. If only a single-phase clock is required as the capture clock CLKO, the reference clock CLKI270 is not used. Since other description is the same as that of the second embodiment, a description thereof will be omitted.

FIG. 19 is a block diagram showing the configuration of the phase adjustment circuit of the fourth embodiment.
The phase adjustment circuit according to the fourth embodiment includes a code conversion circuit 61, a reference phase adjustment circuit 62, a mixing circuit 63, and a band pass filter 64.

  The phase adjustment circuit according to the fourth embodiment generates a capture clock CLKO having a frequency four times that of the reference clock CLKI. For example, the frequency of the reference clock CLKI is 2.5 GHz, and the frequency of the capture clock CLKO is 10 GHz. The code conversion circuit 61 converts an acquisition phase adjustment code indicating a phase shift amount with respect to an input data signal of the 10 GHz acquisition clock CLKO into a reference adjustment phase adjustment code for 2.5 GHz. The reference phase adjustment circuit 62 performs phase adjustment using a 2.5 GHz multiphase reference clock CLKI and a 2.5 GHz reference clock phase adjustment code, and generates a 2.5 GHz adjusted clock CLKT. The mixing circuit 63 mixes the adjusted clock CLKT of 2.5 GHz and the reference clock CLKR of 7.5 GHz to generate a synthesized clock CLKS. Synthetic clock CLKS includes a frequency component of 10 GHz, a frequency component of 5 GHz, 2.5 GHz, a direct current component, and the like. The BPF 64 is a bandpass filter that passes a frequency component of 10 GHz, and passes a frequency component of 10 GHz from the synthesized clock CLKS and outputs a 10 GHz acquisition clock CLKO.

FIG. 20 is a diagram for explaining the conversion processing of the code conversion circuit 61 in the fourth embodiment, and shows an example of a 4-bit digital phase adjustment code.
As shown in FIG. 20A, the digital phase adjustment code before code conversion indicates a phase position (angle) from 0 ° to 360 °, and as shown in FIG. Two bits indicate the position of the quadrant. The digital phase adjustment code for 10 GHz is converted into a digital phase adjustment code for 2.5 GHz indicating a phase position from 0 ° to 90 °, as shown in FIG. Accordingly, the phase position indicated by the digital phase adjustment code for 2.5 GHz is limited to the first quadrant from 0 ° to 90 °.

  FIG. 21 is a diagram illustrating a code conversion table included in the code conversion circuit 61 according to the fourth embodiment. 21A shows a 10-GHz 4-bit digital phase adjustment code before conversion, and FIG. 21B shows a 2.5-GHz 4-bit digital phase adjustment code after conversion. In the fourth embodiment, the converted digital phase adjustment code is only in the first quadrant. Four bits are used to indicate the phase position within the first quadrant.

  In the fourth embodiment, since the phase adjustment is performed only in the first quadrant, only the set of VIT0 and VIT1 in FIG. 8 is used, and VIT2 and VIT3 are not used. In the fourth embodiment, a single-phase mixer amplifier may be used. If only a single-phase clock is required as the capture clock CLKO, the reference clocks CLK180 and CLKI270 are not used. Since other description is the same as that of the second embodiment, a description thereof will be omitted.

FIG. 22 is a block diagram showing the configuration of the phase adjustment circuit of the fifth embodiment.
The phase adjustment circuit of the fifth embodiment includes a code conversion circuit 71, a reference phase adjustment circuit 72, a mixing circuit 73, and a band pass filter 74.

  The phase adjustment circuit according to the fifth embodiment generates the capture clock CLKO having a frequency that is ¼ times the reference clock CLKI. For example, the frequency of the reference clock CLKI is 2.5 GHz, and the frequency of the capture clock CLKO is 625 MHz. The code conversion circuit 71 converts the acquisition phase adjustment code indicating the phase shift amount with respect to the input data signal of the 625 MHz acquisition clock CLKO into a reference clock phase adjustment code for 2.5 GHz. The reference phase adjustment circuit 72 performs phase adjustment using a 2.5 GHz multiphase reference clock CLKI and a 2.5 GHz reference clock phase adjustment code, and generates a 2.5 GHz adjusted clock CLKT. The mixing circuit 73 mixes the adjusted clock CLKT of 2.5 GHz and the reference clock CLKR of 2 GHz to generate a synthesized clock CLKS. Synthetic clock CLKS includes frequency components such as 4.5 GHz, 2.5 GHz, and 625 MHz, a DC component, and the like. The BPF 74 is a band-pass filter that passes a frequency component of 625 MHz, and passes a frequency component of 625 MHz from the synthesized clock CLKS and outputs a 625 MHz acquisition clock CLKO.

FIG. 23 is a diagram for explaining the conversion processing of the code conversion circuit 71 in the fifth embodiment, and shows an example of a 4-bit digital phase adjustment code.
As shown in FIG. 23A, the digital phase adjustment code before code conversion indicates a phase position (angle) from 0 ° to 360 °. This digital phase adjustment code for 625 MHz is converted into a digital phase adjustment code for 2.5 GHz that indicates angular positions in the range of 0 ° to 1440 ° at coarse intervals of 90 °. However, among the phase positions indicated by the digital phase adjustment code for 2.5 GHz, the angle positions from 360 ° to 1440 ° correspond to CLKI from 0 ° to 360 ° shown in FIG. The prepared digital phase adjustment code may be prepared.

  FIG. 24 is a diagram illustrating a code conversion table included in the code conversion circuit 71 according to the fifth embodiment. 24A shows a 625 MHz 4-bit digital phase adjustment code before conversion, and FIG. 24B shows a 2.5 GHz 4-bit digital phase adjustment code after conversion. In the fifth embodiment, the converted digital phase adjustment code indicates the phase position at coarse intervals of 90 °, and the same pattern is repeated four times. Since other description is the same as that of the second embodiment, a description thereof will be omitted.

In the second embodiment to the fifth embodiment, the code conversion circuit is realized by using the code conversion table, but may be realized by a gate circuit.
FIG. 25 is a circuit diagram in the case where the code conversion circuit 71 of the fifth embodiment is realized by a gate circuit. The 4 bits of the 625 MHz digital phase adjustment code before conversion in FIG. 24A are A, B, C, and D in order from the upper bits, and the 2.5 GHz digital phase adjustment after conversion in FIG. The two bits of the code are X and Y in order from the upper bit. The code conversion circuit 71 shown in FIG. 25 receives the above A, B, C, and D, outputs X and Y, and performs the conversion shown in FIG. Since the circuit of FIG. 25 is a gate circuit, description thereof is omitted.

FIG. 26 is a block diagram showing the configuration of the phase adjustment circuit of the sixth embodiment.
In the phase adjustment circuit of the sixth embodiment, the code conversion circuit and the band pass filter are switched by the control signal, and the frequency of the reference clock supplied to the reference phase adjustment circuit and the reference clock supplied to the mixing circuit is switched. It is.

  The phase adjustment circuit according to the sixth embodiment includes a code conversion unit, a reference phase adjustment unit, a mixing unit, and a band pass filter unit.

  The code conversion unit includes three code conversion circuits (CTA-CTC) 81A-81C, a selector 85, and a selector 86. The selector 85 receives the digital phase adjustment code before conversion, and selects which of the three code conversion circuits 81A-81C is to input according to the control signal. The three code conversion circuits 81A-81C convert the input digital phase adjustment code before conversion into a digital phase adjustment code corresponding to the clock frequency when the reference phase adjustment circuit 82 performs phase adjustment. The code conversion circuit 81A-81C is a digital phase adjustment code of 2.5 GHz, for example, a digital phase adjustment code of 5 GHz, 7.5 GHz, or 10 GHz corresponding to three types of acquisition clocks with different digital phase adjustment codes before conversion. Convert to code. In other words, the code conversion circuits 81A-81C are, for example, the code conversion circuits 31, 51, and 61 of the second to fourth embodiments. The selector 86 selects the converted digital phase adjustment code output from any of the three code conversion circuits 81A-81C in accordance with the control signal, and outputs it to the reference phase adjustment circuit 82.

  The reference phase adjustment unit includes a reference phase adjustment circuit 82 and a selector 87. The reference phase adjustment circuit 82 is realized by the reference phase adjustment circuits 22, 32, 52, 62, and 72 described in the first to fifth embodiments. The selector 87 receives the four-phase reference clock CLKI, selects a reference clock having a phase to be used by the reference phase adjustment circuit 82 according to the control signal, and outputs the selected reference clock to the reference phase adjustment circuit 82. The frequency of the reference clock is fixed. As shown in FIG. 9, the selector 87 is not provided when the reference phase adjustment circuit 82 outputs the four-phase adjusted clock CLKT or outputs the differential adjusted clock CLKT.

  The mixing unit includes a mixing circuit 83 and a selector 88. The mixing circuit 83 is realized by, for example, a circuit used in the second to fifth embodiments shown in FIGS. 11 to 13. The selector 88 selects any one of the reference clocks CLKR having three different frequencies (f0, f1, and f3) and outputs the selected clock to the mixing circuit 83. Three different frequencies (f0, f1, f3) of the reference clock CLKR are set corresponding to the frequency of the fetch clock, and also correspond to the three code conversion circuits 81A-81C. For example, if the frequency of the reference clock for phase adjustment is 2.5 GHz and the acquisition clock is changed to 5 GHz, 7.5 GHz, and 10 GHz, three different frequencies (f0, f1, and f3) are 2.5 GHz, 5 GHz and 7.5 GHz.

  The band pass filter unit includes three band pass filters (BPFA-BPFC) 84A-84C, a selector 89, and a selector 90. The selector 89 receives the output of the mixing circuit 83 and selects which of the three band-pass filters 84A to 84C is input in accordance with the control signal. The characteristics of the three band-pass filters 84A to 84C are set corresponding to the frequency of the acquisition clock. If the acquisition clock is changed to 5 GHz, 7.5 GHz, and 10 GHz, 5 GHz and 7. Narrow band pass characteristics centered on 5 GHz and 10 GHz. The selector 90 selects one of the outputs of the three band pass filters 84A to 84C in accordance with the control signal, and outputs the selected clock CLKO.

  As described above, in the phase adjustment circuit of the sixth embodiment, the acquisition clock CLKO changes to a different frequency according to the control signal, but the phase adjustment in the reference phase adjustment circuit 82 is performed with the reference clock having a constant frequency. To do. For example, in the phase adjustment circuit of the sixth embodiment, the phase adjustment is performed only with the reference clock of 2.5 GHz, and the frequency of the acquisition clock is changed from 5 GHz, 7.5 GHz, and 10 GHz shown in the second to fourth embodiments. it can. Note that the frequency of the acquisition clock can be set to another frequency, and phase adjustment can be performed using a reference clock having another frequency. In any case, since the phase adjustment in the reference phase adjustment circuit 82 is performed with a reference clock having a constant frequency, the linearity of the phase adjustment does not change.

  FIG. 27 shows the reception circuit shown in FIG. 1 having the phase adjustment circuit of the sixth embodiment as the phase adjustment circuit 15, sets the frequency of the acquisition clock according to the input data signal, performs the phase adjustment, and receives the signal. It is a flowchart which shows the setting operation | movement which enables it to perform.

In step S11, the conversion ratio of the frequency conversion circuit (mixing circuit and bandpass filter) is determined.
In step S12, the code conversion circuit and the band pass filter corresponding to the determined conversion ratio are selected, and control signals are sent to the selectors 85, 86, 88, 89 and 90 so as to select the reference clock to be supplied to the mixing circuit 83. Send.

  In step S13, the digital phase adjustment code after code conversion, the pass frequency characteristic of the band pass filter, and the frequency of the reference clock CLKR supplied to the mixing circuit 83 are set.

  In step S14, the receiving circuit receives the test signal and extracts the transmission clock CLK from the input data signal.

  In step S15, time management is performed so that the phase adjustment is repeated for a predetermined time until the digital CDR 14 becomes stable and can perform a reception operation in which the phase of the fetch clock CLKO is good. As a result, the input data signal is normally received.

  In step S16, the process proceeds to a normal operation for receiving an input data signal.

FIG. 28 is a block diagram showing the configuration of the phase adjustment circuit of the seventh embodiment.
The phase adjustment circuit according to the eighth embodiment includes a code conversion circuit 91, a reference phase adjustment circuit 92, a selector 94, and a PLL circuit 93. The code conversion circuit 91 and the reference phase adjustment circuit 92 are realized by any one of the first to fifth embodiments. The selector 94 is realized in the same manner as the selector 87 of the sixth embodiment, and selects a reference clock having a phase to be used in the reference phase adjustment circuit 92 from the four-phase reference clock CLKI according to the control signal. Output to the adjustment circuit 92.

  The PLL circuit 93 operates so as to be phase-synchronized with the adjusted clock CLKT having the frequency f0 output from the reference phase adjusting circuit 92, and outputs the take-in clock CLKO having the frequency N × f0 having the multiplication ratio N of the frequency f0. The multiplication ratio N of the PLL circuit 93 can be set by a multiplication ratio adjustment signal among the control signals.

  In the phase adjustment circuit of the seventh embodiment, by switching the multiplication ratio of the PLL circuit 93, a plurality of capture clocks CLKO having different frequencies are output without changing the clock frequency of the phase adjustment in the reference phase adjustment circuit 92. . Since the clock frequency for phase adjustment in the reference phase adjustment circuit 92 does not change, the linearity of phase adjustment does not change.

  The phase adjustment circuit of the seventh embodiment, like the phase adjustment circuit of the sixth embodiment, is used in the receiving circuit of FIG. 1 according to the input data signal according to the flowchart of FIG. You can set the frequency and adjust the phase to enable reception.

  Although the embodiment has been described above, it goes without saying that there can be various modifications. For example, the illustrated circuit is an example, and can be replaced with a circuit having a similar function. The illustrated clock frequency is an example, and any frequency may be used.

  The embodiment has been described above, but all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and technology. In particular, the examples and conditions described are not intended to limit the scope of the invention, and the construction of such examples in the specification does not indicate the advantages and disadvantages of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

11 equalization circuit 12 determination circuit 13 demultiplexing circuit 14 digital CDR
15 Phase adjustment circuit 21, 31 Code conversion circuit 22, 32 Reference phase adjustment circuit 23 Frequency conversion circuit 33 Mixing circuit 34 Band pass filter (BPF)

Claims (8)

A clock phase adjustment circuit that adjusts the phase of the capture clock in order to capture an input data signal with a capture clock having a frequency N (N = integer or N = 1 / integer) times the frequency of the reference clock. And
A code conversion circuit that converts a capture phase adjustment code indicating a phase shift amount of the captured input data signal with the capture clock into a reference clock phase adjustment code according to a conversion table;
A reference phase adjustment circuit that mixes the reference clock and the phase adjustment code for the reference clock, adjusts the phase of the reference clock according to the phase shift amount, and outputs an adjusted clock;
And a frequency conversion circuit for converting the adjusted clock into the fetch clock having the N times frequency. The frequency conversion circuit is a conversion mixing circuit that mixes the adjusted clock and a reference clock to output a conversion signal including a signal having the N times frequency, and
The clock phase adjustment circuit according to claim 1, further comprising: a filter circuit that passes the N times the frequency component of the output signal of the conversion mixing circuit.   2. The clock phase adjustment circuit according to claim 1, wherein the frequency conversion circuit includes a PLL circuit having a multiplication ratio N using the adjusted clock as a reference clock. The code conversion circuit includes a plurality of conversion tables for acquisition clocks having a plurality of different multiples of the frequency of the reference clock;
4. The clock phase adjustment circuit according to claim 1, further comprising: a table selection circuit that selects one of the plurality of conversion tables according to a frequency of the fetch clock. 5. The filter circuit includes a plurality of filters that pass a plurality of different multiple frequency components, and
The clock phase adjustment circuit according to claim 2, further comprising: a filter selection circuit that selects any of the plurality of filters according to a frequency of the fetch clock. Reference clocks of different frequencies are supplied from the outside,
3. The clock phase adjustment circuit according to claim 2, wherein the conversion mixing circuit includes a reference selection circuit that selects one reference clock from the plurality of reference clocks. The reference phase adjustment circuit is supplied with a plurality of phase shift reference clocks having different phases from the outside as the reference clock,
7. The clock phase according to claim 1, wherein the reference phase adjustment circuit includes a phase shift selection circuit that selects a phase shift reference clock to be used from the plurality of phase shift reference clocks. Adjustment circuit. A determination circuit that captures an input data signal with a capture clock having a predetermined frequency relative to the frequency of the reference clock;
A demultiplexing circuit that converts the output of the determination circuit, which is serial data, into parallel data and performs speed conversion;
A digital CDR circuit that detects phase information of a data signal from an output of the demultiplexing circuit and generates a capture phase adjustment code;
A phase adjustment circuit that adjusts the phase of the clock CLK by a take-in phase adjustment code generated by a digital CDR circuit;
The phase adjustment circuit includes:
A code conversion circuit that converts the acquisition phase adjustment code into a reference clock phase adjustment code according to the conversion table;
A reference phase adjustment circuit that mixes the reference clock and the phase adjustment code for the reference clock, adjusts the phase of the reference clock according to the phase shift amount, and outputs an adjusted clock;
And a frequency conversion circuit for converting the adjusted clock into the fetch clock having the predetermined frequency.

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