JP2005026760A - Timing signal generating circuit and signal receiving circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a timing signal generating circuit capable of highly accurately generating a plurality of timing signals having a predetermined phase difference with a simple configuration, and a signal receiving circuit provided with the timing signal generating circuit. <P>SOLUTION: A resistor value control unit 24 outputs a resistance control signal for controlling weight of composite for each of signals in phase-compositing a plurality of clock signals Va, Vax, Vb, Vbx having a plurality of kinds of phases. Upon receiving the plurality of clock signals respectively, transconductance amplifiers 22a-22d output a plurality of current outputs I1-I4 whose amplitudes are controlled by allowing resistors R1-R4 to change the resistances according to the resistance control signals. An output terminal OUT connected to the outputs OUT1 of the plurality of transconductance amplifiers 22a-22d sums the current outputs I1-I4 outputted from the transconductance amplifiers 22a-22d to output a phase-composited signal. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

これにより、出力電流Ｉ１、Ｉ１ｘ（＝トランジスタＴｒ２１、Ｔｒ２２に流れる電流）は、以下の式で表される。
Ｉ１ ＝Ｉ０＋Ｉｒ＝Ｉ０＋（Ｖａ−Ｖａｘ）／Ｒ１
Ｉ１ｘ＝Ｉ０−Ｉｒ＝Ｉ０−（Ｖａ−Ｖａｘ）／Ｒ１
【００４０】
以上に示すように、出力電流Ｉ１、Ｉ１ｘは、トランジスタＴｒ２１、Ｔｒ２２のソース端子間を結ぶ抵抗Ｒ１の値によって定まる値である。すなわち、従来技術のように差動アンプを用いた場合に見られたトランジスタの非線形動作を考慮する必要がなく、基準クロックであるクロック信号（Ｖａ、Ｖａｘ、Ｖｂ、Ｖｂｘ）の位相を出力に正確に伝えることができる。また、以上の特徴は、アンプ２２ａのみならず、アンプ２２ｂ〜２２ｄにおいても同様である。
【００４１】
次に、以上に示したアンプ２２ａ〜２２ｄの出力電流Ｉ１〜Ｉ４を足し合わせた図１における抵抗素子２１に流れる電流Ｉｏを求める。
まず、上述した式と、Ｖａ、Ｖａｘは差動関係にあるためＶａ＝−Ｖａｘとし、Ｖｂ、Ｖｂｘも同様に差動関係にあるのでＶｂ＝−Ｖｂｘとすると、アンプ２２ａ〜２２ｄの出力電流Ｉ１〜Ｉ４が以下の式で求まる。
Ｉ１＝Ｉ０＋（Ｖａ−Ｖａｘ）／Ｒ１＝Ｉ０＋２×Ｖａ／Ｒ１
Ｉ２＝Ｉ０＋（Ｖａｘ−Ｖａ）／Ｒ２＝Ｉ０＋２×Ｖａｘ／Ｒ２
Ｉ３＝Ｉ０＋（Ｖｂ−Ｖｂｘ）／Ｒ３＝Ｉ０＋２×Ｖｂ／Ｒ３
Ｉ４＝Ｉ０＋（Ｖｂｘ−Ｖｂ）／Ｒ４＝Ｉ０＋２×Ｖｂｘ／Ｒ４
【００４２】
ここで、出力端子ＯＵＴに電圧を出力するための抵抗素子２１に流れる電流ＩｏはＩ１〜Ｉ４の総和であるので、以下の式となる。

以上より本実施形態のタイミング信号発生回路によれば、クロック信号の位相合成の結果は、入力されるクロック信号の電圧値と可変抵抗値によってのみ決定されるので、高精度の位相合成が可能である。
【００４３】
ここで、図１における可変抵抗の実現例を示す。
図３は、図１に示したタイミング信号発生回路における抵抗Ｒ１〜Ｒ４の実現例を含むタイミング信号発生回路を示す図である。図３に示すように、図１の抵抗Ｒ１〜Ｒ４を、複数個の抵抗素子ｒ１〜ｒｎ及び複数個のスイッチＳＷ１〜ＳＷｎ（ｎは任意の自然数）で構成したものである。各抵抗Ｒ１〜Ｒ４において、抵抗素子ｒ１およびスイッチＳＷ１を介してトランジスタＴｒ２１、Ｔｒ２２のソース端子間が接続されている。同様に、抵抗素子ｒ１とスイッチＳＷ１に並列に抵抗素子ｒ２とスイッチＳＷ２、抵抗素子ｒ３とスイッチＳＷ３、…、抵抗素子ｒｎとスイッチＳＷｎが接続されている。
【００４４】
尚、抵抗素子ｒ１〜ｒｎは、全て同じ抵抗値であっても良く、全て違う抵抗値であってもよい。また、抵抗値制御部２４は、各アンプ２２ａ〜２２ｄに接続されているスイッチＳＷ１〜ＳＷｎの内の少なくとも１つはオンするように制御する。また、抵抗値制御部２４は、各アンプ２２ａ〜２２ｄに接続されているスイッチＳＷ１〜ＳＷｎをオンすることで定まる抵抗値の合計が一定になるように制御することで、出力信号の振幅を一定に保つことができる。
【００４５】
図３において、例えば抵抗Ｒ１におけるスイッチＳＷ１〜ＳＷｎがオンしている個数が多ければ、抵抗Ｒ１の抵抗値が低下するため、クロック信号Ｖａの変化に応じた電流Ｉ１の変化量（振幅）が増大する。すなわち、電流Ｉ１の変化が出力電流Ｉｏの変化へ影響する割合が増大する。また、逆に抵抗Ｒ１においてスイッチＳＷ１〜ＳＷｎのオンしている個数が少なければ、抵抗Ｒ１の抵抗値が増加するため、クロック信号Ｖａの変化に応じた電流Ｉ１の変化量（振幅）が減少する。すなわち、電流Ｉ１の変化が出力電流Ｉｏの変化へ影響する割合が低下する。
【００４６】
以上に示すように、抵抗値制御部２４が抵抗Ｒ１〜Ｒ４の抵抗値を変えることで、電流Ｉ１〜Ｉ４のいずれかに重みを付けて出力電流Ｉｏに足し合わせることができる。すなわち、抵抗値制御部２４は、抵抗Ｒ１〜Ｒ４の抵抗値を変えることで位相合成用の位相の異なる４種類の出力電流Ｉ１〜Ｉ４の振幅を制御して任意の位相の出力電流Ｉｏが合成されるように制御することができる。
【００４７】
次に、本発明の第２の実施形態として、図１に示した抵抗Ｒ１〜Ｒ４の部分に、同様の機能を有するトランジスタ回路を用いた構成のタイミング信号発生回路について説明する。図４は、本発明の第２の実施形態におけるタイミング信号発生回路の回路構成例を示す図である。図４に示すトランスコンダクタンス・アンプ３１ａ〜３１ｄ（以下、アンプ３１ａ〜３１ｄとする）は、図１に示したトランスコンダクタンス・アンプ（アンプ２２ａ〜２２ｄ）の抵抗Ｒ１〜Ｒ４部分が、トランジスタＴｒ２３、Ｔｒ２４（ｎ型ＭＯＳＦＥＴ）を含むトランジスタ回路で構成されている。また、ＤＡＣ３２は、電流出力型のデジタル／アナログ−コンバータであり、制御信号に応じてアンプ３１ａ〜３１ｄに重み付けに応じた電流値の電流を供給する。尚、図４において図１と同じ符号を付与しているものは同じ機能を有するものであり、説明を省略する。
【００４８】
また、アンプ３１ａ〜３１ｄにおいて、トランジスタＴｒ２３のドレイン端子およびソース端子は、トランジスタＴｒ２１およびトランジスタＴｒ２２のソース端子に接続される。また、トランジスタＴｒ２３のゲート端子は、トランジスタＴｒ２４のドレイン端子およびゲート端子と、ＤＡＣ３２の出力端子に接続されている。また、トランジスタＴｒ２４のソース端子はグランドに接続される。
【００４９】
次に、上述したタイミング信号発生回路の動作について説明する。まず、ＤＡＣ３２の出力電流に応じた電圧をトランジスタＴｒ２４が生成し、トランジスタＴｒ２３のゲート端子にその電圧が印加される。これにより、トランジスタＴｒ２３がゲート端子に印加される電圧に応じて抵抗値が変化する可変抵抗として動作させる事ができる。すなわち、ＤＡＣ３２は、アンプ３１ａ〜３１ｄのトランジスタＴｒ２３にそれぞれ重み付けした電流値の電流を出力することで、トランジスタＴｒ２３のオン抵抗値を制御することができる。これにより、アンプ３１ａ〜３１ｄの出力する電流Ｉ１〜Ｉ４は、重み付けに応じた振幅となる。
【００５０】
以上より、ＤＡＣ３２から出力する電流量を多くすると、トランジスタＴｒ２４で発生する電圧が高くなり、トランジスタＴｒ２３のドレイン端子−ソース端子間の抵抗値が低下する。また、ＤＡＣ３２から出力する電流量を少なくすると、トランジスタＴｒ２４の電圧が低くなり、トランジスタＴｒ２３のドレイン端子−ソース端子間の抵抗値が高くなる。この時、トランジスタＴｒ２３においてオン抵抗値がゲート端子に印加される電圧の変化に対して線形的に変化する部分を利用することで、制度の良い制御を行なうことができる。
【００５１】
以上に示したように、ＤＡＣ３２アンプが重み付けした出力電流を出力することにより位相合成用の位相の異なる４種類の出力電流Ｉ１〜Ｉ４の振幅を制御して、任意の位相の出力電流Ｉｏが合成されるように制御することができる。
【００５２】
次に、本発明の第３の実施形態として、複数のトランスコンダクタンス・アンプの出力経路をスイッチで切換えて足し合わせることで、位相合成を実現する構成のタイミング信号発生回路について説明する。図５および図６は、本発明の第３の実施形態におけるタイミング信号発生回路の回路構成例を示す図である。図５は、クロック信号Ｖａ、Ｖａｘの位相合成の処理を、図６は、クロック信号Ｖｂ、Ｖｂｘの位相合成の処理を主に行う回路であり、位相合成の原理は同様である。また、図５には、クロック信号Ｖａ、Ｖａｘを位相合成した信号とクロック信号Ｖｂ、Ｖｂｘを位相合成した信号を足し合わせる回路構成も含む。尚、図５および図６において、図１と同じ符号を付与したものは、同じ機能を有するものなので、説明を省略する。
【００５３】
図５に示すように、トランスコンダクタンス・アンプａ１、ａ２、…、ａｎ（以下、アンプａ１〜ａｎとする）は、トランジスタＴｒ２１、Ｔｒ２２および抵抗素子Ｒより構成される。ここで、ｎは１から始まる任意の自然数である。尚、アンプａ１〜ａｎのトランジスタＴｒ２１、Ｔｒ２２と抵抗素子Ｒの接続関係や入力信号および電流源２３との接続関係は、図１に示したアンプ２２ａ〜２２ｄと同様なので説明を省略する。
【００５４】
また、アンプａ１〜ａｎの出力電流Ｉ１〜Ｉｎは、スイッチＳ１、Ｓ２、…、Ｓｎを介して足し合わされて出力電流Ｉｏａとなる。同様に図６の回路においてアンプｂ１〜ｂｎの出力電流Ｊ１〜Ｊｎは、スイッチＷ１〜Ｗｎを介して足し合わされて出力電流Ｉｏｂとなる。この出力電流Ｉｏａと出力電流Ｉｏｂが足し合わされて出力電流Ｉｏとなり、抵抗素子２１で電圧に変換されて出力端子ＯＵＴより出力される。
【００５５】
次に、スイッチＳ１〜Ｓｎの構成について説明する。スイッチＳ１〜Ｓｎは、電流ルート（経路）切換えスイッチであり、トランジスタＴｒ１０〜Ｔｒ１３およびインバータ４１より構成される。各スイッチＳ１〜ＳｎのトランジスタＴｒ１０およびトランジスタＴｒ１１のドレイン端子は、出力端子ＯＵＴに接続される。各スイッチＳ１〜ＳｎのトランジスタＴｒ１２およびトランジスタＴｒ１３のドレイン端子は、出力端子ＯＵＴＸに接続される。各スイッチＳ１〜ＳｎのトランジスタＴｒ１０およびトランジスタＴｒ１２のソース端子は、アンプａ１〜ａｎのトランジスタＴｒ２１のドレイン端子にそれぞれ接続される。各スイッチＳ１〜ＳｎのトランジスタＴｒ１１およびトランジスタＴｒ１３のソース端子は、アンプａ１〜ａｎのトランジスタＴｒ２２のドレイン端子にそれぞれ接続される。また、各スイッチＳ１〜Ｓｎは、スイッチ制御回路４２が出力する電流ルート切換え信号ＲＴＡ１〜ＲＴＡｎが入力される入力端子ＲＴＡ１〜ＲＴＡｎを備える。この入力端子ＲＴＡ１〜ＲＴＡｎは、各スイッチＳ１〜ＳｎのトランジスタＴｒ１１およびトランジスタＴｒ１２のゲート端子に接続される。また、入力端子ＲＴＡ１〜ＲＴＡｎは、各スイッチＳ１〜ＳｎのトランジスタＴｒ１０およびトランジスタＴｒ１３のゲート端子にインバータ４１を介して接続される。
【００５６】
また、スイッチ制御回路４２は、例えば図１０に示した位相比較回路１４より受信する制御信号ＳＥを基に、電流ルート切換え信号ＲＴＡ１〜ＲＴＡｎおよび電流ルート切換え信号ＲＴＢ１〜ＲＴＢｎを生成して出力する。尚、図６のスイッチＷ１〜Ｗｎは、入力端子ＲＴＢ１〜ＲＴＢｎを備え接続先がアンプｂ１〜ｂｎであること以外は図５のスイッチＳ１〜Ｓｎと同様の構成であり、説明を省略する。また、図６のアンプｂ１〜ｂｎは、図５に示したアンプａ１〜ａｎと同様の構成なので説明を省略する。
【００５７】
ここで、図５に示す回路を用いて本実施形態における位相合成の原理およびスイッチ制御回路４２での制御方法について説明する。まず、電流ルート切換え端子ＲＴＡ１に繋がるアンプａ１の動作について説明する。例えば、スイッチ制御回路４２が電流ルート切換え端子ＲＴＡ１を“Ｌ（ロウ）レベル”にすると、トランジスタＴｒ１０、Ｔｒ１３がオンしてトランジスタＴｒ１１、Ｔｒ１２はオフする。これにより、アンプａ１は、トランジスタＴｒ２１のゲート端子に入力されるクロック信号Ｖａと同位相の電流Ｉ１を、スイッチＳ１を介して出力端子ＯＵＴへ出力する。
【００５８】
また、例えば、スイッチ制御回路４２が電流ルート切換え端子ＲＴＡ１を“Ｈ（ハイ）レベル”にすると、トランジスタＴｒ１０、Ｔｒ１３がオフして、トランジスタＴｒ１１、Ｔｒ１２がオンする。これにより、アンプａ１は、トランジスタＴｒ２２のゲート端子に入力されるクロック信号Ｖａｘと同位相の電流Ｉ１ｘを、スイッチＳ１を介して出力端子ＯＵＴへ出力する。以上に示すように、スイッチ制御回路４２の制御によりアンプａ１〜ａｎよりクロック信号Ｖａと同位相の電流Ｉ１〜Ｉｎまたはクロック信号Ｖａｘと同位相の電流Ｉ１ｘ〜Ｉｎｘのいずれかを選択して出力端子ＯＵＴおよび出力端子ＯＵＴＸへ出力することができる。
【００５９】
次に、図５および図６に示したアンプａ１〜ａｎおよびアンプｂ１〜ｂｎ全体としての動作を説明する。
例えば、スイッチ制御回路４２が、全ての電流ルート切換え信号ＲＴＡ１〜ＲＴＡｎおよびＲＴＢ１〜ＲＴＢｎを“Ｌ（ロウ）”にした場合、アンプａ１〜ａｎおよびアンプｂ１〜ｂｎの出力電流を足し合わせた、出力端子ＯＵＴに見える電流変化ΔＩｏｕｔは以下の式となる。

【００６０】
以上より、出力端子ＯＵＴより出力される信号の電流変化はクロック信号Ｖａとクロック信号Ｖｂに対して同一の重みで足し合わせた位相となる。すなわち、出力端子ＯＵＴより、クロック信号Ｖａの位相とクロック信号Ｖｂの位相の中間に位置する位相の出力が得られる。
【００６１】
また、例えば、スイッチ制御回路４２が、電流ルート切換え信号ＲＴＡ１〜ＲＴＡｎを全て“Ｌ”、ＲＴＢ１〜ＲＴＢｎのうち半分を“Ｌ”、残り半分を“Ｈ（ハイ）”とした場合、アンプａ１〜ａｎおよびアンプｂ１〜ｂｎの出力電流を足し合わせた、出力端子ＯＵＴより出力される電流変化ΔＩｏｕｔは以下の式となる。

すなわち、出力端子ＯＵＴより出力される信号の電流変化はクロック信号Ｖａと同じ位相の出力が得られる。
【００６２】
以上に示したように、本実施形態におけるタイミング信号発生回路は、スイッチ制御回路４２が出力する電流ルート切換え信号で“Ｌ”と“Ｈ”を設定する組み合わせにより、クロック信号Ｖａ、Ｖａｘ、Ｖｂ、Ｖｂｘに応じた電流を足し合わせて任意の位相に合成して出力することができる。
【００６３】
尚、上述した第３の実施形態においては、スイッチ制御回路４２は、電流ルート切換え信号ＲＴＡ１〜ＲＴＡｎおよびＲＴＢ１〜ＲＴＢｎの内、“Ｈ”とする数を一定に制御する。すなわち、スイッチＳ１〜ＳｎおよびスイッチＷ１〜Ｗｎの内、オンする数を一定に制御することで、一定の振幅となる出力信号を出力端子ＯＵＴより出力することができる。
【００６４】
次に、本発明の第４の実施形態として、可変抵抗を備える２つのトランスコンダクタンス・アンプの出力経路をスイッチで切換えて足し合わせることで、位相合成を実現する構成のタイミング信号発生回路について説明する。図７は、本発明の第４の実施形態におけるタイミング信号発生回路の回路構成例を示す図である。図７に示すように、可変抵抗を含むトランスコンダクタンス・アンプＡ、Ｂ（以下、アンプＡ、Ｂとする）の出力側にそれぞれ電流ルート切換えスイッチＳＡ、ＳＢが接続されている。また、制御部５１は、例えば図１０に示した位相比較回路１４より受信する制御信号ＳＥを基に、電流ルート切換え信号ＲＴＡ、ＲＴＢおよび抵抗ＲＡ、ＲＢの抵抗値制御信号を生成して出力する。
【００６５】
尚、アンプＡ、Ｂの構成は、図１に示したアンプ２２ａと同様であり、スイッチＳＡ、ＳＢの構成は、図６に示したスイッチＳ１と同様であるので説明を省略する。また、アンプＡとスイッチＳＡと出力端子ＯＵＴ、ＯＵＴＸの接続関係も図６に示したアンプａ１とスイッチＳ１と出力端子ＯＵＴ、ＯＵＴＸの接続関係と同様であるので説明を省略する。
【００６６】
ここで、出力端子ＯＵＴにおける出力信号の電流値の変化は、電流ルート切換え信号ＲＴＡ、ＲＴＢの組み合わせで以下の様に示せる。
（１）ＲＴＡ＝Ｌ、ＲＴＢ＝Ｌ

（２）ＲＴＡ＝Ｌ、ＲＴＢ＝Ｈ

（３）ＲＴＡ＝Ｈ、ＲＴＢ＝Ｈ

（４）ＲＴＡ＝Ｈ、ＲＴＢ＝Ｌ

【００６７】
図８は、上述した電流ルート切換え信号ＲＴＡ、ＲＴＢの４パターンの組み合わせ（１）〜（４）に応じて定まる位相関係ｇ１〜ｇ４を示す図である。すなわち、電流ルート切換え信号ＲＴＡ、ＲＴＢの組み合わせ（１）〜（４）において（１）がクロック信号Ｖａ、Ｖｂの中間位相ｇ１
（２）がクロック信号Ｖａ、Ｖｂｘの中間位相ｇ２
（３）がクロック信号Ｖａｘ、Ｖｂｘの中間位相ｇ３
（４）がクロック信号Ｖａｘ、Ｖｂの中間位相ｇ４
を合成することができることを示している。
【００６８】
以上に示すように、上述した第１〜第３の実施形態と同様、本実施形態のタイミング信号発生回路においても、任意の位相を合成して出力することができる。また、本実施形態の構成にした場合には、他の実施形態と比べても分かるように、タイミング信号発生回路を構成する素子数が少なく、個々の素子が有する寄生容量の影響を低減できるため、高速動作に有利である。
【００６９】
次に、本発明の第５の実施形態として、負帰還により出力のコモンモード電圧（出力変化の中心電圧）を一定にできるタイミング信号発生回路について説明する。図９は、本発明の第５の実施形態におけるタイミング信号発生回路の回路構成例を示す図である。図９に示すように、出力負荷としてトランジスタＴｒ３０、Ｔｒ３１を用い、オペアンプ５１およびコンデンサ５２により負帰還を構成している。トランジスタＴｒ３０、Ｔｒ３１は、ｐ型ＭＯＳＦＥＴであり、ソース端子が電源に接続されている。また、トランジスタＴｒ３０のドレイン端子は、出力端子ＯＵＴおよびオペアンプ５１の入力端子１に接続されている。また、トランジスタＴｒ３１のドレイン端子は、出力端子ＯＵＴＸおよびオペアンプ５１の入力端子２に接続されている。また、オペアンプ５１の出力端子は、トランジスタ３０、３１のゲート端子に接続され、コンデンサ５２を介してグランドにも接続されている。
【００７０】
また、図９において、上述した以外のトランスコンダクタンス・アンプ２２ａ〜２２ｄ等の図１と同じ符号を有する構成は、図１に示したものと同様であるので説明を省略する。すなわち、図１に示した第１の実施形態におけるタイミング信号発生回路の抵抗素子２１の替わりに負帰還回路を設定して、出力のコモンモード電圧を一定にできる構成に変更したものが、本実施形態におけるタイミング信号発生回路である。
【００７１】
オペアンプ５１は、出力端子ＯＵＴに出力される信号と出力端子ＯＵＴＸに出力される信号の差分を増幅した信号を出力し、コンデンサ５２がこれを平坦化する。これにより、トランジスタＴｒ３０、Ｔｒ３１のゲート端子には、オペアンプ５１の出力信号の変化における中心電圧（直流成分）が供給される。すなわち、出力端子ＯＵＴおよび出力端子ＯＵＴＸのコモンモード電圧が増加すると、トランジスタＴｒ３０、Ｔｒ３１のゲート端子へ供給される電圧値も増加して、トランジスタＴｒ３０、Ｔｒ３１を流れる電流が減少する。また、出力端子ＯＵＴおよび出力端子ＯＵＴＸのコモンモード電圧が減少すると、トランジスタＴｒ３０、Ｔｒ３１のゲート端子へ供給される電圧値も減少して、トランジスタＴｒ３０、Ｔｒ３１を流れる電流が増加する。以上に示したように、第５の実施形態に示す負帰還の構成をタイミング信号発生回路に備えることで、出力のコモンモード電圧を安定させることができる。
【００７２】
ここで、出力のコモンモード電圧を安定させる理由を説明する。例えば、上述した第１〜第４の実施形態に示した構成の場合、出力電圧は、電源側に接続した抵抗負荷（抵抗素子２１）により決定する。また、出力端子ＯＵＴにおける電流変化は、可変抵抗値（例えば図１のＲ１〜Ｒ４）または電流ルート切換えスイッチ（例えば図５のスイッチＳ１）によりその振幅が変化する。すなわち、出力電圧振幅も変化する。そのため、位相合成の精度を向上させるためには、出力のコモンモード電圧を安定させる方が有利となる。
また、第５の実施形態で示した手段は、第１の実施形態のみならず第２〜第４の実施形態のどの構成にも適用可能である。
【００７３】
尚、第２〜第５の実施形態に示したタイミング信号発生回路も、第１の実施形態に示したタイミング信号発生回路と同様に、図１０のタイミング信号発生回路１３として、信号受信回路１に組み込まれて好適である。この時、出力端子ＯＵＴ、ＯＵＴＸから出力される２つの信号は、例えば、図１０の信号再生タイミング信号ＯＵＴと変化点検出タイミング信号ＯＵＴＸに対応する。
【００７４】
また、上述した第１の実施形態においては、図１０に示した位相比較回路１４が抵抗値制御部２４へ出力する制御信号ＳＥとして、例えば、抵抗Ｒ１〜Ｒ４の抵抗値を各々制御する複数ビットの抵抗値制御信号を４種類含むものである。また、制御信号ＳＥは上述した限りではなく、位相比較回路１４が位相を進めるまたは遅くする旨を伝達する１ビットの制御信号ＳＥを出力して、抵抗値制御部２４においてこれをデコードして抵抗Ｒ１〜Ｒ４を制御する抵抗値制御信号を生成するなどの構成でもよい。
【００７５】
同様に、第２の実施形態においては、図１０に示した位相比較回路１４がＤＡＣ３２へ出力する制御信号ＳＥは、例えば、ＤＡＣ３２のチャネル数（４チャネル）分の制御信号ＳＥ（例えば各８ビット）である。また、第３の実施形態においては、図１０に示した位相比較回路１４がスイッチ制御回路４２へ出力する制御信号ＳＥは、例えば、オンするスイッチ数を伝達する制御信号ＳＥである。また、第４の実施形態においては、図１０に示した位相比較回路１４が制御部５１へ出力する制御信号ＳＥは、例えば、抵抗ＲＡ、ＲＢの抵抗値を各々制御する複数ビットの抵抗値制御信号と、スイッチＳＡ、ＳＢをオン／オフするスイッチ制御信号とを含む制御信号ＳＥである。
【００７６】
以上、この発明の実施形態について図面を参照して詳述してきたが、具体的な構成はこの実施形態に限られるものではなく、この発明の要旨を逸脱しない範囲の設計等も含まれる。
本発明の実施形態は、例えば以下に示すような種々の適用が可能である。
【００７７】
（付記１） 同一の周波数であって複数種類の位相を有する複数の入力信号を用いて位相合成する際に、各前記入力信号に対する合成の重み付けを制御する制御信号を出力する制御手段と、
複数の前記入力信号をそれぞれ受けて、各前記入力信号と同じ位相であって前記制御手段が出力する前記制御信号に応じて振幅を制御した複数の振幅制御後信号を出力する複数のトランスコンダクタンス・アンプと、
複数の前記トランスコンダクタンス・アンプが出力する複数の前記振幅制御後信号を足し合わせて位相合成したタイミング信号を出力する位相合成手段と
を具備することを特徴とするタイミング信号発生回路。
【００７８】
（付記２） 前記位相合成手段は、複数の前記トランスコンダクタンス・アンプの出力を結線することで前記振幅制御後信号を足し合わせて位相合成した前記タイミング信号を出力する構成であることを特徴とする付記１に記載のタイミング信号発生回路。
【００７９】
（付記３） 前記入力信号として、位相が１８０度異なるものを一組として、複数組が入力される場合に、前記トランスコンダクタンス・アンプは、少なくとも２つのトランジスタと１つの可変抵抗回路と２つの電流源から構成され、前記一組の入力信号は２つの前記トランジスタのゲート端子にそれぞれ入力され、前記抵抗回路は、２つの前記トランジスタのソース端子間に設置され、２つの前記トランジスタのソース端子はそれぞれ２つの前記電流源を介して接地され、前記２つのトランジスタのドレイン端子より位相の１８０度異なる２つの出力電流を前記振幅制御後信号として出力し、
前記制御手段が出力する前記制御信号は、前記トランスコンダクタンス・アンプの有する前記可変抵抗回路の抵抗値を制御する信号であり、
前記位相合成手段は、複数の前記トランスコンダクタ・アンプにおける２つの出力電流を出力する前記ドレイン端子を別々にまとめて結線する構成により、複数の前記トランスコンダクタンス・アンプが出力する２つの前記出力電流を前記振幅制御後信号としてそれぞれ足し合わせて位相合成して位相の１８０度異なる２つの前記タイミング信号を生成する構成であること
を特徴とする付記１に記載のタイミング信号発生回路。
【００８０】
（付記４） 前記可変抵抗回路は、直列に接続した抵抗素子とスイッチを、２つの前記トランジスタのソース端子間に並列に複数接続した構成であり、
前記制御手段が出力する前記制御信号は、前記可変抵抗回路の前記スイッチのオン／オフを制御する信号であること
を特徴とする付記３に記載のタイミング信号発生回路。
【００８１】
（付記５） 前記可変抵抗回路は、抵抗用トランジスタおよび前記抵抗用トランジスタのゲート端子への電圧印加回路により構成され、２つの前記トランジスタのソース端子間を前記抵抗用トランジスタで接続し、前記電圧印加回路は、前記制御手段からの前記制御信号に応じた電圧を前記抵抗用トランジスタのゲート端子に印加することで前記抵抗用トランジスタのオン抵抗値を制御する構成であり、
前記制御手段が出力する前記制御信号は、前記抵抗用トランジスタのオン抵抗値を制御する信号であること
を特徴とする付記３に記載のタイミング信号発生回路。
【００８２】
（付記６） 前記位相合成手段は、スイッチを更に備え、複数の前記トランスコンダクタンス・アンプが出力する複数の前記振幅制御後信号を前記スイッチにより選択的に足し合わせて位相合成を行うことを特徴とする付記１に記載のタイミング信号発生回路。
【００８３】
（付記７） 前記振幅制御後信号が電流出力である場合に、前記振幅制御後信号を足し合わせて位相合成した後に電圧値に変換した前記タイミング信号を出力する前記位相合成手段は、
前記電圧値の変動の平均電圧値を出力する平均電圧値出力手段と、
前記平均電圧値出力手段が出力する前記平均電圧値の増減に応じた負帰還が前記電圧値にかかるよう制御する負帰還制御手段と
を更に具備すること
を特徴とする付記３に記載のタイミング信号発生回路。
【００８４】
（付記８） 同一の周波数であって複数種類の位相を有する複数の入力信号を用いて位相合成する際に、各前記入力信号に対する合成の重み付けを制御する制御信号を出力する制御手段と、
複数の前記入力信号をそれぞれ受けて、各前記入力信号と同じ位相であって一定の振幅を有する複数の振幅制御後信号を出力する複数のトランスコンダクタンス・アンプと、
複数の前記トランスコンダクタンス・アンプが出力する複数の前記振幅制御後信号を選択的に足し合わせて位相合成したタイミング信号を出力する位相合成手段と
を具備することを特徴とするタイミング信号発生回路。
【００８５】
（付記９） 前記位相合成手段は、複数の前記トランスコンダクタンス・アンプの出力をスイッチ回路により選択的に結線することで前記振幅制御後信号を足し合わせて位相合成した前記タイミング信号を出力する構成であることを特徴とする付記８に記載のタイミング信号発生回路。
【００８６】
（付記１０） 前記入力信号として、位相が１８０度異なるものを一組として、複数組が入力される場合に、前記トランスコンダクタンス・アンプは、少なくとも２つのトランジスタと１つの抵抗回路と２つの電流源から構成され、前記一組の入力信号は２つの前記トランジスタのゲート端子にそれぞれ入力され、前記抵抗回路は、２つの前記トランジスタのソース端子間に設置され、２つの前記トランジスタのソース端子はそれぞれ２つの前記電流源を介して接地され、前記２つのトランジスタのドレイン端子より位相の１８０度異なる２つの出力電流を前記振幅制御後信号として出力し、
前記制御手段が出力する前記制御信号は、前記トランスコンダクタンス・アンプの出力する２つの前記出力電流の出力先を制御する信号であり、
前記位相合成手段は、複数の前記トランスコンダクタ・アンプにおける２つの出力電流をそれぞれ出力する２つの前記ドレイン端子と、２つの前記タイミング信号を出力する出力端子との接続を切り替える複数のスイッチ回路を備え、前記制御手段からの前記制御信号に応じて前記スイッチ回路が切替わることで、複数の前記トランスコンダクタンス・アンプが出力する２つの前記出力電流を前記振幅制御後信号として選択的に足し合わせて位相合成して位相の１８０度異なる２つの前記タイミング信号を生成する構成であること
を特徴とする付記８に記載のタイミング信号発生回路。
【００８７】
（付記１１） 前記抵抗回路は可変抵抗であり、
前記制御手段が出力する前記制御信号は、前記抵抗回路の抵抗値を制御する信号を更に含むこと
を特徴とする付記１０に記載のタイミング信号発生回路。
【００８８】
（付記１２） 前記抵抗回路は、直列に接続した抵抗素子とスイッチを、２つの前記トランジスタのソース端子間に並列に複数接続した構成であり、
前記制御手段が出力する前記制御信号に含まれる前記抵抗回路の抵抗値を制御する信号は、前記抵抗回路の前記スイッチのオン／オフを制御する信号であること
を特徴とする付記１１に記載のタイミング信号発生回路。
【００８９】
（付記１３） 前記抵抗回路は、抵抗用トランジスタおよび前記抵抗用トランジスタのゲート端子への電圧印加回路により構成され、２つの前記トランジスタのソース端子間を前記抵抗用トランジスタで接続し、前記電圧印加回路は、前記制御手段からの前記制御信号に応じた電圧を前記抵抗用トランジスタのゲート端子に印加することで前記抵抗用トランジスタのオン抵抗値を制御する構成であり、
前記制御手段が出力する前記制御信号に含まれる前記抵抗回路の抵抗値を制御する信号は、前記抵抗用トランジスタのオン抵抗値を制御する信号であること
を特徴とする付記１１に記載のタイミング信号発生回路。
【００９０】
（付記１４） 前記位相合成手段が位相合成後の前記タイミング信号を電圧値に変換する場合に、前記位相合成手段は、
前記電圧値の変動の平均電圧値を出力する平均電圧値出力手段と、
前記平均電圧値出力手段が出力する前記平均電圧値の増減に応じた負帰還が前記電圧値にかかるよう制御する負帰還制御手段と
を更に具備すること
を特徴とする付記１０に記載のタイミング信号発生回路。
【００９１】
（付記１５） 入力信号の変化タイミングに応じて位相を調整したクロック信号を出力するタイミング信号発生回路と、前記入力信号を前記タイミング信号発生回路が出力する前記クロック信号に同期して受信および再生する受信回路とを備える信号受信回路であって、
前記タイミング信号発生回路は、
同一の周波数であって複数種類の位相を有する複数のクロック信号を用いて位相合成する際に、各前記クロック信号に対する合成の重み付けを制御する制御信号を出力する制御手段と、
複数の前記クロック信号をそれぞれ受けて、各前記クロック信号と同じ位相であって前記制御手段が出力する前記制御信号に応じて振幅を制御した複数の振幅制御後信号を出力する複数のトランスコンダクタンス・アンプと、
複数の前記トランスコンダクタンス・アンプが出力する複数の前記振幅制御後信号を足し合わせて位相合成したタイミング信号を出力する位相合成手段と
を具備すること
を特徴とする信号受信回路。
【００９２】
（付記１６） 前記タイミング信号発生回路の前記位相合成手段は、複数の前記トランスコンダクタンス・アンプの出力を結線することで前記振幅制御後信号を足し合わせて位相合成した前記タイミング信号を出力する構成であることを特徴とする付記１５に記載の信号受信回路。
【００９３】
（付記１７） 前記タイミング信号発生回路において、
前記クロック信号として、位相が１８０度異なるものを一組として、複数組が入力される場合に、前記トランスコンダクタンス・アンプは、少なくとも２つのトランジスタと１つの可変抵抗回路と２つの電流源から構成され、前記一組のクロック信号は２つの前記トランジスタのゲート端子にそれぞれ入力され、前記抵抗回路は、２つの前記トランジスタのソース端子間に設置され、２つの前記トランジスタのソース端子はそれぞれ２つの前記電流源を介して接地され、前記２つのトランジスタのドレイン端子より位相の１８０度異なる２つの出力電流を前記振幅制御後信号として出力し、
前記制御手段が出力する前記制御信号は、前記トランスコンダクタンス・アンプの有する前記可変抵抗回路の抵抗値を制御する信号であり、
前記位相合成手段は、複数の前記トランスコンダクタ・アンプにおける２つの出力電流を出力する前記ドレイン端子を別々にまとめて結線する構成により、複数の前記トランスコンダクタンス・アンプが出力する２つの前記出力電流を前記振幅制御後信号としてそれぞれ足し合わせて位相合成して位相の１８０度異なる２つの前記タイミング信号を生成する構成であること
を特徴とする付記１５に記載の信号受信回路。
【００９４】
（付記１８） 前記タイミング信号発生回路において、
前記可変抵抗回路は、直列に接続した抵抗素子とスイッチを、２つの前記トランジスタのソース端子間に並列に複数接続した構成であり、
前記制御手段が出力する前記制御信号は、前記抵抗回路の前記スイッチのオン／オフを制御する信号であること
を特徴とする付記１７に記載の信号受信回路。
【００９５】
（付記１９） 入力信号の変化タイミングに応じて位相を調整したクロック信号を出力するタイミング信号発生回路と、前記入力信号を前記タイミング信号発生回路が出力する前記クロック信号に同期して受信および再生する受信回路とを備える信号受信回路であって、
前記タイミング信号発生回路は、
同一の周波数であって複数種類の位相を有する複数のクロック信号を用いて位相合成する際に、各前記クロック信号に対する合成の重み付けを制御する制御信号を出力する制御手段と、
複数の前記クロック信号をそれぞれ受けて、各前記クロック信号と同じ位相であって一定の振幅を有する複数の振幅制御後信号を出力する複数のトランスコンダクタンス・アンプと、
複数の前記トランスコンダクタンス・アンプが出力する複数の前記振幅制御後信号を選択的に足し合わせて位相合成したタイミング信号を出力する位相合成手段と
を具備すること
を特徴とする信号受信回路。
【００９６】
（付記２０） 前記タイミング信号発生回路の前記位相合成手段は、複数の前記トランスコンダクタンス・アンプの出力をスイッチ回路により選択的に結線することで前記振幅制御後信号を足し合わせて位相合成した前記タイミング信号を出力する構成であることを特徴とする付記１９に記載の信号受信回路。
【００９７】
【発明の効果】
以上に説明したように、本発明によるタイミング信号発生回路においては、例えば、複数種類の位相を有する複数のクロック信号を用いて位相合成する際に、複数のトランスコンダクタンス・アンプが、入力される複数のクロック信号と同じ位相であって振幅を制御した複数の振幅制御後信号を出力して、位相合成手段がそれらの振幅制御後信号を足し合わせて位相合成したタイミング信号を出力することができる。ここで、トランスコンダクタンス・アンプとは、一般的に２つのトランジスタと１つの抵抗回路と２つの電流源とを備える簡単な構成である。また、トランスコンダクタ・アンプは、入力されるクロック信号と同位相であって抵抗回路の抵抗値を制御することで精度よく振幅を制御した振幅制御後信号を出力することができる。すなわち、本発明によるタイミング信号発生回路は、所定の位相差を有する複数のタイミング信号を、簡単な構成でしかも高精度に発生することができる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態によるタイミング信号発生回路の全体構成を示すブロック図である。
【図２】図１に示したアンプ２２ａの動作を説明するための図である。
【図３】図１に示したタイミング信号発生回路における抵抗Ｒ１〜Ｒ４の実現例を示す図である。
【図４】本発明の第２の実施形態におけるタイミング信号発生回路の回路構成例を示す図である。
【図５】本発明の第３の実施形態におけるタイミング信号発生回路の回路構成例を示す図である。
【図６】本発明の第３の実施形態におけるタイミング信号発生回路の回路構成例を示す図である。
【図７】本発明の第４の実施形態におけるタイミング信号発生回路の回路構成例を示す図である。
【図８】上述した電流ルート切換え信号ＲＴＡ、ＲＴＢの４パターンの組み合わせ（１）〜（４）に応じて定まる位相関係を示す図である。
【図９】本発明の第５の実施形態におけるタイミング信号発生回路の回路構成例を示す図である。
【図１０】クロック復元回路の一例を示すブロック図である。
【図１１】タイミング信号発生回路１３が出力する、信号再生タイミング信号ＯＵＴと変化点検出タイミング信号ＯＵＴＸの位相差ΔΦと入力信号の関係を示す図である。
【図１２】従来のタイミング信号発生回路１３の回路構成例を示す図である。
【図１３】位相合成の原理を示す図である。
【図１４】図１２に示した４つの差動アンプ２０２ａ〜２０２ｄの１つである差動アンプ２０２ａを取り上げた、上述した問題を説明するための図である。
【符号の説明】
１ 信号受信回路
１１、１２ 受信回路
１３ タイミング信号発生回路
１４ 位相比較回路
２１ 抵抗素子
２２ａ〜２２ｄ トランスコンダクタンス・アンプ（可変抵抗を含む）
２３ 電流源
２４ 抵抗値制御部
３２ ＤＡＣ
４２ スイッチ制御回路
５０ 制御部
５１ オペアンプ
５２ コンデンサ
Ｔｒ２１〜Ｔｒ２４ トランジスタ（ｎ型ＭＯＳＦＥＴ）
Ｒ１〜Ｒ４ 抵抗（可変抵抗）
ｒ１〜ｒｎ 抵抗素子
ＳＷ１〜ＳＷｎ スイッチ
ａ１〜ａｎ、ｂ１〜ｂｎ トランスコンダクタンス・アンプ
Ｓ１〜Ｓｎ、Ｗ１〜Ｗｎ スイッチ
Ｔｒ１０〜Ｔｒ１３ トランジスタ（ｎ型ＭＯＳＦＥＴ）
Ａ、Ｂ トランスコンダクタンス・アンプ
ＲＡ、ＲＢ 抵抗（可変抵抗）
ＳＡ、ＳＢ スイッチ
Ｔｒ３０、Ｔｒ３１ トランジスタ（ｐ型ＭＯＳＦＥＴ）[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a timing signal generating circuit that performs phase interpolation (phase interpolator) on a timing signal such as a clock signal, and a signal receiving circuit including the timing signal generating circuit.
[0002]
[Prior art]
In recent years, a technique for speeding up signal transmission between a plurality of LSI (Large-Scale Integrated Circuits) chips or between a plurality of elements and circuit blocks in one chip has become necessary. Specifically, it is necessary to perform signal transmission between a DRAM (Dynamic Random Access Memory) and a processor, and signal transmission between a plurality of elements and circuit blocks in one LSI chip at high speed. Yes.
[0003]
In order to increase the speed of signal transmission between LSIs, it is necessary for a circuit that receives a signal to operate at an accurate timing with respect to the signal. As a method for generating such an accurate timing, a high-accuracy and high-speed timing signal can be generated, and a timing signal having a wide operating frequency range and a small jitter can be generated with a simple circuit configuration. A timing signal generating circuit that can be used is disclosed (for example, see Patent Document 1).
[0004]
As another example of a method for generating accurate timing, for example, a Schmitt circuit (trigger circuit) having excellent characteristics in which the hysteresis voltage is easily adjusted over a wide range to suppress the influence of variations in characteristics of semiconductor elements. ) Is disclosed (for example, see Patent Document 2). In addition, as another example of a method for generating accurate timing, a current switch circuit that can perform a current switch with small ringing over a wide range of output current from a small output current to a large output current is disclosed (for example, (See Patent Document 3).
[0005]
As another example of generating accurate timing, a clock restoration circuit (signal reception circuit) in which a phase variable timing signal generation (phase interpolation) circuit is provided in a feedback loop is known.
FIG. 10 is a block diagram illustrating an example of a clock recovery circuit. In the block diagram of FIG. 10, reference numeral 11 denotes a receiving circuit that receives an input signal and outputs a reproduction signal. A receiving circuit (change point detection circuit) 12 receives an input signal and outputs a change point detection signal. Reference numeral 13 denotes a timing signal generation circuit (phase interpolation circuit) that detects a change point between the first timing signal for outputting the input signal received by the reception circuit 11 as a reproduction signal and the input signal received by the reception circuit 12. A second timing signal to be output as a signal is generated and output. The circuit configurations of the receiving circuit 11 and the receiving circuit 12 are the same, and the input signal received according to the timing signal is latched and output.
[0006]
Reference numeral 14 denotes a phase comparison circuit. A reproduction signal output from the reception circuit 11 in response to the first timing signal output from the timing signal generation circuit 13 and a change output from the reception circuit 12 in response to the second timing signal. By comparing the point detection signals, it is determined whether or not the phases of the first and second timing signals are appropriate, and the phases of the first and second timing signals are advanced or delayed by the determination. A control signal for controlling the output is output. Details of this phase control will be described later.
[0007]
Here, the timing signal generation circuit 13 described above will be further described. The output of the timing signal generation circuit 13 described above outputs a clock having an arbitrary phase corresponding to the phase control signal based on the reference clock as the first and second timing signals. At this time, the output clocks (= first and second timing signals) are the following two types of timing signals.
First timing signal = timing signal for reproducing the input signal in the receiving circuit 11 (hereinafter referred to as a signal reproduction timing signal OUT)
Second timing signal = timing signal for detecting a change point of the input signal in the receiving circuit 12 (hereinafter referred to as a change point detection timing signal OUTX)
[0008]
Further, the timing signal generation circuit 13 sets the phase difference ΔΦ between the signal reproduction timing signal OUT and the change point detection timing signal OUTX to a phase relationship corresponding to half of the input signal 1 bit as shown in FIG. FIG. 11 is a diagram illustrating the relationship between the input signal and the phase difference ΔΦ between the signal reproduction timing signal OUT and the change point detection timing signal OUTX output from the timing signal generation circuit 13. Thus, the receiving circuit 11 can reliably receive and latch the input signal at the rising edge of the signal reproduction timing signal OUT.
[0009]
Next, the operation of the feedback loop in the clock restoration circuit 1 shown in FIG. 10 will be described. First, based on the two types of first and second timing signals output from the timing signal generation circuit 13, the reception circuit 11 performs signal reproduction and the reception circuit 12 performs change point detection. Next, the phase comparison circuit 14 compares the reproduction signal output from the reception circuit 11 with the change point detection signal output from the reception circuit 12, and determines whether the first and second timing signals are in an appropriate phase. The control signal SE for controlling whether the phase of the first and second timing signals output from the timing signal generating circuit 13 is advanced or delayed is output. Next, the timing signal generation circuit 13 performs phase correction according to the control signal SE from the phase comparison circuit 14, and outputs first and second timing signals having new phases to the reception circuits 11 and 12.
[0010]
By repeating the above operation, in the feedback loop of the clock restoration circuit 1, the change point detection timing signal OUTX converges near the change point of the input signal as shown in FIG. Therefore, the signal reproduction timing signal OUT having a half phase difference with respect to the input signal 1 bit has a phase relationship at the center of the input signal 1 bit, and the receiving circuit 11 has a reliable timing at the center portion between the changing points in the input signal. An input signal can be received and a reproduction signal can be output.
In order to realize the feedback loop in the clock recovery circuit 1 described above, the timing signal generation circuit 13 capable of highly accurate phase control is required.
[0011]
Next, the circuit configuration of the conventional timing signal generation circuit 13 will be described with reference to the drawings.
FIG. 12 is a diagram showing a circuit configuration example of a conventional timing signal generation circuit 13. As shown in FIG. 12, the conventional timing signal generation circuit 13 includes a phase synthesis unit 200, a comparator 201, and a DAC (digital / analog converter) 204. The phase synthesis unit 200 includes differential amplifiers 202a to 202d, bias current sources 203a to 203d, and an output voltage generation circuit 205. Here, the DAC 204 is, for example, a 4-channel 8-bit DAC, which receives four types of control signals SE (8 bits) from the phase comparison circuit 14 and supplies four types of DC signals (analog signals) to the bias current sources 203a to 203a. To 203d.
[0012]
As shown in FIG. 12, each of the differential amplifiers 202a to 202d has the same circuit configuration, and transistors Tr1 and Tr2 which are two n-type MOSFETs (Metal-Oxide Semiconductor Field-Effect Transistors) are differentially formed. Connected and configured. At this time, clock signals Va, Vax, Vb, and Vbx, which are four-phase reference clocks, are input to the gate terminals of the transistors Tr1 and Tr2 of the differential amplifiers 202a to 202d. The clock signal Va and the clock signal Vb are 90 degrees out of phase, and the clock signal Va and the clock signal Vax, and the clock signal Vb and the clock signal Vbx are 180 degrees out of phase.
[0013]
Specifically, the clock signal Va is input to the gate terminal of the transistor Tr1 of the differential amplifier 202a, and Vax is input to the gate terminal of the transistor Tr2. Further, the clock signal Vb is input to the gate terminal of the transistor Tr1 of the differential amplifier 202b, and Vbx is input to the gate terminal of the transistor Tr2. Further, the clock signal Vax is input to the gate terminal of the transistor Tr1 of the differential amplifier 202c, and Va is input to the gate terminal of the transistor Tr2. Further, the clock signal Vbx is input to the gate terminal of the transistor Tr1 of the differential amplifier 202d, and Vb is input to the gate terminal of the transistor Tr2.
[0014]
In addition, bias current sources 203a to 203d are respectively connected to the differential amplifiers 202a to 202d, and the bias current sources 203a to 203d supply currents according to control of the DAC 204 to the differential amplifiers 202a to 202d. The differential amplifiers 202a to 202d have two output terminals, and the transistors Tr1 and Tr2 are connected to each other. One of the output terminals of the differential amplifiers 202a to 202d is collectively connected to one input terminal of the comparator 201. The other output terminals of the differential amplifiers 202 a to 202 d are connected together to the other input terminal of the comparator 201.
[0015]
The bias current sources 203a to 203d are circuits in which a current mirror circuit is configured by transistors Tr3 and Tr4 which are n-type MOSFETs. As a result, the bias current sources 203a to 203d cause the current having the same amount of current as the current flowing in the transistor Tr3 to flow in the transistor Tr4 in accordance with the four types of DC signals supplied from the DAC 204, and thus the DAC 204 is supplied to the differential amplifiers 202a to 202d. The current according to the control can be supplied.
[0016]
The output voltage generation circuit 205 includes transistors Tr5 and Tr6 which are p-type MOSFETs, and the transistor Tr5 adds the output current values (a1 to d1) from the transistors Tr1 of the differential amplifiers 202a to 202d. The current value is converted into a voltage value and output to the input terminal 1 of the comparator 201, and the transistor Tr6 adds the output current value (a2 to d2) from the transistor Tr2 of the differential amplifiers 202a to 202d to the voltage value. And output to the input terminal 2 of the comparator 201.
[0017]
The comparator 201 compares the signals input to the input terminal 1 and the input terminal 2. For example, when the voltage value input to the input terminal 1 is larger, the comparator 201 inputs the signal to the input terminal 1. When the applied voltage value is smaller, a signal that is H (high) level is output from the output terminal OUT. The signal output from the output terminal OUT is the signal reproduction timing signal OUT described above, and the change point detection timing signal OUTX obtained by inverting the signal reproduction timing signal OUT is output from the output terminal OUTX.
[0018]
Further, the DAC 204 receives four types of control signals SE that determine whether to advance or slow down the phase, and generates four types of weighting signals. That is, the output current a1 having the same phase as the clock signal Va output from the differential amplifier 202a, the output current b1 having the same phase as the clock signal Vb output from the differential amplifier 202b, and the differential amplifier 202c are output. A current larger than the other two flows in any two of the output current c1 having the same phase as the clock signal Vax to be output and the output current d1 having the same phase as the clock signal Vbx output from the differential amplifier 202d. A weighting signal for performing weighting is output. Here, the output currents a1, b1, c1, and d1 are out of phase by 90 degrees (when a1 = 0 degrees, b1 = 90 degrees, c1 = 180 degrees, d1 = 270 degrees). For example, if the output currents a1 and b1 are weighted, the two output currents a1 and b1 are added according to the weighting, so the intermediate phase (phase between 0 degrees and 90 degrees) of the output currents a1 and b1 is set. Can be obtained (phase synthesis). It should be noted that the same phase composition processing is performed with the inverted phases in the output currents a2 to d2.
[0019]
Here, the principle of the above-described phase synthesis will be further described. FIG. 13 is a diagram illustrating the principle of phase synthesis. FIG. 13 shows the phase synthesis of two clock signals Va and Vb among the clock signals Va, Vax, Vb, and Vbx that are inputted in the above-described four phases. Here, assuming that the signal waveform of the clock signal Va is the waveform φ0 and the signal waveform of the clock signal Vb is the waveform φ1, the waveforms φ0 and φ1 are expressed by the following equations with the time t as a variable.
φ0 = s (t), φ1 = c (t)
[0020]
Here, s (t) and c (t) are triangular wave functions that periodically change in accordance with changes in time t as shown in FIG. Further, as shown in FIG. 13, the periods of φ0 and φ1 are the same, and the phase in the period is shifted by 90 degrees. That is, the clock signal Va changing in the phase shown by the waveform φ0 and the clock signal Vax having the opposite phase are input to the differential amplifier 202a, and the clock signal Vb changing in the phase shown by the waveform φ1 and the clock signal Vbx having the opposite phase are inputted. Input to the differential amplifier 202b.
[0021]
On the other hand, the DAC 204 controls the amount of current output from the current sources 203a to 203d so that the outputs of the differential amplifier 202a and the differential amplifier 202b are weighted 1-x and x (0 ≦ x ≦ 1). wear. At this time, the weight is reduced by supplying a minute current to the remaining two differential amplifiers 202c and 202d. As a result, a combined signal of θ = (1−x) × s (t) + xx × c (t) is obtained as the output θ after phase synthesis. The obtained output signal is an intermediate phase signal between the phase of the waveform s (t) and the phase of the waveform c (t). Further, by changing the weighting factor x, a composite signal having an arbitrary phase between the phase of the waveform s (t) and the phase of the waveform c (t) can be obtained.
[0022]
As described above, the phase synthesis unit 200 has two outputs (a1 to d1 and four outputs) of the four differential amplifiers 202a to 202d that receive the clock signals Va, Vax, Vb, and Vbx, which are four-phase reference clocks. a2 to d2) are connected to each other. Further, the phase synthesizing unit 200 changes the current values of the bias current sources 203a to 203d connected to the differential amplifiers 202a to 202d in accordance with the change of the output of the DAC 204, so that the reference clock of two phases By adding weights (for example, clock signals Va and Vb) and adding them through the comparator 201, a signal (signal reproduction timing signal OUT) that is an intermediate phase between the two clock signals Va and Vb is obtained. ing.
[0023]
In FIG. 12 described above, the configuration in which the four-phase reference clock is received by the differential amplifiers 202a to 202d is shown, but this is not restrictive. For example, a phase interpolation circuit including two differential amplifiers to which a two-phase reference clock is input is disclosed (for example, see Patent Document 4).
[0024]
[Patent Document 1]
JP 2000-196418 A
[Patent Document 2]
JP-A 63-74210
[Patent Document 3]
Japanese Utility Model Publication No. 5-28127
[Patent Document 4]
Japanese Patent Laid-Open No. 11-261408 (FIG. 15)
[0025]
[Problems to be solved by the invention]
However, when the phase synthesizing unit 200 is configured in a differential amplifier format as shown in FIG. 12, the following problems occur when attempting to realize highly accurate phase control.
FIG. 14 is a diagram for explaining the above-described problem in which the differential amplifier 202a that is one of the four differential amplifiers 202a to 202d shown in FIG. 12 is taken up. When the potential of the clock signal Va input to the differential amplifier 202a shown in FIG. 14 is high (above the saturation region of the transistor Tr1) and the potential of the clock signal Vb is low, the current I1 flowing through the transistor Tr1 is the current of the current source 203a. It becomes equal to the current value Ic (I1 = Ic). That is, the output current a1 = I1 = Ic. At this time, the current I2 flowing through the transistor Tr2 becomes 0 (output current a2 = I2 = 0).
[0026]
That is, the transistor Tr2 is turned off when the potential of the clock signal Va is high regardless of the change in the potential of the clock signal Vb input to the gate terminal of the transistor Tr2. This means that the transistor Tr2 cannot operate linearly according to the voltage change of the clock signal Vb that changes as shown in FIG. If the transistor Tr2 cannot perform a linear operation for outputting according to the magnitude of the input voltage, accurate phase information cannot be transmitted to the output current a2.
[0027]
In order to avoid this, the amplitude of the input to the differential amplifier 202a is reduced to a range that does not reach the saturation region of the transistors Tr1 and Tr2, and a circuit that adjusts so that the input can be performed with the optimum common mode voltage is performed differentially. A method of inserting the amplifier 202a before the amplifier 202a can be considered, but the circuit becomes complicated. That is, when a phase interpolation circuit configured in the form of a differential amplifier is used, it is difficult to realize a highly accurate phase change with a simple configuration. There is a demand for providing a timing signal generation circuit capable of generating a plurality of timing signals having a predetermined phase difference in synchronization with a reference clock with a simple configuration and high accuracy.
[0028]
The present invention has been made in consideration of the above-described circumstances, and a timing signal generation circuit capable of generating a plurality of timing signals having a predetermined phase difference with high accuracy with a simple configuration and the timing signal generation An object of the present invention is to provide a signal receiving circuit including a circuit.
[0029]
[Means for Solving the Problems]
The present invention has been made to solve the above-described problems. In the timing signal generation circuit according to the present invention, when the phase synthesis is performed using a plurality of input signals having the same frequency and a plurality of types of phases. A control means for outputting a control signal for controlling the weighting of the synthesis for each input signal; and a plurality of input signals, respectively, having the same phase as each input signal and having an amplitude according to the control signal output by the control means A plurality of transconductance amplifiers for outputting a plurality of controlled signals after amplitude control, and a phase synthesis means for outputting a timing signal obtained by adding and synthesizing a plurality of signals after amplitude control output from the plurality of transconductance amplifiers. It is characterized by comprising.
[0030]
As a result, in the timing signal generation circuit according to the present invention, for example, when phase synthesis is performed using a plurality of clock signals having a plurality of types of phases, a plurality of transconductance amplifiers and a plurality of input clock signals A plurality of post-amplitude control signals having the same phase and controlled amplitude can be output, and a phase synthesis unit can add the post-amplitude control signals and output a timing signal obtained by phase synthesis. Here, the transconductance amplifier has a simple configuration including two transistors, one resistance circuit, and two current sources. In addition, the transconductor amplifier can output an amplitude-controlled signal whose amplitude is controlled accurately by controlling the resistance value of the resistance circuit in phase with the input clock signal. That is, the timing signal generating circuit according to the present invention can generate a plurality of timing signals having a predetermined phase difference with a simple configuration and high accuracy.
[0031]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the invention will be described below.
First, the overall configuration of the timing signal generation circuit according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a timing signal generating circuit according to the first embodiment of the present invention. The timing signal generation circuit in the first embodiment shown in FIG. 1 can be applied to, for example, the timing signal generation circuit 13 of the signal reception circuit 1 schematically shown in FIG. Further, the timing signal generation circuit shown in FIG. 1 is greatly different in that it uses a transconductance amplifier instead of the differential amplifiers 202a to 202d in the timing signal generation circuit 13 shown in FIG.
[0032]
In FIG. 1, reference numeral 21 denotes a resistance element, one connected between the power supply and the output terminal OUT, and one connected between the power supply and the output terminal OUTX. A transconductance amplifier (hereinafter simply referred to as an amplifier) described later. The output current of 22a-22d is converted into a voltage. The resistance element 21 functions in the same manner as the voltage conversion circuit 205 shown in FIG. 12, and in this embodiment, the voltage conversion circuit 205 shown in FIG. It may be used.
[0033]
The amplifiers 22a to 22d are transconductance amplifiers composed of transistors Tr21 and Tr22 and resistors R1 to R4. As shown in FIG. 1, the clock signal Va is input to the gate terminal of the transistor Tr21 of the amplifier 22a, and the clock signal Vax is input to the gate terminal of the transistor Tr22. The clock signal Vax is input to the gate terminal of the transistor Tr21 of the amplifier 22b, and the clock signal Va is input to the gate terminal of the transistor Tr22. The clock signal Vb is input to the gate terminal of the transistor Tr21 of the amplifier 22c, and the clock signal Vbx is input to the gate terminal of the transistor Tr22. The clock signal Vbx is input to the gate terminal of the transistor Tr21 of the amplifier 22d, and the clock signal Vb is input to the gate terminal of the transistor Tr22.
[0034]
That is, the transistors Tr21 and Tr22 are n-type MOSFETs, and any one set of clock signals Va and Vax or clock signals Vb and Vbx which are reference clocks is input to their gate terminals. As described above, the clock signal Va and the clock signal Vax, and the clock signal Vb and the clock signal Vbx are 180 degrees out of phase (reverse phase). The clock signal Va and the clock signal Vb are 90 degrees out of phase.
[0035]
The source terminals of the transistors Tr21 and Tr22 of the amplifiers 22a to 22d are connected to the ground via a current source 23 described later. In each of the amplifiers 22a to 22d, the source terminals of the transistors Tr21 and Tr22 are connected to each other via resistors R1 to R4.
[0036]
The drain terminals (output terminals) of the transistors Tr21 of the amplifiers 22a to 22d are all connected to the output terminal OUT. As a result, the output currents (I1 to I4 in FIG. 1) of the transistors Tr21 of the amplifiers 22a to 22d are added to form an output current Io, which is output from the output terminal OUT after being converted into a voltage by the resistance element 21. The drain terminals (output terminals) of the transistors Tr22 of the amplifiers 22a to 22d are all connected to the output terminal OUTX. As a result, the output currents of the transistors Tr22 of the amplifiers 22a to 22d are added to become an output current Iox, which is converted into a voltage by the resistance element 21 and output from the output terminal OUTX. Further, the resistance values of the resistors R1 to R4 are variable and become resistance values according to the control of the resistance value control unit 24 described later.
[0037]
Further, the current source 23 is a current source for flowing a current I0. Further, the resistance value control unit 24 controls the resistance values of the resistors R1 to R4 based on, for example, the control signal SE received from the phase comparison circuit 14 of FIG. The control signal SE is, for example, four types of 8-bit data signals for the amplifiers 22a to 22d. In this embodiment, the outputs of the amplifiers 22a to 22d are directly output from the output terminals OUT and OUTX. However, the present invention is not limited to this, and may be output via a comparator as shown in FIG. Good. By using the comparator in this way, the amplitude of the signal output from the output terminals OUT and OUTX can be amplified. Further, the two signals output from the output terminals OUT and OUTX in the present embodiment correspond to, for example, the signal reproduction timing signal OUT and the change point detection timing signal OUTX in FIG.
[0038]
Next, operations of the amplifiers 22a to 22d (transconductance amplifiers) shown in FIG. 1 will be described. Here, the amplifier 22a will be described.
FIG. 2 is a diagram for explaining the operation of the amplifier 22a shown in FIG. As shown in FIG. 2, the amplifier 22a includes transistors Tr21 and Tr22 and a resistor R1. As shown in FIG. 2, the output terminal of the amplifier 22a connected to the drain terminal of the transistor Tr21 is OUT1, and the output terminal of the amplifier 22a connected to the drain terminal of the transistor Tr22 is OUT2. Also, currents output to the output terminals Out1 and Out2 are currents I1 and I1x. Further, when the threshold voltage of the transistors Tr21 and Tr22 to which the clock signals Va and Vax are input is Vth, a potential difference of Va−Vth is generated between the gate terminal and the source terminal of the transistor Tr21, and the gate terminal and the source terminal of the transistor Tr22 are generated. A potential difference of Vax−Vth is generated between them.
[0039]
From the above, the current Ir flowing through the resistor R1 is expressed by the following equation.

Thereby, the output currents I1 and I1x (= currents flowing through the transistors Tr21 and Tr22) are expressed by the following equations.
I1 = I0 + Ir = I0 + (Va−Vax) / R1
I1x = I0-Ir = I0- (Va-Vax) / R1
[0040]
As described above, the output currents I1 and I1x are values determined by the value of the resistor R1 connecting the source terminals of the transistors Tr21 and Tr22. That is, it is not necessary to consider the non-linear operation of the transistor seen when using a differential amplifier as in the prior art, and the phase of the clock signal (Va, Vax, Vb, Vbx) that is the reference clock is accurately output. Can tell. The above features are the same not only in the amplifier 22a but also in the amplifiers 22b to 22d.
[0041]
Next, the current Io flowing through the resistance element 21 in FIG. 1 obtained by adding the output currents I1 to I4 of the amplifiers 22a to 22d described above is obtained.
First, since Va and Vax have a differential relationship with Va = Vax, and Vb and Vbx have a differential relationship as well, assuming that Vb = −Vbx, the output current I1 of the amplifiers 22a to 22d. ˜I4 is determined by the following formula.
I1 = I0 + (Va−Vax) / R1 = I0 + 2 × Va / R1
I2 = I0 + (Vax−Va) / R2 = I0 + 2 × Vax / R2
I3 = I0 + (Vb−Vbx) / R3 = I0 + 2 × Vb / R3
I4 = I0 + (Vbx−Vb) / R4 = I0 + 2 × Vbx / R4
[0042]
Here, since the current Io flowing through the resistance element 21 for outputting a voltage to the output terminal OUT is the sum of I1 to I4, the following equation is obtained.

As described above, according to the timing signal generation circuit of the present embodiment, the result of the clock signal phase synthesis is determined only by the voltage value and variable resistance value of the input clock signal, so that highly accurate phase synthesis is possible. is there.
[0043]
Here, an implementation example of the variable resistor in FIG. 1 is shown.
FIG. 3 is a diagram illustrating a timing signal generation circuit including an implementation example of resistors R1 to R4 in the timing signal generation circuit illustrated in FIG. As shown in FIG. 3, the resistors R1 to R4 in FIG. 1 are configured by a plurality of resistance elements r1 to rn and a plurality of switches SW1 to SWn (n is an arbitrary natural number). In each of the resistors R1 to R4, the source terminals of the transistors Tr21 and Tr22 are connected via the resistance element r1 and the switch SW1. Similarly, a resistance element r2 and a switch SW2, a resistance element r3 and a switch SW3,..., A resistance element rn and a switch SWn are connected in parallel with the resistance element r1 and the switch SW1.
[0044]
The resistance elements r1 to rn may all have the same resistance value or may all have different resistance values. Further, the resistance value control unit 24 performs control so that at least one of the switches SW1 to SWn connected to the amplifiers 22a to 22d is turned on. Further, the resistance value control unit 24 controls the amplitude of the output signal to be constant by controlling the total of the resistance values determined by turning on the switches SW1 to SWn connected to the amplifiers 22a to 22d. Can be kept in.
[0045]
In FIG. 3, for example, if the number of switches SW1 to SWn in the resistor R1 is large, the resistance value of the resistor R1 decreases, so that the amount of change (amplitude) of the current I1 corresponding to the change of the clock signal Va increases. To do. That is, the rate at which the change in the current I1 affects the change in the output current Io increases. On the other hand, if the number of switches SW1 to SWn turned on in the resistor R1 is small, the resistance value of the resistor R1 increases, and the amount of change (amplitude) of the current I1 corresponding to the change in the clock signal Va decreases. . That is, the rate at which the change in the current I1 affects the change in the output current Io decreases.
[0046]
As described above, when the resistance value control unit 24 changes the resistance values of the resistors R1 to R4, any one of the currents I1 to I4 can be weighted and added to the output current Io. That is, the resistance value control unit 24 controls the amplitudes of the four types of output currents I1 to I4 having different phases for phase synthesis by changing the resistance values of the resistors R1 to R4, and the output current Io having an arbitrary phase is synthesized. Can be controlled.
[0047]
Next, as a second embodiment of the present invention, a timing signal generation circuit having a configuration in which transistor circuits having similar functions are used in the portions of the resistors R1 to R4 shown in FIG. FIG. 4 is a diagram illustrating a circuit configuration example of the timing signal generation circuit according to the second embodiment of the present invention. The transconductance amplifiers 31a to 31d (hereinafter referred to as amplifiers 31a to 31d) shown in FIG. 4 have the resistors R1 to R4 of the transconductance amplifiers (amplifiers 22a to 22d) shown in FIG. The transistor circuit includes (n-type MOSFET). The DAC 32 is a current output type digital / analog converter, and supplies currents having current values corresponding to the weights to the amplifiers 31a to 31d according to a control signal. 4 having the same reference numerals as those in FIG. 1 have the same functions and will not be described.
[0048]
In the amplifiers 31a to 31d, the drain terminal and the source terminal of the transistor Tr23 are connected to the source terminals of the transistor Tr21 and the transistor Tr22. The gate terminal of the transistor Tr23 is connected to the drain terminal and gate terminal of the transistor Tr24 and the output terminal of the DAC 32. The source terminal of the transistor Tr24 is connected to the ground.
[0049]
Next, the operation of the timing signal generation circuit described above will be described. First, the transistor Tr24 generates a voltage corresponding to the output current of the DAC 32, and the voltage is applied to the gate terminal of the transistor Tr23. Thereby, the transistor Tr23 can be operated as a variable resistor whose resistance value changes according to the voltage applied to the gate terminal. That is, the DAC 32 can control the on-resistance value of the transistor Tr23 by outputting a current having a weighted value to each of the transistors Tr23 of the amplifiers 31a to 31d. Thereby, the currents I1 to I4 output from the amplifiers 31a to 31d have amplitudes corresponding to the weights.
[0050]
As described above, when the amount of current output from the DAC 32 is increased, the voltage generated in the transistor Tr24 increases, and the resistance value between the drain terminal and the source terminal of the transistor Tr23 decreases. Further, when the amount of current output from the DAC 32 is decreased, the voltage of the transistor Tr24 is decreased and the resistance value between the drain terminal and the source terminal of the transistor Tr23 is increased. At this time, good control of the system can be performed by using a portion in which the on-resistance value linearly changes with respect to the change in voltage applied to the gate terminal in the transistor Tr23.
[0051]
As described above, the DAC 32 amplifier outputs the weighted output current to control the amplitudes of the four types of output currents I1 to I4 having different phases for phase synthesis, and the output current Io having an arbitrary phase is synthesized. Can be controlled.
[0052]
Next, as a third embodiment of the present invention, a timing signal generation circuit configured to realize phase synthesis by switching and adding the output paths of a plurality of transconductance amplifiers with a switch will be described. 5 and 6 are diagrams showing circuit configuration examples of the timing signal generation circuit according to the third embodiment of the present invention. FIG. 5 is a circuit that mainly performs phase synthesis processing of the clock signals Va and Vax, and FIG. 6 is a circuit that mainly performs phase synthesis processing of the clock signals Vb and Vbx, and the principle of phase synthesis is the same. FIG. 5 also includes a circuit configuration in which a signal obtained by phase combining clock signals Va and Vax and a signal obtained by phase combining clock signals Vb and Vbx are added. In FIG. 5 and FIG. 6, those given the same reference numerals as those in FIG.
[0053]
As shown in FIG. 5, transconductance amplifiers a1, a2,..., An (hereinafter referred to as amplifiers a1 to an) are composed of transistors Tr21 and Tr22 and a resistance element R. Here, n is an arbitrary natural number starting from 1. The connection relationship between the transistors Tr21 and Tr22 of the amplifiers a1 to an and the resistance element R and the connection relationship between the input signal and the current source 23 are the same as those of the amplifiers 22a to 22d shown in FIG.
[0054]
Further, the output currents I1 to In of the amplifiers a1 to an are added together via the switches S1, S2,..., Sn to become an output current Ioa. Similarly, in the circuit of FIG. 6, the output currents J1 to Jn of the amplifiers b1 to bn are added through the switches W1 to Wn to become the output current Iob. The output current Ioa and the output current Iob are added to form an output current Io, which is converted into a voltage by the resistance element 21 and output from the output terminal OUT.
[0055]
Next, the configuration of the switches S1 to Sn will be described. The switches S <b> 1 to Sn are current route (path) switching switches, and include transistors Tr <b> 10 to Tr <b> 13 and an inverter 41. The drain terminals of the transistors Tr10 and Tr11 of each of the switches S1 to Sn are connected to the output terminal OUT. The drain terminals of the transistors Tr12 and Tr13 of each of the switches S1 to Sn are connected to the output terminal OUTX. The source terminals of the transistors Tr10 and Tr12 of the switches S1 to Sn are respectively connected to the drain terminals of the transistors Tr21 of the amplifiers a1 to an. The source terminals of the transistors Tr11 and Tr13 of each switch S1 to Sn are connected to the drain terminals of the transistors Tr22 of the amplifiers a1 to an, respectively. Each of the switches S1 to Sn includes input terminals RTA1 to RTAn into which current route switching signals RTA1 to RTAn output from the switch control circuit 42 are input. The input terminals RTA1 to RTAn are connected to the gate terminals of the transistors Tr11 and Tr12 of the switches S1 to Sn. The input terminals RTA1 to RTAn are connected to the gate terminals of the transistors Tr10 and Tr13 of the switches S1 to Sn via the inverter 41.
[0056]
Further, the switch control circuit 42 generates and outputs current route switching signals RTA1 to RTAn and current route switching signals RTB1 to RTBn based on, for example, the control signal SE received from the phase comparison circuit 14 shown in FIG. The switches W1 to Wn in FIG. 6 have the same configuration as the switches S1 to Sn in FIG. 5 except that the input terminals RTB1 to RTBn are provided and the connection destinations are the amplifiers b1 to bn. Also, the amplifiers b1 to bn in FIG. 6 have the same configuration as the amplifiers a1 to an shown in FIG.
[0057]
Here, the principle of phase synthesis and the control method in the switch control circuit 42 in this embodiment will be described using the circuit shown in FIG. First, the operation of the amplifier a1 connected to the current route switching terminal RTA1 will be described. For example, when the switch control circuit 42 sets the current route switching terminal RTA1 to “L (low) level”, the transistors Tr10 and Tr13 are turned on and the transistors Tr11 and Tr12 are turned off. As a result, the amplifier a1 outputs a current I1 having the same phase as that of the clock signal Va input to the gate terminal of the transistor Tr21 to the output terminal OUT via the switch S1.
[0058]
For example, when the switch control circuit 42 sets the current route switching terminal RTA1 to “H (high) level”, the transistors Tr10 and Tr13 are turned off and the transistors Tr11 and Tr12 are turned on. Thereby, the amplifier a1 outputs the current I1x having the same phase as the clock signal Vax input to the gate terminal of the transistor Tr22 to the output terminal OUT via the switch S1. As described above, the switch control circuit 42 controls the amplifiers a1 to an to select either the currents I1 to In having the same phase as the clock signal Va or the currents I1x to Inx having the same phase as the clock signal Vax to output terminals. It can output to OUT and the output terminal OUTX.
[0059]
Next, the operation of the amplifiers a1 to an and the amplifiers b1 to bn shown in FIGS. 5 and 6 as a whole will be described.
For example, when the switch control circuit 42 sets all the current route switching signals RTA1 to RTAn and RTB1 to RTBn to “L (low)”, the output is obtained by adding the output currents of the amplifiers a1 to an and the amplifiers b1 to bn. The current change ΔIout visible at the terminal OUT is expressed by the following equation.

[0060]
From the above, the current change in the signal output from the output terminal OUT has a phase obtained by adding the same weight to the clock signal Va and the clock signal Vb. That is, an output having a phase located between the phase of the clock signal Va and the phase of the clock signal Vb is obtained from the output terminal OUT.
[0061]
For example, when the switch control circuit 42 sets all the current route switching signals RTA1 to RTAn to “L”, half of RTB1 to RTBn to “L”, and the other half to “H (high)”, the amplifiers a1 to a1 The current change ΔIout output from the output terminal OUT, which is the sum of the output currents of an and the amplifiers b1 to bn, is expressed by the following equation.

That is, the current change of the signal output from the output terminal OUT can be output in the same phase as the clock signal Va.
[0062]
As described above, the timing signal generation circuit according to the present embodiment has the clock signals Va, Vax, Vb, and the combination of setting “L” and “H” in the current route switching signal output from the switch control circuit 42. The currents corresponding to Vbx can be added together to be combined into an arbitrary phase and output.
[0063]
In the third embodiment described above, the switch control circuit 42 controls the number of “H” among the current route switching signals RTA1 to RTAn and RTB1 to RTBn to be constant. That is, an output signal having a constant amplitude can be output from the output terminal OUT by controlling the number of switches S1 to Sn and switches W1 to Wn that are turned on to be constant.
[0064]
Next, as a fourth embodiment of the present invention, a timing signal generation circuit configured to realize phase synthesis by switching and adding together output paths of two transconductance amplifiers having variable resistors will be described. . FIG. 7 is a diagram illustrating a circuit configuration example of a timing signal generation circuit according to the fourth embodiment of the present invention. As shown in FIG. 7, current route changeover switches SA and SB are connected to output sides of transconductance amplifiers A and B (hereinafter referred to as amplifiers A and B) including variable resistors, respectively. Further, the control unit 51 generates and outputs resistance value control signals for the current route switching signals RTA and RTB and the resistors RA and RB based on, for example, the control signal SE received from the phase comparison circuit 14 shown in FIG. .
[0065]
The configuration of the amplifiers A and B is the same as that of the amplifier 22a shown in FIG. 1, and the configuration of the switches SA and SB is the same as that of the switch S1 shown in FIG. The connection relationship between the amplifier A, the switch SA, and the output terminals OUT and OUTX is the same as the connection relationship between the amplifier a1, the switch S1, and the output terminals OUT and OUTX shown in FIG.
[0066]
Here, the change in the current value of the output signal at the output terminal OUT can be shown as follows by the combination of the current route switching signals RTA and RTB.
(1) RTA = L, RTB = L

(2) RTA = L, RTB = H

(3) RTA = H, RTB = H

(4) RTA = H, RTB = L

[0067]
FIG. 8 is a diagram showing the phase relationships g1 to g4 determined according to the combinations (1) to (4) of the four patterns of the current route switching signals RTA and RTB described above. That is, in the combinations (1) to (4) of the current route switching signals RTA and RTB, (1) is the intermediate phase g1 of the clock signals Va and Vb.
(2) is the intermediate phase g2 of the clock signals Va and Vbx
(3) is the intermediate phase g3 of the clock signals Vax and Vbx.
(4) is the intermediate phase g4 of the clock signals Vax and Vb.
It can be synthesized.
[0068]
As described above, similarly to the first to third embodiments described above, the timing signal generation circuit of this embodiment can also synthesize and output arbitrary phases. Further, in the case of the configuration of this embodiment, as can be seen from the other embodiments, the number of elements constituting the timing signal generation circuit is small and the influence of the parasitic capacitance of each element can be reduced. , Advantageous for high-speed operation.
[0069]
Next, as a fifth embodiment of the present invention, a timing signal generation circuit capable of making the output common mode voltage (center voltage of output change) constant by negative feedback will be described. FIG. 9 is a diagram illustrating a circuit configuration example of a timing signal generation circuit according to the fifth embodiment of the present invention. As shown in FIG. 9, transistors Tr30 and Tr31 are used as output loads, and an operational amplifier 51 and a capacitor 52 constitute negative feedback. The transistors Tr30 and Tr31 are p-type MOSFETs, and their source terminals are connected to a power source. The drain terminal of the transistor Tr30 is connected to the output terminal OUT and the input terminal 1 of the operational amplifier 51. The drain terminal of the transistor Tr31 is connected to the output terminal OUTX and the input terminal 2 of the operational amplifier 51. The output terminal of the operational amplifier 51 is connected to the gate terminals of the transistors 30 and 31, and is also connected to the ground via the capacitor 52.
[0070]
Further, in FIG. 9, the configurations having the same reference numerals as those in FIG. 1 such as the transconductance amplifiers 22a to 22d other than those described above are the same as those shown in FIG. That is, a configuration in which a negative feedback circuit is set instead of the resistance element 21 of the timing signal generation circuit in the first embodiment shown in FIG. 3 is a timing signal generation circuit according to an embodiment.
[0071]
The operational amplifier 51 outputs a signal obtained by amplifying the difference between the signal output to the output terminal OUT and the signal output to the output terminal OUTX, and the capacitor 52 flattens this. Thereby, the center voltage (DC component) in the change of the output signal of the operational amplifier 51 is supplied to the gate terminals of the transistors Tr30 and Tr31. That is, when the common mode voltage of the output terminal OUT and the output terminal OUTX increases, the voltage value supplied to the gate terminals of the transistors Tr30 and Tr31 also increases, and the current flowing through the transistors Tr30 and Tr31 decreases. Further, when the common mode voltage at the output terminal OUT and the output terminal OUTX decreases, the voltage value supplied to the gate terminals of the transistors Tr30 and Tr31 also decreases, and the current flowing through the transistors Tr30 and Tr31 increases. As described above, by providing the timing signal generation circuit with the negative feedback configuration shown in the fifth embodiment, the output common mode voltage can be stabilized.
[0072]
Here, the reason for stabilizing the output common mode voltage will be described. For example, in the case of the configuration shown in the first to fourth embodiments described above, the output voltage is determined by a resistive load (resistive element 21) connected to the power supply side. Further, the amplitude of the current change at the output terminal OUT is changed by a variable resistance value (for example, R1 to R4 in FIG. 1) or a current route switching switch (for example, the switch S1 in FIG. 5). That is, the output voltage amplitude also changes. Therefore, in order to improve the accuracy of phase synthesis, it is advantageous to stabilize the output common mode voltage.
The means shown in the fifth embodiment can be applied not only to the first embodiment but also to any configuration of the second to fourth embodiments.
[0073]
Note that the timing signal generation circuits shown in the second to fifth embodiments are also provided in the signal reception circuit 1 as the timing signal generation circuit 13 in FIG. 10 in the same manner as the timing signal generation circuit shown in the first embodiment. It is preferably incorporated. At this time, the two signals output from the output terminals OUT and OUTX correspond to, for example, the signal reproduction timing signal OUT and the change point detection timing signal OUTX in FIG.
[0074]
In the first embodiment described above, as the control signal SE output to the resistance value control unit 24 by the phase comparison circuit 14 shown in FIG. 10, for example, a plurality of bits for controlling the resistance values of the resistors R1 to R4, respectively. 4 types of resistance value control signals. Further, the control signal SE is not limited to the above, and a 1-bit control signal SE for transmitting that the phase comparison circuit 14 advances or slows the phase is output, and the resistance value control unit 24 decodes the control signal SE. For example, a resistance value control signal for controlling R1 to R4 may be generated.
[0075]
Similarly, in the second embodiment, the control signal SE output from the phase comparison circuit 14 shown in FIG. 10 to the DAC 32 is, for example, a control signal SE corresponding to the number of channels (4 channels) of the DAC 32 (for example, 8 bits each). ). In the third embodiment, the control signal SE output from the phase comparison circuit 14 shown in FIG. 10 to the switch control circuit 42 is, for example, a control signal SE that transmits the number of switches to be turned on. In the fourth embodiment, the control signal SE output from the phase comparison circuit 14 shown in FIG. 10 to the control unit 51 is, for example, a multi-bit resistance value control for controlling the resistance values of the resistors RA and RB, respectively. The control signal SE includes a signal and a switch control signal for turning on / off the switches SA and SB.
[0076]
The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes designs and the like that do not depart from the gist of the present invention.
The embodiment of the present invention can be applied variously as shown below, for example.
[0077]
(Supplementary Note 1) When phase combining is performed using a plurality of input signals having the same frequency and a plurality of types of phases, control means for outputting a control signal for controlling the weighting of the combination for each of the input signals;
A plurality of transconductances for receiving a plurality of the input signals and outputting a plurality of post-amplitude control signals having the same phase as each of the input signals and controlling the amplitude according to the control signal output by the control means; An amplifier,
Phase synthesizing means for outputting a timing signal obtained by adding and synthesizing the plurality of post-amplitude control signals output from the plurality of transconductance amplifiers;
A timing signal generation circuit comprising:
[0078]
(Additional remark 2) The said phase synthetic | combination means is the structure which outputs the said timing signal which added the said signal after amplitude control by connecting the output of several said transconductance amplifier, and was phase-synthesized. The timing signal generation circuit according to appendix 1.
[0079]
(Supplementary Note 3) When a plurality of sets of input signals having a phase difference of 180 degrees is input as a set, the transconductance amplifier includes at least two transistors, one variable resistance circuit, and two currents. A pair of input signals are input to the gate terminals of the two transistors, the resistance circuit is disposed between the source terminals of the two transistors, and the source terminals of the two transistors are respectively Two output currents that are grounded via the two current sources and that are 180 degrees out of phase from the drain terminals of the two transistors are output as the amplitude-controlled signals,
The control signal output by the control means is a signal for controlling a resistance value of the variable resistance circuit included in the transconductance amplifier.
The phase synthesizing unit is configured to separately connect the drain terminals that output two output currents in the plurality of transconductor amplifiers, and to connect the two output currents output from the plurality of transconductance amplifiers. It is a configuration that generates two timing signals that are 180 degrees different in phase by adding and phase-combining the signals after the amplitude control.
The timing signal generating circuit according to appendix 1, wherein:
[0080]
(Supplementary Note 4) The variable resistance circuit has a configuration in which a plurality of series-connected resistance elements and switches are connected in parallel between the source terminals of the two transistors.
The control signal output by the control means is a signal for controlling on / off of the switch of the variable resistance circuit.
4. The timing signal generating circuit according to appendix 3, wherein
[0081]
(Supplementary Note 5) The variable resistance circuit includes a resistance transistor and a voltage application circuit to a gate terminal of the resistance transistor, the source terminals of the two transistors are connected by the resistance transistor, and the voltage application The circuit is configured to control an on-resistance value of the resistance transistor by applying a voltage according to the control signal from the control means to a gate terminal of the resistance transistor.
The control signal output by the control means is a signal for controlling an on-resistance value of the resistance transistor.
4. The timing signal generating circuit according to appendix 3, wherein
[0082]
(Additional remark 6) The said phase synthetic | combination means is further provided with a switch, It is characterized by performing a phase synthesis | combination by selectively adding together the several said signal after amplitude control which the said several transconductance amplifier outputs. The timing signal generation circuit according to appendix 1.
[0083]
(Supplementary note 7) When the post-amplitude control signal is a current output, the phase synthesis unit that outputs the timing signal converted into a voltage value after adding the post-amplitude control signal and performing phase synthesis,
Average voltage value output means for outputting an average voltage value of the fluctuation of the voltage value;
Negative feedback control means for controlling negative feedback according to increase or decrease of the average voltage value output by the average voltage value output means to be applied to the voltage value;
Further comprising
4. The timing signal generating circuit according to appendix 3, wherein
[0084]
(Supplementary Note 8) When performing phase synthesis using a plurality of input signals having the same frequency and a plurality of types of phases, control means for outputting a control signal for controlling weighting of the synthesis for each of the input signals;
A plurality of transconductance amplifiers each receiving a plurality of the input signals and outputting a plurality of amplitude-controlled signals having the same phase and a constant amplitude as each of the input signals;
Phase synthesizing means for outputting a timing signal obtained by phase-synthesizing a plurality of post-amplitude control signals output from a plurality of transconductance amplifiers;
A timing signal generation circuit comprising:
[0085]
(Supplementary Note 9) The phase synthesizing unit is configured to output the timing signal obtained by adding the post-amplitude control signals and combining the phases by selectively connecting the outputs of the plurality of transconductance amplifiers with a switch circuit. 9. The timing signal generation circuit according to appendix 8, wherein the timing signal generation circuit is provided.
[0086]
(Supplementary Note 10) When a plurality of sets of input signals having a phase difference of 180 degrees is input as a set, the transconductance amplifier includes at least two transistors, one resistance circuit, and two current sources. The pair of input signals are respectively input to the gate terminals of the two transistors, the resistance circuit is disposed between the source terminals of the two transistors, and the source terminals of the two transistors are each 2 Two output currents that are grounded via the two current sources and that are 180 degrees out of phase with respect to the drain terminals of the two transistors, and output as amplitude-controlled signals;
The control signal output by the control means is a signal for controlling the output destinations of the two output currents output by the transconductance amplifier,
The phase synthesizing unit includes a plurality of switch circuits that switch connection between two drain terminals that respectively output two output currents of the plurality of transconductor amplifiers and two output terminals that output the timing signals. The switch circuit is switched in accordance with the control signal from the control means, so that the two output currents output from the plurality of transconductance amplifiers are selectively added as the amplitude-controlled signals to obtain a phase. It is the structure which synthesize | combines and produces | generates the two said timing signals which are 180 degrees different in phase.
9. The timing signal generating circuit according to appendix 8, wherein:
[0087]
(Appendix 11) The resistance circuit is a variable resistor,
The control signal output by the control means further includes a signal for controlling a resistance value of the resistance circuit.
11. The timing signal generation circuit according to appendix 10, wherein:
[0088]
(Additional remark 12) The said resistance circuit is the structure which connected in parallel the resistance element and switch which were connected in series between the source terminals of two said transistors,
The signal for controlling the resistance value of the resistance circuit included in the control signal output by the control means is a signal for controlling on / off of the switch of the resistance circuit.
12. The timing signal generating circuit according to appendix 11, wherein:
[0089]
(Additional remark 13) The said resistance circuit is comprised by the voltage application circuit to the gate terminal of a resistance transistor and the said resistance transistor, and connects between the source terminals of two said transistors by the said resistance transistor, The said voltage application circuit Is configured to control the on-resistance value of the resistance transistor by applying a voltage according to the control signal from the control means to the gate terminal of the resistance transistor,
The signal for controlling the resistance value of the resistance circuit included in the control signal output by the control means is a signal for controlling the on-resistance value of the resistance transistor.
12. The timing signal generating circuit according to appendix 11, wherein:
[0090]
(Supplementary Note 14) When the phase synthesis unit converts the timing signal after phase synthesis into a voltage value, the phase synthesis unit includes:
Average voltage value output means for outputting an average voltage value of the fluctuation of the voltage value;
Negative feedback control means for controlling negative feedback according to increase or decrease of the average voltage value output by the average voltage value output means to be applied to the voltage value;
Further comprising
11. The timing signal generation circuit according to appendix 10, wherein:
[0091]
(Supplementary Note 15) A timing signal generation circuit that outputs a clock signal whose phase is adjusted according to a change timing of an input signal, and receives and reproduces the input signal in synchronization with the clock signal output from the timing signal generation circuit A signal receiving circuit comprising a receiving circuit,
The timing signal generation circuit includes:
A control means for outputting a control signal for controlling a weight of synthesis for each of the clock signals when phase synthesis is performed using a plurality of clock signals having the same frequency and a plurality of types of phases;
A plurality of transconductances respectively receiving a plurality of the clock signals and outputting a plurality of post-amplitude control signals having the same phase as each of the clock signals and controlling the amplitude according to the control signal output by the control means; An amplifier,
Phase synthesizing means for outputting a timing signal obtained by adding and synthesizing the plurality of post-amplitude control signals output from the plurality of transconductance amplifiers;
Having
A signal receiving circuit.
[0092]
(Supplementary Note 16) The phase synthesizing unit of the timing signal generating circuit outputs the timing signal obtained by adding the signals after the amplitude control by connecting the outputs of the plurality of transconductance amplifiers and synthesizing the phase. 16. The signal receiving circuit according to appendix 15, wherein there is a signal receiving circuit.
[0093]
(Supplementary Note 17) In the timing signal generation circuit,
When a plurality of sets of clock signals having a phase difference of 180 degrees is input, the transconductance amplifier is composed of at least two transistors, one variable resistance circuit, and two current sources. The set of clock signals are respectively input to the gate terminals of the two transistors, the resistance circuit is disposed between the source terminals of the two transistors, and the source terminals of the two transistors are each the two currents. Two output currents that are grounded via a source and differ in phase by 180 degrees from the drain terminals of the two transistors, and output as the amplitude-controlled signal;
The control signal output by the control means is a signal for controlling a resistance value of the variable resistance circuit included in the transconductance amplifier.
The phase synthesizing unit is configured to separately connect the drain terminals that output two output currents in the plurality of transconductor amplifiers, and to connect the two output currents output from the plurality of transconductance amplifiers. It is a configuration that generates two timing signals that are 180 degrees different in phase by adding and phase-combining the signals after the amplitude control.
The signal receiving circuit according to appendix 15, characterized by:
[0094]
(Supplementary Note 18) In the timing signal generation circuit,
The variable resistance circuit has a configuration in which a plurality of resistance elements and switches connected in series are connected in parallel between the source terminals of two transistors.
The control signal output by the control means is a signal for controlling on / off of the switch of the resistance circuit.
18. The signal receiving circuit according to appendix 17, characterized by:
[0095]
(Supplementary Note 19) A timing signal generation circuit that outputs a clock signal whose phase is adjusted according to a change timing of an input signal, and receives and reproduces the input signal in synchronization with the clock signal output from the timing signal generation circuit A signal receiving circuit comprising a receiving circuit,
The timing signal generation circuit includes:
A control means for outputting a control signal for controlling a weight of synthesis for each of the clock signals when phase synthesis is performed using a plurality of clock signals having the same frequency and a plurality of types of phases;
A plurality of transconductance amplifiers each receiving a plurality of the clock signals and outputting a plurality of amplitude-controlled signals having the same phase and a constant amplitude as each of the clock signals;
Phase synthesizing means for outputting a timing signal obtained by phase-synthesizing a plurality of post-amplitude control signals output from a plurality of transconductance amplifiers;
Having
A signal receiving circuit.
[0096]
(Supplementary note 20) The timing of the phase synthesis unit of the timing signal generation circuit adds and combines the post-amplitude control signals by selectively connecting the outputs of the plurality of transconductance amplifiers by a switch circuit. 20. The signal receiving circuit according to appendix 19, wherein the signal receiving circuit is configured to output a signal.
[0097]
【The invention's effect】
As described above, in the timing signal generation circuit according to the present invention, for example, a plurality of transconductance amplifiers are input when phase synthesis is performed using a plurality of clock signals having a plurality of types of phases. A plurality of post-amplitude control signals having the same phase as that of the clock signal of which the amplitude is controlled can be output, and the phase synthesis means can add the post-amplitude control signals and output a timing signal obtained by phase synthesis. Here, the transconductance amplifier generally has a simple configuration including two transistors, one resistance circuit, and two current sources. In addition, the transconductor amplifier can output an amplitude-controlled signal whose amplitude is controlled accurately by controlling the resistance value of the resistance circuit in phase with the input clock signal. That is, the timing signal generating circuit according to the present invention can generate a plurality of timing signals having a predetermined phase difference with a simple configuration and high accuracy.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of a timing signal generation circuit according to a first embodiment of the present invention.
FIG. 2 is a diagram for explaining the operation of an amplifier 22a shown in FIG.
3 is a diagram showing an implementation example of resistors R1 to R4 in the timing signal generation circuit shown in FIG. 1; FIG.
FIG. 4 is a diagram illustrating a circuit configuration example of a timing signal generation circuit according to a second embodiment of the present invention.
FIG. 5 is a diagram illustrating a circuit configuration example of a timing signal generation circuit according to a third embodiment of the present invention.
FIG. 6 is a diagram illustrating a circuit configuration example of a timing signal generation circuit according to a third embodiment of the present invention.
FIG. 7 is a diagram illustrating a circuit configuration example of a timing signal generation circuit according to a fourth embodiment of the present invention.
FIG. 8 is a diagram showing a phase relationship determined according to combinations (1) to (4) of the four patterns of the current route switching signals RTA and RTB described above.
FIG. 9 is a diagram illustrating a circuit configuration example of a timing signal generation circuit according to a fifth embodiment of the present invention.
FIG. 10 is a block diagram illustrating an example of a clock recovery circuit.
FIG. 11 is a diagram showing the relationship between the phase difference ΔΦ between the signal reproduction timing signal OUT and the change point detection timing signal OUTX output from the timing signal generation circuit 13 and the input signal.
FIG. 12 is a diagram illustrating a circuit configuration example of a conventional timing signal generation circuit 13;
FIG. 13 is a diagram illustrating the principle of phase synthesis.
14 is a diagram for explaining the above-described problem, taking up a differential amplifier 202a that is one of the four differential amplifiers 202a to 202d shown in FIG. 12;
[Explanation of symbols]
1 Signal receiving circuit
11, 12 Receiver circuit
13 Timing signal generation circuit
14 Phase comparison circuit
21 Resistance element
22a to 22d transconductance amplifier (including variable resistance)
23 Current source
24 Resistance control unit
32 DAC
42 Switch control circuit
50 Control unit
51 operational amplifier
52 capacitors
Tr21 to Tr24 transistor (n-type MOSFET)
R1-R4 resistance (variable resistance)
r1 to rn resistance elements
SW1 to SWn switch
a1-an, b1-bn transconductance amplifier
S1-Sn, W1-Wn switch
Tr10 to Tr13 transistor (n-type MOSFET)
A, B transconductance amplifier
RA, RB resistance (variable resistance)
SA, SB switch
Tr30, Tr31 transistor (p-type MOSFET)

Claims (5)

Control means for outputting a control signal for controlling the weighting of each input signal when performing phase synthesis using a plurality of input signals having the same frequency and a plurality of types of phases;
A plurality of transconductances for receiving a plurality of the input signals and outputting a plurality of post-amplitude control signals having the same phase as each of the input signals and controlling the amplitude according to the control signal output by the control means; An amplifier,
A timing signal generating circuit comprising: a phase synthesizing unit that outputs a timing signal obtained by adding and synthesizing a plurality of the post-amplitude control signals output from the plurality of transconductance amplifiers. 2. The configuration according to claim 1, wherein the phase synthesizing unit is configured to output the timing signal obtained by combining the outputs of the plurality of transconductance amplifiers and adding the post-amplitude control signals to perform phase synthesis. The timing signal generation circuit described. When a plurality of sets of input signals having a phase difference of 180 degrees are input, the transconductance amplifier includes at least two transistors, one variable resistance circuit, and two current sources. The pair of input signals are respectively input to the gate terminals of the two transistors, the resistance circuit is disposed between the source terminals of the two transistors, and the source terminals of the two transistors are each the two currents Two output currents that are grounded via a source and differ in phase by 180 degrees from the drain terminals of the two transistors, and output as the amplitude-controlled signal;
The control signal output by the control means is a signal for controlling a resistance value of the variable resistance circuit included in the transconductance amplifier.
The phase synthesizing unit is configured to separately connect the drain terminals that output two output currents in the plurality of transconductor amplifiers together, and thereby to output the two output currents output from the plurality of transconductance amplifiers. 2. The timing signal generation circuit according to claim 1, wherein the timing signal generation circuit is configured to generate two timing signals having a phase difference of 180 degrees by adding and phase-combining the signals after amplitude control. Control means for outputting a control signal for controlling the weighting of each input signal when performing phase synthesis using a plurality of input signals having the same frequency and a plurality of types of phases;
A plurality of transconductance amplifiers each receiving a plurality of the input signals and outputting a plurality of amplitude-controlled signals having the same phase and a constant amplitude as each of the input signals;
A timing signal generating circuit comprising: a phase synthesizing unit that outputs a timing signal obtained by phase-synthesizing a plurality of post-amplitude control signals output from the plurality of transconductance amplifiers. A timing signal generation circuit that outputs a clock signal whose phase is adjusted according to a change timing of the input signal; and a reception circuit that receives and reproduces the input signal in synchronization with the clock signal output from the timing signal generation circuit. A signal receiving circuit comprising:
The timing signal generation circuit includes:
A control means for outputting a control signal for controlling a weight of synthesis for each of the clock signals when phase synthesis is performed using a plurality of clock signals having the same frequency and a plurality of types of phases;
A plurality of transconductances respectively receiving a plurality of the clock signals and outputting a plurality of post-amplitude control signals having the same phase as each of the clock signals and controlling the amplitude according to the control signal output by the control means; An amplifier,
A signal receiving circuit comprising: a phase synthesizing unit that outputs a timing signal obtained by adding and synthesizing a plurality of the amplitude-controlled signals output from the plurality of transconductance amplifiers.

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