JP2012028935A - Reception circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reception circuit capable of recovering output data with a small error.SOLUTION: A reception circuit includes: a phase adjustment circuit (202) for adjusting a phase of a clock signal in accordance with a phase adjustment code; a sampling circuit (112) for over-sampling data with respect to one unit interval in synchronization with the clock signal output by the phase adjustment circuit; a digital equalizer (204) for performing equalization processing on the data sampled by the sampling circuit; a clock data recovery circuit (210) for recovering output data based on the data equalized by the digital equalizer; and a control circuit (801) for designating a tracking system or a blind system. The control circuit compares an error when the tracking system is designated with an error when the blind system is designated, so as to designate the system with the smaller error.

Description

  The present invention relates to a receiving circuit.

  The clock data recovery circuit is a circuit that receives a signal on a transmission line in which a clock signal is superimposed on data and restores the data in digital communication.

  A multi-mode clock data recovery circuit having at least two operating modes, comprising a first connection including a recovered clock signal, the first connection being coupled to a controlled oscillator, the controlled oscillator being Providing a recovered clock signal on a first connection, a first operating mode, the first connection is coupled to a phase interpolator, and the phase interpolator provides a recovered clock signal on the first connection A multimode clock data recovery circuit having a second operation mode is known (see, for example, Patent Document 1).

  In addition, a voltage-controlled oscillator that outputs a clock signal having a bit rate frequency of the input data signal, a discriminator that identifies the input data signal based on the clock signal, and a phase comparison between the input data signal and the output signal of the discriminator In a clock data recovery circuit comprising a phase comparator and a low-pass filter that extracts a DC component from an output signal of the phase comparator and inputs it as a control voltage to a voltage controlled oscillator, a predetermined advance phase and delay with respect to the input data signal The phase reference signal that identifies the phase reference signal by the output signal of the discriminator, outputs a phase determination signal that indicates the phase relationship between the clock signal and the input data signal, and the clock signal output from the voltage-controlled oscillator are input to determine the phase. A variable phase shifter that outputs a clock signal in which the phase of the clock signal is changed according to the signal to the discriminator; Clock data recovery circuit, characterized in that it comprises are known (e.g., see Patent Document 2).

JP 2006-203908 A JP 2006-101268 A

  An object of the present invention is to provide a receiving circuit capable of restoring output data with a small error.

  A receiving circuit for adjusting a phase of a clock signal in accordance with a phase adjustment code; a sampling circuit for oversampling data for one unit interval in synchronization with the clock signal output by the phase adjusting circuit; A digital equalization circuit that performs equalization processing on the data sampled by the sampling circuit, a clock data recovery circuit that restores output data based on the data equalized by the digital equalization circuit, and tracking The clock data recovery circuit includes a boundary of one unit interval of the data equalized by the digital equalization circuit and an estimated value of the boundary of the one unit interval. A phase detection circuit that detects the phase error and A low-pass filter for low-pass filtering the phase error detected by the phase detection circuit; and a determination circuit for restoring output data based on the data equalized by the digital equalization circuit. When the tracking method is specified, the phase of the clock signal is adjusted according to the phase adjustment code that is output by the low-pass filter, and when the blind method is specified, the phase of the clock signal is fixed. When the tracking method is designated, the determination circuit outputs the output data using data sampled for the center of one unit interval among the data equalized by the digital equalization circuit. When the blind method is specified, the low-pass filter The data sampled closest to the center of one unit interval among the data equalized by the digital equalization circuit based on the signal that is equalized is restored to the output data, and the control circuit is An error when the tracking method is specified for the phase adjustment circuit and the determination circuit is compared with an error when the blind method is specified for the phase adjustment circuit and the determination circuit. The smaller method is designated for the phase adjustment circuit and the determination circuit.

  Since the method with the smaller error between the tracking method and the blind method is designated, the output data with the smaller error can be restored.

It is a figure which shows the structural example of the communication system by embodiment. 2A and 2B are diagrams showing a receiving circuit of the tracking CDR system. 3A and 3B are diagrams showing the phase adjustment circuit of FIG. 4A and 4B are diagrams showing more specific configuration examples of the phase adjustment circuit of FIG. 3A. It is a figure which shows the structural example of the digital equalization circuit of FIG. FIGS. 6A and 6B are diagrams illustrating a blind CDR reception circuit. 7A to 7C are diagrams for explaining the problems of the tracking CDR method. It is a figure which shows the structural example of the receiving circuit by this embodiment. 9A and 9B are diagrams illustrating a configuration example of the control circuit. It is a flowchart which shows the system designation | designated method of a receiving circuit. It is a figure which shows the structural example of the phase detection circuit of FIG. FIG. 12A is a diagram illustrating the characteristics of the first phase detection circuit, and FIG. 12B is a diagram illustrating the characteristics of the second phase detection circuit. It is a flowchart which shows the other system designation | designated method of a receiving circuit.

  FIG. 1 is a diagram illustrating a configuration example of a communication system according to an embodiment. The communication system includes a transmission circuit 101 and a reception circuit 103. The transmission circuit 101 and the reception circuit 103 are connected by a transmission line 102 and perform signal transmission within a semiconductor chip, signal transmission between semiconductor chips, or signal transmission between boards or housings. The transmission circuit 101 has a driver 131. The reception circuit 103 includes an analog equalization (EQ) circuit 111, an analog / digital converter 112, a digital equalization circuit, and a clock data recovery (CDR) circuit 113.

  The transmission circuit 101 amplifies the signal of the input terminal IN by the driver 131 and outputs the digital signal 121 to the reception circuit 103 via the transmission line 102. The receiving circuit 103 receives the signal 122. Since the high-frequency component of the transmission signal 121 is lost by the transmission line 102, the waveform of the reception signal 122 of the reception circuit 103 deteriorates. Since the data cannot be received correctly as it is, the reception circuit 103 performs equalization processing with the equalization circuits 111 and 113, and performs timing extraction and data determination with the clock data recovery circuit 113.

  Hereinafter, processing of the receiving circuit 103 will be described. First, the analog equalization circuit 111 outputs a signal 123 in which the signal 122 whose waveform has deteriorated due to the loss of the transmission line 102 is recovered to some extent by equalization processing. The analog-digital converter 112 samples the analog signal 123 and outputs a digital signal 124. The digital equalization circuit 113 generates a signal in which the waveform deterioration of the digital signal 124 is recovered to an appropriate level by equalization processing. The clock data recovery circuit 113 performs data phase estimation and data determination based on this signal, and outputs the output data 125 to the output terminal OUT. The analog-digital converter 112 may be a comparator and may be a sampling circuit that samples data.

  In the present embodiment, the tracking CDR method or the blind CDR method can be selected. In the tracking CDR method, the receiving circuit 103 adjusts the phase of the sampling clock signal of the analog-digital converter 112 based on the phase information estimated by the clock data recovery circuit 113. In this way, by sampling data at appropriate timing, the error rate can be made sufficiently low. In the blind CDR method, the clock data recovery circuit 113 determines data based on the estimated phase information. In this way, it is possible to sufficiently reduce the error rate by restoring data at an appropriate timing. The receiving circuit 103 performs processing by the tracking CDR method of FIG. 2A when the tracking CDR method is designated, and performs processing by the blind CDR method of FIG. 6A when the blind CDR method is designated.

  2A is a diagram showing a configuration example of the tracking CDR type receiving circuit 103, and FIG. 2B is a diagram showing input data 221 and reception clock signals 222 and 223. The analog equalization circuit 111 outputs a signal obtained by recovering the input signal of the terminal IN1 deteriorated by the transmission line 102 by the equalization process. The phase lock loop (PLL) circuit 201 generates, for example, a four-phase clock signal based on the reference clock signal at the terminal CLK, and outputs the clock signal to the phase adjustment circuit 202. The phase adjustment circuit 202 receives a four-phase clock signal and outputs clock signals 222 and 223 whose phases are adjusted based on the phase adjustment code output from the low-pass filter 206 to the analog-to-digital converter 112. The input data 221 can change in units of one unit interval (UI) 224. One unit interval 224 is a duration of one data bit and one cycle of the bit clock. The clock signal 222 is a sampling clock signal for the center of one unit interval 224. The clock signal 223 is a sampling clock signal for the boundary of 1 unit interval 224. The analog-digital converter 112 samples the analog input data 221 in synchronization with the rising edges of the clock signals 222 and 223, and outputs a digital signal. Data near the center of the 1-unit interval 224 of the input data 221 is sampled in synchronization with the rising edge of the clock signal 222, and near the boundary of the 1-unit interval 224 of the input data 221 in synchronization with the rising edge of the clock signal 223. Are sampled. The phase of one unit interval 224 is determined by the oscillator of the transmission circuit 101 for the input data 221, and the phase of the clock signals 222 and 223 is determined by the oscillator of the reception circuit 103. For this reason, the phase of the boundary of the 1-unit interval 224 of the input data 221 and the phase of the rising edge of the clock signal 223 do not necessarily match. Therefore, the phase adjustment circuit 202 adjusts the phases of the clock signals 222 and 223 in accordance with the phase adjustment code so that the phases of both coincide. The analog-to-digital converter 112 is a sampling circuit that oversamples data twice with respect to one unit interval 224 in synchronization with rising edges of the clock signals 222 and 223.

  The demultiplexing circuit 203 converts the data output from the analog / digital converter 112 from serial to parallel and outputs the data to the digital equalization circuit 204. The demultiplexing circuit 203 reduces the bit rate of the digital signal to a bit rate that can be processed by a subsequent circuit. The demultiplexing circuit 203 can be omitted.

  The digital equalization circuit 204 performs equalization processing on the output data of the demultiplexing circuit 203 and recovers the signal deteriorated by the transmission line 102. At this time, the digital equalization circuit 204 updates the internal coefficient so that the error in the equalization process approaches 0, and also updates the coefficient of the analog equalization circuit 111.

  The clock data recovery circuit 210 includes a phase detection circuit 205, a low-pass filter 206, and a determination circuit 207. The phase detection circuit 205 detects a change point of input data and determines that the change point is a boundary of one unit interval 224. Since data has randomness in the medium to long term, the boundary of one unit interval 224 can be estimated by processing one unit interval of a plurality of periods. The phase detection circuit 205 detects a boundary phase error of the 1 unit interval 224 of the data output from the digital equalization circuit 204 with respect to the estimated boundary phase of the 1 unit interval 224. That is, the phase detection circuit 205 detects a phase error between the boundary of the 1 unit interval 224 and the estimated value of the boundary of the 1 unit interval 224 of the data equalized by the digital equalization circuit 204.

  The low-pass filter 206 performs low-pass filtering on the phase error detected by the phase detection circuit 205 and outputs the filtered signal to the phase adjustment circuit 202 as a phase adjustment code. The low-pass filter 206 integrates the phase error and suppresses the sensitive response of the phase adjustment. The phase adjustment circuit 202 adjusts the phases of the clock signals 222 and 223 based on the phase adjustment code. Thus, the phase of the rising edge of the clock signal 223 matches the boundary phase of the 1 unit interval 224 of the input data 221, and the phase of the rising edge of the clock signal 222 is the center of the 1 unit interval 224 of the input data 221. Match the phase.

  The determination circuit 207 restores the output data using the data sampled by the center clock signal 222 in the unit interval 224 of the data equalized by the digital equalization circuit 204. The data near the boundary of one unit interval 224 is an indefinite value because it is a change point, and the data near the center of one unit interval 224 is stable data. Compared to the data sampled by the rising edge of the clock signal 223, the data sampled by the rising edge of the clock signal 222 is data closer to the center of the one unit interval 224. Therefore, the determination circuit 207 selects sampled data in synchronization with the rising edge of the clock signal 222, determines the data as 0/1, and outputs the output data to the output terminal OUT. When the data level is greater than the threshold, the data is determined to be 1, and when the data level is less than the threshold, the data is determined to be 0. As a result, the clock data recovery circuit 210 can restore the data.

  3A is a diagram illustrating a configuration example of the phase adjustment circuit 202 in FIG. 2A, and FIG. 3B is a time chart for explaining the operation of the phase adjustment circuit 202. For example, the clock signal θ0 is a clock signal having a phase of 0 degrees, the clock signal θ1 is a clock signal having a phase of 90 degrees, the clock signal θ2 is a clock signal having a phase of 180 degrees, and the clock signal θ3 is a clock signal having a phase of 270 degrees, for example. Signal.

  The voltage-current conversion circuit 301 converts the differential clock signals θ0 and θ2 from voltage to current, and outputs them to the capacitors 303 and 304. Thus, a triangular wave signal SA as shown in FIG. 3B can be generated. The differential amplifier 307 amplifies the signal SA and the like stored in the capacitors 303 and 304 with a weighting coefficient w, and outputs a signal w × SA and its phase inversion signal.

  The voltage / current conversion circuit 302 converts the differential clock signals θ 1 and θ 3 from voltage to current, and outputs them to the capacitors 305 and 306. Thereby, a triangular wave signal SB or the like as shown in FIG. 3B can be generated. The differential amplifier 308 amplifies the signal SB and the like stored in the capacitors 305 and 306 with a weighting coefficient 1-w, and outputs a signal (1-w) × SB and its phase inverted signal.

  The comparator 309 inputs a signal SC or the like obtained by combining the output signals of the differential amplifiers 307 and 308. The signal SC is a signal obtained by combining the signal w × SA and the signal (1-w) × SB, and is represented by w × SA + (1-w) × SB. The comparator 309 outputs a signal φ0 corresponding to the comparison result of the two input signals and its logical inversion signal φ2. The comparator 309 outputs a high level signal φ0 when one of the two input signals is larger than the other signal, and outputs a low level signal φ0 when it is smaller. That is, the comparator 309 converts the input signal SC into a rectangular wave signal φ0 and outputs it. The clock signal φ0 corresponds to the clock signal 222 in FIG. 2B, and the clock signal φ2 corresponds to the clock signal 223 in FIG. By changing the weighting coefficient w by the phase adjustment code, the phases of the clock signals φ0 and φ2 can be changed.

  FIG. 4A is a circuit diagram illustrating a more specific configuration example of the phase adjustment circuit 202 in FIG. In the current digital-to-analog converter 440, a plurality of series connection circuits of p-channel field effect transistors 441 and switches 442 are connected in parallel. The gate of the transistor 441 is connected to a fixed bias potential node. A plurality of switches 442 are turned on or off according to the phase adjustment code. The current digital-to-analog converter 440 outputs an analog current having weighting coefficients w0 to w3 corresponding to the phase adjustment code to the circuits 421 to 424.

  The circuit 421 for the weighting coefficient w0 includes field effect transistors 431 to 433. In the p-channel field effect transistor 431, the source is connected to the power supply potential node, and the gate is connected to the drain. The n-channel field effect transistor 432 has a drain connected to the drain of the transistor 431, a gate connected to the output terminal of the current digital-to-analog converter 440, and a source connected to the ground potential node. The n-channel field effect transistor 433 has a drain and a gate connected to the output terminal of the current digital-to-analog converter 440 and a source connected to the ground potential node.

  The weighting coefficients w1 to w3 circuits 422 to 424 have the same configuration as the weighting coefficient w0 circuit 421, and input the analog currents of the weighting coefficients w1 to w3 from the current digital-to-analog converter 440. The circuits 421 to 424 output the voltages of the weighting coefficients w0 to w3 to the voltage / current conversion circuits 401 to 404.

  By connecting elements 451-457 to nodes N1 and N2, nodes N1 and N2 become capacitive nodes. The node N1 is connected to the ground potential node through the resistor 454 and the capacitor 456, and the node N2 is connected to the ground potential node through the resistor 455 and the capacitor 457.

  The voltage-current conversion circuit 401 includes field effect transistors 411 to 416. The p-channel field effect transistor 415 has a source connected to the power supply potential node and a gate connected to the drain of the p-channel field effect transistor 431 in the circuit 421. The n-channel field effect transistor 416 has a source connected to the ground potential node and a gate connected to the drain of the transistor 433 in the circuit 421. In the p-channel field effect 411, the source is connected to the drain of the transistor 415, the gate is connected to the node of the clock signal θ0, and the drain is connected to the node N1. In the n-channel field effect transistor 412, the drain is connected to the node N 1, the gate is connected to the node of the clock signal θ 0, and the source is connected to the drain of the transistor 416. In the p-channel field effect 413, the source is connected to the drain of the transistor 415, the gate is connected to the node of the clock signal θ2, and the drain is connected to the node N2. The n-channel field effect transistor 414 has a drain connected to the node N2, a gate connected to the node of the clock signal θ2, and a source connected to the drain of the transistor 416.

  The voltage-current conversion circuits 402 to 404 have the same configuration as the voltage-current conversion circuit 401 and are connected to the circuits 422 to 424, respectively. The voltage / current conversion circuit 402 receives clock signals θ1 and θ3, the voltage / current conversion circuit 403 inputs clock signals θ2 and θ0, and the voltage / current conversion circuit 404 inputs clock signals θ3 and θ1.

  The voltage-current conversion circuits 401 to 404 can generate and add a triangular wave by outputting the current amplified by the weighting coefficients w0 to w3 to the capacitive nodes N1 and N2. The comparator 460 outputs rectangular-wave clock signals φ0 and φ2 similarly to the comparator 309 in FIG.

  FIG. 4B is a graph showing the phase adjustment code of the phase adjustment circuit 202 of FIG. 4A and the phase delay time of the clock signal φ0. A characteristic 471 indicates a characteristic according to a simulation result, and a characteristic 472 indicates an ideal characteristic. By changing the phase adjustment code between 0 and 16, a phase delay time of 0 to 100 [ps] = 0 to π / 4 [rad] can be realized. The error 473 indicates an error of the simulation characteristic 471 with respect to the ideal characteristic 472 and is 1 [ps] or less. The phase adjustment circuit 202 can linearly adjust the delay times of the clock signals φ0 and φ2 by the phase adjustment code.

  FIG. 5 is a diagram illustrating a configuration example of the digital equalization circuit 204 in FIG. The analog equalization circuit 111 in FIG. 2A also has a configuration similar to that of the digital equalization circuit 204. Multiplier 500 multiplies the data at input terminal IN2 by coefficient c0 and outputs the result. The m adders 521 to 52m add and output the output signals of the m + 1 multipliers 500 to 50m. Here, m is a positive integer. The switch 531 is connected to the training data node TR in the initialization mode, and is connected to the output terminal of the adder 521 in the normal mode.

  First, the initialization mode will be described. In the initialization mode, the transmission circuit 101 in FIG. 1 transmits a predetermined training data string. The same data as the training data string is input to the training data node TR. The slicer circuit 532 binary-determines the training data of the training data node TR and outputs 1-bit digital data “0” or “1”. The m delay circuits 511 to 51m are flip-flop circuits, for example, and are connected in series to delay the output data of the slicer circuit 532. The delay circuit 511 outputs data delayed by one cycle. The delay circuit 51m outputs data delayed by m cycles. The m multipliers 501 to 50m multiply the output data of the m delay circuits 511 to 51m by coefficients c1 to cm, respectively. The adder 521 outputs data obtained by adding data weighted by coefficients c0 to cm to current data and past data. The subtracter 533 subtracts the output data of the adder 521 from the output data of the slicer circuit 532, and outputs an error ER1. The calculator 535 squares the error (voltage) ER1 and outputs an error (power) ER2. The coefficient updating unit 534 updates the coefficients c0 to cm of the multipliers 500 to 50m so that the error ER1 approaches zero. By this feedback loop processing, the coefficients c0 to c0 that minimize the error ER1 can be determined. The slicer circuit 536 performs binary determination on the output data of the adder 521 and outputs 1-bit digital data “0” or “1” to the output terminal OUT2.

  Next, the normal mode will be described. Hereinafter, differences from the initialization mode will be described. The switch 531 is connected to the output terminal of the adder 521. The slicer circuit 532 performs binary determination on the output data of the adder 521 and outputs 1-bit digital data of “0” or “1”. The coefficient updating unit 534 updates the coefficients c0 to cm so that the error ER1 is minimized as in the initialization mode.

  6A is a diagram illustrating a configuration example of the receiving circuit 103 of the blind CDR system, and FIG. 6B is a diagram illustrating the input data 221 and the reception clock signals 222 and 223. Hereinafter, differences from the tracking CDR receiving circuit 103 in FIG. 2A will be described. The phase lock loop circuit 201 generates the clock signals 222 and 223 in FIG. 6B based on the reference clock signal at the terminal CLK, and outputs the clock signals 222 and 223 to the analog-digital converter 112. The phases of the clock signals 222 and 223 are fixed. Therefore, the phases of the clock signals 222 and 223 are independent of the phase of the input data 221.

  The clock data recovery circuit 210 includes a phase detection circuit 205, a low-pass filter 206, and a determination circuit 207. The determination circuit 207 selects and outputs the data sampled closest to the center of one unit interval 224 from the data equalized by the digital equalization circuit 204 based on the signal filtered by the low-pass filter 206. Restore data. The output signal of the low pass filter 206 means the phase from the boundary of the 1 unit interval 224. The phase of the center of one unit interval 224 is a half phase of the period of one unit interval 224. Therefore, the determination circuit 207 can determine the phase of the center of the 1-unit interval 224 based on the output signal of the low-pass filter 206. The determination circuit 207 inputs data synchronized with the rising edge of the clock signal 222 and data synchronized with the rising edge of the clock signal 223, and data sampled closest to the center of one unit interval 224 of those data. Select to output a binary judgment of the output data. For example, the determination circuit 207 selects data synchronized with the rising edge of the clock signal 222 as data sampled closest to the center of the 1-unit interval 224.

  The period Td of the input data 221 and the period Ts of the sampling clock signals 222 and 223 are preferably the same. However, the periods Td and Ts may differ due to a difference in oscillation frequency between the oscillator of the transmission circuit 101 and the oscillator of the reception circuit 102. When the periods Td and Ts are substantially the same and one restoration data is output from the output terminal OUT for one unit interval 224, the determination circuit 207 sends slip information indicating that the data is normal from the terminal SI. Output. When the period Td is larger than the period Ts and two or more restoration data are output from the output terminal OUT for one unit interval 224, the determination circuit 207 displays slip information indicating that too much data is taken. Output from SI. In this case, unnecessary data is discarded by the subsequent circuit. Further, when the period Td is smaller than the period Ts and no data can be output from the output terminal OUT for one unit interval 224, the determination circuit 207 indicates slip information indicating that data is missed at the terminal SI. Output from. In this case, the subsequent circuit requests the transmission circuit 101 to retransmit.

  Note that the clock data recovery circuit 210 in FIG. 2A may output the clock signal 222 and / or 223 adjusted in phase by the phase adjustment circuit 202 to the subsequent stage together with the recovered data as a recovered clock. In addition, the clock data recovery circuit 210 in FIG. 6A may output the clock signal 222 and / or 223 generated by the phase lock loop circuit 201 to the subsequent stage together with the restoration data.

  In the tracking CDR method (FIG. 2A), the phase of the sampling clock signals 222 and 223 is adjusted in accordance with the phase of the input data 221. Therefore, in the absence of noise, the blind CDR method (FIG. 6A) The phase error is small and the error rate of the restored data is low. However, when noise occurs, the tracking CDR method may be worse than the blind CDR method.

  The problem of the tracking CDR method will be described with reference to FIGS. FIG. 7A is a time chart showing the relationship between time (cycle time) and the phase of the sampling clock signals 222 and 223, and FIG. 7B is a time chart showing the relationship between time and the phase adjustment code. FIG. 7C is a diagram showing a multi-bit phase adjustment code output from the low-pass filter 206 to the phase adjustment circuit 202.

  As shown in FIG. 7C, the low pass filter 206 outputs the phase adjustment code to the phase adjustment circuit 202 via a plurality of signal lines. The plurality of signal lines generate a skew of the phase adjustment code by long-distance transmission, and different skews are generated between the plurality of signal lines. For example, a case where the phase adjustment code is changed from “10” to “01” in the case of a 2-bit phase adjustment code using two signal lines will be described. In that case, due to the skew deviation between the signal lines, as shown in FIG. 7B, during the transition from the phase adjustment code “10” in the period T1 to the phase adjustment code “01” in the period T3, The phase adjustment code “00” may be generated. That is, first, 2LSB of the second bit of the phase adjustment code is changed from “1” to “0”, and then 1LSB of the first bit of the phase adjustment code is converted from “0” to “1”. is there. In this case, as shown in FIG. 7A, the phase adjustment code is “10” before time t1, and the phase adjustment code starts changing from “10” to “00” at time t1. Thereafter, the phase adjustment code changes from “00” to “01”, and the phase adjustment code is stabilized to “01” after time t2. Ideally, the phase fluctuation amount 702 when the phase adjustment code changes from “10” to “01” is −30 [ps]. However, due to skew deviation, phase error jitter 701 continues to occur for several cycles. This jitter 701 becomes a factor that lowers the error rate of the tracking CDR method, and the tracking CDR method has a lower error rate than the blind CDR method.

  In order to avoid the occurrence of such jitter 701, a method of using a flip-flop circuit 712 as a deskew circuit as shown in FIG. The flip-flop circuit 712 holds the phase adjustment code in synchronization with the clock signal CLK1. However, in this case, the buffer 711 for transmitting the clock signal CLK1 and the phase adjustment code for a long distance is necessary, and the flip-flop circuit 712 for deskew is also arranged, so these circuits become noise generation sources. Jitter may be generated.

  Therefore, the tracking CDR method does not always have a lower error rate than the blind CDR method. Depending on the environment used, the error rate may be lower in the tracking CDR method and the error rate may be lower in the blind CDR method.

  FIG. 8 is a diagram illustrating a configuration example of the receiving circuit 103 according to the present embodiment. The receiving circuit 103 of the present embodiment can switch between the tracking CDR system of FIG. 2A and the blind CDR system of FIG. Hereinafter, differences between the receiving circuit 103 in FIG. 8 and the receiving circuit 103 in FIG. 2A and the receiving circuit 103 in FIG. 6A will be described.

  The phase adjustment circuit 202 adjusts the phases of the clock signals 222 and 223 in accordance with the phase adjustment code B1. The analog-digital converter (sampling circuit) 112 oversamples data for one unit interval 224 in synchronization with the clock signals 222 and 223 output by the phase adjustment circuit 202. The digital equalization circuit 204 receives the output signal of the demultiplexing circuit 203 and performs equalization processing on the data sampled by the analog-digital converter 112. The clock data recovery circuit 210 restores the output data based on the data equalized by the digital equalization circuit 204 and outputs it to the output terminal OUT.

  The clock data recovery circuit 210 includes a phase detection circuit 205, a low-pass filter 206, and a determination circuit 207. The phase detection circuit 205 detects a phase error between the boundary of the 1 unit interval 224 and the estimated value of the boundary of the 1 unit interval 224 of the data equalized by the digital equalization circuit 204. The low-pass filter 206 performs low-pass filtering on the phase error detected by the phase detection circuit 205. The determination circuit 207 restores the output data based on the data equalized by the digital equalization circuit 204 and outputs it to the terminal OUT.

  The control circuit 801 specifies a tracking CDR method or a blind CDR method. When the tracking CDR method is designated, the receiving circuit 103 performs the processing of the tracking CDR method shown in FIG. On the other hand, when the blind CDR method is designated, the receiving circuit 103 performs the blind CDR method shown in FIG.

  When the tracking CDR method is designated, the phase adjustment circuit 202 adjusts and outputs the phases of the clock signals 222 and 223 according to the phase adjustment code B1, which is the signal F1 output from the low-pass filter 206, and the blind CDR method is used. When specified, the phase of the clock signals 222 and 223 is fixed and output.

  When the tracking CDR method is designated, the determination circuit 207 restores the output data using the data sampled for the center of one unit interval 224 among the data equalized by the digital equalization circuit 204, When the blind CDR method is designated, the data sampled closest to the center of one unit interval 224 among the data equalized by the digital equalization circuit 204 based on the signal F1 filtered by the low-pass filter 206. Select to restore the output data. Further, when the blind CDR method is designated, the determination circuit 207 outputs slip information from the terminal SI as in the blind CDR method of FIG.

  The control circuit 801 compares the error when the tracking CDR method is specified for the phase adjustment circuit 202 and the determination circuit 207 with the error when the blind CDR method is specified for the phase adjustment circuit 202 and the determination circuit 207. Then, the method with the smaller error is designated to the phase adjustment circuit 202 and the determination circuit 207.

  Next, three examples of error comparison methods of the control circuit 801 will be described. First, the first comparison method of the control circuit 801 will be described. The control circuit 801 compares the equalization error ER2 of the digital equalization circuit 204 when the tracking CDR method is designated with the equalization error ER2 of the digital equalization circuit 204 when the blind CDR method is designated. To do. The error ER2 is an error output from the calculator 535 of the digital equalization circuit 204 in FIG.

  Next, a second comparison method of the control circuit 801 will be described. The control circuit 801 compares the phase error A2 detected by the phase detection circuit 205 when the tracking CDR method is designated with the phase error A2 detected by the phase detection circuit 205 when the blind CDR method is designated. Specifically, the control circuit 801 has a low-pass filter, and compares the phase errors obtained by filtering the phase error A2 with the low-pass filter. A low-pass filter inside the control circuit 801 performs short-term filtering on the low-pass filter 206. The control circuit 801 uses a low-pass filter to compare temporal fluctuation amounts of the phase error.

  Next, a third comparison method of the control circuit 801 will be described. The control circuit 801 outputs the error in the output data of the terminal OUT restored by the determination circuit 207 when the tracking CDR method is designated, and the output data of the terminal OUT restored by the decision circuit 207 when the blind CDR method is designated. Compare the error. Specifically, the control circuit 801 compares the restoration data of the terminal OUT output from the determination circuit 207 and the training data of the training data node TR, and compares the errors. As described above, the training data is expected value data used in the initialization process. In addition, the control circuit 801 compares the error in consideration of the slip information of the terminal SI output from the determination circuit 207.

  Further, the control circuit 801 controls the phase detection circuit 205 by the control signal B2 and controls the digital equalization circuit 204 by the control signal B3 according to the error.

  FIG. 11 is a diagram illustrating a configuration example of the phase detection circuit 205 of FIG. The phase detection circuit 205 includes a first phase detection circuit 1101, a second phase detection circuit 1102, and a selector 1103. The data G1 is data sampled by the sampling clock signal 222. The data G2 is data sampled by the sampling clock signal 223. The control circuit 801 in FIG. 8 can designate either the first phase detection circuit 1101 or the second phase detection circuit 1102 by the control signal B2. When the first phase detection circuit 1101 is designated by the control signal B2, the first phase detection circuit 1101 receives the data G1 and G2 and outputs a phase error in the same manner as the phase detection circuit 205 described above. When the second phase detection circuit 1102 is designated by the control signal B2, the second phase detection circuit 1102 receives data G1 and G2 and outputs a phase error in the same manner as the phase detection circuit 205 described above. The selector 1103 selects and outputs the output signal of the first phase detection circuit 1101 when the first phase detection circuit 1101 is designated by the control signal B2, and the second phase detection circuit 1102 designates by the control signal B2. Then, the output signal of the second phase detection circuit 1102 is selected and output.

  FIG. 12A is a diagram illustrating the characteristics of the first phase detection circuit 1101. The first phase detection circuit 1101 is a Bang-bang type phase detection circuit. When the first phase detection circuit 1101 is designated, the data equalized by the digital equalization circuit 204 is converted into binary data. The phase error is detected after conversion. The phase θd is the phase of the input data 221. The phase θc is the phase of the sampling clock signals 222 and 223. The data is assumed to be binary data “−1” and “+1”. Here, consider a case where data transitions from “−1” to “+1”. In the first phase detection circuit 1101, the data is “−1” when the phase difference θd−θc is a negative value, and the data is “+1” when the phase difference θd−θc is a positive value. However, when the phase difference θd−θc is 0, since it is a data change point, it becomes an indefinite value, and the data accuracy is lowered. The first phase detection circuit 1101 can realize the characteristics shown in FIG. 2A by using a flip-flop circuit, and thus has an advantage that the configuration is simple and power consumption can be reduced.

  FIG. 12B is a diagram illustrating characteristics of the second phase detection circuit 1102. The second phase detection circuit 1102 is a linear interpolation type phase detection circuit. When the second phase detection circuit 1102 is designated, the data equalized by the digital equalization circuit 204 is ternary with respect to the phase. The phase error is detected by linear conversion into the above data. The input data is binary data of “−1” and “+1”, and the binary data is converted into multi-value data of three or more values in the range of −1 to +1. Here, consider a case where the input data transitions from “−1” to “+1”. The second phase detection circuit 1102 linearly interpolates data according to the phase difference θd−θc. As a result, there is an advantage that the data accuracy is high even in the vicinity of the data change point where the phase difference θd−θc is zero. However, the second phase detection circuit 1102 can realize the characteristics shown in FIG. 2B by using a linear interpolation circuit, but there is a problem that the configuration is complicated and power consumption increases.

  As described above, the first phase detection circuit 1101 has an advantage of low power consumption and has a defect of low accuracy. On the other hand, the second phase detection circuit 1102 has an advantage of high accuracy and a disadvantage of high power consumption. Therefore, if the error can be suppressed below the threshold value, it is preferable to use the first phase detection circuit 1101 as much as possible to reduce power consumption. However, if the first phase detection circuit 1101 is used and the error becomes larger than the threshold value, it is necessary to use the second phase detection circuit 1102 with high accuracy.

  The control circuit 801 designates the first phase detection circuit 1101 when the error when the first phase detection circuit 1101 is designated is less than or equal to the threshold value, and the error when the first phase detection circuit 1101 is designated is the threshold value. When it is larger, the second phase detection circuit 1102 is designated. As the error, the error shown in the above first to third comparison methods is used.

  Next, a method in which the control circuit 801 controls the digital equalization circuit 204 with the control signal B3 according to the error will be described. The control circuit 801 can designate the first equalization method or the second equalization method for the digital equalization circuit 204. When the first equalization method is designated, the digital equalization circuit 204 in FIG. 5 performs equalization processing on all the order coefficients c0 to cm so that the error ER1 of the equalization processing approaches 0. When the second equalization method is designated, equalization processing is performed with the coefficients of some orders being updated and the coefficients of other orders being fixed values so that the error ER1 of the equalization processing approaches 0 .

  In the second equalization method, the low-order coefficients c0 to cj are updated, and the high-order coefficients cj + 1 to cm are set to fixed values to perform equalization processing. Here, j is an integer larger than 0 and smaller than m. Specifically, the outputs of the high-order coefficient cj + 1 to cm multipliers 50j + 1 to 50m are fixed to 0, and the operations of the high-order coefficient cj + 1 to cm multipliers 50j + 1 to 50m and the delay circuits 51j + 1 to 51m are stopped. Thereby, power consumption can be reduced.

  The first equalization method has the advantage of high accuracy and has the disadvantage of high power consumption. On the other hand, the second equalization method has an advantage of low power consumption and has a disadvantage of low accuracy. Therefore, if the error can be suppressed below the threshold, it is preferable to use the second equalization method as much as possible to reduce power consumption. However, when the second equalization method is used, if the error becomes larger than the threshold value, it is necessary to use the first equalization method with high accuracy.

  The control circuit 801 designates the second equalization method when the error when the second equalization method is designated is less than or equal to the threshold, and when the error when the second equalization method is designated is greater than the threshold. Specifies the first equalization method. As the error, the error shown in the above first to third comparison methods is used. Note that one of three or more equalization methods may be selected by changing the number of coefficients to be updated.

  FIG. 9A is a diagram illustrating a configuration example of the control circuit 801 according to the first comparison method. In the initialization process, the error storage unit 901 stores tracking CDR error and blind CDR error under the control of the sequencer 902. Further, the error storage unit 901 specifies, for each CDR method, an error when the first phase detection circuit 1101 is specified, an error when the second phase detection circuit 1102 is specified, and the first equalization method. And the error when the second equalization method is designated are stored. The error comparison unit 903 compares the error of the tracking CDR method with the error of the blind CDR method, and determines the designation of the CDR method having the smaller error. Further, the error comparison unit 903 determines designation of the first phase detection circuit 1101 or the second phase detection circuit 1102 by the above method, and outputs the control signal B2 to the phase detection circuit 205. Further, the error comparison unit 903 determines the designation of the first equalization method or the second phase detection circuit 1102 by the above method, and outputs the control signal B3 to the digital equalization circuit 204. When the tracking CDR method is designated, the tracking / fixing unit 904 outputs the phase adjustment code F1 input from the low-pass filter 206 as it is to the phase adjustment circuit 202 as the phase adjustment code B1. When the blind CDR method is designated, the tracking / fixing unit 904 outputs a fixed value phase adjustment code B1 to the phase adjustment circuit 202.

  The control circuit 801 using the second comparison method is different from the control of the control circuit 801 using the first comparison method in that the error A2 is input instead of the error ER2.

  FIG. 9B is a diagram illustrating a configuration example of the control circuit 801 according to the third comparison method. The control circuit 801 in FIG. 9B is obtained by adding a data comparator 905 to the control circuit 801 in FIG. 9A. Hereinafter, differences from the control circuit 801 in FIG. 9A will be described. In the initialization process, the data comparator 905 compares the restored data at the terminal OUT with the training data at the training data node TR, and outputs the error. The error storage unit 901 stores the error under the control of the sequencer 902. After that, the control circuit 801 designates the CDR method, the phase detection circuit method, and the equalization method according to the error in the same manner as described above.

  FIG. 10 is a flowchart showing a method designation method of the receiving circuit 103. In step S1001, the receiving circuit 103 starts an initialization process. Next, in step S1002, the receiving circuit 103 starts CDR method designation processing. Next, in step S1003, the control circuit 801 sets the blind CDR method. Next, in step S1004, the control circuit 801 acquires an error and stores it in the first memory in the error storage unit 901. Next, in step S1005, the control circuit 801 sets the tracking CDR method. In step S <b> 1006, the control circuit 801 acquires an error and stores it in a second memory in the error storage unit 901. In step S1007, the error comparison unit 903 compares the error in the first memory with the error in the second memory. Next, in step S1008, the control circuit 801 designates the CDR method with the smaller error. Next, in step S1009, the receiving circuit 103 ends the CDR method designation processing. Next, in step S1010, the receiving circuit 103 performs another initialization process.

  FIG. 13 is a flowchart showing another method designation method of the receiving circuit 103. In step S1301, the reception circuit 103 starts an initialization process. Next, in step S1302, the receiving circuit 103 starts CDR method designation processing. Next, in step S1303, the control circuit 801 sets the blind CDR method. Next, in step S1304, the control circuit 801 sets the number of taps of the digital equalization circuit 204. By setting the number of taps, the number of coefficients to be updated can be set as described above. By the processing in step S1307, which will be described later, a plurality of taps can be set one by one in order. Next, in step S1305, the control circuit 801 sets the use of the first phase detection circuit 1101. Next, in step S1306, the control circuit 801 acquires an error and stores it in the first memory in the error storage unit 901. Next, in step S1307, the control circuit 801 checks whether or not the setting of all the tap numbers of the digital equalization circuit 204 has been completed. If not completed, the process returns to step S1304, and the control circuit 801 sets another tap number of the digital equalization circuit 204. If completed, the process proceeds to step S1308.

  In step S1308, the control circuit 801 sets the tracking CDR method. Next, in step S1309, the control circuit 801 sets the number of taps of the digital equalization circuit 204. By setting the number of taps, the number of coefficients to be updated can be set as described above. By the processing in step S1312, which will be described later, a plurality of taps can be set one by one in order. Next, in step S1310, the control circuit 801 sets the use of the first phase detection circuit 1101. Next, in step S1311, the control circuit 801 acquires an error and stores it in a second memory in the error storage unit 901. Next, in step S1312, the control circuit 801 checks whether or not the setting of all the tap numbers of the digital equalization circuit 204 has been completed. If not completed, the process returns to step S1309, and the control circuit 801 sets another tap number for the digital equalization circuit 204. If completed, the process proceeds to step S1313.

  In step S1313, the error comparison unit 903 compares the error in the first memory with the error in the second memory. Next, in step S1314, the control circuit 801 designates the CDR method with the smaller error between the blind CDR method and the tracking CDR method. Then, in the designated CDR method, the control circuit 801 designates the first phase detection circuit 1101 when the error of the first phase detection circuit 1101 is equal to or smaller than the threshold value with any number of taps. When the error of the first phase detection circuit 1101 is larger than the threshold value, the second phase detection circuit 1102 is designated. Then, when the error in any of the number of taps is less than or equal to the threshold, the control circuit 801 applies an equalization method for the number of taps having the smallest error to be updated to the digital equalization circuit 204. specify. The control circuit 801 designates the equalization method for the maximum number of taps for updating all the coefficients to the digital equalization circuit 204 when the errors in all the tap numbers are larger than the threshold value. Next, in step S1315, the reception circuit 103 ends the CDR method designation processing. Next, in step S1316, the receiving circuit 103 performs another initialization process.

  According to the present embodiment, the bit error rate and power consumption of the restored data can be reduced by specifying the CDR method, the method of the phase detection circuit, and / or the equalization method according to the error.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

111 Analog Equalization Circuit 112 Analog to Digital Converter 201 Phase Lock Loop Circuit 202 Phase Adjustment Circuit 203 Demultiplexing Circuit 204 Digital Equalization Circuit 205 Phase Detection Circuit 206 Low Pass Filter 207 Determination Circuit 210 Clock Data Recovery Circuit 801 Control Circuit

Claims (4)

A phase adjustment circuit for adjusting the phase of the clock signal according to the phase adjustment code;
A sampling circuit for oversampling data for one unit interval in synchronization with the clock signal output by the phase adjustment circuit;
A digital equalization circuit that performs equalization processing on the data sampled by the sampling circuit;
A clock data recovery circuit for restoring output data based on the data equalized by the digital equalization circuit;
A control circuit for specifying a tracking method or a blind method,
The clock data recovery circuit includes:
A phase detection circuit for detecting a phase error between a boundary of one unit interval of the data equalized by the digital equalization circuit and an estimated value of the boundary of one unit interval;
A low-pass filter for low-pass filtering the phase error detected by the phase detection circuit;
A determination circuit that restores output data based on data equalized by the digital equalization circuit;
The phase adjustment circuit adjusts and outputs the phase of a clock signal in accordance with a phase adjustment code that is a signal output from the low-pass filter when the tracking method is designated, and when the blind method is designated, the phase adjustment circuit outputs a clock. The signal phase is fixed and output,
When the tracking method is designated, the determination circuit restores output data using data sampled for the center of one unit interval among the data equalized by the digital equalization circuit, and When the blind method is designated, the data sampled closest to the center of one unit interval is selected from the data equalized by the digital equalization circuit based on the signal filtered by the low-pass filter. Restore the output data,
The control circuit compares an error when the tracking method is specified for the phase adjustment circuit and the determination circuit with an error when the blind method is specified for the phase adjustment circuit and the determination circuit. The receiving circuit is characterized in that the method with the smaller error is specified for the phase adjustment circuit and the determination circuit. The first phase detection circuit detects the phase error by converting the data equalized by the digital equalization circuit into binary data when the first phase detection method is designated. When the circuit and the second phase detection method are designated, the phase error is detected by linearly converting the data equalized by the digital equalization circuit into data having three or more values with respect to the phase. Two phase detection circuits,
The control circuit designates the first phase detection method when an error when the first phase detection method is designated is equal to or less than a threshold value, and the error when the first phase detection method is designated is a threshold value. 2. The receiving circuit according to claim 1, wherein when it is larger, the second phase detection method is designated. When the first equalization method is designated, the digital equalization circuit performs equalization processing on all the order coefficients so that the error of the equalization processing approaches 0, and the second equalization method Is specified, the coefficients of some orders are updated and the coefficients of the orders of other parts are set to fixed values so that the error of the equalization process approaches 0, and equalization processing is performed.
The control circuit designates the second equalization method when the error when the second equalization method is designated is less than or equal to the threshold value, and the error when the second equalization method is designated is the threshold value. 3. The receiving circuit according to claim 1, wherein the first equalization method is designated when the value is larger.   The control circuit compares an error in equalization processing of the digital equalization circuit, a phase error detected by the phase detection circuit, or an error of output data restored by the clock data recovery circuit. The receiving circuit according to any one of claims 1 to 3.

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