JP2013016985A - Phase interpolation circuit and method of designing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase interpolation circuit that resolves a phase distortion by suppressing effects of variations of transistors.SOLUTION: The phase interpolation circuit includes a plurality of differential pairs for receiving input waveforms out of phase, and combines output waveforms of a first differential pair and a second differential pair of the plurality of differential pairs. The phase interpolation circuit further includes: a variable current source including n current sources for supplying bias currents to the plurality of differential pairs, and capable of supplying a bias current to be supplied to the first differential pair from m current sources of the n current sources and capable of supplying a bias current to be supplied to the second differential pair from n-m current sources of the n current sources, in which the currents supplied by the n current sources are each weighted on the basis of a predetermined unit current value; and a control circuit for changing the number of m current sources of the variable current source on the basis of a phase shift of the output waveforms.

Description

  The present invention relates to a phase interpolation circuit and a design method thereof. In particular, the present invention relates to a phase interpolation circuit including a variable current source.

  In recent years, high-speed serial data is often used in communication between semiconductor devices. In order to perform such high-speed serial data communication, it is necessary for the semiconductor device on the serial data receiving side to operate at an accurate timing with respect to the communication data. Therefore, a phase interpolation circuit for interpolating the phase of a clock used for serial data transmission / reception is used.

  The phase interpolation circuit is a circuit that accepts a plurality of clocks as input and arbitrarily shifts the clocks between the accepted clocks. However, the waveform of the clock input to the phase interpolation circuit is not necessarily a highly linear waveform, and there is a problem that phase distortion (non-linear phase shift amount) due to this nonlinearity occurs.

  Here, Patent Documents 1 to 3 disclose a technique for controlling a current flowing in a current source included in a phase interpolation circuit by generating a control code considering phase distortion and performing DA conversion on the control code. Yes.

JP 2002-123332 A JP 2001-217682 A JP 2004-235875 A JP 2003-229663 A JP 2004-159163 A

  Each disclosure of the above prior art document is incorporated herein by reference. The following analysis has been made from the viewpoint of the present invention.

  As described above, in the technique disclosed in Patent Document 1, a control code considering phase distortion is generated, and a current supplied from a current source included in the phase interpolation circuit is controlled based on the control code. At that time, the control code is input to the DA converter and the weight current is output. The weight current output from the DA converter is input as a reference current to the current source connected to the differential pair transistor and the transistors constituting the current mirror circuit. As a result, a weight current flows through the current source connected to the differential pair transistor, thereby eliminating phase distortion.

  However, the technique disclosed in Patent Document 1 achieves the elimination of phase distortion by using a current mirror circuit and causing a weight current to flow through a current source, and the influence of variations in transistors constituting the current mirror circuit. There is a problem of receiving strong. The accuracy of the current mirror circuit is determined by the ratio of the sizes of the transistors constituting the current mirror circuit.

  On the other hand, the size of the transistor varies not a little at the manufacturing stage. As a result, the transistors constituting the current mirror circuit may amplify each other's variation. More specifically, when one transistor is the upper limit of the assumed range of variation and the variation of the other transistor is the lower limit of the range, the current mirror circuit configured by these transistors The accuracy is greatly degraded.

  If the accuracy of the current mirror circuit deteriorates, the phase distortion in the phase interpolation circuit also deteriorates. That is, when a current mirror circuit is used in the phase interpolation circuit, there is a problem that the influence due to transistor variations in the manufacturing stage becomes obvious. Therefore, a phase interpolation circuit that suppresses the influence of transistor variations and eliminates phase distortion and a design method thereof are desired.

  According to the first aspect of the present invention, it includes a plurality of differential pairs that accept input waveforms having different phases, and outputs the first differential pair and the second differential pair among the plurality of differential pairs. A phase interpolation circuit for synthesizing a waveform, including n current sources for supplying a bias current to the plurality of differential pairs (where n is an integer of 2 or more), and supplying the current to the first differential pair Bias current can be supplied from m (n is an integer of 2 or more) of the n current sources, and the bias current supplied to the second differential pair is n. Among the current sources, nm current sources can be supplied, and the currents supplied by the n current sources are respectively weighted with reference to a predetermined unit current value. Based on the variable current source and the phase shift amount of the output waveform, the m number of the variable current sources A control circuit for changing the number of current sources, the phase interpolator comprising is provided.

  According to a second aspect of the present invention, the first differential pair, the second differential pair receiving an input waveform having a phase different from that of the first differential pair, and the first and second A phase interpolation circuit design method comprising: a plurality of current sources for supplying a bias current to a differential pair, wherein each of the plurality of current sources is a weighted variable current source; Calculating a correlation between a ratio between a first current flowing in a pair and a second current flowing in the second differential pair and a phase shift amount of an output waveform of the phase interpolation circuit; Each of the plurality of current sources and the plurality of current sources based on a step of determining a current value in which the correlation is linear, a current value in which the correlation is linear, and a predetermined unit current value Determining a weight of each current source, and a method of designing a phase interpolation circuit It is provided.

  According to each aspect of the present invention, there are provided a phase interpolation circuit that suppresses the influence of transistor variations and eliminates phase distortion, and a design method thereof.

It is a figure for demonstrating the outline | summary of one Embodiment of this invention. It is a figure which shows an example of the circuit structure of the phase interpolation circuit 1 which concerns on the 1st Embodiment of this invention. It is a figure which shows an example of the circuit structure of the variable current source 10 shown in FIG. FIG. 3 is a diagram illustrating an example of a clock input to the phase interpolation circuit 1 illustrated in FIG. 2. It is a figure which shows an example of the simulation waveform of the phase interpolation circuit 1 when an input clock is made linear. It is a figure which shows an example of the simulation waveform of the phase interpolation circuit 1 when an input clock is made nonlinear. 4 is a diagram illustrating an example of weighting of current sources included in the variable current source 10. FIG. It is a flowchart which shows an example of the design method of the weight of each current source. It is an example of the simulation of the phase shift amount of the composite waveform when a bias current is supplied from each current source. It is a figure which shows an example of the circuit structure of the phase interpolation circuit 2 which concerns on the 2nd Embodiment of this invention. It is the figure which cut out the part applicable to the N channel type MOS transistors N21-N23 shown in FIG. 3 of the phase interpolation circuit 2 which concerns on the 2nd Embodiment of this invention. It is a figure which shows an example of the internal structure of the phase interpolation circuit 3 which concerns on the 3rd Embodiment of this invention. It is a figure which shows an example of an internal structure of the variable current source 10b which incorporated the waveform normalization circuit in the variable current source 10 of the phase interpolator 1. FIG.

  First, an outline of an embodiment will be described with reference to FIG. Note that the reference numerals of the drawings attached to this summary are attached to the respective elements for convenience as an example for facilitating understanding, and are not intended to limit the present invention to the illustrated embodiment.

  As described above, when a bias current is supplied to the differential pair of the phase interpolation circuit using the current mirror circuit, phase distortion may occur due to the influence of variations in the transistors constituting the current mirror circuit. Therefore, a phase interpolation circuit that suppresses the influence of transistor variations and eliminates phase distortion and a design method thereof are desired.

  Accordingly, the phase interpolation circuit shown in FIG. 1 is provided as an example. The phase interpolation circuit shown in FIG. 1 includes a plurality of differential pairs that accept input waveforms having different phases, and synthesizes the output waveforms of the first differential pair and the second differential pair among the plurality of differential pairs. This is a phase interpolation circuit. In addition, n current sources that supply bias currents to a plurality of differential pairs (where n is an integer equal to or greater than 2) include bias currents that are supplied to the first differential pair among n current sources. , M (where m is an integer greater than or equal to 2) current sources, and n-m current sources among the n current sources are bias currents supplied to the second differential pair. The current supplied from the n current sources is based on a variable current source that is weighted with reference to a predetermined unit current value, and the phase shift amount of the output waveform. And a control circuit for changing the number of m current sources of the variable current source.

  The variable current source of the phase interpolation circuit shown in FIG. 1 can be switched by the control circuit to supply the current supplied from each current source to the first differential pair or the second differential pair. It is. By switching by the control circuit, the current ratio between the bias current flowing through the first differential pair and the bias current flowing through the second differential pair is varied to realize phase shift. Further, unlike the patent document 1, the phase interpolation circuit shown in FIG. 1 does not use a current mirror circuit, so that the influence of transistor variations is limited. As a result, it is possible to realize a phase interpolation circuit that eliminates phase distortion while suppressing the influence of transistor variations.

[First Embodiment]
Next, the first embodiment of the present invention will be described in more detail with reference to the drawings.

  FIG. 2 is a diagram illustrating an example of a circuit configuration of the phase interpolation circuit 1 according to the present embodiment.

  The phase interpolation circuit 1 includes N-channel MOS transistors N01 to N12, resistors R01 and R02, capacitors C01 and C02, a variable current source 10, and a control circuit 20.

  The phase interpolation circuit 1 receives a clock CLK_0, a clock CLK_90, a clock CLK_180, a clock CLK_270, and clock selection signals SEL01 to SEL04. The clock CLK_0 is a reference clock, and the phases of the clock CLK_90, the clock CLK_180, and the clock CLK_270 are shifted by 90 degrees, 180 degrees, and 270 degrees with respect to the clock CLK_0, respectively. Further, a clock to be phase-interpolated is determined based on the clock selection signals SEL01 to SEL04.

  The phase interpolation circuit 1 outputs a differential clock (non-inverted clock, inverted clock) from the output terminals OUTP and OUTN. The capacitance values of the capacitors C01 and C02 are varied so that the output waveform of the phase interpolation circuit 1 becomes a triangular wave, and the rise time and fall time of the output waveform of the phase interpolation circuit 1 are adjusted.

  The source terminal of the N-channel MOS transistor N01 and the source terminal of the N-channel MOS transistor N02 are commonly connected to each other and connected to the drain terminal of the N-channel MOS transistor N03. The drain terminal of the N-channel MOS transistor N01 is connected to the resistor R01. The clock CLK_0 is received by the gate terminal of the N-channel MOS transistor N01. The gate terminal of the N-channel MOS transistor N01 is commonly connected to the gate terminal of the N-channel MOS transistor N05.

  The source terminal of the N-channel MOS transistor N02 and the source terminal of the N-channel MOS transistor N01 are commonly connected to each other and connected to the drain terminal of the N-channel MOS transistor N03. The drain terminal of the N-channel MOS transistor N02 is connected to the resistor R02. The clock CLK_180 is received by the gate terminal of the N-channel MOS transistor N02. The gate terminal of the N-channel MOS transistor N02 is commonly connected to the gate terminal of the N-channel MOS transistor N04.

  The source terminal of the N-channel MOS transistor N03 and the source terminal of the N-channel MOS transistor N06 are connected in common with each other and connected to the variable current source 10.

  A connection node between the drain terminal of the N-channel MOS transistor N01 and the resistor R01 is defined as an output terminal OUTN. Similarly, a connection node between the drain terminal of the N-channel MOS transistor N02 and the resistor R02 is defined as an output terminal OUTP.

  The drain terminal of the N channel type MOS transistor N03 is connected to the source terminals of the N channel type MOS transistors N01 and N02. The clock selection signal SEL01 is received by the gate terminal of the N-channel MOS transistor N03.

  N-channel MOS transistors N04 to N06 are also connected in the same manner as N-channel MOS transistors N01 to N03. The clock CLK_180 is received by the gate terminal of the N-channel MOS transistor N04, and the clock CLK_0 is received by the gate terminal of the N-channel MOS transistor N05. The clock selection signal SEL02 is received by the gate terminal of the N-channel MOS transistor N06.

  Further, the N channel type MOS transistors N07 to N12 are connected in the same manner as the N channel type MOS transistors N01 to N06. The clock CLK_270 is received by the gate terminals of the N-channel MOS transistors N07 and N11, and the clock CLK_90 is received by the gate terminals of the N-channel MOS transistors N08 and N10. The clock selection signals SEL03 and SEL04 are received at the gate terminals of the N-channel MOS transistors N09 and N12. The source terminals of the N-channel MOS transistors N09 and N12 are connected to the variable current source 10.

  Here, the connection node between the source terminals of the N-channel MOS transistors N03 and N06 and the variable current source 10 is the node S1, and the connection node between the source terminals of the N-channel MOS transistors N09 and N12 and the variable current source 10 is the node S2. Stipulate that

  The variable current source 10 includes current sources IS01 and IS02. The current source IS01 supplies a bias current to a differential pair formed by N-channel MOS transistors N01 and N02 or a differential pair formed by N-channel MOS transistors N04 and N05. Similarly, the current source IS02 supplies a bias current to a differential pair formed by N-channel MOS transistors N07 and N08 or a differential pair formed by N-channel MOS transistors N10 and N11.

  The control circuit 20 controls the bias current supplied from the current sources IS01 and IS02. A specific control method will be described later.

  Next, the variable current source 10 will be described.

  FIG. 3 is a diagram illustrating an example of a circuit configuration of the variable current source 10. The variable current source 10 includes N channel type MOS transistors N21 to N48.

  The source terminal of the N-channel MOS transistor N21 and the source terminal of the N-channel MOS transistor N22 are commonly connected to each other and connected to the drain terminal of the N-channel MOS transistor N23. The drain terminals of N-channel MOS transistors N21 and N22 are connected to nodes S1 and S2, respectively. The gate terminals of N-channel MOS transistors N21 and N22 receive current source selection signals 1T and 1B, respectively. The source terminal of the N-channel MOS transistor N23 is connected to the ground voltage VSS, and the drain terminal is connected to the source terminals of the N-channel MOS transistors N21 and N22. The gate terminal of the N channel type MOS transistor N23 receives a bias voltage.

  N-channel MOS transistor N23 operates as a current source. N-channel MOS transistor N21 operates as a switch for determining whether or not to supply current to node S1, and N-channel MOS transistor N22 operates as a switch for determining whether or not to supply current to node S2.

  The operations of the N-channel MOS transistors N21 and N22 are determined by the current source selection signals 1T and 1B. The control circuit 20 outputs the current source selection signals 1T and 1B.

  Connections for the N channel type MOS transistors N24 to N48 are the same as those of the N channel type MOS transistors N21 to N23.

  As described above, the variable current source 10 includes 16 current sources and a switch that determines whether the current supplied from each current source is supplied to the node S1 or the node S2.

  By selecting the current source selection signal (1T to 16T, 1B to 16B), each current source (N-channel MOS transistors N23, N26 to N48) is operated as the current source IS01 or the current source IS02. , Switch. In addition, the current supply capability of each current source included in the variable current source 10 is different. The reason for changing the current supply capability and the design method of the current supply capability will be described later.

  Next, the operation of the phase interpolation circuit 1 will be described.

  The phase interpolation circuit 1 is a circuit that accepts a plurality of clocks as inputs and arbitrarily shifts the clocks between the accepted clocks. As described above, the phase interpolation circuit 1 accepts a four-phase clock (0 degrees, 90 degrees, 180 degrees, and 270 degrees).

  Here, the operation of the phase interpolation circuit 1 when the phase is shifted between 0 degrees and 90 degrees using the 0 degree and 90 degree input clocks will be described.

  In this case, the clock selection signals SEL01 and SEL04 are set to the H level in order to validate clocks (CLK_0 and CLK_90) having phases of 0 degrees and 90 degrees (see FIG. 2).

  When the clock selection signals SEL01 and SEL04 are set to H level, the N-channel MOS transistors N03 and N12 are turned on, and the bias current supplied from the variable current source 10 is a differential pair (N-channel MOS transistor N01). And N02) and the differential pair (N-channel MOS transistors N10 and N11). Further, a combined waveform of the clocks CLK_0 and CLK_90 is output from the output terminals OUTP and OUTN. When synthesizing this waveform, the ratio of the current supplied from the variable current source 10 to the nodes S1 and S2 is changed (controlled by the control circuit 20), thereby changing the synthesis ratio of the synthesized waveform generated from the clocks CLK_0 and CLK_90. To do.

  Note that a current supplied to the node S1 is a current Ia, and a current supplied to the node S2 is Ib. Even when the phase is shifted between 90 degrees and 180 degrees, between 180 degrees and 270 degrees, between 270 degrees and 0 degrees, the clock selection signals SEL01 to SEL04 are appropriately switched, and the currents Ia and Ib are switched. By changing the ratio, the composite ratio of the composite waveform is changed.

  Next, a method for changing the ratio between the current Ia and the current Ib will be described.

  As described above, the variable current source 10 includes 16 current sources and switches corresponding to the respective current sources. With this switch, it is possible to select whether the bias current supplied from each current source is supplied to either the node S1 or the node S2. The control circuit 20 performs the selection (control of the switch).

  For example, it is assumed that the current source selection signals 1T to 16T are all set to the H level and the current source selection signals 1B to 16B are set to the L level. In this case, current flows only in the node S1, and no current flows in the node S2. Therefore, the synthesis of the clock CLK_0 and the clock CLK_90 is not performed (only the waveform of the clock CLK_0 is output).

  Next, among the current source selection signals 1T to 16T, the current source selection signal 1T is set to L level, and the other signals are set to H level, and among the current source selection signals 1B to 16B, the current source selection signal 1B is set to H level. Consider the case where other signals are set to H level. In this case, a current is supplied to the node S1 (current Ia) from a current source (15 current sources) other than the N-channel MOS transistor N23, and an N-channel MOS is supplied to the node S2 (current Ib). A current is supplied from the transistor N23 (one current source). Therefore, the current ratio between the current Ia and the current Ib is 15: 1. This ratio is directly the combined ratio of the waveforms of the clock CLK_0 and the clock CLK_90. As a result, the synthesized waveform is shifted by 6 degrees (90 degrees / 15) based on the clock CLK_0.

  Thus, the control circuit 20 controls the variable current source 10 so that a desired phase shift amount can be obtained. Although the case where the phase is shifted between 0 degrees and 90 degrees has been described here, the same control is performed when the phase is shifted between 90 degrees and 180 degrees. At that time, switching between the current sources is the same control method regardless of whether it is between 0 degrees and 90 degrees and between 90 degrees and 180 degrees.

  For example, when switching from 0 degrees to 90 degrees in the direction from the left side (N-channel MOS transistor N23) to the right side (N-channel MOS transistor N48) in FIG. 3, even between 90 degrees and 180 degrees. Switch from left to right. As will be described later, each current source is weighted, and the weight is determined so as to cancel the nonlinearity of the input clock. As long as the phase difference is 90 degrees, the nonlinearity of the input clock is the same whether it is between 0 and 90 degrees or between 90 and 180 degrees. This is because the weight to be applied is the same. Therefore, when shifting the phase between 0 degrees and 90 degrees, switching from the left side to the right side is not performed, and when shifting the phase between 90 degrees and 180 degrees, the switching from the right side to the left side is not performed. This is because the weight to be applied shifts when such control is performed.

  Next, the reason why the current supply capabilities of the current sources included in the variable current source 10 are different will be described.

  The reason why the current supply capability of each current source is different is to suppress phase distortion caused by the relationship between the current supply capability (transistor size) of the current source and the input clock.

  Here, when phase distortion occurs in the clock output from the phase interpolation circuit, the characteristics of the circuit operating based on the clock output from the phase interpolation circuit may be deteriorated. Therefore, an ideal output characteristic of the phase interpolation circuit is to realize a phase shift without phase distortion. However, it is difficult to obtain ideal output characteristics unless the waveform of the clock input to the phase interpolation circuit is linear.

  FIG. 4 is a diagram illustrating an example of a clock input to the phase interpolation circuit 1.

  If the input clock is linear and the current supply capability of each current source included in the variable current source 10 is equivalent as shown by the dotted line in FIG. 4, the synthesized waveform can also maintain linearity. However, in practice, the clock input to the phase interpolation circuit 1 is often a sine wave as shown by the solid line in FIG. In such a case, since the waveform to be combined is not linear with respect to the phase, if the section for phase shift is divided at equal intervals (that is, the current supply capability of each current source is equivalent), The waveform is non-linear.

  For example, even if 16 current sources are used to divide the signal between 0 degree and 90 degrees in FIG. 4 into 15 parts, the input clock is not linear with respect to the phase, and thus the synthesized waveform is nonlinear. The non-linearity of the synthesized waveform is output as it is as the phase distortion of the phase interpolation circuit 1 (the phase shift amount is non-linear).

  FIG. 5 is a diagram illustrating an example of a simulation waveform of the phase interpolation circuit 1 when the input clock is linear. The waveform of FIG. 5 is a waveform when the state of each current source of the variable current source 10 is sequentially switched. From FIG. 5, it can be seen that if the input clock is linear, no phase distortion occurs in the output of the phase interpolation circuit 1.

  FIG. 6 is a diagram showing an example of a simulation waveform of the phase interpolation circuit 1 when the input clock is non-linear. From FIG. 6, it can be seen that when the input clock is nonlinear, phase distortion occurs in the output of the phase interpolation circuit 1.

  Therefore, in order to eliminate such phase distortion, the current supply capability of each current source included in the variable current source 10 is weighted to eliminate the influence of nonlinearity of the input clock. That is, the waveform of the clock input to the phase interpolation circuit 1 is determined in advance, and its nonlinearity can be grasped in advance at the design stage of the phase interpolation circuit 1. Each current source is weighted so as to cancel the nonlinearity of the input clock.

  FIG. 7 is a diagram illustrating an example of weighting of current sources included in the variable current source 10. In the weighting shown in FIG. 7, a large weight is given to the first current source, the weight is gradually decreased, and the weight is increased again from the intermediate current source. Thus, the weight of the current source included in the variable current source 10 is changed with respect to the nonlinearity of the input clock, and the output waveform of the phase interpolation circuit 1 is made linear. That is, the linearity of the output waveform is ensured by adapting the current supply capability of the current source nonlinearly to the nonlinearity of the input clock.

  Next, a method for designing the weight of each current source included in the variable current source 10 will be described.

  FIG. 8 is a flowchart showing an example of a method for designing the weight of each current source.

  In step S01, the correlation between the current ratio between the currents Ia and Ib and the phase shift amount is calculated. At that time, a method of obtaining the correlation between the current ratio and the phase shift from the simulation result of the phase interpolation circuit 1 can be considered. Alternatively, the current Ia and the current Ib may be supplied to the actual phase interpolation circuit 1, and the correlation between the current ratio and the phase shift amount may be calculated.

In step S02, the current supply capability (current step size) of each current source is calculated. Here, the current Ia can be expressed by the following formula (1).

Ia = I1 + I2 + ... Im-1 (1)

Similarly, the current Ib can be expressed by the following equation (2).

Ib = Im + Im + 1 +... + I15 + I16 (2)

Note that I1 is a current supplied from the N-channel MOS transistor N23, and I2 is a current supplied from the N-channel MOS transistor N26. The same applies to I3 to I16.

Here, m is a positive integer from 2 to 16, and the current values of the current Ia and the current Ib are determined by m. In addition, since the sum total of the current Ia and the current Ib does not change, the relationship of the following formula (3) is established between the current Ia and the current Ib.

Ia + Ib = I1 + I2 + I3 +... + I15 + I16 (3)

  In this step, the current values of I1 to I16 in the equations (1) to (3) are determined so that the current ratio between the current Ia and the current Ib and the phase shift amount are linear. That is, the current to be supplied from each current source included in the variable current source 10 is determined by this step.

In step S03, the weight of each current source is calculated. Specifically, the current supplied by each current source is expressed by the following equation (4), and the weight is calculated.

I1 = r1 × I0
I2 = r2 × I0
(4)
I15 = r15 × I0
I16 = r16 × I0

Here, I0 is a unit current value of each current source, and r1 to r16 are weights of each current source.

  In step S02, the currents (I1 to I16) to be supplied by each current source are calculated. Therefore, a unit current value I0 is determined in advance as a reference value of the current supplied by each current source, and the respective weights r1 to r16 are determined based on the currents I1 to I16 and the unit current value I0.

  In the description of the present embodiment, the case where the variable current source 10 includes 16 current sources has been described. However, this is not intended to limit the number of current sources. The current source included in the variable current source 10 can be easily expanded, and the resolution of the phase shift amount can be changed.

  Furthermore, although the case where the phase interpolation circuit 1 corresponds to a four-phase clock has been described, the present invention is not limited to this. The type of clock phase to which the phase interpolation circuit 1 corresponds can be changed. For example, when dealing with an 8-phase clock, the number of differential pairs is increased and the current source supplied to each differential pair is expanded. More specifically, in addition to the currents Ia and Ib, the switches of the current sources are expanded so that the currents Ic and Id can be supplied in correspondence with the added differential pair.

  The phase interpolation circuit 1 according to the present embodiment can be applied to a PLL (Phase Locked Loop) circuit, a CDR (Clock and Data Recovery) circuit, and the like.

  The variable current source 10 is configured and controlled as described above. As a result, phase distortion due to nonlinearity of the input clock can be eliminated.

  FIG. 9 is an example of a simulation of the phase shift amount of the combined waveform when a bias current is supplied from each current source. FIG. 9 shows an ideal phase shift amount, a phase shift amount when each current source is not weighted, and a phase shift amount when a weight is added. As can be seen from FIG. 9, if the current sources are not weighted, the nonlinearity of the input clock affects and the phase shift amount deviates from the ideal value.

  However, weighting each current source can eliminate the non-linear effect of the input clock and make the phase shift amount substantially equal to the ideal value.

  Furthermore, in the variable current source 10 included in the phase interpolation circuit 1 according to the present embodiment, weighting is performed based on the unit current value I0, and the influence of variation when each current source (transistor) is manufactured is limited. Is. That is, the variation in the transistors (current supply capability) of each current source is equivalent to the variation in the current supply capability of each current source.

  On the other hand, since the variable current source disclosed in Patent Document 1 uses a current mirror circuit, the variation of a plurality of transistors affects the current supply capability of the current source. In other words, the current supply capability of the variable current source disclosed in Patent Document 1 may fluctuate beyond the variation of individual transistors (the variation is amplified).

  As described above, the phase interpolation circuit disclosed in Patent Document 1 is strongly affected by transistor variations in the manufacturing process, whereas the phase interpolation circuit 1 according to the present embodiment can manage the effects of transistor variations. It is possible to eliminate the phase distortion while keeping it within the proper range.

[Second Embodiment]
Next, a second embodiment will be described in detail with reference to the drawings.

  In the phase interpolation circuit 1 according to the first embodiment, the weight of each current source is realized by changing the size of the transistor used in the variable current source 10. However, the phase interpolation circuit 1 cannot change the weight determined at the design stage. In the phase interpolation circuit 2 according to the present embodiment, the weight of each current source is corrected using the output of the phase interpolation circuit 2.

  FIG. 10 is a diagram illustrating an example of the circuit configuration of the phase interpolation circuit 2. 10, the same components as those in FIG. 2 are denoted by the same reference numerals, and the description thereof is omitted.

  The difference between the phase interpolation circuit 2 and the phase interpolation circuit 1 is the internal configuration of the variable current source 10a and the configuration and control method of the control circuit 20a.

  The control circuit 20a receives an input clock (clock CLK_0 in FIG. 10) and an output waveform from the output terminals OUTP and OUTN of the phase interpolation circuit 2. The control circuit 20a calculates the phase difference between the input clock and the output waveform, and finely adjusts the weight of each current source included in the variable current source 10a if the calculated phase difference is not a desired phase difference.

  FIG. 11 is a diagram in which portions corresponding to the N-channel MOS transistors N21 to N23 in FIG. 3 are cut out.

  Each current source included in the variable current source 10a includes a basic transistor and an auxiliary transistor for correcting a current supplied from the basic transistor. In FIG. 11, an N-channel MOS transistor N23 is a basic transistor, and N-channel MOS transistors N50 and N51 are auxiliary transistors. The drain terminal of the auxiliary transistor is connected to the drain terminal of the basic transistor via switches SW01 and SW02.

  By switching the switches SW01 and SW02 from the control circuit 20a, the amount of current supplied from the current source included in the variable current source 10a is finely adjusted. More specifically, the current supplied by the current source shown in FIG. 11 is designed as the amount of current supplied by the N-channel MOS transistors N23 and N50.

  When the phase shift amount does not match the design value as a result of measuring the output waveform in the control circuit 20a (when the phase shift amount deviates from the design value), the phase is controlled by appropriately controlling the switches SW01 and SW02. Correct the shift amount.

  In order to finely adjust the weight of the current source included in the variable current source 10a, a method of preparing a plurality of small-sized transistors and changing the number of effective transistors can be considered. In other words, the transistors constituting each current source are divided into small-sized transistors, and the transistors that supply current are switched according to the required amount of current.

  As described above, in the phase interpolation circuit 2 according to the present embodiment, the output waveform is fed back to the control circuit 20a, and the weight of the current source included in the variable current source 10a is finely adjusted. As a result, even if phase distortion occurs due to variations in transistor size in the manufacturing stage of the phase interpolation circuit, the phase distortion can be eliminated by finely adjusting the weight of each current source.

[Third Embodiment]
Next, a third embodiment will be described in detail with reference to the drawings.

  In the phase interpolation circuits 1 and 2 according to the first and second embodiments, it is assumed that the waveform of the input clock is predetermined. However, it is more convenient if the input clock that can be received by the phase interpolation circuit can be changed. For example, even when the specifications of the circuit including the phase interpolation circuit are changed, it is not necessary to redesign the phase interpolation circuit, and the design cost can be reduced.

  Therefore, in the phase interpolation circuit 3 according to the present embodiment, the received input clock waveform is corrected to a predetermined clock waveform to cope with a plurality of waveforms.

  FIG. 12 is a diagram illustrating an example of the internal configuration of the phase interpolation circuit 3.

  The phase interpolation circuit 3 includes a phase interpolation unit 30, a waveform normalization resistor unit 40, a waveform normalization current source 50, a frequency divider circuit 60, and N-channel MOS transistors N60 and N61. The phase interpolation unit 30 corresponds to the phase interpolation circuit 1 or 2 described in the first and second embodiments. Therefore, the description regarding the phase interpolation unit 30 is omitted.

  The waveform normalizing resistor unit 40 is composed of a plurality of resistors and a P-channel MOS transistor. Each resistor and a P-channel MOS transistor are paired. The source terminal of each P-channel MOS transistor is connected to the power supply voltage VDD, and the drain terminal is connected to each resistor. The gate terminal receives a control signal, and each P-channel MOS transistor serves as a switch.

  The waveform normalized current source 50 is composed of a plurality of current sources. The N-channel MOS transistors N60 and N61 accept differential clocks from the clock input terminals (CLK_INP and CLK_INN) and output the differential clocks to the frequency dividing circuit 60.

  The frequency divider 60 uses a latch circuit or the like to generate a four-phase clock and outputs it to the phase interpolation unit 30.

  The phase interpolation circuit 3 is configured as described above, and the waveform of the input clock is normalized to a predetermined clock waveform (assumed at the design stage) using the waveform normalization resistor 40 or the waveform normalization current source 50. . Normalization at that time is performed according to the frequency of the input clock received at the clock input terminals (CLK_INP and CLK_INN).

  Specifically, the resistance value connected to the N-channel MOS transistors N60 and N61 is changed by the waveform normalization resistor section 40, or the amount of current supplied from the waveform normalization current source 50 is changed. By such normalization, the rising time and falling time of the input clock are made to coincide with a predetermined waveform. As a result, the phase shift can be kept linear even for a plurality of input clocks.

  Note that a control signal for switching the capacity of the phase interpolation circuit can be used as a control signal for controlling the waveform normalization resistor 40 or the waveform normalization current source 50. This is because the capacity of the phase interpolation circuit is used to generate a triangular wave, but the optimum capacity value differs depending on the frequency and is often used by switching the capacity value.

  In the present embodiment, the case where an input clock waveform normalization circuit is added to the first or second phase interpolation circuit 1 or 2 has been described. However, this waveform normalization circuit can be incorporated in the phase interpolation circuit 1 or 2.

  FIG. 13 is a diagram illustrating an example of an internal configuration of a variable current source 10 b in which a waveform normalization circuit is incorporated in the variable current source 10 of the phase interpolator 1.

  As shown in FIG. 13, it is also possible to include a plurality of variable current sources in the variable current source 10b and select a current source in which the current weight is optimized according to the frequency of the input clock.

  Each disclosure of the cited patent documents and the like cited above is incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiment can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

1, 2, 3 Phase interpolation circuit 10, 10a, 10b Variable current source 20, 20a Control circuit 30 Phase interpolation unit 40 Waveform normalization resistor unit 50 Waveform normalization current source 60 Frequency dividing circuit C01, C02 Capacitors IS01, IS02 Current source N01 to N12, N21 to N48, N50, N51, N60, N61 N-channel MOS transistors R01, R02 Resistors SW01, SW02 switches

Claims (5)

A phase interpolation circuit that includes a plurality of differential pairs that receive input waveforms having different phases, and synthesizes output waveforms of a first differential pair and a second differential pair among the plurality of differential pairs;
N current sources for supplying a bias current to the plurality of differential pairs (where n is an integer equal to or greater than 2), and a bias current to be supplied to the first differential pair is supplied to each of the n current sources. Among them, m (where m is an integer of 2 or more) current sources can be supplied, and the bias current supplied to the second differential pair is nm among the n current sources. The currents supplied by the n current sources are variable current sources that are weighted with reference to a predetermined unit current value, and
A control circuit that changes the number of the m current sources of the variable current source based on a phase shift amount of the output waveform;
A phase interpolation circuit comprising: Each of the n current sources can change a supplied current value,
The phase interpolation circuit according to claim 1, wherein the control circuit changes a current value supplied from the n current sources based on a phase shift amount of the output waveform. The n current sources include a transistor and a plurality of auxiliary transistors having a current supply capability lower than that of the transistor,
The phase interpolation circuit according to claim 2, wherein the current value to be supplied is changed by adding the amount of current supplied from the transistor and the current supplied from the plurality of auxiliary transistors.   The phase interpolation according to any one of claims 1 to 3, further comprising a waveform normalization circuit that normalizes a rise time and a fall time of the input waveform to a predetermined rise time and fall time of the waveform. circuit. A first differential pair;
A second differential pair for receiving an input waveform having a phase different from that of the first differential pair;
A plurality of current sources for supplying a bias current to the first and second differential pairs, each of the plurality of current sources being a weighted variable current source;
A phase interpolation circuit design method comprising:
The correlation between the ratio between the first current flowing through the first differential pair and the second current flowing through the second differential pair and the phase shift amount of the output waveform of the phase interpolation circuit is calculated. And a process of
Determining a current value that is a current flowing through each of the plurality of current sources and in which the correlation is linear; and
Determining a weight of each of the plurality of current sources based on a current value at which the correlation is linear and a predetermined unit current value;
A method for designing a phase interpolation circuit, comprising:

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