JP2014110345A - Field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nitride semiconductor field effect transistor which has a high threshold value and which can reduce a gate leakage current and obtain a large maximum current.SOLUTION: A field effect transistor comprises: a semiconductor lamination structure 10 including a first semiconductor layer 11 composed of a first nitride semiconductor and a second semiconductor layer 12 composed of a second nitride semiconductor having bandgap energy larger than that of the first nitride semiconductor, in which a two-dimensional electron gas layer is produced on a boundary surface of the first semiconductor layer 11 on the second semiconductor layer 12 side; a source electrode 32 and a drain electrode 33; and a gate electrode 21 arranged on the second semiconductor layer 12, for controlling a flow of electrons in the two-dimensional electron gas layer between the source electrode 32 and the drain electrode 33. The field effect transistor further comprises: a third semiconductor layer 23 composed of a p-type nitride semiconductor between the gate electrode 21 and the second semiconductor layer 12; and a fourth semiconductor layer 22 composed of a nitride semiconductor arranged between the third semiconductor layer 23 and the gate electrode, in which the gate electrode forms Schottky contact with the fourth semiconductor layer 22.

Description

  The present invention relates to a field effect transistor using a nitride semiconductor.

  In recent years, field effect transistors (hereinafter referred to as “GaN-based FETs”) represented by high electron mobility transistors (GaN-based HEMTs) using GaN-based compound semiconductors instead of GaAs-based compound semiconductors have been developed as next-generation high-speed transistors. It is attracting attention as an FET. Since GaN-based compound semiconductors have a wide band gap and high saturation electron mobility estimated from the effective electron mass, there is a possibility that a high-frequency device capable of operating at higher voltage and operating at higher temperatures can be realized. ing.

A GaN-based FET using a GaN-based compound semiconductor is formed by, for example, sequentially stacking a buffer layer, a GaN layer, and an AlGaN layer on an insulating sapphire substrate, and forming a source electrode, a gate electrode, and a drain electrode on the upper surface of the AlGaN layer. It is constituted by being done. Unlike the GaAs compound semiconductor FET that is driven by carriers generated by impurity doping, the HEMT having this structure operates by high-concentration carriers generated by both actions of spontaneous polarization and piezoelectric polarization. That is, when an AlGaN layer is grown on the GaN layer, positive fixed charges are generated at the heterointerface due to both spontaneous polarization and piezoelectric polarization, and negative polarization charges are generated on the surface of the AlGaN layer. Although the polarization charge concentration varies depending on the composition and film thickness of the AlGaN layer, an extremely large sheet electron concentration of about 1 × 10 ¹³ / cm ² is generated in the AlGaN / GaN heterostructure. When an ohmic electrode is formed in this heterostructure and an electric field is applied between the electrodes, a current based on charge transport with a high electron concentration of about 1 × 10 ¹³ / cm ² flows.

  This GaN-based FET is said to be able to produce a device having a higher breakdown voltage and a lower on-resistance than conventional Si power devices (MOSFETs and IGBTs). By using this GaN-based FET, the power consumption of the device Is expected to be reduced.

  However, a field effect transistor made of a nitride semiconductor has a problem that it is difficult to make normally-off.

In view of the above problems, Patent Document 1 discloses that a gate electrode is formed on a nitride semiconductor multilayer structure via a high-concentration p-type GaN layer for the purpose of providing a field effect transistor made of a normally-off type nitride semiconductor. Forming a pn junction in the gate region by forming an ohmic contact between the gate electrode and the high-concentration p-type GaN layer.
Further, in Patent Document 2, an i-GaN selective regrowth layer 29 having a thickness of about 1 nm is formed on the p-GaN selective regrowth layer 28 formed for the same purpose as that of Patent Document 1, and p- A technique for preventing surface oxidation of the GaN selective regrowth layer 28 and obtaining stable enhancement mode GaN-HEMT characteristics is disclosed.

JP 2006-339561 A JP 2008-153330 A

However, the field effect transistor made of a nitride semiconductor disclosed in Patent Documents 1 and 2 has a problem that the threshold voltage is not sufficiently high even if normally-off can be realized.
Further, the field effect transistors disclosed in Patent Documents 1 and 2 have a problem that the gate leakage current is large and the loss is large. In such a field effect transistor, in order to suppress the gate leakage current, it is necessary to drive with a small gate bias. However, the depletion layer in the portion where the channel is generated cannot be sufficiently eliminated by the gate bias. There is a problem that a part of the depletion layer remains in the channel.
As a result, the resistance between the source and the drain cannot be made sufficiently small, the maximum current obtained becomes small, the loss is large, and the gate leakage current is large.

  The present invention solves such problems, has a high threshold voltage, can reduce a gate leakage current when a forward bias is applied to the gate electrode, and can be an electric field made of a nitride semiconductor that can obtain a large maximum current. An object is to provide an effect transistor.

To achieve the above objectives,
The field effect transistor according to the present invention is
A first semiconductor layer made of a first nitride semiconductor; and a second semiconductor layer made of a second nitride semiconductor having a bandgap energy larger than that of the first nitride semiconductor. A semiconductor stacked structure in which a two-dimensional electron gas layer is formed at an interface of the semiconductor layer on the second semiconductor layer side;
A source electrode, a drain electrode, a gate electrode that is provided on the second semiconductor layer and controls a flow of electrons flowing through a two-dimensional electron gas layer between the source electrode and the drain electrode;
With
A third semiconductor layer made of a p-type nitride semiconductor and a nitride semiconductor provided between the third semiconductor layer and the gate electrode are disposed between the gate electrode and the second semiconductor layer. A fourth semiconductor layer,
The gate electrode is provided in contact with the fourth semiconductor layer, and the gate electrode is in Schottky contact.

The field effect transistor according to the present invention is
A first semiconductor layer made of a first nitride semiconductor; and a second semiconductor layer made of a second nitride semiconductor having a bandgap energy larger than that of the first nitride semiconductor. A semiconductor stacked structure in which a two-dimensional electron gas layer is formed at an interface of the semiconductor layer on the second semiconductor layer side;
A source electrode, a drain electrode, a gate electrode that is provided on the second semiconductor layer and controls a flow of electrons flowing through a two-dimensional electron gas layer between the source electrode and the drain electrode;
With
A third semiconductor layer made of a p-type nitride semiconductor and a nitride semiconductor provided between the third semiconductor layer and the gate electrode are disposed between the gate electrode and the second semiconductor layer. A fourth semiconductor layer,
The fourth semiconductor layer has a p-type impurity concentration of 5 × 10 ¹⁷ cm ⁻³ or less and a film thickness of 3 nm or more.

  Therefore, according to the present invention, it is possible to provide a field effect transistor made of a nitride semiconductor that has a high threshold voltage, can reduce a gate leakage current, and can obtain a large maximum current and a low resistance.

It is sectional drawing which shows typically the structure of the field effect transistor of embodiment which concerns on this invention. It is a figure which shows the band structure of the field effect transistor of FIG. Example 4 and 5 according to the present invention, is a graph of drain current I _d with respect to the gate voltage V _g. It is a graph which shows the gate leakage current Ig of Example 4 and 5 which concerns on this invention. It is a graph which shows the threshold value _Vth of Examples 1-5 which concern on this invention. It is a top view of the field effect transistor of the Example which concerns on this invention.

  Hereinafter, field effect transistors according to embodiments of the present invention will be described with reference to the drawings.

Embodiment.
The field effect transistor according to the embodiment of the present invention is a GaN-based HEMT. As shown in FIG. 1, for example, a first nitride semiconductor layer 11 (first semiconductor layer) made of undoped GaN, for example, And a semiconductor multilayer structure 10 including a second nitride semiconductor layer 12 (second semiconductor layer) made of AlGaN containing undoped or n-type impurities. In the semiconductor stacked structure 10 described above, the second nitride semiconductor layer is composed of a second nitride semiconductor having a bandgap energy larger than that of the first nitride semiconductor, whereby the second nitride semiconductor is formed. A two-dimensional electron gas layer 15 is formed on the first nitride semiconductor layer 11 in the vicinity of the interface with the semiconductor layer. In the above configuration, the depletion layer 16 controls the two-dimensional electron gas layer 15 (channel) in response to a voltage applied to the gate electrode 21 described later.
The semiconductor multilayer structure 10 according to the embodiment may further include a spacer layer 13 made of, for example, AlN between the first nitride semiconductor layer 11 and the second nitride semiconductor layer 12.

  In the semiconductor multilayer structure 10 of the embodiment, for example, the mesa portion 10a is formed in a stripe shape, and the two-dimensional electron gas layer 15 exists only in the mesa portion. That is, the mesa portion 10a is formed by removing both sides of the first nitride semiconductor layer 11 to the middle of the first nitride semiconductor layer 11, for example, by etching or the like, and the two-dimensional electron gas layer 15 is formed in the first portion of the mesa portion 10a. The nitride semiconductor layer 11 is formed over the entire vicinity of the interface with the second nitride semiconductor layer 12.

  In the field effect transistor of the embodiment, the source electrode 32 is provided, for example, on one of the two side surfaces (first side surface) of the mesa unit and connected to the two-dimensional electron gas layer 15. The source electrode 32 may be provided so as to extend from the first side surface of the mesa portion to the upper surface of the mesa portion, or provided only on the upper surface of the mesa portion as long as it is electrically connected to the two-dimensional electron gas layer 15. It may be. When the source electrode 32 is provided only on the upper surface of the mesa portion, for example, the second nitride semiconductor layer 12 is doped with an n-type impurity to make the resistance low, or the portion where the source electrode 32 is formed is highly doped with n-type. A high-concentration source region having a low resistance can be formed by doping impurities.

  In the field effect transistor of the embodiment, the drain electrode 33 is provided, for example, on the other of the two side surfaces (second side surface) of the mesa unit and connected to the two-dimensional electron gas layer 15. The drain electrode 33 may be provided to extend from the second side surface of the mesa unit 10 a to the upper surface of the mesa unit, or provided only on the upper surface of the mesa unit as long as it is electrically connected to the two-dimensional electron gas layer 15. It may be done. When the drain electrode 33 is provided only on the upper surface of the mesa portion, as in the case of the source electrode 32, for example, the second nitride semiconductor layer 12 is doped with an n-type impurity to reduce resistance, or the drain electrode 33 is formed. A high-concentration drain region having a low resistance can be formed by doping the portion to be doped with n-type impurities at a high concentration.

  In the field effect transistor of the embodiment, the gate structure 20 including the gate electrode 21 is made of, for example, a third p-type nitride semiconductor layer 23 (third semiconductor layer) made of p-type GaN and, for example, undoped GaN. It further includes a fourth nitride semiconductor layer 22 (fourth semiconductor layer) in Schottky contact with the gate electrode 21.

With the gate structure as described above, the following operational effects can be obtained.
First, a p-type third p-type nitride semiconductor layer 23 is formed on the second nitride semiconductor layer 12 to thereby form the first nitride semiconductor layer 11 and the second nitride semiconductor layer 12. Potential energy is raised, and normally-off becomes easier. That is, normally-off is the conduction band of the portion where the two-dimensional electron gas layer 15 occurs when the gate voltage is zero (near the interface between the first nitride semiconductor layer 11 and the second nitride semiconductor layer 12). This is realized by raising the lower end of Fermi level higher than the Fermi level, but the lower end of the conduction band is raised by the amount of potential energy being raised, and normally-off is facilitated. The position of the lower end of the conduction band of the two-dimensional electron gas layer 15 can also be adjusted by appropriately changing the composition of the first nitride semiconductor layer 11 and the second nitride semiconductor layer 12.

Further, in addition to the p-type third p-type nitride semiconductor layer 23, in this embodiment, the undoped fourth nitride semiconductor layer 22 is replaced with the third p-type nitride semiconductor layer 21 and the gate electrode 21. Between.
Since the fourth nitride semiconductor layer 22 is undoped, the hole concentration is low, the junction with the gate electrode 21 is Schottky, and a depletion layer is generated in the vicinity of the interface with the gate electrode 21. In a field effect transistor including a gate structure 20 having a stacked structure including such a depletion layer, when a voltage is applied in a direction in which the gate voltage is positive, an ON operation is performed mainly in the gate structure. It is considered that a bias is applied to a small portion, that is, a depletion layer in the fourth nitride semiconductor layer 22, and a portion where the two-dimensional electron gas layer 15 of the first nitride semiconductor layer 11 is generated is hardly biased. That is, by providing the fourth nitride semiconductor layer 22, it is possible to reduce the conduction band pull-down width associated with the application of the gate voltage in the portion where the two-dimensional electron gas layer 15 is generated.
This is shown in the schematic diagram of the band gap of FIG. The schematic diagram of FIG. 2 shows a state where a two-dimensional electron gas layer has not yet been generated with a gate voltage lower than the threshold value. Thus, even when a voltage is applied in the direction in which the gate voltage is positive (+), the depletion layer at the Schottky junction between the fourth nitride semiconductor layer 22 and the gate electrode 21 is greatly lowered (in the arrow A1). However, there is little decrease in the portion that becomes the two-dimensional electron gas layer (indicated by arrow A2).

As described above, unless the gate bias is applied strongly, the lower end of the conduction band of the portion that becomes the two-dimensional electron gas layer does not fall below the Fermi level FL, and the two-dimensional electron gas layer (channel) is not generated. Therefore, by providing the gate structure of this embodiment, a normally-off transistor having a large threshold voltage of the gate electrode can be realized. In FIG. 2, the spacer layer 13 is omitted, but the same applies to the case where the spacer layer 13 is present.
Further, when the gate bias is increased, the gate leakage current tends to increase in the conventional structure. However, in the structure of this embodiment, the gate bias is increased and the conduction band of the first nitride semiconductor layer 11 is lower than the Fermi level. Even when the two-dimensional electron gas layer is generated by lowering the gate current, the Schottky barrier is present because the gate electrode 21 and the fourth nitride semiconductor layer 22 are in Schottky junction, and the gate leakage current can be reduced.

Therefore, the field effect transistor of this embodiment having the gate structure 20 can increase the threshold and reduce the gate leakage current when a forward bias is applied to the gate electrode.
In addition, since the gate leakage current is reduced, the gate voltage can be sufficiently increased so that no depletion layer remains in the channel, so that the resistance between the source and the drain can be sufficiently reduced. The maximum current that can be obtained can be increased.

 Thus, in the field effect transistor of this embodiment, in order to increase the threshold value, it is important that the gate electrode 21 and the fourth nitride semiconductor layer 22 are in Schottky junction. In order to achieve good Schottky junction, the thickness of the fourth nitride semiconductor layer 22 is preferably set to 3 nm or more, more preferably 5 nm or more, and even more preferably 7 nm or more. The film thickness of the fourth nitride semiconductor layer 22 is preferably set to 1000 nm or less, more preferably 300 nm or less. Furthermore, the film thickness can be reduced to 100 nm or less. As a result, it is possible to prevent an excessive increase in the threshold voltage and the gate drive voltage necessary for actual driving. Moreover, it is preferable to set it as such a film thickness range also from the point of manufacture accuracy. That is, when the third nitride semiconductor layer 23 and the fourth nitride semiconductor layer 22 are selectively provided directly below the gate electrode 21 as in the gate structure 20 shown in FIG. After the growth of the third nitride semiconductor layer 23 and the fourth nitride semiconductor layer 22, a part thereof is removed by etching or the like to expose the second nitride semiconductor layer 12 and have such a shape. When the removal amount is excessively large, it is difficult to control the removal amount. Therefore, the thickness of the fourth nitride semiconductor layer 22 is preferably set in the above range. When selective etching described later is used, the removal amount can be easily controlled. However, the larger the removal amount, the larger the etching time margin becomes, and the exposed second nitride semiconductor layer 12 is etched. As a result, the damage to the second nitride semiconductor layer 12 due to etching tends to increase. For this reason, it is preferable that the film thickness of the fourth nitride semiconductor layer 22 be in the above range.

  Hereinafter, each component in the field effect transistor according to the embodiment will be described in detail.

First nitride semiconductor layer 11
The first nitride semiconductor layer 11 is a layer on which the two-dimensional electron gas layer 15 is formed. In the structure in which the source electrode 32 and the drain electrode 33 are provided on the same surface side as the gate electrode 21, an undoped nitride semiconductor is formed. It is preferable that it is comprised. In a structure represented by a vertical GaN-based HEMT, the source electrode 32 is provided on the same surface side (upper surface side) as the gate electrode 21, and the drain electrode is provided on the surface (lower surface) opposite to the gate electrode 21. Preferably, the n-type nitride semiconductor is doped with a type impurity.
The material constituting the layer in which the two-dimensional electron gas layer 15 is formed is not limited to GaN, and can be selected from a group III nitride semiconductor. In _x Al _y Ga _1-xy N (0 ≦ x, 0 ≦ y, x + y ≦ 1) can be used.

Second nitride semiconductor layer 12
The second nitride semiconductor layer 12 is preferably an AlGaN layer when the first group nitride semiconductor layer 11 is a GaN layer. As the AlGaN layer, Al _a Ga _1-a N (0 <A <1) can be used. Preferably, 0 <a ≦ 0.4. If the Al mixed crystal ratio a is less than 0.4, an AlGaN layer with good crystallinity can be formed, and the mobility can be increased. In order to increase the withstand voltage, an undoped layer is preferable.
As described above, when the first nitride semiconductor layer 11 is a GaN layer, the second nitride semiconductor layer is preferably an AlGaN layer, but the second nitride semiconductor layer is the first nitride semiconductor layer. The first and second nitride semiconductor layers may have various band gap energies as long as the two-dimensional electron gas layer is formed on the first nitride semiconductor layer. A nitride semiconductor material can be employed.
The second nitride semiconductor layer 12 can reduce the resistance of the field-effect transistor by increasing the film thickness, increasing the n-type impurity concentration, increasing the Al mixed crystal ratio of AlGaN, etc. This is a relationship between the threshold rise and the trade-off. However, as described above, the field effect transistor according to the present embodiment can increase the threshold without increasing the resistance, so that a sufficient threshold can be obtained even when such a resistance reduction means is employed. Is possible.

Semiconductor laminated structure 10
The semiconductor multilayer structure 10 may further include the following layers in addition to the first nitride semiconductor layer 11 and the second nitride semiconductor layer 12.

(A) Spacer layer 13 provided between first nitride semiconductor layer 11 and second nitride semiconductor layer 12
When the first nitride semiconductor layer 11 is a GaN layer and the second nitride semiconductor layer 12 is an AlGaN layer, the spacer layer 13 can be composed of, for example, an AlN layer.
The spacer layer 13 made of AlN is provided in a thinner film than the second nitride semiconductor layer 12 made of AlGaN. By providing such a spacer layer 13, the carrier mobility in the channel can be improved as compared with the case of only the second nitride semiconductor layer 12. When the spacer layer 13 is made of AlN, the film thickness is preferably 2 nm or less so that it can be formed with good crystallinity, and particularly preferably about 0.5 to 1 nm.

Source electrode 32, drain electrode 33
The electrodes such as the source electrode 31 and the drain electrode 33 are made of a material having excellent conductivity such as Ti, Al, Cu, W, Au, Ag, Mo, Ni, Pt, In, Rh, Ir, and Cr. Moreover, it is not limited to a metal material, A conductive oxide, the conductive plastic which has electroconductivity, etc. can be utilized. Furthermore, the electrode is composed of not only a single element material but also a plurality of elements such as alloying, eutectic, mixed crystal, etc., and for example, ITO, zinc oxide (ZnO) or the like can be used. Furthermore, a layer structure of two or more layers can be employed. Preferably, a Ti / Al electrode is employed for an AlGaN-based or GaN-based semiconductor layer. Further, the pad electrode may be formed in consideration of the adhesion between each electrode and the wire. In this specification, for example, Ti / Al refers to a structure in which Ti and Al are sequentially stacked from the semiconductor side.

Gate structure 20
In the present invention, as described above, the gate structure 20 includes the third p-type nitride semiconductor layer 23, the undoped fourth nitride semiconductor layer 22, and the gate electrode 21 in this order from the semiconductor multilayer structure 10 side. The fourth nitride semiconductor layer 22 is in Schottky contact with the gate electrode 21.

(Third p-type nitride semiconductor layer 23)
The third p-type nitride semiconductor layer 23 can be formed of a group III nitride semiconductor, but is preferably formed of p-type AlGaN or p-type GaN. In the case of forming with AlGaN, AlGaN having a band gap energy smaller than that of the second nitride semiconductor layer 12 is used. Further, as described above, in the case where a part thereof is removed, selective etching is performed in which the third p-type nitride semiconductor layer 23 is selectively etched so that the second nitride semiconductor layer 12 is not removed. In this case, the third p-type nitride semiconductor layer 23 has a composition different from that of the second nitride semiconductor layer 12. For example, if the second nitride semiconductor layer 12 is AlGaN, the third p-type nitride semiconductor layer 23 is preferably GaN. The third p-type nitride semiconductor layer 23 contains, for example, Mg as a p-type impurity. The hole concentration of the third p-type nitride semiconductor layer 23 can be 5 × 10 ¹⁷ cm ⁻³ or more.
The film thickness of the third p-type nitride semiconductor layer 23 is preferably 5 nm or more, more preferably 10 nm or more in order to obtain the above-described effect of providing the p-type layer. When the film thickness is increased, the gate bias is less effective for the channel, and for ease of manufacture, the thickness is preferably 1000 nm or less, more preferably 100 nm or less. Typically, the thickness is 10 to 50 nm.

(Fourth Nitride Semiconductor Layer 22)
The fourth nitride semiconductor layer 22 can be formed of a group III nitride semiconductor having a p-type impurity concentration lower than that of the third p-type nitride semiconductor layer 23 or containing no p-type impurity. Specifically, it is preferable that p-type impurity concentration of 1 × ¹⁰ 18 ^{cm -3} or less, and more preferably less than 1 × ¹⁰ 18 ^{cm -3,} even more preferably 5 × ¹⁰ 17 ^{cm -3} or less And Furthermore, it is preferable to set it as 1 * 10 < ¹⁷ > cm <^-3> or less. Similarly, the n-type impurity concentration is preferably 1 × 10 ¹⁷ cm ⁻³ or less. Preferably, it is made of undoped GaN. In the present embodiment, undoped means that an impurity is not intentionally added at the time of formation, for example, an impurity concentration of 1 × 10 ¹⁷ cm ⁻³ or less or no impurity. The hole concentration of the fourth nitride semiconductor layer 22 is preferably smaller than 5 × 10 ¹⁷ cm ⁻³ .
In addition, the third p-type nitride semiconductor layer 23 and the fourth nitride semiconductor layer 22 can have the same shape in plan view as viewed from the gate electrode side. The gate electrode 21 may be provided with a width smaller than these layers, and a part of the surface of the fourth nitride semiconductor layer 22 may be exposed from the gate electrode 21. The surface of the layer 22 can be completely covered. The third and fourth nitride semiconductor layers 22 and 23 provided between the gate electrode 21 and the second nitride semiconductor layer 12 are arranged so as not to contact the source electrode 32 and the drain electrode 33.
The film thickness of the fourth nitride semiconductor layer 22 is preferably 3 nm or more, more preferably 5 nm or more, and further preferably 7 nm or more. As shown in FIG. 5 described later, the threshold can be raised by providing a fourth nitride semiconductor layer 22 of 3 nm or more, and the threshold can be further raised by setting it to 7 nm or more. Furthermore, the thickness is preferably 10 nm or more, and the gate leakage current can be significantly reduced by setting the thickness to 50 nm or more. When the film thickness is increased, the gate bias is less effective for the channel, and for ease of manufacture, the thickness is preferably 1000 nm or less, more preferably 300 nm or less. The film thickness can be further reduced to 100 nm or less. In the present embodiment, the third p-type nitride semiconductor layer and the fourth nitride semiconductor layer are provided as separate layers. As a form, the third p-type nitride semiconductor layer and the fourth nitride semiconductor layer are formed as one layer, and a p-type impurity corresponding to the fourth nitride semiconductor layer is formed on the side in contact with the gate electrode of this layer A low concentration region can be formed, and a p-type impurity high concentration region corresponding to the third p-type nitride semiconductor layer can be formed on the channel side of the region. The p-type impurity concentration may be continuously changed.

(Gate electrode 21)
As a material of the gate electrode 21, a material that makes a Schottky contact with the fourth nitride semiconductor layer 22 can be selected. Examples of such a material include materials having a small work function, and it is preferable to use Hg, Zr, Ti, Ta, Al, Zn, and Fe. For example, Ti / Al or Ti / Al / Ti / Pt is used. Further, a pad electrode for connecting a wire or the like may be further provided thereon.

  Examples according to the present invention will be described below.

Example As an example, in the gate structure, the thickness of the fourth nitride semiconductor layer 22 is 3 nm (Example 1), 5 nm (Example 2), 7 nm (Example 3), 10 nm (Example 4). A field effect transistor having a thickness of 50 nm (Example 5) was prepared, and each threshold voltage was measured.
In Examples 1 to 5, the thickness of the fourth nitride semiconductor layer 22 other than the thickness was set as follows.
The electrode arrangement (planar structure) viewed from above the field effect transistors of Examples 1 to 5 was as shown in FIG. 6, and the dimensions thereof were described later.

Semiconductor laminated structure 10
The semiconductor multilayer structure 10 includes a first nitride semiconductor layer 11 made of an undoped GaN layer having a thickness of 3 μm and a spacer layer made of undoped AlN having a thickness of 0.75 nm on a sapphire substrate via a buffer layer. 13 and a second nitride semiconductor layer 12 made of undoped Al _0.3 Ga _0.7 N having a thickness of 11 nm were sequentially stacked.

Mesa structure 10a
The mesa structure 10a was produced by laminating each semiconductor layer on a sapphire substrate and then removing both sides of the portion to be the mesa portion 10a by etching to the middle of the first nitride semiconductor layer 11.
The mesa portion 10a was configured such that the length L in the longitudinal direction was 12 μm, the width W1 was 100 μm, and the height h was 100 nm.

Gate structure 20
The gate structure 20 is formed by sequentially stacking a third nitride semiconductor layer 23 made of p-type GaN having a thickness of 20 nm and a fourth nitride semiconductor layer 22 made of undoped GaN, and then the third nitride semiconductor layer 23. A part of the fourth nitride semiconductor layer 22 was removed, and the mesa structure 10a was formed over the entire length so that the width W2 was 1 μm. The gate electrode 21 was formed on the fourth nitride semiconductor layer 22 with substantially the same width.
The gate electrode 21 has a four-layer structure of Ti (thickness 10 nm) / Al (thickness 100 nm) / Ti (thickness 50 nm) / Pt (thickness 200 nm) from the fourth nitride semiconductor layer 22 side. did.

Source electrode 32, drain electrode 33
For example, the source electrode 32 extends from one side surface of the mesa unit 10 to the upper surface of the mesa unit 10, and the drain electrode 33 extends from the other side surface of the mesa unit 10 to the upper surface of the mesa unit 10. Formed. The intervals between the source and drain electrodes 32 and 33 and the gate electrode 21 (gate structure 20) were 2 μm and 7 μm, respectively.

Furthermore, in order to compare with Examples 1 to 5, a field effect transistor produced in the same manner as in Example was produced except that the fourth nitride semiconductor layer 22 made of undoped GaN was not formed. did.
A protective film 40 made of SiO ₂ was formed on the upper surfaces of the field effect transistors of the example and the comparative example, except for the connection surfaces of the gate electrode 21, the source electrode 32, and the drain electrode 33.

The threshold voltage _Vth at the drain current I _d = 1 mA / mm per gate electrode width of the field effect transistors of Examples 1 to 5 and the field effect transistor of the comparative example manufactured as described above was evaluated.
The result is shown in FIG.
As shown in FIG. 5, the threshold value V _th of the field effect transistor of the comparative example is about 1.3 V, whereas the threshold value V _th of the field effect transistor of the example is about a low value (Example 2). The voltage was 1.9 V, and the other Examples 1 and 3-5 were all 2 V or higher.
Further, when the thickness of the fourth nitride semiconductor layer 22 is 7 nm or more, the threshold value _Vth tends to increase as the thickness increases.

In Examples 4 and 5 show the drain current versus gate voltage V _g of Comparative Example 3 shows a gate leakage current in FIG.

DESCRIPTION OF SYMBOLS 15 Two-dimensional electron gas layer 10 Semiconductor laminated structure 11 GaN layer 12 AlGaN layer 16 Depletion layer 20 Gate structure 21 Gate electrode 22 4th nitride semiconductor layer 23 p-type GaN layer 32 Source electrode 33 Drain electrode 40 Protective film

Claims (8)

A first semiconductor layer made of a first nitride semiconductor; and a second semiconductor layer made of a second nitride semiconductor having a bandgap energy larger than that of the first nitride semiconductor. A semiconductor stacked structure in which a two-dimensional electron gas layer is formed at an interface of the semiconductor layer on the second semiconductor layer side;
A source electrode, a drain electrode, a gate electrode that is provided on the second semiconductor layer and controls a flow of electrons flowing through a two-dimensional electron gas layer between the source electrode and the drain electrode;
With
A third semiconductor layer made of a p-type nitride semiconductor and a nitride semiconductor provided between the third semiconductor layer and the gate electrode are disposed between the gate electrode and the second semiconductor layer. A fourth semiconductor layer,
The field effect transistor, wherein the gate electrode is provided in contact with the fourth semiconductor layer, and the gate electrode is in Schottky contact.   The field effect transistor according to claim 1, wherein the fourth semiconductor layer has a p-type impurity concentration lower than that of the third semiconductor layer. 3. The field effect transistor according to claim 1, wherein the fourth semiconductor layer has a p-type impurity concentration of 1 × 10 ¹⁸ cm ⁻³ or less and a thickness of 7 nm or more. A first semiconductor layer made of a first nitride semiconductor; and a second semiconductor layer made of a second nitride semiconductor having a bandgap energy larger than that of the first nitride semiconductor. A semiconductor stacked structure in which a two-dimensional electron gas layer is formed at an interface of the semiconductor layer on the second semiconductor layer side;
A source electrode, a drain electrode, a gate electrode that is provided on the second semiconductor layer and controls a flow of electrons flowing through a two-dimensional electron gas layer between the source electrode and the drain electrode;
With
A third semiconductor layer made of a p-type nitride semiconductor and a nitride semiconductor provided between the third semiconductor layer and the gate electrode are disposed between the gate electrode and the second semiconductor layer. A fourth semiconductor layer,
The fourth semiconductor layer has a p-type impurity concentration of 1 × 10 ¹⁸ cm ⁻³ or less and a film thickness of 3 nm or more.   The field effect transistor according to claim 1, wherein the third semiconductor layer is made of p-type GaN.   The field effect transistor according to claim 1, wherein the fourth semiconductor layer is made of GaN.   The field effect transistor according to claim 1, wherein the film thickness of the fourth semiconductor layer is 10 nm or more.   The field effect transistor according to claim 1, wherein the film thickness of the fourth semiconductor layer is 50 nm or more.

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