JP2013183034A - Power semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve trade-off between small on-resistance and large voltage-withstanding.SOLUTION: A gallium nitride substrate 1 is provided on a first electrode 31 and is formed by a gallium nitride semiconductor. A drift region 11 is provided on the gallium nitride substrate 1 and is formed by a group III nitride semiconductor having a larger energy gap compared to an energy gap of the gallium nitride semiconductor. A semiconductor element is provided on the drift region 11. A second electrode 132 is provided on the semiconductor element so that electric connection with the first electrode 31 is controlled by the semiconductor element.

Description

  The present invention relates to a power semiconductor device, and more particularly to a power semiconductor device having a gallium nitride substrate.

  In a power semiconductor device, generally, a small on-resistance and a large breakdown voltage are in a trade-off relationship. In order to solve this problem, it has been studied to use a wide band gap semiconductor such as a gallium nitride (GaN) based semiconductor in place of a silicon semiconductor that has been widely used. For example, the thing using the two-dimensional electron gas (2DEG) provided using the heterojunction is proposed.

  For example, a semiconductor device according to Japanese Patent Application Laid-Open No. 2006-286542 includes a GaN-based semiconductor layer having an opening, an electron traveling layer formed on a side surface of the opening, and an electron traveling formed on a side surface on the opening side of the electron traveling layer. An electron supply layer having a larger band gap than the layer, a gate electrode formed on the side surface of the electron supply layer on the opening side, a source electrode formed on the GaN-based semiconductor layer, and a source electrode of the GaN-based semiconductor layer And a drain electrode connected to the surface to be connected. Here, the GaN-based semiconductor is, for example, any one of GaN, AlN and InN, or a mixed crystal thereof.

JP 2006-286542 A

  With the recent increase in demand for the performance of power semiconductor devices, it is desired to further eliminate the trade-off between a small on-resistance and a large breakdown voltage.

  The present invention has been made to solve the above-described problems, and an object thereof is to improve a trade-off between a small on-resistance and a large breakdown voltage.

  The power semiconductor device of the present invention includes a first electrode, a gallium nitride substrate, a drift region, a semiconductor element, and a second electrode. The gallium nitride substrate is provided on the first electrode and is made of a gallium nitride semiconductor. The drift region is provided on the gallium nitride substrate and is made of a group III nitride semiconductor having an energy gap larger than that of the gallium nitride semiconductor. The semiconductor element is provided on the drift region. The second electrode is provided on the semiconductor element such that the electrical connection with the first electrode is controlled by the semiconductor element.

  According to this power semiconductor device, a group III nitride semiconductor having an energy gap larger than that of the gallium nitride semiconductor is used in the drift region. Thereby, the trade-off between a small on-resistance and a large breakdown voltage can be improved as compared with the case where a drift region made of a gallium nitride semiconductor is used.

  The group III nitride semiconductor may contain at least one of Ga and In and Al as a group III element. Thereby, a group III nitride semiconductor having an energy gap larger than that of the gallium nitride semiconductor can be obtained.

The group III nitride semiconductor may contain only one of Ga and In and Al as a group III element. Thereby, compared with the case where both Ga and In are used, the kind of element used can be decreased. Thereby, the manufacturing method can be further simplified. The group III nitride semiconductor may be Al _x Ga _1-x N (0 <x <1).

The group III nitride semiconductor may be Al _x In _y Ga _1-xy N (0 <x <1, 0 <y <1, x + y <1). Thus, by adjusting the two parameters x and y, it becomes easy to achieve consistency with the lattice constant of the gallium nitride substrate.

  Preferably, the semiconductor element includes a gallium nitride region made of a gallium nitride semiconductor in contact with the second electrode. Thereby, the connection between the semiconductor element and the second electrode can be made more ohmic.

  Preferably, the group III nitride semiconductor has the same lattice constant as that of the gallium nitride semiconductor. Thereby, the lattice constant of the drift region and the lattice constant of the gallium nitride substrate become the same. Therefore, mismatch of lattice constants between the drift region and the gallium nitride substrate can be suppressed.

  The semiconductor element includes, for example, at least one of HFET (heterojunction field effect transistor), JFET (junction field effect transistor), MISFET (Metal Insulator Semiconductor Field Effect Transistor), and diode. Thereby, in a semiconductor device having at least one of HFET, JFET, MISFET, and diode, the trade-off between a small on-resistance and a large breakdown voltage can be improved.

  As described above, according to the present invention, a trade-off between a small on-resistance and a large breakdown voltage can be improved.

FIG. 3 is a partial cross-sectional view taken along line II of FIG. 2 schematically showing the configuration of the power semiconductor device according to the first embodiment of the present invention. FIG. 2 is a schematic plan view of FIG. 1. It is a graph which shows roughly a lattice constant and an energy gap about GaN, AlN, and InN, and these mixed crystals. FIG. 2 is a diagram schematically showing a current path in FIG. 1. It is a fragmentary sectional view which shows schematically the structure of the semiconductor device for electric power in Embodiment 2 of this invention. FIG. 6 is a partial perspective view schematically showing a configuration of a semiconductor layer in FIG. 5. FIG. 6 is a partial plan view schematically showing a configuration of a semiconductor layer in FIG. 5. FIG. 8 is a partial plan view showing the configuration of the semiconductor layer of FIG. 7 in more detail. It is a fragmentary sectional view which shows schematically the structure of the semiconductor device for electric power in Embodiment 3 of this invention. It is a fragmentary sectional view which shows schematically the structure of the semiconductor device for electric power in Embodiment 4 of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
First, an outline of the configuration of the power semiconductor device 100 of the present embodiment will be described.

  1 and 2, a power semiconductor device 100 includes a GaN substrate 1 (gallium nitride substrate), a drain electrode 31 (first electrode), a source electrode 132 (second electrode), and a gate electrode 130. A semiconductor layer 110, an electron transit layer 121, and an electron supply layer 122.

  The GaN substrate is made of a gallium nitride semiconductor to which a conductivity type impurity is added so as to have an n-type (first conductivity type). The GaN substrate 1 is provided on a drain electrode 31 that is an ohmic electrode.

  The semiconductor layer 110 includes an n-type n drift region 11, a p-type p region 112, and an n-type n region 113. The n drift region 11 is provided on the GaN substrate 1. On the n drift region 11, an HFET (semiconductor element) having an n-type channel is provided. The source electrode 132 is provided on the HFET so that the electrical connection with the drain electrode 31 is switched by the HFET.

  The n region 113 is a gallium nitride region made of a gallium nitride (GaN) semiconductor and is in ohmic contact with the source electrode 132. Preferably, the p region 112 is also a gallium nitride region made of a gallium nitride (GaN) semiconductor and is in ohmic contact with the source electrode 132.

Referring to FIG. 3, n drift region 11 is made of a III group nitride semiconductor having a larger energy gap E _g than the energy gap E _GaN gallium nitride (GaN) semiconductor. The group III nitride semiconductor may contain at least one of Ga and In and Al as a group III element. Such a group III nitride semiconductor corresponds to a hatched portion in the figure. The group III nitride semiconductor may contain only one of Ga and In and Al as a group III element. For example, the group III nitride semiconductor is Al _x Ga _1-x N (0 <x <1). Alternatively, the group III nitride semiconductor may be Al _x In _y Ga _1-xy N (0 <x <1, 0 <y <1, x + y <1). Preferably, the group III nitride semiconductor has the same lattice constant L _c as the lattice constant L _{GaN of the} gallium nitride semiconductor.

Next, details of the power semiconductor device 100 will be described.
Referring to FIGS. 1 and 2 again, the semiconductor layer 110 has a back surface F1 and an upper surface F2 that face each other in the thickness direction (vertical direction in FIG. 1). The n drift region 11 of the semiconductor layer 110 forms a back surface F <b> 1 that faces the GaN substrate 1. The p region 112 is provided on the n drift region 11 so as to be separated from the back surface F1 by the n drift region 11. The n region 113 is provided on the p region 112 so as to be separated from the n drift region 11 by the p region 112, and forms the upper surface F2.

  On the upper surface F2 of the semiconductor layer 110, a gate trench GT that penetrates the n region 113 and the p region 112 to reach the n drift region 11 and has a bottom portion BT and a side wall SG is provided. The gate electrode 130 is a Schottky electrode provided on the electron supply layer 122 so as to face the p region 112 via the electron supply layer 122 on the sidewall SG. The gate electrode 130 is, for example, a Ni / Au electrode. Preferably, the side wall SG of the gate trench GT is inclined with respect to the upper surface F2 of the semiconductor layer 110 by an angle larger than 0 ° and smaller than 90 °.

  The electron transit layer 121 covers the p region 112 of the semiconductor layer 110 on the sidewall SG of the gate trench GT. The electron transit layer 121 is made of undoped GaN. That is, the electron transit layer is a GaN film. The electron supply layer 122 is provided on the electron transit layer 121. The electron supply layer 122 is made of AlGaN having a band gap larger than that of undoped GaN. That is, the electron supply layer 122 is an AlGaN film. With this configuration, 2DEG can be generated by a heterojunction at the interface between the electron transit layer 121 and the electron supply layer 122. Therefore, a current path with low resistance can be provided along the interface between the electron transit layer 121 and the electron supply layer 122.

  The drain electrode 31 and the source electrode 132 are ohmic electrodes, for example, Al-based electrodes. Preferably, the source electrode 132 is in contact with the interface between the electron transit layer 121 and the electron supply layer 122.

  The operation of the power semiconductor device 100 will be described with reference to FIG. The power semiconductor device 100 is used as a switching element that switches a current path (see an arrow in the figure) between the drain electrode 31 and the source electrode 132. A positive voltage is applied to the drain electrode 31 with respect to the source electrode 132. The channel is formed by 2DEG generated at the interface between the electron transit layer 121 and the electron supply layer 22 on the side wall SG of the gate trench GT. The channel is sandwiched between the p region 112 and the gate electrode 130. When the voltage of gate electrode 130 is more positive than the threshold value, power semiconductor device 100 is in an on state. That is, electrons supplied from the source electrode 132 reach the n drift region 11 through the channel and are discharged from the drain electrode 31. In order to turn off the power semiconductor device 100, the current path is cut off between the gate electrode 130 and the p region 112, so that the voltage of the gate electrode 130 is more negative than the threshold value. It is said.

  According to power semiconductor device 100 of the present embodiment, group III nitride semiconductor having an energy gap larger than that of gallium nitride semiconductor is used for n drift region 11. Thereby, compared with the case where the n drift region 11 made from a gallium nitride semiconductor is used, the trade-off between a small on-resistance and a large breakdown voltage can be improved.

  The group III nitride semiconductor may contain at least one of Ga and In and Al as a group III element. Thereby, a group III nitride semiconductor having an energy gap larger than that of the gallium nitride semiconductor can be obtained.

  The group III nitride semiconductor may contain only one of Ga and In and Al as a group III element. Thereby, compared with the case where both Ga and In are used, the kind of element used can be decreased. Thereby, the manufacturing method can be further simplified.

The group III nitride semiconductor may be Al _x In _y Ga _1-xy N (0 <x <1, 0 <y <1, x + y <1). Thereby, by adjusting the two parameters x and y, it becomes easy to achieve consistency with the lattice constant of the GaN substrate 1.

  The HFET includes a p region 112 and an n region 113 as gallium nitride regions in contact with the source electrode 132 and made of a gallium nitride semiconductor. Thereby, the connection between the HFET and the source electrode 132 can be made more ohmic.

  The conductivity type (first conductivity type) of the n drift region 11 is n type. Thereby, the electrical resistance of the n drift region 11 can be reduced. Therefore, the on-resistance of the power semiconductor device 100 can be further reduced.

  Preferably, the group III nitride semiconductor has the same lattice constant as that of the gallium nitride semiconductor. Thereby, the lattice constant of the n drift region 11 and the lattice constant of the GaN substrate 1 become the same. Therefore, mismatch of lattice constants between the n drift region 11 and the GaN substrate 1 can be suppressed.

(Embodiment 2)
As shown in FIGS. 5 to 8, the power semiconductor device 200 is provided with a MISFET as a semiconductor element. The power semiconductor device 200 includes a GaN substrate 1, a semiconductor layer 210, a drain electrode 31, a source electrode 232, a gate insulating film 221, an interlayer insulating film 222, a gate electrode 230, and a source wiring layer 233. Have.

The semiconductor layer 210 has a back surface F1 and an upper surface F2 that face each other in the thickness direction (vertical direction in FIG. 1). The back surface F1 and the top surface F2 are substantially parallel to each other. The semiconductor layer 210 includes an n drift region 11, a p type p region 212, an n type n region 213, and a p type p ⁺ contact region 215. The p region 212 is provided on the n ⁻ drift region 11. N region 213 is provided on p region 212 and is separated from n ⁻ drift region 11 by p region 212. The p ⁺ contact region 215 is provided directly on a part of the p region 212. The p ⁺ contact region 215 forms part of the upper surface F2 of the semiconductor layer 210.

Preferably, the p region 212 is a gallium nitride region made from a gallium nitride (GaN) semiconductor. The p ⁺ contact region 215 is also preferably a gallium nitride region made from a gallium nitride (GaN) semiconductor.

The upper surface F2 of the semiconductor layer 210 is provided with a gate trench GT that penetrates the n region 213 and the p region 212 to reach the n ⁻ drift region 11 and has a bottom portion BT and a sidewall SS. Sidewall SS has a portion composed of n ⁻ drift region 11, p region 212, and n region 213.

Gate insulating film 221 is provided on p region 212 so as to connect between n ⁻ drift region 11 and n region 213. Specifically, the gate insulating film 221 covers the p region 212 of the semiconductor layer 210 on the sidewall SS. The gate electrode 230 is provided on the gate insulating film 221. Thereby, the gate electrode 230 is located on the p region 212 of the semiconductor layer 210 via the gate insulating film 221. The source electrode 232 is an ohmic electrode provided directly on the n region 213 and the p ⁺ contact region 215 of the semiconductor layer 210.

  Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof is not repeated.

  According to the present embodiment, the power semiconductor device 200 having the MISFET provided on the n drift region 11 can obtain substantially the same effect as that of the first embodiment.

(Embodiment 3)
As shown in FIG. 9, the power semiconductor device 300 is provided with a JFET as a semiconductor element. The power semiconductor device 300 includes a drain electrode 31, a GaN substrate 1, a semiconductor layer 310, and a source electrode 332.

The semiconductor layer 310 includes an n drift region 11, a p-type p gate region 312, and an n ⁺ layer 313. The p gate region 312 is embedded in the n ⁻ drift region 11 and has a function as a gate in the JFET. The n ⁺ layer 313 is provided on the n ⁻ drift region 11 so as to sandwich the n ⁻ drift region 11 with the GaN substrate 1. Preferably, the n ⁺ layer 313 is a gallium nitride region made from a gallium nitride (GaN) semiconductor. The source electrode 332 is provided on the n ⁺ layer 313.

  Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof is not repeated.

  According to the present embodiment, in power semiconductor device 200 having a JFET provided on n drift region 11, substantially the same effect as in the first embodiment can be obtained.

(Embodiment 4)
As shown in FIG. 10, the power semiconductor device 400 is provided with a diode as a semiconductor element. The power semiconductor device 400 includes an n-type GaN substrate 1, a semiconductor layer 410, a cathode electrode 431 (first electrode), and an anode electrode 432 (second electrode).

  The semiconductor layer 410 has a mesa structure. The semiconductor layer 410 includes a drift region 411 and a p-type p region 412 provided on the drift region 411. The drift region 411 is provided on the GaN substrate. The drift region 411 has an impurity concentration lower than that of the conductivity type impurity of the GaN substrate 1. The drift region 411 is a region that is not intentionally doped. Drift region 411 is made of a group III nitride semiconductor similar to n drift region 11 of the first embodiment.

  The cathode electrode 431 has substantially the same configuration as the drain electrode 31 of the first embodiment. The anode electrode 432 is an ohmic electrode provided on the p region 412.

  Preferably, the p region 412 is a gallium nitride region made from a gallium nitride (GaN) semiconductor.

  According to the present embodiment, in power semiconductor device 400 having a diode provided on drift region 411, substantially the same effect as in the first embodiment can be obtained.

  In each of the above embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but these conductivity types may be interchanged.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the claims of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 GaN substrate (gallium nitride substrate), 11 n drift region (drift region), 411 drift region, 121 electron transit layer, 122 electron supply layer, 31 drain electrode (first electrode), 100, 200, 300, 400 For power Semiconductor device, 110, 210, 310, 410 Semiconductor layer, 130, 230 Gate electrode, 132, 232, 332 Source electrode (second electrode), 431 Cathode electrode (first electrode), 432 Anode electrode (second electrode).

Claims (8)

A first electrode;
A gallium nitride substrate provided on the first electrode and made of a gallium nitride semiconductor;
A drift region provided on the gallium nitride substrate and made of a group III nitride semiconductor having an energy gap larger than that of the gallium nitride semiconductor;
A semiconductor element provided on the drift region;
A power semiconductor device comprising: a second electrode provided on the semiconductor element such that an electrical connection with the first electrode is controlled by the semiconductor element.   The power semiconductor device according to claim 1, wherein the group III nitride semiconductor includes at least one of Ga and In and Al as a group III element.   The power semiconductor device according to claim 1, wherein the group III nitride semiconductor includes only one of Ga and In and Al as a group III element. 2. The power semiconductor device according to claim 1, wherein the group III nitride semiconductor is Al _x Ga _1-x N (0 <x <1). 2. The power semiconductor device according to claim 1, wherein the group III nitride semiconductor is Al _x In _y Ga _1-xy N (0 <x <1, 0 <y <1, x + y <1).   The power semiconductor device according to claim 1, wherein the semiconductor element includes a gallium nitride region in contact with the second electrode and made of a gallium nitride semiconductor.   The power semiconductor device according to claim 1, wherein the group III nitride semiconductor has the same lattice constant as that of the gallium nitride semiconductor.   The power semiconductor device according to claim 1, wherein the semiconductor element includes at least one of HFET, JFET, MISFET, and diode.

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