JP2014107809A - Multiplexer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform bit-by-bit multiplexing/demultiplexing processing with a small delay by a control unit.SOLUTION: A multiplexer includes: an identification information storage unit 106 for identifying which received bit-by-bit data in a reception data sequence 601 is which terminal data; a distribution control unit 104 for distributing the received reception data sequence 601 to each terminal data buffer unit 105 on the basis of bit-by-bit data; a terminal data buffer readout control unit 107 for reading out data from the data buffer unit 105 according to allocation information indicative of a transfer destination of the terminal data; and according to a synchronous signal, a terminal data output unit (output data memory units 109, 110) for outputting the readout data to a line interface unit 3 or a terminal interface unit 4 as a transmission data sequence.

Description

  The present invention relates to a multiplexing device that is connected to a digital leased line or the like, accommodates a plurality of low-speed terminals, time-division multiplexes the terminal data, and efficiently transmits between bases via a digital leased line. .

  A conventional multiplexing apparatus includes a control unit having a plurality of time slot conversion memories capable of writing / reading in variable frame units, and a multi-frame Consists of a line interface unit with a write timing generation circuit that can instruct writing / reading to the alignment memory in variable frame units, a terminal interface unit, and a clock unit that generates and distributes clock and multiframe timing (For example, refer to Patent Document 1).

  Then, the control unit selects and processes the optimum multiframe size that reduces the delay time for each data with different transmission speeds for each multiframe alignment memory in the line interface unit and terminal interface unit. Notify information as you do. The line interface unit and the terminal interface unit perform low-delay demultiplexing processing by exchanging data in units of notified frames based on the information.

Japanese Patent Application Laid-Open No. 07-193554

  Since the conventional multiplexing apparatus is configured as described above, it is necessary to individually manage the number of frame units to be processed for each terminal data and to notify all line / terminal interface units from the control unit. There is a problem that communication for management control between the line / terminal interface unit becomes complicated.

  The present invention has been made to solve the above-described problems. The line interface unit and the terminal interface unit do not perform demultiplexing processing, transfer data to the control unit, and perform demultiplexing in bit units to the control unit. It is an object of the present invention to provide a multiplexing apparatus that includes a means and that can perform low-delay demultiplexing processing in a concentrated manner.

  The multiplexing device according to the present invention includes a clock unit that generates a synchronization signal, and outputs data received from the line as a received data string according to the synchronization signal, and detects and outputs synchronization information of the received data string An interface unit, a terminal interface unit that outputs data received from the terminal as a received data sequence according to the synchronization signal, and a received data sequence from the line interface unit or the terminal interface unit are received. And a control unit that performs demultiplexing processing of data in bit units, and the control unit holds identification information that identifies which terminal data is communicated between the data of each bit position of the multiframe, Based on the identification information, the synchronization signal, and the synchronization information, which terminal data is the bit-unit data of the received received data string A terminal data identification unit for identifying each received terminal data, a plurality of terminal data buffer units for storing input data, and a received data string received in bit units based on the identification result by the terminal data identification unit A distribution control unit that distributes data to each terminal data buffer unit, a terminal data buffer read control unit that reads data from the terminal data buffer unit according to allocation information indicating a transfer destination of terminal data, and a terminal signal according to a synchronization signal And a terminal data output unit that outputs the data read by the buffer read control unit to the line interface unit or the terminal interface unit as a transmission data string.

  Also, the multiplexing device according to the present invention includes a clock unit that generates a synchronization signal, a line interface unit that outputs data received from the line as a received data sequence according to the synchronization signal, and data received from the terminal according to the synchronization signal For receiving a received data sequence from the line interface unit or the terminal interface unit, and performing demultiplexing processing on the received data sequence in units of bits according to the synchronization signal A multi-frame synchronization detection unit that detects synchronization information of a received frame sequence received from the line interface unit, and between which terminals the data at each bit position of the multi-frame is communicated Holding identification information for identifying the identification information, synchronization signal and multi-frame synchronization detection unit Based on the detected synchronization information, a terminal data identification unit for identifying which terminal data is the bit-unit data of the received received data sequence, and a plurality of terminals that are provided for each terminal data and store input data Based on the identification result by the terminal data buffer unit and the terminal data identification unit, the distribution control unit that distributes the received data string received to the terminal data buffer unit for each bit unit of data, and the allocation information indicating the transfer destination of the terminal data A terminal data buffer read control unit for reading data from the terminal data buffer unit, and a terminal for outputting the data read by the terminal data buffer read control unit to the line interface unit or the terminal interface unit as a transmission data string according to the synchronization signal And a data output unit.

  The multiplexing apparatus according to the present invention outputs a data received from a line as a received data string according to the clock signal for generating a synchronizing signal and a synchronizing signal, and detects and outputs the synchronizing information of the received data string A line interface unit, a terminal interface unit that outputs data received from the terminal as a received data sequence according to the synchronization signal, and a received data sequence from the line interface unit or the terminal interface unit, and the received data according to the synchronization signal A control unit that performs demultiplexing processing of bit-wise data on the column, and the control unit holds identification information that identifies which terminal data the data of each bit position of the multiframe communicates with. Based on the identification information, the synchronization signal, and the synchronization information, which terminal receives the bit unit data of the received data string A terminal data identification unit for identifying the data and an address for each terminal data, and assigning a corresponding address to the bit-unit data of the received received data string based on the identification result by the terminal data identification unit A terminal data memory write address control unit, a single terminal data memory unit for storing a received data sequence in which an address is assigned for each bit unit data by the terminal data memory write address control unit, and an address for each terminal data The terminal data memory read address control unit reads the data assigned the corresponding address from the terminal data memory unit according to the allocation information indicating the transfer destination of the terminal data, and the terminal data memory read address control unit according to the synchronization signal. The read data is used as a transmission data string for the line interface unit or terminal interface. Those having a terminal data output section that outputs the over scan portion.

  According to the present invention, since it is configured as described above, the control unit is provided with means for demultiplexing each terminal data bit by bit, and the control unit performs the low-delay demultiplexing processing in a concentrated manner so that the terminal data There is no need to individually manage the number of processing frames for each time, and there is an effect that management control communication between the control unit, the line interface unit, and the terminal interface unit can be simplified.

It is a block diagram which shows the structure of the multiplexing apparatus which concerns on Embodiment 1 of this invention. It is a schematic diagram which shows the flow of the signal of the multiplexing apparatus which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the multiplexing apparatus which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the multiplexing apparatus which concerns on Embodiment 3 of this invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
Embodiment 1 FIG.
1 is a diagram showing a configuration of a multiplexing apparatus according to Embodiment 1 of the present invention.
As shown in FIG. 1, the multiplexing apparatus includes a control unit 1, a clock unit 2, a plurality of line interface units 3a and 3b, and a plurality of terminal interface units 4a and 4b. In the following description, the line interface units 3a and 3b and the terminal interface units 4a and 4b are referred to as a line interface unit 3 and a terminal interface unit 4 respectively, unless it is necessary to distinguish between them.

  The control unit 1 receives the received data sequence 601 from the line interface unit 3 or the terminal interface unit 4 in accordance with the signal 501 from the clock unit 2, and demultiplexes the data in bit units with respect to the data of the received data sequence 601. The processing is performed. The control unit 1 includes a temporary reception buffer unit 101, an identification information storage unit (terminal data identification unit) 102, a distribution / allocation processing high-speed clock generation unit 103, a distribution control unit 104, a plurality of terminal data buffer units 105a to 105n, Allocation information storage unit 106, terminal data buffer read control unit 107, line / terminal allocation control unit 108, output data memory units (terminal data output units) 109a and 109b for a plurality of terminal interface units, and output data for a plurality of line interface units The memory unit (terminal data output unit) 110a and 110b is configured. In the following description, the terminal data buffer units 105a to 105n, the terminal interface unit output data memory units 109a and 109b, and the line interface unit output data memory units 110a and 110b are respectively connected to the terminal data buffer units unless otherwise distinguished. Reference numeral 105 denotes an output data memory unit 109 for a terminal interface unit and an output data memory unit 110 for a line interface unit.

  The temporary reception buffer unit 101 receives and stores the received data string 601 from the line interface unit 3 or the terminal interface unit 4 via the reception bus 6.

  The identification information storage unit 102 stores in advance identification information for identifying which terminal data the data of each bit position of the multiframe communicates with. This identification information is mutually agreed between the multiplexers, and the address of the terminal data buffer unit 105 that is the storage destination is associated with the data at each bit position. Further, the identification information storage unit 102 receives the signal 501 from the clock unit 2 via the timing bus 5, and receives the received data string 601 output from the line interface unit 3 via the reception bus 6 from the line interface unit 3. Multi-frame information (synchronization information) 602 indicating what frame of the multi-frame is received is received. Then, the data in the reception data string 601 is specified in units of bits from the multiframe number of the reception data string 601 in the multiframe information 602 and the bit position from the head of the frame pulse in the signal 501, and the reception is performed from the identification information. It identifies which terminal the data of the bit unit of the data string 601 communicates with.

The distribution / allocation processing high-speed clock generation unit 103 generates a high-speed clock.
Based on the identification result by the identification information storage unit 102, the distribution control unit 104 uses the high-speed clock generated by the distribution / allocation processing high-speed clock generation unit 103 to receive the received data string 601 stored in the temporary reception buffer unit 101. Each bit unit of data is distributed to the terminal data buffer unit 105 and written.

  The terminal data buffer unit 105 is provided for each terminal data, and stores data distributed by the distribution control unit 104 in accordance with the high-speed clock generated by the distribution / allocation processing high-speed clock generation unit 103. The terminal data buffer unit 105 has a maximum number of inter-terminal communications that can be processed by the multiplexing device.

The allocation information storage unit 106 stores in advance allocation information indicating a transfer destination of each terminal data for performing transfer processing in bit units.
The terminal data buffer read control unit 107 receives the signal 501 from the clock unit 2 via the timing bus 5, and allocates the allocation data stored in the allocation information storage unit 106 at a timing synchronized with the clock and frame pulse in the signal 501. In accordance with the information, the terminal data buffer unit 105 is instructed to transfer the stored data to the line / terminal allocation control unit 108 and the allocation information is transferred to the line / terminal allocation control unit 108.

The line / terminal allocation control unit 108 starts from the terminal data buffer unit 105 according to the high-speed clock generated by the allocation / allocation processing high-speed clock generation unit 103 based on the allocation information transferred from the terminal data buffer read control unit 107. The transferred data is assigned to the output data memory unit 109 for the terminal interface unit or the output data memory unit 110 for the line interface unit.
At this time, when data is sent to a terminal connected to the multiplexing device, the data is transferred to the output data memory unit 109 for the terminal interface unit, and when the data is relayed to another multiplexing device, the data is transferred. The data is transferred to the output data memory unit 110 for the line interface unit. When transferring to the output data memory unit 110 for the line interface unit for relaying, the line / terminal allocation control unit 108 performs an order in which the bits of each terminal data are multiplexed in an arrangement arranged between the multiplexing devices. Control to write data with.

  The terminal interface unit output data memory unit 109 is provided for each transfer destination terminal interface unit 4 and is allocated by the line / terminal allocation control unit 108 according to the high-speed clock generated by the allocation / allocation processing high-speed clock generation unit 103. Stored data. The output data memory unit 109 for the terminal interface unit receives the signal 501 from the clock unit 2 via the timing bus 5, and transmits the stored data to the transmission data at a timing synchronized with the clock and the frame pulse in the signal 501. The data is output to the transmission bus 7 as a column 701.

  An output data memory unit 110 for the line interface unit is provided for each transfer destination line interface unit 3 and is allocated by the line / terminal allocation control unit 108 in accordance with the high-speed clock generated by the high-speed clock generation unit 103 for distribution / allocation processing. Stored data. Further, the output data memory unit 110 for the line interface unit receives the signal 501 from the clock unit 2 via the timing bus 5, and transmits the stored data to the transmission data at a timing synchronized with the clock and the frame pulse in the signal 501. The data is output to the transmission bus 7 as a column 701.

  The clock unit 2 includes various timing generation units 201 that generate signals (synchronization signals) 501 such as clocks for synchronous transmission, frame pulses, multi-frame pulses, and various timing signals, and distribute them to the respective units via the timing bus 5. Is.

  The line interface unit 3 transmits / receives data 801 and 803 to / from a carrier digital dedicated line or the like, and outputs the received data 801 to the control unit 1 as a received data string 601 in accordance with a signal 501 from the clock unit 2. At the same time, the multi-frame information 602 of the received data string 601 is detected and output to the control unit 1. The line interface units 3a and 3b have the same configuration. The line interface unit 3 includes a receiver 301, a transmission line clock extraction unit 302, a speed conversion buffer memory unit 303, a reception multiframe synchronization detection unit 304, a speed conversion buffer memory unit 305, a transmission line clock unit 306, and a driver 307. ing.

The receiver 301 receives data 801 that is time-division multiplexed from a line such as a digital dedicated line of a carrier.
The transmission path clock extraction unit 302 extracts a clock 802 synchronized with the data 801 received by the receiver 301.

  The speed conversion buffer memory unit 303 stores the data 801 received by the receiver 301 using the clock 802 extracted by the transmission path clock extraction unit 302. Further, the speed conversion buffer unit 303 receives the signal 501 from the clock unit 2 via the timing bus 5, and reads the stored data 801 according to the clock and frame pulse in the signal 501. Then, in accordance with the timing signal in the signal 501, the read data 801 is output to the reception bus 6 as the reception data string 601 in accordance with the timing of the bus output by itself.

  The reception multiframe synchronization detection unit 304 detects the multiframe information 602 of the reception data string 601 output from the speed conversion buffer memory unit 303 to the reception bus 6 and outputs it to the reception bus 6.

The speed conversion buffer memory unit 305 receives the signal 501 from the clock unit 2 via the timing bus 5, and in the transmission data string 701 from the control unit 1 via the transmission bus 7 according to the clock and frame pulse in the signal 501. The predetermined data is received and stored. The speed conversion buffer memory unit 305 reads the stored data in accordance with the clock generated by the transmission path clock unit 306.
The transmission line clock unit 306 receives the signal 501 from the clock unit 2 via the timing bus 5 and generates a clock according to the transmission speed of the line using the clock in the signal 501.
The driver 307 outputs the data read by the speed conversion buffer memory unit 305 as transmission data 803 to a line such as a carrier digital dedicated line.

  The terminal interface unit 4 transmits / receives data 901 and 903 to / from various terminals of the user, and outputs the received data 901 as a received data string 601 in accordance with a signal 501 from the clock unit 2. The terminal interface units 4a and 4b have the same configuration. The terminal interface unit 4 includes a data reception receiver 401, a clock reception receiver 402, a speed conversion buffer memory unit 403, a speed conversion buffer memory unit 404, a terminal clock unit 405, a data transmission driver 406, and a clock transmission driver 407. It is configured.

The data reception receiver 401 receives reception data 901 from a connected terminal.
The clock reception receiver 402 receives the reception clock 902 from the connected terminal.

  The speed conversion buffer memory unit 403 writes and stores the reception data 901 received by the data reception receiver 401 using the reception clock 902 received by the clock reception receiver 402. Further, the speed conversion memory buffer unit 403 receives the signal 501 from the clock unit 2 via the timing bus 5, and reads the stored reception data 901 according to the clock and frame pulse in the signal 501. Then, according to the timing signal in the signal 501, the read reception data 901 is output to the reception bus 6 as a reception data string 601 in accordance with the timing at which the bus outputs itself.

The speed conversion buffer memory unit 404 receives the signal 501 from the clock unit 2 via the timing bus 5, and in the transmission data string 701 from the control unit 1 via the transmission bus 7 according to the clock and frame pulse in the signal 501. The predetermined data is received and stored. Further, the speed conversion buffer memory unit 404 reads the stored data in accordance with the low-speed clock generated by the terminal clock unit 405.
The terminal clock unit 405 receives the signal 501 from the clock unit 2 via the timing bus 5 and generates a low-speed clock that matches the transmission speed with the terminal using the clock in the signal 501.

The data transmission driver 406 outputs the data read by the speed conversion buffer memory unit 404 to the terminal as transmission data 903.
The clock transmission driver 407 is generated by the terminal clock unit 405 and used for data reading, and outputs a low-speed clock synchronized with the data as a transmission clock 904 to the terminal.

Next, the operation of the multiplexing apparatus configured as described above will be described with reference to FIG. 2 showing an operation outline timing image in the control unit 1.
First, a case where data is received from a digital dedicated line of a carrier connected to a multiplexing device at another point will be described by taking as an example a case where data is transferred from the circuit interface unit 3a to the control unit 1.

  First, in the line interface unit 3a, the receiver 301 receives the time-division multiplexed data 801 from the carrier's digital dedicated line, and the transmission line clock extraction unit 302 extracts the clock 802 synchronized with the data 801. Data 801 is stored in the speed conversion buffer memory unit 303 using the clock 802.

  Next, the speed conversion buffer memory unit 303 reads the stored data 801 in accordance with the clock and frame pulse in the signal 501 received from the clock unit 2. Then, in accordance with the timing signal in the signal 501, the read data 801 is output to the reception bus 6 as the reception data string 601 in accordance with the timing of the bus output by itself. As shown in FIG. 2, the received data string 601 has a configuration in which the data of each terminal is multiplexed in bit units (“a-1”, “a-2”, “b-1”, etc. in FIG. 2). It has become. In addition, the reception multiframe synchronization detection unit 304 detects the multiframe information 602 of the reception data string 601 output to the reception bus 6 and outputs it to the reception bus 6 in the same manner.

Next, the control unit 1 receives the received data string 601 from the line interface unit 3 a and stores it in the temporary reception buffer unit 101. Further, the identification information storage unit 102 receives the multi-frame information 602 and the signal 501, and from the multi-frame number of the reception data string 601 in the multi-frame information 602 and the bit position from the head of the frame pulse in the signal 501, The data of the received data string 601 is specified in units of bits, and the identification information stored in advance is used to identify and distribute to which terminal the data in the bit unit of the received data string 601 is communicated. Notify the control unit 104. The distribution control unit 104 distributes and writes the received data string 601 to each terminal data buffer unit 105 on a bit-by-bit basis according to the high-speed clock generated by the distribution / allocation processing high-speed clock generation unit 103.
Through the above processing, each terminal data buffer unit 105 stores data for each terminal data in time series.

  Next, transfer processing in bit units is performed based on allocation information indicating a transfer destination of each terminal data stored in advance in the allocation information storage unit 106. That is, the terminal data buffer read control unit 107 sends the data stored in the terminal data buffer unit 105 to the line / terminal allocation control unit 108 according to the allocation information at a timing synchronized with the clock and frame pulse in the signal 501. In addition to instructing transfer, the allocation information is transferred to the line / terminal allocation control unit 108.

Next, the line / terminal allocation control unit 108 outputs the data transferred from the terminal data buffer unit 105 based on the allocation information transferred from the terminal data buffer read control unit 107 to the output data memory unit 109 for the terminal interface unit or the line Assigned to the output data memory unit 110 for the interface unit.
Low delay is achieved by processing from the above data distribution processing to storing in the output data memory unit 109 for the terminal interface unit or the output data memory unit 110 for the line interface unit with a high-speed clock and completing demultiplexing within one frame. Realize the process.

Next, a case where data is transmitted to a terminal connected to the multiplexing apparatus will be described by taking as an example a case where data is transferred from the control unit 1 to the terminal interface unit 4a.
First, in the control unit 1, the output data memory unit 109a for the terminal interface unit outputs the stored data to the transmission bus 7 as a transmission data string 701 at a timing synchronized with the clock and frame pulse in the signal 501.

  Next, the terminal interface unit 4 a receives predetermined data from the transmission data string 701 according to the clock and frame pulse in the signal 501 and stores them in the speed conversion buffer memory unit 404. The terminal clock unit 405 generates a low-speed clock that matches the transmission speed with the terminal using the clock in the signal 501, reads data from the speed conversion buffer memory unit 404 using the clock, and transmits the data transmission driver 406. And output as transmission data 903. At this time, a low-speed clock used for data reading and synchronized with the data is also output to the terminal as a transmission clock 904 via the clock transmission driver 407.

Next, a case in which data received from a terminal is transmitted to a multiplexing device at another point via a digital dedicated line will be described as an example in which data is transferred from the terminal interface unit 4a to the control unit 1.
First, the terminal interface unit 4a receives the reception data 901 and the reception clock 902 from the connected terminal, and the speed conversion buffer memory unit 403 writes and stores the reception data 901 by the reception clock 902.

  Next, the speed conversion memory buffer unit 403 reads the stored reception data 901 according to the clock and frame pulse in the signal 501 received from the clock unit 2. Then, according to the timing signal in the signal 501, the read reception data 901 is output to the reception bus 6 as a reception data string 601 in accordance with the timing at which the bus outputs itself.

  Next, the control unit 1 receives the received data string 601 from the terminal interface unit 4 a and stores it in the temporary reception buffer unit 101. In the identification information storage unit 102, the data of the reception data string 601 is specified in bit units from the bit position from the head of the frame pulse in the signal 501, and the bit unit of the reception data string 601 is determined from the identification information stored in advance. And which terminal data is communicated between the terminals is notified to the distribution control unit 104.

  Next, the distribution control unit 104 distributes and writes the received data string 601 to each terminal data buffer unit 105 on a bit-by-bit basis using the high-speed clock generated by the distribution / allocation processing high-speed clock generation unit 103.

  Next, transfer processing in bit units is performed based on the allocation information indicating the transfer destination of each terminal data stored in the allocation information storage unit 106. That is, the terminal data buffer read control unit 107 transfers data to the line / terminal allocation control unit 108 to the terminal data buffer unit 105 according to the allocation information at a timing synchronized with the clock / frame pulse in the signal 501. At the same time, the allocation information is transferred to the line / terminal allocation control unit 108.

Next, the line / terminal allocation control unit 108 allocates data to the terminal interface unit output data memory unit 109 or the line interface unit output data memory unit 110 based on the allocation information.
The processing from the above data distribution processing to the storage of the output data memory unit 109 for the terminal interface unit or the output data memory unit 110 for the line interface unit is processed with a high-speed clock, and demultiplexing is completed within one frame with low delay. Realize the process.

Next, a case in which data is transmitted from the multiplexing device to the multiplexing device at another point via the digital dedicated line will be described by taking an example in which data is transferred from the control unit 1 to the line interface unit 3a.
First, in the control unit 1, the output data memory unit 110a for the line interface unit outputs the stored data to the transmission bus 7 as a transmission data string 701 at a timing synchronized with the clock and frame pulse in the signal 501.

  Next, the line interface unit 3 a receives predetermined data from the transmission data string 701 according to the clock and frame pulse in the signal 501 and stores them in the speed conversion buffer memory unit 305. The transmission line clock unit 306 receives a clock from the clock unit 2 via the timing bus 5, generates a clock that matches the transmission speed of the dedicated line using the clock, and uses this clock to generate a speed conversion buffer memory. Data is read from the unit 305 and output as transmission data 803 via the data transmission driver 307.

  As described above, according to the first embodiment, the control unit 1 is provided with means for demultiplexing each terminal data in bit units, and the control unit 1 is configured to concentrate and perform low-delay demultiplexing processing. Therefore, it is not necessary to individually manage the number of processing frame units for each terminal data, and communication for management control between the control unit 1, the line interface unit 3, and the terminal interface unit 4 can be simplified.

Embodiment 2. FIG.
In the first embodiment, an example in which the reception multiframe synchronization detection unit 304 is provided in the line interface unit 3 has been described.
FIG. 3 is a diagram showing the configuration of the multiplexing apparatus according to Embodiment 2 of the present invention. The multiplexer according to Embodiment 2 shown in FIG. 3 deletes the multiframe synchronization detection unit 304 from the line interface unit 3 of the multiplexer according to Embodiment 1 shown in FIG. The reception multi-frame synchronization detectors 111a and 111b are added. Other configurations are the same, and only different parts will be described. In the following description, the reception multiframe synchronization detection units 111a and 111b are referred to as reception multiframe synchronization detection unit 111 unless it is necessary to distinguish between them.

The reception multiframe synchronization detection unit 111 detects multiframe information 602 of the reception data string 601 received from the line interface unit 3 via the reception bus 6. The reception multiframe synchronization detection unit 111 needs to be mounted on the control unit 1 for each line interface unit 3. In the example of FIG. 3, the reception multiframe synchronization detection unit 110a corresponds to the line interface unit 3a, and the reception multiframe synchronization detection unit 110b corresponds to the line interface unit 3b.
The identification information storage unit 102 uses the multiframe information detected by the multiframe synchronization detection unit 111 to specify the data of the reception data string 601 in bit units.

  As described above, according to the second embodiment, the reception multiframe synchronization detection unit 111 is provided in the control unit 1 instead of the reception multiframe synchronization detection unit 304 of the line interface unit 3. The effect equivalent to that of the first embodiment can be obtained, and transmission / reception of multi-frame information between the control unit 1 and each line interface unit 3 becomes unnecessary, so that the number of reception buses 6 can be reduced and the configuration can be reduced. Can be simplified.

Embodiment 3 FIG.
Although the terminal data buffer unit 105 is prepared for each terminal data in the first embodiment, a single terminal data memory unit 113 may be used instead.
FIG. 4 is a diagram showing the configuration of the multiplexing apparatus according to Embodiment 3 of the present invention. The multiplexing apparatus according to Embodiment 3 shown in FIG. 4 includes a distribution control unit 104, a plurality of terminal data buffer units 105, and a terminal data buffer read control unit 107 of the multiplexing apparatus according to Embodiment 1 shown in FIG. The terminal data memory write address control unit 112, the terminal data memory unit 113, and the terminal data memory read address control unit 114 are added. Other configurations are the same, and only different parts will be described.

  The terminal data memory write address control unit 112 holds an address for each terminal data, and on the basis of the identification result by the identification information storage unit 102, according to the high-speed clock generated by the allocation / allocation processing high-speed clock generation unit 103, A corresponding address is assigned to the bit unit data of the reception data string 601 stored in the reception buffer unit 101.

  The terminal data memory unit 113 is a single memory that stores the received data string 601 to which an address is assigned for each bit data by the terminal data memory write address control unit 112.

  The terminal data memory read address control unit 114 holds an address for each terminal data, receives the signal 501 from the clock unit 2 via the timing bus 5, and is synchronized with the clock and frame pulse in the signal 501. In accordance with the allocation information stored in the allocation information storage unit 106, the terminal data memory unit 113 is instructed to transfer the data to which the address corresponding to the allocation information is allocated to the line / terminal allocation control unit 108, and the line / Allocation information is transferred to the terminal allocation control unit 108.

  The line / terminal allocation control unit 108 uses the terminal data memory according to the high-speed clock generated by the allocation / allocation processing high-speed clock generation unit 103 based on the allocation information transferred from the terminal data memory read address control unit 114. The data transferred from the unit 113 is allocated to the output data memory unit 109 for the terminal interface unit or the output data memory unit 110 for the line interface unit.

  As described above, according to the third embodiment, the terminal data memory write address control unit 112 that assigns an address to each terminal data and performs address control when data is written, and the terminal data memory read address that performs address control when data is read. Since the control unit 114 is used to write / read data to / from the terminal data memory unit 113, the same effect as in the first embodiment can be obtained, and the number of components can be reduced by using a single memory. Reduction can be achieved.

  In the present invention, within the scope of the invention, any combination of the embodiments, or any modification of any component in each embodiment, or omission of any component in each embodiment is possible. .

  1 control unit, 2 clock unit, 3, 3a, 3b line interface unit, 4, 4a, 4b terminal interface unit, 5 timing bus, 6 reception bus, 7 transmission bus, 101 temporary reception buffer unit, 102 identification information storage unit ( Terminal data identification unit), 103 high-speed clock generation unit for distribution / allocation processing, 104 distribution control unit, 105, 105a to 105n terminal data buffer unit, 106 allocation information storage unit, 107 terminal data buffer read control unit, 108 line / terminal Assignment control unit, 109, 109a, 109b Output data memory unit for terminal interface unit (terminal data transmission unit), 110, 110a, 110b Output data memory unit for line interface unit (terminal data transmission unit), 111, 111a, 111b Reception Multi-frame synchronization detector, 12 terminal data memory write address control unit, 113 terminal data memory unit, 114 terminal data memory read address control unit, 201 various timing generation units, 301 receiver, 302 transmission path clock extraction unit, 303 speed conversion buffer memory unit, 304 reception multi Frame synchronization detection unit, 305 speed conversion buffer memory unit, 306 transmission line clock unit, 307 driver, 401 data reception receiver, 402 clock reception receiver, 403 speed conversion buffer memory unit, 404 speed conversion buffer memory unit, 405 terminal clock , 406 data transmission driver, 407 clock transmission driver, 501 signal (synchronization signal), 601 reception data string, 602 multiframe information, 701 transmission data string, 801 data, 80 Clock 803 transmits data, 901 receiving data, 902 receive clock 903 transmits data, 904 transmit clock.

A multiplexing device according to the present invention outputs a data received from a line as a received data string in accordance with a clock unit that generates a synchronizing signal and a synchronizing signal, and how many frames of the multi-frame the received data string corresponds to a line interface unit which detects and outputs the synchronization information indicating, in accordance with the synchronization signal, receives a terminal interface unit for outputting data received from the terminal as reception data sequence, the received data sequence from the line interface unit or the terminal interface unit And a control unit that performs demultiplexing processing of the bit-unit data on the received data sequence according to the synchronization signal, and the control unit transmits terminal data in which data at each bit position of the multiframe is communicated Holding identification information for identifying the received information based on the identification information, synchronization signal and synchronization information. A terminal data identification unit for identifying which terminal data is data in bit units of a data string, a plurality of terminal data buffer units provided for each terminal data and storing input data, and identification by the terminal data identification unit Based on the result, a terminal that reads data from the terminal data buffer unit in accordance with the allocation control unit that distributes the received data string received to the terminal data buffer unit for each bit unit of data and the allocation information indicating the transfer destination of the terminal data A data buffer read control unit and a terminal data output unit that outputs data read by the terminal data buffer read control unit as a transmission data string to a line interface unit or a terminal interface unit in accordance with a synchronization signal.

Also, the multiplexing device according to the present invention includes a clock unit that generates a synchronization signal, a line interface unit that outputs data received from the line as a received data sequence according to the synchronization signal, and data received from the terminal according to the synchronization signal For receiving a received data sequence from the line interface unit or the terminal interface unit, and performing demultiplexing processing on the received data sequence in units of bits according to the synchronization signal A control unit, a multi-frame synchronization detection unit for detecting synchronization information indicating which frame of the multi-frame the received data sequence received from the line interface unit, and data at each bit position of the multi-frame Holds identification information that identifies the terminal data to be communicated between which terminals, and the identification A terminal data identification unit for identifying which terminal data is the data in bit units of the received data sequence based on the synchronization information detected by the information, the synchronization signal and the multiframe synchronization detection unit, and provided for each terminal data A plurality of terminal data buffer units for storing input data, and a distribution control unit for allocating the received data string received to the terminal data buffer unit for each bit data based on the identification result by the terminal data identification unit; A terminal data buffer read control unit for reading data from the terminal data buffer unit in accordance with the allocation information indicating the transfer destination of the terminal data, and the data read by the terminal data buffer read control unit in accordance with the synchronization signal as a transmission data string And a terminal data output unit for outputting to the interface unit or the terminal interface unit.

The multiplexing apparatus according to the present invention outputs a data received from a line as a received data string in accordance with the clock unit for generating a synchronizing signal and the synchronizing signal, and the received data string corresponds to what frame of the multiframe. A line interface unit that detects and outputs synchronization information indicating that, a terminal interface unit that outputs data received from the terminal as a received data sequence according to the synchronization signal, and a received data sequence from the line interface unit or the terminal interface unit. And a control unit that performs demultiplexing processing of bit-unit data on the received data sequence in accordance with a synchronization signal, and the control unit communicates data at each bit position of the multiframe between which terminals It holds identification information that identifies whether it is terminal data, and receives it based on the identification information, synchronization signal, and synchronization information. A terminal data identification unit for identifying which terminal data is bit data of the received data string, and a bit unit of the received data string received based on the identification result by the terminal data identification unit, holding an address for each terminal data Terminal data memory write address control unit for assigning a corresponding address to the data of the terminal, and a single terminal data memory for storing a received data sequence in which an address is assigned for each bit unit of data by the terminal data memory write address control unit A terminal data memory read address control unit that holds an address for each terminal data and reads data assigned a corresponding address from the terminal data memory unit according to allocation information indicating a transfer destination of the terminal data, and a synchronization signal The data read by the terminal data memory read address control unit in accordance with As those having a terminal data output section that outputs to the line interface unit or the terminal interface unit.

Claims (3)

A clock unit that generates a synchronization signal, outputs data received from the line as a reception data string according to the synchronization signal, detects a synchronization information of the reception data string, and outputs the synchronization information according to the synchronization signal A terminal interface unit that outputs data received from the terminal as a received data sequence, and a received data sequence from the line interface unit or the terminal interface unit, and according to the synchronization signal, the received data sequence in bit units And a control unit that performs demultiplexing processing of the data of
The controller is
It holds identification information that identifies which terminal data of each bit position of the multiframe is to be communicated between, and based on the identification information, the synchronization signal, and the synchronization information, A terminal data identification unit for identifying which terminal data is bit-wise data;
A plurality of terminal data buffer units for storing input data provided for each terminal data;
Based on the identification result by the terminal data identification unit, a distribution control unit that distributes the received received data string to the terminal data buffer unit for each bit unit of data,
A terminal data buffer read control unit for reading data from the terminal data buffer unit according to the allocation information indicating the transfer destination of the terminal data;
A multiplexing apparatus comprising: a terminal data output unit that outputs data read by the terminal data buffer read control unit according to the synchronization signal as a transmission data string to the line interface unit or the terminal interface unit. A clock unit that generates a synchronization signal, a line interface unit that outputs data received from the line as a received data string according to the synchronization signal, and a terminal interface that outputs data received from a terminal as a received data string according to the synchronization signal And a control unit that receives a received data sequence from the line interface unit or the terminal interface unit and performs demultiplexing processing of data in bit units on the received data sequence according to the synchronization signal Device.
The controller is
A multi-frame synchronization detection unit that detects synchronization information of a received frame sequence received from the line interface unit;
It holds identification information for identifying which terminal data of each bit position of the multiframe is communicated between, and based on the identification information, the synchronization signal, and the synchronization information detected by the multiframe synchronization detection unit. A terminal data identification unit for identifying which terminal data the bit-unit data of the received received data sequence;
A plurality of terminal data buffer units for storing input data provided for each terminal data;
Based on the identification result by the terminal data identification unit, a distribution control unit that distributes the received received data string to the terminal data buffer unit for each bit unit of data,
A terminal data buffer read control unit for reading data from the terminal data buffer unit according to the allocation information indicating the transfer destination of the terminal data;
A multiplexing apparatus comprising: a terminal data output unit that outputs data read by the terminal data buffer read control unit according to the synchronization signal as a transmission data string to the line interface unit or the terminal interface unit. A clock unit that generates a synchronization signal, outputs data received from the line as a reception data string according to the synchronization signal, detects a synchronization information of the reception data string, and outputs the synchronization information according to the synchronization signal A terminal interface unit that outputs data received from the terminal as a received data sequence, and a received data sequence from the line interface unit or the terminal interface unit, and according to the synchronization signal, the received data sequence in bit units And a control unit that performs demultiplexing processing of the data of
The controller is
It holds identification information that identifies which terminal data of each bit position of the multiframe is to be communicated between, and based on the identification information, the synchronization signal, and the synchronization information, A terminal data identification unit for identifying which terminal data is bit-wise data;
A terminal data memory write address control unit that holds an address for each of the terminal data, and assigns a corresponding address to the data in bit units of the received data string received based on the identification result by the terminal data identification unit;
A single terminal data memory unit for storing a received data string in which an address is assigned to each bit data by the terminal data memory write address control unit;
A terminal data memory read address control unit that holds an address for each terminal data and reads data to which a corresponding address is allocated from the terminal data memory unit according to allocation information indicating a transfer destination of the terminal data;
A multiplexing apparatus comprising: a terminal data output unit that outputs data read by the terminal data memory read address control unit according to the synchronization signal as a transmission data string to the line interface unit or the terminal interface unit.

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