JP2008103921A - Jitter buffer circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit capable of transmitting a data channel and a control channel held in an identical packet with a same timing, without increasing the capacity of a jitter buffer which accumulates a control channel contained in a packet signal generated by line emulation of a time division multiplex signal. <P>SOLUTION: The line emulation device according to the present invention stores association between a memory storage area where a data channel is accumulated and a time slot number of a time division multiplex signal in a memory. When a data channel is read, a relevant control channel is selected based on the association stored at the memory. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a jitter buffer circuit that realizes time-division multiplex transmission on a packet switching network in a pseudo manner by circuit emulation.

  In a communication network, a circuit emulation technique that realizes time division multiplexing (TDM) transmission on a packet switching network in a pseudo manner is known. For example, Patent Document 1 discloses an invention related to circuit emulation technology. Here, a device for converting a time division multiplexed signal into a packet signal and sending it to the packet network, and conversely, converting the packet signal into a time division multiplexed signal and sending it to the time division multiplexed signal network is disclosed. Has been.

  Usually, time division multiplexed signals include line data and signaling bits. Line data is a data signal transmitted by a user of a network line. The signaling bit is a signal representing line control information or line maintenance information. These are multiplexed in a TDM frame having a fixed time interval, and a series of frames are transmitted as a time division multiplexed signal. In the circuit emulation technology, usually, a plurality of these TDM frames are accommodated to generate a packet signal, which is transmitted to the packet switching network. Among the elements constituting the packet signal, a group of data lines is called a data channel, and a group of signaling bits is called a control channel. The data channel is composed of a plurality of data frames.

A circuit emulation device that receives a packet signal generated by circuit emulation of a time division multiplexed signal, reconverts it into a time division multiplexed signal, and transmits it is usually provided with a buffer that temporarily stores the packet signal. This buffer is provided to absorb the fluctuation (jitter) of the transmission time of the packet signal in the packet switching network, and is called a jitter buffer. Usually, two jitter buffers, a data channel jitter buffer for accumulating line data and a control channel jitter buffer for accumulating signaling bits, are provided. The accumulated line data and signaling bits are read from each jitter buffer, converted to a time division multiplexed signal, and then transmitted to the TDM transmission network.
JP 2005-244470 A

  There are signaling bits to be transmitted at the same timing as the line data. For example, a signaling bit representing error monitoring information such as a parity calculation result for the data line can be mentioned. However, since line data and signaling bits are usually stored in different jitter buffers, it is difficult to read them at a common timing and transmit them at the same timing.

  Here, for example, it is assumed that the data channel jitter buffer includes a plurality of storage areas for accumulating data frames, and the control channel jitter buffer includes the same number of storage areas for accumulating control channels. By assigning the same number to each storage area, accumulating the control channel at the same number as the number for accumulating the data frame, and simultaneously reading out the data frame and the control channel in numerical order from each jitter buffer, The timing for reading the control channel is made common. When this method is used, if the number of data frames accommodated in the packet signal is m and the number of control channels is one, the storage area of the control channel jitter buffer has m times the actual information amount of the control channel. As a result, the capacity of the jitter buffer for the control channel increases.

  The present invention has been made in view of the above-described problems, and without increasing the capacity of the control channel jitter buffer, the data frame and the control channel are read at a common timing, and the line data and the signaling bit are read out. An object is to provide an apparatus capable of transmitting at the same timing.

  A jitter buffer circuit according to the present invention is a jitter buffer circuit that receives a packet signal generated by circuit emulation of a time division multiplexed signal, converts the packet signal into a time division multiplexed signal, and transmits the packet signal. The jitter buffer circuit is accommodated in the packet signal. Data channel jitter buffer including a storage area capable of storing a data frame for each packet ID, and a control channel jitter including a storage area capable of storing a control channel contained in the packet signal together with the data frame for each packet ID A writing surface memory for storing a correspondence relationship between a buffer, a time slot in which a data frame accommodated in the packet having the packet ID is output, and a storage area in which the data frame is stored; the data frame; The control channel and the correspondence relationship are respectively shown in the data. Control channel selector for determining whether the control channel of the time slot being read is valid based on the correspondence when reading from the channel jitter buffer, the control channel jitter buffer, and the writing surface memory It is characterized by including.

  Examples according to the present invention will be described below.

  FIG. 1 is a block diagram showing a jitter buffer circuit 120 according to the present invention together with a circuit emulation device 100. The circuit emulation device 100 includes a packet receiver 110, a jitter buffer circuit 120, and a TDM frame transmitter 130.

  The packet receiving unit 110 receives a packet signal generated by circuit emulation of time division multiplexed signals from a packet switching network (not shown) such as the Internet. Further, the packet receiving unit 110 extracts a data channel, a control channel, and a packet header from the received packet signal, and provides them to the jitter buffer circuit 120.

  The TDM frame transmission unit 130 generates a TDM frame from the data channel and the control channel received from the jitter buffer circuit 120, and transmits this to a TDM transmission network (not shown). The configuration of the TDM frame is, for example, a configuration conforming to SDH (Synchronous Digital Hierarchy) or SONET (Synchronous Optical Network).

  The jitter buffer circuit 120 includes a write control unit 121, a data channel jitter buffer 122, a write surface memory 123, a control channel jitter buffer 124, a data channel read control unit 125, a control channel selection unit 126, and a control. A channel read controller 127.

  The write controller 121 receives packet header information included in the packet signal from the packet receiver 110. The write control unit 121 identifies the packet ID from the received packet header information and confirms the number of the storage area from which the data channel buffer 122 is reading the data channel in order to give the data channel to the TDM frame transmission unit 130 To do. Based on the packet ID and the number of the storage area from which the data channel is read, the write control unit 121 sets the data channel buffer 122 and the control channel buffer 124 as storage areas for storing the data channel and the control channel. Instruct. In addition, the write control unit 121 stores the number of the storage area in which the first data frame accommodated in the packet signal is stored in the writing surface memory 123 for each packet ID.

  The data channel jitter buffer 122 receives the data channel from the packet receiving unit 110 and accumulates the data channel in the storage area designated by the write control unit 121. Further, the data channel buffer 122 reads the data channel stored in the storage area designated by the data channel read control unit 125 and supplies it to the TDM frame transmission unit 130.

  The control channel jitter buffer 124 receives the control channel from the packet receiver 110 and accumulates the control channel in the storage area designated by the write controller 121. Further, the control channel buffer 124 reads the control channel stored in the storage area designated by the control channel read control unit 125, and supplies this to the TDM frame transmission unit 130.

  The writing surface memory 123 stores the correspondence between the number of the storage area in which the first data frame accommodated in the packet signal is accumulated and the packet ID.

  The data channel read control unit 125 instructs the data channel jitter buffer 122 to specify the number of the storage area from which the data channel is to be read.

  The control channel read control unit 127 instructs the control channel jitter buffer 124 to specify the storage area number from which the control channel is to be read. Further, the control channel read control unit 127 instructs the control channel selection unit 126 to refer to the correspondence relationship stored in the writing surface memory 123.

  The control channel selection unit 126 refers to the correspondence stored in the writing surface memory 123 and selects a control channel to be read based on the correspondence.

  FIG. 2 is a diagram illustrating a time division multiplexed signal. The time division multiplexed signal includes a data channel and a control channel. A data channel consists of a series of data frames. In the figure, f1 is one data frame. Similarly, f2 to f8 represent data frames. One data frame includes a plurality of line data (line data not shown). In the present embodiment, the number of line data included in one data frame is N. That is, N lines are multiplexed. CH1 to CNN in the figure represent N lines. The control channel consists of a plurality of signaling bits. The signaling bits are assigned to the line data on a one-to-one basis, and the number of signaling bits corresponding to one data frame is N. S1 in FIG. 2 is a collection of N signaling bits (S2 to S8 are the same). The data amount of each line data included in one data frame is 8 bits, and the data amount of signaling bits corresponding to each line data is 1 bit. The time width of each data frame is 125 μs. The time division multiplexed signal is converted into a packet signal by using eight data frames as a unit by circuit emulation. A packet ID that can identify the packet signal is given to the packet signal. For example, IA, IB, IC, ID, IE, IF, IG, and IH are assigned to the packet IDs in the order of packet signalization. A packet signal whose packet ID is IA is called PA. Similarly, each of packet signals having packet IDs IB to IH is represented by PB to PH. In the present embodiment, the circuit emulation device 100 repeatedly receives packet signals having packet IDs IA to IH.

  FIG. 3 shows a packet signal PA generated by circuit emulation. The packet signal includes a packet header, a data channel, and a control channel. The packet header includes address information that can identify the packet ID. The data channel is a group of line data and includes eight data frames f1 to f8. The arrangement order of the data frames accommodated in the packet signal is the same as the arrangement order in the time division multiplexed signal, and the first data frame is f1, and the order is f1, f2, f3, f4, f5, f6, f7, f8. It is. The types and order of the line data multiplexed in each data frame are the same as those in each data frame before being packetized. Each data frame includes line data for N lines. The data amount of each line data included in one frame is 8 bits. A control channel is a group of signaling bits. The control channel includes signaling bits for N lines, and the number of signaling bits per line is 8 bits.

  FIG. 4 is a diagram illustrating a storage area included in the data channel jitter buffer 122. The storage area is composed of eight data channel storage surfaces T0 to T7 arranged in the Y-axis direction in FIG. Hereinafter, the data channel storage surface numbers are represented by eight patterns T0 to T7. The data channel storage surface is a storage area composed of eight multi-frame surfaces 0 to 7 arranged in the X-axis direction in FIG. In FIG. 4, the multi-frame surface is represented by the symbol M. Hereinafter, the number of the multi-frame surface is represented by 8 types of 0-7. Further, the storage area numbers provided in the data channel buffer 122 are changed to T0-0, T0-1,... By combining the data channel storage surface numbers T0 to T7 and the multiframe surface numbers 0 to 7. , T7-7 and the like. Further, the multi-frame surface is composed of eight frame storage areas capable of storing one data frame for each packet ID. Frame storage area numbers 0 to 7 correspond to time slot numbers 0 to 7 of the time division multiplexed signal. In this embodiment, the data frame accommodated in the packet signal with the packet ID “IA” is stored in the storage area of the number 0. Similarly, the number 1 stores the packet ID “IB”, the number 2 stores the packet ID “IC”,..., The number 7 stores the data frame accommodated in the packet signal of the packet ID “IH”. Is done. In FIG. 4, the frame storage area is represented by the symbol F. Accumulation of data channels in the multi-frame plane is performed in units of data frames. When receiving a plurality of packet signals having the same packet ID, the data channel buffer 122 accumulates data channels in the order of T0, T1,... T7 on the data channel accumulation surface every time a data channel is received. When the data channel is stored up to T7 on the data channel storage surface, it is stored again in order from T0.

  FIG. 5 is a diagram showing a storage area provided in the control channel jitter buffer 124. The storage area is composed of eight control channel storage surfaces T0 to T7 arranged in the Y-axis direction in FIG. Hereinafter, the numbers of the control channel storage surfaces are represented by T0 to T7. In FIG. 5, the control channel accumulation surface is represented by the symbol T. The control channel storage surface is composed of eight control channel storage areas capable of storing one control channel for each packet ID. Numbers 0 to 7 in the control channel storage area correspond to time slots 0 to 7 of the time division multiplexed signal. In the present embodiment, the control channel accommodated in the packet signal of the packet ID “IA” is stored in the storage area of the number 0. Similarly, the number 1 stores the packet ID “IB”, the number 2 stores the packet ID “IC”, and the number 7 stores the control channel accommodated in the packet signal of the packet ID “IH”. Is done. In FIG. 5, the control channel storage area is represented by the symbol S. When a plurality of packet signals having the same packet ID are received, the control channel buffer 124 accumulates control channels in the order of T0, T1,... T7 on the control channel accumulation surface every time a control channel is received. When the control channel is stored up to T7 on the control channel storage surface, it is stored again in order from T0.

  FIG. 6 is a diagram showing a storage area of the writing surface memory 123. The storage area is composed of eight number storage areas capable of storing one multiframe surface number for each packet ID. Numbers 0 to 7 in the number storage area correspond to time slots 0 to 7 of the time division multiplexed signal. In the present embodiment, the number 0 storage area stores the number of the multi-frame plane in which the first data frame accommodated in the packet signal with the packet ID “IA” is stored. Similarly, number 1 is packet ID “IB”, number 2 is packet ID “IC”,..., Number 7 is the first data frame contained in the packet signal of packet ID “IH”. The number of the multi-frame surface in which is stored is stored. In FIG. 6, the number storage area is represented by the symbol N.

  Hereinafter, accumulation of the data channel and the control channel when the line emulation apparatus 100 receives a packet signal will be described. There are eight types of packet IDs of packet signals received by the circuit emulation device 100, IA to IH. A packet signal whose packet ID is IA is PA. Similarly, each of the packet signals whose packet IDs are IB to IH are PB to PH. It is assumed that the circuit emulation device 100 receives packet signals in the order of PA, PB, PC, PD, PE, PF, PG, and PH at intervals of 125 μs. For one packet ID, the packet reception period is about 1 ms.

    FIG. 7 is a diagram showing the relationship between the storage area of the data channel jitter buffer 122 and the accumulation of packet signals. The storage area is represented by data channel storage surface numbers T0 to T3 and multiframe surface numbers 0 to 7. The symbol R in FIG. 7 indicates that when the write control unit 121 receives the packet header from the packet receiving unit 110, the data channel buffer 122 reads the data channel to give the data channel to the TDM frame transmitting unit 130. Represents a storage area. A symbol W in FIG. 7 represents a storage area in which the first data frame accommodated in the packet signal is accumulated. These symbols R and W are shown for each packet signal represented by symbols PA to PH in FIG.

  When the write control unit 121 receives the packet header from the packet reception unit 110, the write control unit 121 determines the packet ID from the address information included in the packet header. Here, it is assumed that the packet ID is IA. Subsequently, the write control unit 121 confirms the number of the storage area from which the data channel buffer 122 is reading the data channel in order to give the data channel to the TDM frame transmission unit 130. Here, it is assumed that the number of the storage area from which the data channel is read is T1-0 (corresponding to the symbol R of the packet signal IA in FIG. 7). The write control unit 121 instructs the data channel buffer 122 as T3-0 as the number of the storage area in which the first data frame accommodated in the packet signal is to be accumulated (indicated by the symbol W of the packet signal IA in FIG. 7). Applicable).

  The number intervals T1-1 to T3-0, that is, the number intervals corresponding to two data channel storage surfaces are stored in the write control unit 121 in advance. In this embodiment, in order to time-division multiplex transmit data frames, the data channel buffer 122 reads the data frames stored in each multiframe plane in the order of the numbers of the multiframe planes at intervals of 125 μs. The interval between the numbers of two channel storage surfaces corresponds to 2 ms (= 125 μs × 8 × 2).

  Similarly for the packet signals IB to IH, the number interval between the symbol R storage area and the symbol W storage area in FIG. 7 is equivalent to two data channel storage surfaces (interval corresponding to 2 ms). Since the reception interval between the packet signal IA and the packet signal IB is about 125 μs, the symbol R of the packet signal IB in FIG. 7 is T1-1 and the symbol W is T3-1. Since the reception intervals of the packet signals IC to IH are also about 125 μs, the symbol R of the packet signals IC to IH in FIG. 7 is T1-2 to T1-7, and the symbol W is T3 to T3-7, respectively. . As described above, the data frame is accumulated by shifting the number of the storage area by an interval corresponding to 2 ms from the number of the storage area from which the data frame is read when the packet signal is received. Thus, if the data channel buffer 122 reads the data frames in the order of the storage area numbers, the data channel buffer 122 can read them after a desired delay time (for example, about 2 ms) from the time when the data frames are accumulated.

  FIG. 8 shows data frames f1 to f1 stored in the multiframe planes of the data channel storage planes T3 to T5 of the data channel jitter buffer 122 when the circuit emulation apparatus 100 receives the packet signals PA to PH twice. It is a figure showing f8. In the figure, the packet ID and the frame storage area, that is, the time slot number are shown in the column direction, and the storage area number of the data channel jitter buffer is shown in the row direction.

  First, as shown in FIG. 8, the data channel buffer 122 converts the eight data frames f1 to f8 contained in the packet signal PA into storage area numbers T3-0 corresponding to the packet ID “IA”. Accumulate at T3-7. The number T3-0 of the storage area in which the first data frame f1 is stored is designated by the write control unit 121. Next, as shown in FIG. 8, the data channel buffer 122 stores the eight data frames f1 to f8 accommodated in the packet signal PB as storage area numbers T3-1 to TIB1 corresponding to the packet ID “IB”. Accumulate at T4-0. Subsequently, similarly for the packet signals PC to PH, data frames are sequentially accumulated from the storage area designated by the write control unit 121. Subsequently, when the packet signal PA whose packet ID is IA is received again, the data channel buffer 122, as shown in FIG. 8, has eight data f1 to f8 accommodated in the packet signal PA. The frame is accumulated in the numbers T4-0 to T4-7 of the next storage area corresponding to the packet ID “IA”. Next, when the packet signal PB is received, the eight data frames f1 to f8 accommodated in the packet signal PB are accumulated in the numbers T4-1 to T5-0 of the next storage area corresponding to the packet ID “IB”. Data frames accommodated in the packet signals PC to PH are also accumulated sequentially from the storage area designated by the write control unit 121 by the same processing.

  FIG. 9 is a diagram illustrating the control channels SA to SH accumulated in the control channel accumulation surfaces T3 to T5 of the control channel jitter buffer 124 when the circuit emulation apparatus 100 receives the packet signals PA to PH twice. is there. In the figure, the packet ID and the number of the control channel storage area, that is, the number of the time slot are shown in the column direction, and the number of the control channel storage surface is shown in the row direction. The control channel accommodated in the packet signal PA is called SA. Similarly, control channels accommodated in the packet signals PB to PH are called SB to SH.

  The write control unit 121 instructs the control channel buffer 124 of the number of the control channel storage surface where the control channel stored in the packet signal should be stored. The number of the designated control channel storage surface is the same as the number of the data channel storage surface where the first data frame accommodated in the packet signal is stored. For example, if the number of the data channel storage surface in which the first data frame of the packet signal PA is stored is T3, the write control unit 121 uses T3 as the control channel storage surface number for storing the control channel for the control channel. The buffer 124 is instructed. Similarly, for the packet signals PB to PH, if the number of the data channel storage surface in which the first data frame is stored is T3, the write control unit 121 uses T3 as the control channel storage surface number for storing the control channel. To the control channel buffer 124. In this embodiment, since the packet signals PA to PH are subsequently received, the control channel is similarly stored for each packet ID in the control channel storage surface number T4.

  FIG. 10 is a diagram showing the numbers of the multi-frame planes stored in the number storage area of the writing plane memory 123. In the figure, the packet ID and number storage area number, that is, the time slot number, are shown in the column direction, and the multi-frame surface number is shown in the row direction.

  The write controller 121 stores the number of the multi-frame surface for each packet ID in the number storage area of the write surface memory 123. The number of the multi-frame plane stored in the number storage area is the number of the multi-frame plane of the storage area where the first data frame accommodated in the packet signal is accumulated (the storage area number is Tx-y). Y when expressed). Since the number of the multi-frame plane in which the first data frame f1 of the packet signal PA is accommodated is 0, 0 is stored in the number storage area corresponding to the packet ID “IA”. Similarly, since the numbers of the multi-frame planes in which the first data frame f1 of each of the packet signals PB to PH is accommodated are 1 to 7, respectively, these numbers are the packet IDs “IB” to “IH”. Is stored in the number storage area corresponding to. Thus, the writing surface memory 123 records the correspondence between the packet ID and the number of the multi-frame surface that accommodates the data frame f1.

  Hereinafter, processing when the data channel jitter buffer 122 and the control channel jitter buffer 124 read the data channel and the control channel will be described. The storage area to be read is number T4 of the data channel storage surface and the control channel storage surface. Further, reading of the data channel from the multi-frame surface is performed in units of data frames.

  FIG. 11A and FIG. 11B are diagrams showing data frames and control channels read from the data channel jitter buffer 122 and the control channel jitter buffer 124. A symbol (A) in FIGS. 11A and 11B represents a time slot number. The time slot numbers 0 to 7 are the frame storage area numbers 0 to 7 of the data channel jitter buffer 122, the control channel storage area numbers 0 to 7 of the control channel jitter buffer 124, and the number storage of the writing surface memory 123. This corresponds to the area numbers 0 to 7, respectively. The number of the multi-frame plane stored in the data channel, the control channel, and the writing plane memory 123 is read in the order of the time slot number. The symbol (B) in the figure represents the numbers of the data channel storage surface and the control channel storage surface from which the data frame and control channel are read. The symbol (C) in the figure represents the number of the multi-frame plane from which the data frame is read. A symbol (D) in the figure represents the number of the multi-frame surface stored in the writing surface memory 123. A symbol (E) in the figure represents a control channel stored in the control channel buffer 124. A symbol (F) in the figure represents a control channel that the control channel selection unit 126 determines to be valid. A symbol (G) in the figure represents a data frame read from the data channel jitter buffer 122. The symbol (H) in the figure represents the packet ID of the packet signal in which the read data frame and control channel are accommodated. In FIG. 11A, the number of the multi-frame plane from which the data frame is read is 0-3. In FIG. 11B, the number of the multi-frame plane from which the data frame is read is 4-7.

  The data channel read control unit 125 sequentially stores the storage areas T0-0, T0-1,..., T7-6, T7-7, T0-0, T0-1,. The data channel jitter buffer 122 is instructed to read the data frame. Here, only the portions of the storage areas T4-0 to T4-7 will be described.

  The data channel jitter buffer 122 first reads out the data frame stored in the storage area T4-0 of the data channel jitter buffer 122. At this time, the data channel jitter buffer 122 reads the data frames in the order of the frame storage area numbers, that is, in the order of the time slot numbers. The data frame at this time is read out in the order of f1, f8, f7, f6, f5, f4, f3, f2, and the TDM frame is transmitted in the read order as shown by the symbol (G) in FIG. Assigned to the time slot of the time division multiplexed signal transmitted from the unit 130. This is the same as the data frame represented by the number T4-0 of the storage area of the data channel jitter buffer shown in FIG.

  The control channel read control unit 127 instructs the control channel jitter buffer 124 to read the control channel stored in the storage area T4 of the control channel jitter buffer 124. At this time, the control channel jitter buffer 124 reads the control channels in the order of the numbers in the control channel storage area, that is, in the order of the timeslot numbers. The number of the time slot from which the control channel is read is the same as the number of the time slot from which the data channel is read. At the same time, the control channel read control unit 127 reads the multi-frame surface numbers stored in the writing surface memory 123 in the order of numbers in the number storage area, that is, in the order of time slot numbers. The time slot number from which the multiframe plane number is read is the same as the time slot number from which the control channel is read. In the control channel selection unit 126, the number of the multi-frame surface ((D) in FIG. 11) read out from the writing surface memory 123 is the number of the multi-frame surface currently reading out the data frame (in FIG. 11). (C)) is determined whether or not. If the control channel selection unit 126 determines that these match, the control channel (E) in FIG. 11 is validated. Here, since the data frame stored in the multi-frame plane number 0 is read, when the multi-frame plane number read from the writing plane memory 123 is 0, the control is being read simultaneously. Enable channel SA. The control channel SA is a control channel accommodated in the same packet signal as the data frame f1 read from the data channel jitter buffer 122. As a result, the data channel f1 accommodated at the head of the packet signal and the control channel accommodated in the same packet signal are respectively read from the data channel jitter buffer 122 and the control channel buffer 124 at the same timing.

  Similarly, when a data frame is read from the multiframe surface of number 1, when the number of the multiframe surface read from the writing surface memory 123 is 1, the control channel SB being read simultaneously is made valid. Also in this case, the effective control channel SB is the control channel accommodated in the same packet signal as the data frame f1 read from the data channel jitter buffer 122.

  With respect to the multiframe numbers 2 to 7, the data frame and the control channel are read out by the same processing. The data frame and the control channel read from the data channel jitter buffer 122 and the control channel jitter buffer 124 are supplied to the TDM frame transmission unit 130. The TDM frame transmission unit 130 transmits these data frames and control channels to a TDM transmission network (not shown) in the form of time division multiplexed signals.

  As described above, in this embodiment, when the accumulated data frame is taken out from the jitter buffer to be transmitted as a time division multiplexed signal, the data frame is read and simultaneously stored in the same packet as the data frame. It is possible in the present invention to read out the control channel. Thereby, it is possible in the present invention to transmit desired line data and signaling bits at the same timing.

  Furthermore, according to the present invention, the storage area of the control channel jitter buffer 124 is not provided with a multi-frame plane unlike the storage area of the data channel jitter buffer 122, and the data frame and the control channel are read at a common timing. It is possible. For example, if the number of data frames accommodated in one packet signal is m, the storage area of the control channel jitter buffer 124 is 1 / m of the storage area of the data channel jitter buffer 122. Further, for example, by preparing the same number of storage areas of the control channel jitter buffer 124 as the storage area of the data channel jitter buffer 122, the control channel jitter can be compared with the method of reading the data frame and the control channel at a common timing. The storage area of the buffer 124 can be reduced to 1 / m.

  Only differences from the first embodiment will be described in detail. FIG. 12 is a block diagram showing the jitter buffer circuit 120 according to the present invention together with the circuit emulation device 100. The address control memory 128 is connected to the write control unit 121. The address control memory 128 stores the correspondence between the packet ID and the time slot number of the time division multiplexed signal. The time slot numbers 0 to 7 are the frame storage area numbers 0 to 7 of the data channel jitter buffer 122, the control channel storage area numbers 0 to 7 of the control channel jitter buffer 124, and the number storage of the writing surface memory 123. This corresponds to the area numbers 0 to 7, respectively.

  FIG. 13 is a diagram showing the correspondence between packet IDs stored in the address control memory 128 and time slot numbers. For example, the packet ID “IB” corresponds to the time slot number 3, and the data frame accommodated in the packet signal PB is stored in the frame storage area 3 of the data channel jitter buffer 122. This correspondence is set by a device control unit (not shown) included in the circuit emulation device 100.

  14 shows the data channel jitter when the circuit emulation device 100 receives the packet signals PA to PH twice in the order of PA, PB,..., PH, PA, PB,. It is a figure showing the data frames f1-f8 accumulate | stored in each multi-frame surface of the data channel storage surface T3-T5 of the buffer 122. FIG. The meanings of the symbols in the figure are the same as those in FIG. For example, the data frames f1 to f8 accommodated in the packet signal PB are stored in the frame storage area 3 based on the correspondence between the packet ID “IB” stored in the address control memory 128 and the time slot number 3. Is done. Since the packet signal PB is received next to the packet signal PA, the data frame f1 is accumulated in the multiframe plane number 1. The data frame f1 accommodated in the packet signal PA is stored in the multiframe plane number 0.

  FIG. 15 is a diagram illustrating the control channels SA to SH accumulated in the control channel accumulation surfaces T3 to T5 of the control channel jitter buffer 124 when the circuit emulation apparatus 100 receives the packet signals PA to PH twice. It is. The meanings of the symbols in the figure are the same as those in FIG. For example, the control channel SB accommodated in the packet signal PB is stored in the control channel storage area 3 based on the correspondence between the packet ID “IB” stored in the address control memory 128 and the time slot number 3. The The write control unit 121 instructs the control channel buffer 124 of the number of the control channel storage surface where the control channel stored in the packet signal should be stored. The number of the designated control channel storage surface is the same as the number of the data channel storage surface in which the first data frame accommodated in the packet signal is stored, as in the first embodiment. For example, if the number of the data channel storage surface in which the first data frame of the packet signal PA is stored is T3, the write control unit 121 uses T3 as the control channel storage surface number for storing the control channel for the control channel. The buffer 124 is instructed.

  FIG. 16 is a diagram showing multiframe surface numbers stored in the number storage area of the writing surface memory 123. The meanings of the symbols in the figure are the same as those in FIG. The write control unit 121 stores the number of the multi-frame plane in the corresponding number storage area based on the correspondence between the packet ID and the time slot number stored in the address control memory 128. For example, since the data frame f1 accommodated in the packet signal PB is accumulated in the multiframe plane number 1, the write control unit 121 sets the packet ID “IB” stored in the address control memory 128 and the time slot number 3 to Based on the correspondence, the multiframe surface number of the number storage area 3 is set to 1.

  FIGS. 17A and 17B are diagrams showing data frames and control channels read from the data channel jitter buffer 122 and the control channel jitter buffer 124. FIG. The meanings of the symbols in the figure are the same as those in FIG.

  The data channel jitter buffer 122 reads a data frame stored in the storage area T4-0 of the data channel jitter buffer 122. The data channel jitter buffer 122 reads the data frames in the order of the frame storage area numbers, that is, in the order of the time slot numbers. At this time, the order in which the data frames are read is f1, f7, f2, f8, f4, f3, f6, and f5, as indicated by the symbol (G) in FIG. The packet IDs of the packet signals in which these data frames are accommodated are in the order of IA, IC, IH, IB, IF, IG, ID, IE, as indicated by the symbol (H) in FIG. These data frames are assigned to the time slots of the time division multiplexed signal transmitted from the TDM frame transmission unit 130 in the read order.

  The process of reading the control channel by the control channel jitter buffer 124 and the process of enabling the control channel by the control channel selection unit 126 are the same as in the first embodiment, and thus the description thereof is omitted here. As an example of the process in which the control channel selection unit 126 validates the control channel, when the data channel jitter buffer 122 reads the data frame stored in the multiframe plane number 1, the control channel selection unit 126 When the number of the multi-frame surface read from the writing surface memory 123 is 1, the control channel SB being read simultaneously is made valid. The control channel SB is a control channel accommodated in the same packet signal as the data frame f1 read from the data channel jitter buffer 122.

  As described above, according to the present invention, based on the correspondence between the packet ID stored in the address control memory 128 and the time slot number, the data channel is allocated to the time slot of the time division multiplexed signal for each packet ID. Is possible. As a result, it is possible to cross-connect the data channel to a desired time slot for each packet ID. As in the first embodiment, when the stored data frame is taken out from the jitter buffer to be transmitted as a time division multiplexed signal, the data frame is read and at the same time, the control accommodated in the same packet as the data frame. It is possible in the present invention to read the channel.

It is a block diagram showing a jitter buffer circuit with a circuit emulation device. It is a figure showing a time division multiplex signal. It is a figure showing the packet signal produced | generated by circuit emulation. It is a figure showing the storage area with which the buffer for data channels is provided. It is a figure showing the memory area with which the buffer for control channels is provided. It is a figure showing the storage area of a writing surface memory. It is a figure showing the relationship between the storage area of the jitter buffer for data channels, and accumulation | storage of a packet signal. It is a figure showing the data frame accumulate | stored in each multi-frame surface of the jitter buffer for data channels. It is a figure showing the control channel accumulate | stored in the control channel storage surface of the jitter buffer for control channels. It is a figure showing the number of the multi-frame surface memorize | stored in the number storage area of the writing surface memory. It is a figure showing the data frame and control channel which are read from the jitter buffer for data channels, and the jitter buffer for control channels. It is a figure showing the data frame and control channel which are read from the jitter buffer for data channels, and the jitter buffer for control channels. It is a block diagram showing a jitter buffer circuit with a circuit emulation device. It is a figure showing the correspondence of packet ID memorize | stored in an address control memory and the number of a time slot. It is a figure showing the data frame accumulate | stored in each multi-frame surface of the jitter buffer for data channels. It is a figure showing the control channel accumulate | stored in the control channel storage surface of the jitter buffer for control channels. It is a figure showing the number of the multi-frame surface memorize | stored in the number storage area of the writing surface memory. It is a figure showing the data frame and control channel which are read from the jitter buffer for data channels, and the jitter buffer for control channels. It is a figure showing the data frame and control channel which are read from the jitter buffer for data channels, and the jitter buffer for control channels.

Explanation of symbols

100 circuit emulation device 110 packet receiving unit 120 jitter buffer circuit 121 write control unit 122 data channel jitter buffer 123 writing surface memory 124 control channel jitter buffer 125 data channel read control unit 126 control channel selection unit 127 control channel read control unit 128 Address control memory 130 TDM frame transmitter

Claims (3)

A jitter buffer circuit that receives a packet signal generated by circuit emulation of a time division multiplexed signal, converts the packet signal into a time division multiplexed signal, and transmits the signal.
A data channel jitter buffer including a storage area capable of storing data frames contained in the packet signal for each packet ID;
A control channel jitter buffer including a storage area capable of storing, for each packet ID, a control channel accommodated in a packet signal together with the data frame;
A writing surface memory for storing a correspondence relationship between a time slot in which a data frame accommodated in a packet having the packet ID is output and a storage area in which the data frame is stored;
When the data frame, the control channel, and the correspondence relationship are read from the data channel jitter buffer, the control channel jitter buffer, and the writing surface memory, reading is performed based on the correspondence relationship. And a control channel selector that determines whether or not the control channel of the time slot is valid. When the type of the packet ID is p (p is a positive integer), the data frame is m (m is a positive integer), and the control channel is one set,
The data channel jitter buffer includes d data channel storage surfaces (d is a positive integer) consisting of m multiframe surfaces capable of storing p data frames for each packet ID.
2. The jitter buffer circuit according to claim 1, wherein the jitter buffer for control channel includes d control channel storage surfaces capable of storing p sets of the control channel for each packet ID. An address control memory for storing time slot information in which a data frame accommodated in the packet is output for each packet ID;
A time slot of a storage area to be accumulated when writing the data frame, the control channel, and the correspondence relationship is determined from an address control memory, the data channel jitter buffer, the control channel jitter buffer, and the writing surface memory The jitter buffer circuit according to claim 1, further comprising: a write control unit that performs the write control.

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