JP4616821B2 - Signal transmission method and circuit emulation device - Google Patents

Description

  The present invention relates to a circuit emulation technique for realizing a TDM (Time Division Multiplexing) circuit on a packet switching network in a pseudo manner.

  In the TDM system conventionally used in circuit-switched networks, a transmission frame (TDM frame) is time-divided into a plurality of fixed-length time slots, and a communication line, that is, a logical channel can be assigned to each time slot. SONET (Synchronous Optical NETwork) / SDH (Synchronous Digital Hierarchy), which is a standard of ITU-T (International Telecommunication Union Telecommunication Standardization Sector), is a standard based on the TDM system.

On the other hand, packet switching networks such as the Internet and Ethernet (registered trademark) communication networks continue to expand. Therefore, development of a circuit emulation technique for realizing a TDM circuit on a packet switching network in a pseudo manner is in progress. Prior art relating to circuit emulation is disclosed in, for example, the following Non-Patent Documents 1 to 4 and Patent Documents 1 to 4.
A. Malis, P. Pate, R. Cohen, and D. Zelig, "SONET / SDH Circuit Emulation over Packet (CEP) draft-ietf-pwe3-sonet-12," Expired Internet draft, IETF, January 9, 2006. A. Vainshtein, I. Sasson, T. Frost, and P. Pate, "Structure-aware TDM Circuit Emulation Service over Packet Switched Network (CESoPSN)," Expired Internet draft, IETF, May 2006. A. Vainshtein, and Y (J) Stein, "Structure-Agnostic TDM over Packet (SAToP)," Expired Internet draft, IETF, February 2006. Y (J) Stein, R. Shashoua, R. Insler, and M. Anavi, "TDM over IP," Expired Internet draft, IETF, September 21, 2005. JP 2005-520375 A International publication WO 03/075501 pamphlet (international publication pamphlet of international patent application related to Patent Document 1) JP 2005-159701 A JP 2006-067040 A

  In the TDM system, when a specific line (channel) is in an unused state, the time slot to which the line is assigned is in a no-communication state, so that transmission efficiency in the circuit switching network decreases. In addition, if a TDM signal including an unused communication line is packetized, transmission efficiency in a packet switching network is also reduced. Therefore, by selectively accommodating only lines other than unused lines (hereinafter referred to as “empty lines” or “empty channels”) in the TDM signal, transmission efficiency in the packet switching network can be improved. It becomes possible.

  When a new line is added, if an unused empty line is accommodated, the empty line can be diverted as an additional line. Therefore, it is possible to perform a new line installation work or an expansion work without temporarily disconnecting the line connection in the opposite apparatus.

  However, if an unused unused line is not accommodated in advance when a new line is added, the opposite apparatus must perform a switching operation for shifting from the currently accommodated accommodation line to the new accommodation line. During this switching operation, the line connection is temporarily disconnected (line interruption), and the communication service is interrupted. Also, maintenance and operation costs for this switching work are required.

  In view of the above, a main object of the present invention is to provide a signal transmission method and a circuit emulation device that can efficiently accommodate a TDM signal in a packet, and can increase the number of lines without instantaneous line interruption. It is.

  To achieve the above object, a first signal transmission system according to the present invention converts a time division multiplexed signal in which a plurality of fixed-length time slots and header signals are time division multiplexed into a packet and converts the packet into a packet. The packet exchange is performed in cooperation between a transmission device that transmits to a switching network and a reception device that is oppositely connected to the transmission device via the packet switching network and converts a received packet from the transmission device into a time division multiplexed signal. A signal transmission system that emulates a time division multiplexed line on a network, wherein the transmitting device adds to existing communication lines respectively assigned to N time slots (N is a positive integer) among the time slots. A transmission control unit that executes transmission control in accordance with the line expansion that allocates an additional communication line to each of M time slots (M is a positive integer); The old packet generated by converting the time division multiplexed signal transmitted on the existing communication line and the new packet generated by converting the time division multiplexed signal transmitted on the added communication line A transmission processing unit configured to transmit in parallel to a packet switching network, and the reception device performs reception control according to the line addition, and receives from the transmission device according to the reception control. A packet detector for detecting either the old packet or the new packet from the received packet based on an identification code inserted in each of the packets; and an old packet detected by the packet detector according to the reception control A first reception buffer for temporarily storing a signal of the first packet, and a signal of a new packet detected by the packet detection unit according to the reception control temporarily A second reception buffer to be stored, a selector for switching a signal to be selected from the output signal of the first reception buffer to the output signal of the second reception buffer according to the reception control, and time division from the output signal selected by the selector And an interface unit for reproducing a multiplexed signal.

  A second signal transmission system according to the present invention includes: a transmission apparatus that converts a time division multiplexed signal obtained by time division multiplexing a plurality of fixed-length time slots and a header signal into a packet and transmits the packet to a packet switching network; A signal that emulates a time division multiplexing line on the packet switching network by a receiving device that is oppositely connected to the transmission device via the packet switching network and that converts a received packet from the transmission device into a time division multiplexing signal. In the transmission method, the transmission device can receive K (K is a positive integer less than N) from existing communication lines allocated to N time slots (N is a positive integer) among the time slots. A transmission control unit that executes transmission control according to line reduction for deleting a communication line; and, according to the transmission control, a time-division multiplexed signal transmitted on the existing communication line A transmission processing unit for transmitting in parallel the old packet generated by conversion and the new packet generated by converting the time-division multiplexed signal transmitted through the reduced communication line to the packet switching network. And the reception device performs the reception control according to the line reduction, and the identification code inserted in each of the received packets from the transmission device according to the reception control. A packet detection unit for detecting either the old packet or the new packet from a received packet; a first reception buffer for temporarily storing a signal of the old packet detected by the packet detection unit according to the reception control; A second reception buffer for temporarily storing a signal of a new packet detected by the packet detection unit according to the reception control; A selector that switches a signal to be selected from an output signal of one reception buffer to an output signal of the second reception buffer; and an interface unit that reproduces a time-division multiplexed signal from the output signal selected by the selector. It is said.

  A circuit emulation device according to the present invention is a circuit emulation device that packetizes a time division multiplexed signal composed of a transmission frame in which a plurality of fixed-length time slots and header signals are time division multiplexed. An interface unit that separates the channel signal inserted in each time slot and the header signal, and a time slot other than an empty time slot to which an empty channel is assigned is selected from the time slots separated by the interface unit. Then, the signal sequence composed of the channel signal of the selected time slot and the header signal separated by the interface unit is time-divided in units of the fixed length, and the time-divided signal sequence is multiplexed to obtain a data fragment. A fragment generation unit to be configured; Is characterized by comprising a packet generation portion for storing the data fragment packet to be transmitted to the Tsu-switched network, the.

  Hereinafter, various embodiments according to the present invention will be described.

  FIG. 1 is a block diagram showing a schematic configuration of a line emulation apparatus 1 according to an embodiment of the present invention. The circuit emulation apparatus 1 includes a frame interface (frame I / F) 10, a packet interface (packet I / F) 11, a transmission processing unit 12, a reception processing unit 13, and a controller 14.

  The frame interface 10 separates the main signal MD and the corresponding header signal OD from the TDM frame, and provides these signals MD and OD to the transmission processing unit 12. The format of the TDM frame may be a format compliant with the ITU-T standard, for example, a format compliant with SONET (Synchronous Optical NETwork) or SDH (Synchronous Digital Hierarchy). The transmission processing unit 12 generates a packet PD containing the main signal MD and the header signal OD, and supplies this packet PD to the packet interface 11. The packet interface 11 transmits the packet PD from the transmission processing unit 12 to a packet switching network (not shown) such as the Internet or an Ethernet (registered trademark) communication network. Here, the packet interface 11 automatically adjusts the transmission bit rate in accordance with fluctuations in the transmission band of the packet switching network in order to suppress the occurrence of packet loss. FIG. 2 is a functional block diagram schematically showing an example of the configuration of the transmission processing unit 12.

  On the other hand, the packet interface 11 has a function of receiving a packet containing a TDM frame from the packet switching network and supplying the received packet PD to the reception processing unit 13. The reception processing unit 13 extracts the main signal MD and the sub signal Od of the time division multiplexed signal from the received packet PD from the packet interface 11. The frame interface 10 has a function of combining the main signal MD and the sub signal Od from the reception processing unit 13 to reproduce the TDM frame. FIG. 3 is a functional block diagram schematically illustrating an example of the configuration of the reception processing unit 13.

  Hereinafter, the operation of the transmission processing unit 12 will be described with reference to FIG. The transmission processing unit 12 illustrated in FIG. 2 includes a transmission buffer 21, a fragment generation unit 22, a packet ID insertion unit 23, a transmission control memory (transmission CM) 24, a header insertion unit 25, and a CW (control word) generation unit 26. . The controller 14 and the transmission control memory 24 can constitute a “transmission control unit” of the present invention.

  As described above, the frame interface 10 separates the main signal MD and the header signal OD from the TDM frame (hereinafter simply referred to as “frame”). The transmission buffer 21 temporarily stores the main signal MD and the header signal OD from the frame interface 10. 4, 5, and 6 exemplify the format of a frame (VC-11) that complies with the TTC (Telecommunication Technology Committee) standard. 4 shows a frame format for a high-speed leased line, FIG. 5 shows a frame format for a low-speed leased line, and FIG. 6 shows a frame format for a general public line.

  Referring to the frame format for the high-speed leased line in FIG. 4, frames F1, F2, F3, and F4 each having a period of 125 μs are repeatedly generated. The frame F1 is composed of bit strings V5 and W constituting the header signal OD and 24 fixed-length (1 octet) time slots TS1, TS2,..., TS24 constituting the main signal MD. Similarly, the frame F2 is composed of bit strings J2 and W constituting the header signal OD and 24 fixed-length (1 octet) time slots TS1, TS2,..., TS24 constituting the main signal MD. F3 is composed of bit strings N2 and W constituting the header signal OD and 24 fixed-length (1 octet) time slots TS1, TS2,..., TS24 constituting the main signal MD. The bit string K4, W constituting the signal OD and 24 fixed-length (1 octet) time slots TS1, TS2,..., TS24 constituting the main signal MD. Channels CH1, CH2,..., CH24 are assigned to the time slots TS1, TS2,.

  Also, the W byte bit string of each of the frames F1 to F4 is composed of octet (8 bits) long bit strings of b1, b2, ST1, ST2, ST3, ST4, c1, c2 as shown in FIG. The Each of ST1, ST2, ST3 and ST4 is a status bit (status bit), which is a parameter indicating a frame transmission state. As shown in FIG. 4, 64 multi-frames (ST frames: status frames) are configured by status bits ST1, ST2, ST3, and ST4 for 64 frames. In FIG. 4, “CH AIS” is an alarm notification bit for the forward channel, “CH BAIS” is an alarm notification bit for the backward channel, “CH PTY” is an error monitoring bit for the forward channel, and “CH “BERR” represents an error notification bit for a reverse channel, and “CH LP” represents a channel return test bit. “TRACE”, “S” and “UNR” indicate reserved bits (= “1”).

  In the frame formats shown in FIGS. 5 and 6, as in the format of FIG. 4, frames F1, F2, F3, and F4 each having a period of 125 μsec are repeatedly generated. Each frame includes 24 time slots TS1 to TS24. These time slots TS1 to TS24 are divided into six blocks 1 to 4, and each block corresponds to a handling group HG1, HG2, HG3, HG4, respectively. It consists of 4 time slots to which channels are assigned. For example, the block 1 is composed of four time slots TS1, TS2, TS3, and TS4 to which channels CH1, CH7, CH13, and CH19 corresponding to the handling groups HG1, HG2, HG3, and HG4, respectively, are assigned.

  Also, the W byte bit string of each of the frames F1 to F4 has an octet (8 bits) length of b1, b2, ST1, ST2, ST3, ST4, c1, c2 as shown in FIGS. Consists of a bit string. Eight multi-frames (ST frames) are configured by the status bits ST1, ST2, ST3, ST4 for eight frames. In FIG. 5, “F” indicates a bit for frame synchronization, “SP” indicates a bit representing one value at the time of alarm or normal, and “D2”, “D3”, “D4”. Indicates a bit for switching information. In FIG. 6, “HG AIS” is a forward alarm notification bit for the handling group, “HG BAIS” is a reverse alarm notification bit, and “HG REC” is an ST frame out-of-sync detection bit. Each is shown.

  Referring to FIG. 2, the fragment generator 22 transmits the transmission buffer 21 in units of an even number of frames (in other words, every packetization period) according to the format specified by the control data held in the transmission control memory 24. The main signal MD and the header signal OD corresponding to the main signal MD are read out, and a data fragment including the read main signal MD and header signal OD is formed. In addition, the fragment generation unit 22 inserts the control word (CW) supplied from the CW generation unit 26 into the data fragment. This data fragment is to be accommodated in the transmission packet. FIG. 7 is a diagram schematically showing an example of the format of this data fragment.

  Referring to FIG. 2, the transmission control memory 24 holds various control data supplied from the controller 14. The transmission control memory 24 holds a control code for specifying an empty time slot to which an empty channel is allocated among the time slots TS1 to TS24 in which the main signal MD is inserted. The fragment generation unit 22 selectively reads time slots other than the empty time slot specified by the control data, and corresponds to the channel signals Ch1 to ChK (K is a positive integer) of the read time slot. A signal sequence composed of a predetermined bit sequence in the header signal to be processed is time-divided in units of a fixed length (1 octet) of a time slot. Further, the fragment generation unit 22 configures a data fragment by multiplexing the time-division signal sequence.

  Referring to FIG. 7, this data fragment is a multiplex of octet length signals. Specifically, the data fragment is composed of a control word (CW), a main fragment MF consisting of channel signals for 8 frames, and a sub-fragment STF consisting of 4 status bits (ST). The main fragment MF includes channel signals Ch1 to ChK (# 1), Ch1 to ChK (# 2), Ch1 to ChK (# 3), Ch1 to ChK (# 4), and Ch1 to ChK (# 5) for 8 frames. , Ch1 to ChK (# 6), Ch1 to ChK (# 7), and Ch1 to ChK (# 8) (where K is a positive integer).

  The control word (CW) includes a control code indicating a flag value (multiframe information) FRG for determining the phase of the multiframe. The flag value FRG is generated by the FRG generation unit 26. 8A is a format for accommodating the status bits ST1 to ST4 of FIG. 4, FIG. 8B is a format for accommodating the status bits ST1 to ST4 of FIG. 5, and FIG. This is a format for accommodating the status bits ST1 to ST4 of FIG. As shown in FIGS. 8A to 8C, the 4-bit status bits of the sub-fragment STF include a 2-bit flag representing one of the values “01”, “11”, and “10”. The value FRG is assigned. For example, referring to FIG. 8A, four status bits “CH AIS”, “1”, “1”, and “1” are assigned to the flag value FRG of “01”. (Here, “1” is a bit representing a logical value of 1). Further, four status bits of “CH AIS”, “1”, “1”, “1” are assigned to the flag value FRG of “10”.

  One of eight flag values FRG “01”, “11”, “11”, “11”, “11”, “11”, “11”, “10” is inserted in the control word (CW) Is done. That is, a value of “01” is inserted for the first ST frame, a value of “11” is inserted for each of the second to seventh ST frames, and a value of “8” is inserted for the eighth ST frame. Is inserted with a value of “10”.

  The CW generation unit 26 shown in FIG. 2 generates a sequence number SN indicating the transmission order of transmission packets, that is, the generation order, in addition to the flag value FRG, and includes this sequence number SN in the control word to generate the fragment generation unit 22. To supply. The sequence number SN is incremented every packetization period (ie every 8 frames).

  The packet ID insertion unit 23 shown in FIG. 2 inserts the packet identifier (packet ID) PID supplied from the transmission control memory 24 into the transmission packet. In this embodiment, the source port number and destination port number of UDP (User Datagram Protocol) can be used as the packet identifier PID, and further, an IP address, Ethernet (registered trademark) address, or VLAN (Virtual Local Area Network) : Virtual LAN) address can be used, but is not limited thereto. The type of old and new packets can be discriminated from the UDP source port number and destination port number, and the destination identity can be discriminated from the IP address, Ethernet (registered trademark) address, or VLAN address. Further, the header insertion unit 25 inserts header information such as an RTP (Real-time Transport Protocol) header or a UDP (User Datagram Protocol) header into the header portion of the transmission packet to generate the transmission packet PD.

  FIG. 9 shows an example of the format of the transmission packet. The header portion of the transmission packet contains an Ethernet (registered trademark) header, a VLAN (Virtual Local Area Network) header, a UDP header and an RTP header, and the payload of the transmission packet contains the data fragment. ing. In the RTP header, time stamp information indicating the generation time of each transmission packet is inserted.

  As described above, the fragment generation unit 22 selects a time slot other than an empty time slot, and time-division-multiplexes a signal sequence composed of the channel signal of the selected time slot and the corresponding header signal. Packetization of channel signals in unused time slots can be avoided. Further, the fragment generation unit 22 forms a data fragment as shown in FIG. 7 by time-dividing the signal sequence in units of a fixed time slot (1 octet). Therefore, the accommodation efficiency of a plurality of types of TDM frames as shown in FIGS. 4, 5, and 6 in the transmission packet can be maximized. Further, as will be described later, by adopting such a data fragment format, it becomes possible to dynamically add or remove lines without instantaneous line interruption.

  Next, the operation of the reception processing unit 13 will be described with reference to FIG. 3 includes a packet ID search unit 40, a packet discard unit 41, a header extraction unit 42, a CW extraction unit 43, a signal separation unit 44, an average reception time measurement unit 49, and a reception buffer control unit 50. Have. The reception processing unit 13 further includes a first reception buffer 45A, a second reception buffer 45B, a first reception control memory 46A, and a second reception control memory 46B. The controller 14, the reception buffer controller 50, and the first reception control memories 46A and 46B can constitute the “reception controller” of the present invention.

  The packet ID search unit 40 extracts the packet identifier PID from the received packet PD and supplies it to the header extraction unit 42 and the average reception time measurement unit 49. The packet ID search unit 40 instructs the packet discard unit 41 to discard the received packet when the packet identifier PID does not match the identification information of the packet to be received. The header extraction unit 42 extracts header information from the received packet PD, and provides the extracted header information to the average reception time measurement unit 49 and the controller 14. The CW extraction unit 43 extracts a control word from the received packet, supplies the flag value FRG of the extracted control word to the signal separation unit 44, and supplies the sequence number SN to the average reception time measurement unit 49. Although not explicitly shown in the figure, the sequence number SN and the packet identifier PID are also supplied to the reception buffer control unit 50. The “packet detection unit” of the present invention can be configured by the packet ID search unit 40, the header extraction unit 42, and the CW extraction unit 43.

  The signal separation unit 44 uses the flag value FRG to separate the main signal MD and the sub signal Od including the status bits from the received packet PD, and the main signal MD and the sub signal Od are separated from the first reception buffer 45A and the first reception buffer 45A. 2 is supplied to the reception buffer 45B.

  The first reception buffer 45A and the second reception buffer 45B have a function of temporarily storing the main signal MD and the sub signal Od supplied from the signal separation unit 44, respectively. These two first reception buffers 45A and 45B are used in a reception process when a line is added or removed, which will be described later. In a normal reception process, only the first reception buffer 45A is used. The The reception buffer control unit 50 performs write control on the first reception buffer 45A and the second reception buffer 45B. The first reception control memory 46A holds address data for executing signal read control for the first reception buffer 45A, and the second reception control memory 46B performs signal read control for the second reception buffer 45B. Holds address data for execution.

  The average reception time measuring unit 49 has a function of measuring the average reception time of the received packet PD using the time stamp information and measuring the fluctuation (jitter) of the transmission delay amount of the packet PD based on the measured value. The reception buffer control unit 50 can perform write control on the first reception buffer 45A and the second reception buffer 45B so as to reduce the influence of such jitter. Therefore, the first reception buffer 45A and the second reception buffer 45B can function as a jitter buffer.

  The signal comparison unit 47 compares the main signal MD1 output from the first reception buffer 45A with the main signal MD2 output from the second reception buffer 45B in bit units, and notifies the controller 14 of the comparison result. The signal comparison unit 47 operates when a line to be described later is added or removed.

  The selector 48 selects one of the output signals MD1 and Od1 of the first reception buffer 45A and the output signals MD2 and Od2 of the second reception buffer 45B according to the control of the controller 14, and uses the selected signal as a frame interface. 10 is supplied. The frame interface 10 reproduces a time division multiplexed signal (TDM frame) from the main signal and the sub signal selected by the selector 48.

  The operation of the circuit emulation device 1 having the above configuration will be described below. When a communication line (channel) is newly established, the line emulation apparatus 1 and a counter apparatus (not shown) having the same configuration as the line emulation apparatus 1 cooperate to perform line establishment work (setting a new line). . Thereby, N (N is a positive integer) communication lines (channels) are emulated on the packet switching network between the line emulation apparatus 1 and the opposite apparatus.

  Next, a signal transmission system when adding communication lines (channels) will be described below with reference to FIGS. 10, 11 and 12. FIG. The circuit emulation devices 1A and 1B shown in FIGS. 10, 11 and 12 both have the same configuration as the circuit emulation device 1 shown in FIGS. 1 to 3, and are connected to each other via the packet switching network PSN. Yes. These opposing line emulation apparatuses 1A and 1B cooperate to execute a communication line expansion procedure.

  As shown in FIG. 10A, it is assumed that packets Pa and Pb in which two existing lines C1 and C3 are multiplexed are transmitted and received between the line emulation apparatuses 1A and 1B. In FIG. 10A, the head portion HD of the packets Pa and Pb indicates the header portion shown in FIG. 9, and the CW following the head portion HD indicates a control word. For convenience of explanation, the two lines C1 and C3 are multiplexed. However, the present invention is not limited to this, and an arbitrary number of configurable lines may be multiplexed.

  Each of the controllers 14 (FIGS. 2 and 3) of the line emulation apparatuses 1A and 1B starts reception control and transmission control in accordance with an extension command for the communication line C2. The circuit emulation device 1A generates a packet (hereinafter referred to as “old packet”) Pa from a TDM signal transmitted through the communication lines C1 and C3 (hereinafter referred to as “old line”) before expansion, and further. Then, a packet (hereinafter referred to as “new packet”) Pb is generated from the TDM signal transmitted through the added communication line (hereinafter referred to as “new line”) C1, C2, C3. Then, as shown in FIG. 10B, the circuit emulation device 1A transmits the old packet Pa and the new packet Pb in parallel to the opposite device 1B. Similarly, in the opposite line emulation apparatus 1B, the old packet Pb is generated from the TDM signal transmitted on the old lines C1 and C3 before the addition, and further the TDM signal transmitted on the new lines C1, C2 and C3 after the addition. To generate a new packet Pd. Then, the circuit emulation device 1B transmits the old packet Pa and the new packet Pd in parallel to the opposite device 1A.

  Here, in each of the transmission processing units 12 of the line emulation apparatuses 1A and 1B, the CW generation unit 26 shown in FIG. 2 generates the first sequence number SN (= SN1) indicating the transmission order of the old packets, In parallel with this, a second sequence number SN (= SN2) indicating the transmission order of new packets is generated. Numbers of the same series may be used for sequence numbers SN1 and SN2. Then, the CW generation unit 26 supplies the sequence numbers SN1 and SN2 of the first sequence and the second sequence to the fragment generation unit 22 as part of the control word (CW). The fragment generation unit 22 inserts the sequence number SN1 into the old packet and inserts the sequence number SN2 into the new packet. Further, the packet ID insertion unit 23 assigns different packet identifiers PID between the old packet and the new packet. For example, only the upper bits of the packet identifier PID (= PID1) assigned to the old packet may be inverted to generate the packet identifier PID (= PID2) to be assigned to the new packet. These packet identifiers PID1, PID2 and sequence numbers SN1, SN2 are identification codes used to identify the old packet and the new packet received at the opposite device, and the same communication between the old packet and the new packet. It is also an identification code indicating that the packet contains the channel signals of the lines C1 and C3.

  The transmission-side controller 14 assigns and manages unique line identifier values to the lines C1 and C3 and the extension line C2. The same line identifier is also managed in the controller 14 on the receiving side. As the line identifier, a value that can identify the insertion positions of the lines C1, C2, and C3 may be set.

  If the reception control setting is not completed in the circuit emulation devices 1A and 1B, the packet ID search unit 40 shown in FIG. 3 determines that the packet identifier PID2 of the received new packet does not match the identification information of the packet to be received. The packet discard unit 41 is instructed to discard the new packet.

  Thereafter, when the reception control setting is completed in the line emulation apparatuses 1A and 1B, as shown in FIG. 11C, the line emulation apparatus 1B discards the pair of old and new packets Pa and Pc from the opposite apparatus 1A. The line emulation apparatus 1A receives the pair of old and new packets Pb and Pd from the opposite apparatus 1B without discarding them.

  At this time, in each of the reception processing units 13 of the line emulation apparatuses 1A and 1B, the reception buffer control unit 50 shown in FIG. 3 is based on the sequence numbers SN1 and SN2 of the supplied received packets and the packet identifiers PID1 and PID2. It is identified whether the received packet PD is an old packet or a new packet. The reception buffer controller 50 reads control signals from the first reception control memory 46A and the second reception control memory 46B, respectively, and based on these control signals, received packet sequence numbers SN1 and SN2, and packet identifiers PID1 and PID2. To specify the write address. The reception buffer control unit 50 stores the main signal MD and the sub signal Od separated from the old packet in the area specified by the write address of the first reception buffer 45A, and the main signal separated from the new packet. The MD and the sub signal Od are stored in the area designated by the write address of the second reception buffer 45B.

  Further, the signal comparison unit 47 uses the line identifier supplied from the controller 14 and the main signal MD1 output from the first reception buffer 45A and the main signal assigned with the same line identifier output from the second reception buffer 45B. The signal MD2 is compared bit by bit. Based on the comparison result, the signal comparison unit 47 denies the validity of the new packet if, for example, the number of mismatch bits is equal to or greater than a predetermined number of bits. On the other hand, if the number of mismatch bits is less than the predetermined number of bits, the signal comparison unit 47 affirms the validity of the new packet and notifies the controller 14 of the affirmative result.

  On the other hand, the average reception time measurement unit 49 measures the average reception time T1 of the old packet and the average reception time T2 of the new packet based on the time stamp information supplied from the header extraction unit 42, and further, the time difference δT ( = | T1-T2 |) is calculated. If the time difference δT exceeds the allowable value Vth, the average reception time measurement unit 49 determines that the transmission delay amount fluctuation is large and cannot guarantee a constant signal quality, and notifies the controller 14 and the reception buffer control unit 50 of an alarm. To emit. When receiving the alarm, the reception buffer control unit 50 stops packet writing to the first reception buffer 45A and the second reception buffer 45B, thereby generating a packet loss.

  The controller 14 receives the selection result for the selector 48 only when it receives the determination result of the validity of the new packet from the signal comparison unit 47 and does not receive an alarm from the average reception time measurement unit 49. An instruction is given to switch from the output signals MD1 and Od1 of the reception buffer 45A to the output signals MD2 and Od2 of the second reception buffer 45B. As a result, the selector 48 supplies the main signal MD2 and the sub signal Od2 separated from the new packet to the frame interface 10. The frame interface 10 generates a TDM frame in which the new lines C1, C2, and C3 are multiplexed.

  Thereafter, the controller 14 stops the transmission of the old packet and cancels the setting for receiving the old packet. As a result, as shown in FIG. 10D, the circuit emulation device 1A stops transmitting the old packet Pa. Further, even when the circuit emulation device 1A receives the old packet Pb from the opposite device 1B, the circuit emulation device 1A discards the old packet Pb. Finally, as shown in FIG. 10E, only new packets Pc and Pd in which the new lines C1, C2, and C3 are multiplexed are transmitted and received between the line emulation apparatuses 1A and 1B.

  Next, a signal transmission system when a communication line (channel) is reduced will be described below with reference to FIGS. 13, 14, and 15. FIG. The circuit emulation devices 1A and 1B shown in FIGS. 13, 14 and 15 both have the same configuration as the circuit emulation device 1 shown in FIGS. 1 to 3, and are connected to each other via the packet switching network PSN. Yes. These opposing line emulation apparatuses 1A and 1B cooperate to execute a communication line reduction procedure. As shown in FIG. 13A, it is assumed that packets Pc and Pd in which three existing lines C1, C2, and C3 are multiplexed are transmitted and received between the line emulation apparatuses 1A and 1B.

  Each of the controllers 14 (FIGS. 2 and 3) of the line emulation apparatuses 1A and 1B starts reception control and transmission control in accordance with a reduction command for the communication line C2. The circuit emulation device 1A generates a packet (hereinafter referred to as “old packet”) Pc from the TDM signal transmitted through the communication lines C1, C2, C3 (hereinafter referred to as “old line”) before the reduction. Further, a packet (hereinafter referred to as “new packet”) Pe is generated from the TDM signals transmitted through the communication lines (hereinafter referred to as “new line”) C1 and C3 after the reduction. Then, as shown in FIG. 13B, the circuit emulation device 1A transmits the old packet Pc and the new packet Pe in parallel to the opposite device 1B. Similarly, the opposite line emulation apparatus 1B generates the old packet Pd from the TDM signal transmitted on the old lines C1, C2, and C3, and further generates the new packet Pf from the TDM signal transmitted on the new lines C1 and C3. To do. Then, the circuit emulation device 1B transmits the old packet Pd and the new packet Pf in parallel to the opposite device 1A.

  Here, in each of the transmission processing units 12 of the line emulation apparatuses 1A and 1B, the CW generation unit 26 shown in FIG. 2 performs a first sequence indicating the transmission order of the old packets, as in the case of the above-mentioned line addition. A number SN (= SN1) is generated, and in parallel therewith, a second sequence number SN (= SN2) indicating the transmission order of new packets is generated. Then, the CW generation unit 26 supplies the sequence numbers SN1 and SN2 of the first sequence and the second sequence to the fragment generation unit 22 as part of the control word (CW).

  If the reception control setting is not completed in the circuit emulation devices 1A and 1B, the packet ID search unit 40 shown in FIG. 3 determines that the packet identifier PID2 of the received new packet does not match the identification information of the packet to be received. The packet discard unit 41 is instructed to discard the new packet.

  Thereafter, when the reception control setting is completed in the line emulation apparatuses 1A and 1B, as shown in FIG. 14C, the line emulation apparatus 1B discards the pair of old and new packets Pc and Pe from the opposite apparatus 1A. The line emulation apparatus 1A receives the pair of new and old packets Pd and Pf from the opposite apparatus 1B without discarding them. At this time, the reception buffer control unit 50 shown in FIG. 3 determines that the received packet PD is old based on the sequence numbers SN1 and SN2 of the supplied received packets and the packet identifiers PID1 and PID2, as in the case of the above-described line addition. Identify whether it is a packet or a new packet. Then, the reception buffer control unit 50 stores the main signal MD and the sub signal Od separated from the old packet in the first reception buffer 45A, and the main signal MD and the sub signal Od separated from the new packet are stored in the second Store in the reception buffer 45B.

  In addition, the signal comparison unit 47 uses the line identifier supplied from the controller 14 and the main signal MD1 output from the first reception buffer 45A and the main signal assigned from the second reception buffer 45B and assigned with the same line identifier. The signal MD2 is compared bit by bit. Based on the comparison result, the signal comparison unit 47 denies the validity of the new packet if, for example, the number of mismatch bits is equal to or greater than a predetermined number of bits. On the other hand, if the number of mismatch bits is less than the predetermined number of bits, the signal comparison unit 47 affirms the validity of the new packet and notifies the controller 14 of the affirmative result.

  On the other hand, based on the time stamp information supplied from the header extraction unit 42, the average reception time measurement unit 49 sets a time difference δT (= | T1-T2) between the average reception time T1 of the old packet and the average reception time T2 of the new packet. |) Is calculated. If the time difference δT exceeds the allowable value Vth, the average reception time measurement unit 49 determines that the transmission delay amount fluctuates largely and cannot guarantee a constant signal quality, and issues an alarm to the controller 14.

  The controller 14 receives the determination result that recognizes the validity of the new packet from the signal comparison unit 47, and only when the alarm is not received from the average reception time measurement unit 49, the output signal MD1, of the first reception buffer 45A. The selector 48 is instructed to switch the selection signal from Od1 to the output signals MD2 and Od2 of the second reception buffer 45B. As a result, the selector 48 supplies the main signal MD2 and the sub signal Od2 separated from the new packet to the frame interface 10. The frame interface 10 generates a TDM frame in which the new lines C1 and C3 are multiplexed.

  As described above, by using the circuit emulation device 1 according to the present embodiment, when switching from the currently operating accommodation line to a new accommodation line, the line connection between the opposing devices is not temporarily disconnected (communication line). It is possible to dynamically add and remove communication lines in a short time and dynamically (without instantaneous interruption). In addition, the switching work can be executed without impairing the communication quality and without interrupting the communication service, and the cost required for maintenance and management can be suppressed at a low cost.

It is a block diagram which shows schematic structure of the circuit emulation apparatus which is an Example which concerns on this invention. It is a functional block diagram which shows an example of a structure of a transmission process part roughly. It is a functional block diagram which shows roughly an example of a structure of a reception process part. It is a figure which illustrates the frame format for high-speed exclusive lines. It is a figure which illustrates the frame format for low-speed exclusive lines. It is a figure which illustrates the frame format for general public lines. It is a figure which shows an example of the format of a data fragment roughly. (A) is a format for accommodating the status bits of FIG. 4, (B) is a format for accommodating the status bits of FIG. 5, and (C) is a format for accommodating the status bits of FIG. It is a figure which shows the format for each. It is a figure which shows an example of the format of a transmission packet. It is a figure for demonstrating the signal transmission system at the time of expansion of a communication line. It is a figure for demonstrating the signal transmission system at the time of expansion of a communication line. It is a figure for demonstrating the signal transmission system at the time of expansion of a communication line. It is a figure for demonstrating the signal transmission system at the time of reduction of a communication line. It is a figure for demonstrating the signal transmission system at the time of reduction of a communication line. It is a figure for demonstrating the signal transmission system at the time of reduction of a communication line.

Explanation of symbols

1 Line emulation device 10 Frame interface (frame I / F)
11 Packet interface (packet I / F)
12 Transmission processing unit 13 Reception processing unit 14 Controller 22 Fragment generation unit 23 Packet ID insertion unit 24 Transmission control memory (transmission CM)
25 Header insertion unit 26 CW generation unit (control word generation unit)
40 packet ID search unit 41 packet discard unit 42 header extraction unit 43 CW extraction unit 44 signal separation unit 45A first reception buffer 45B second reception buffer 47 signal comparison unit 48 selector 50 reception buffer control unit

Claims (19)

A transmission device that converts a time division multiplexed signal in which a plurality of fixed-length time slots and header signals are time division multiplexed into a packet and sends the packet to a packet switching network, and the transmission device via the packet switching network And a signal transmission method for emulating a time division multiplex line on the packet switching network in cooperation with a reception device that is oppositely connected and converts a received packet from the transmission device into a time division multiplex signal,
The transmitter is
In addition to the existing communication lines assigned to N time slots (N is a positive integer) among the time slots, in addition to an additional communication line that assigns additional communication lines to M (M is a positive integer) time slots. A transmission control unit that executes transmission control according to
In accordance with the transmission control, an old packet generated by converting the time division multiplexed signal transmitted on the existing communication line and a new packet generated by converting the time division multiplexed signal transmitted on the added communication line And a transmission processing unit for transmitting to the packet switching network in parallel,
Have
The receiving device is:
A reception control unit that performs reception control according to the line extension;
A packet detector for detecting either the old packet or the new packet from the received packet based on an identification code inserted in each received packet from the transmitter according to the reception control;
A first reception buffer for temporarily storing a signal of an old packet detected by the packet detection unit according to the reception control;
A second reception buffer for temporarily storing a signal of a new packet detected by the packet detection unit according to the reception control;
A selector for switching a signal to be selected from the output signal of the first reception buffer to the output signal of the second reception buffer according to the reception control;
An interface unit for reproducing a time division multiplexed signal from the output signal selected by the selector;
A signal transmission system characterized by comprising: A transmission device that converts a time division multiplexed signal in which a plurality of fixed-length time slots and header signals are time division multiplexed into a packet and sends the packet to a packet switching network, and the transmission device via the packet switching network A signal transmission method for emulating a time division multiplex line on the packet switching network by a receiving device that is oppositely connected and converts a received packet from the transmission device into a time division multiplex signal,
The transmitter is
Corresponding to line reduction to delete K (K is a positive integer less than N) communication lines from existing communication lines respectively assigned to N time slots (N is a positive integer) among the time slots. A transmission control unit for performing transmission control;
In accordance with the transmission control, an old packet generated by converting the time division multiplexed signal transmitted on the existing communication line and a new one generated by converting the time division multiplexed signal transmitted on the reduced communication line A transmission processing unit for transmitting packets in parallel to the packet switching network;
Have
The receiving device is:
A reception control unit that performs reception control according to the line reduction;
A packet detector for detecting either the old packet or the new packet from the received packet based on an identification code inserted in each received packet from the transmitter according to the reception control;
A first reception buffer for temporarily storing a signal of an old packet detected by the packet detection unit according to the reception control;
A second reception buffer for temporarily storing a signal of a new packet detected by the packet detection unit according to the reception control;
A selector for switching a signal to be selected from the output signal of the first reception buffer to the output signal of the second reception buffer according to the reception control;
An interface unit for reproducing a time division multiplexed signal from the output signal selected by the selector;
A signal transmission system characterized by comprising: The signal transmission system according to claim 1 or 2,
The receiving apparatus further includes a signal separation unit that separates a channel signal corresponding to each of the communication lines and a state bit indicating a transmission state of the time division multiplexed signal from the received packet,
The first reception buffer temporarily stores channel signals and status bits separated from the old packet by the signal separation unit, and the second reception buffer is separated from the new packet by the signal separation unit. A signal transmission system characterized by temporarily storing channel signals and status bits. The signal transmission method according to any one of claims 1 to 3,
The receiving apparatus further includes a signal comparison unit that compares the output signal of the first reception buffer with the output signal of the second reception buffer and determines whether the new packet is valid based on the comparison result. And
The reception controller controls the selector to select the output signal of the first reception buffer before confirming the validity of the new packet based on the determination result by the signal comparison unit, and determines the validity of the new packet. A signal transmission method characterized by controlling the selector so as to select the output signal of the second reception buffer after confirming the characteristics. A signal transmission system according to claim 4, wherein
Each of the communication lines is assigned a unique line identifier,
The signal comparison unit uses the line identifier to output a channel signal output from the first reception buffer and a channel signal output from the second reception buffer and assigned the same line identifier as the channel signal. A signal transmission system characterized by comparison. A signal transmission method according to any one of claims 1 to 5,
The transmission processing unit inserts a first sequence number indicating the transmission order of the old packets into each of the old packets and assigns a second sequence number indicating the transmission order of the new packets to each of the new packets. Inserted into
The packet detection unit uses the sequence number of the first sequence and the second sequence as the identification code. The signal transmission method according to claim 6, wherein
The transmission processing unit inserts a first packet identifier corresponding to each of the old packets into each of the old packets, and inserts a second packet identifier corresponding to each of the new packets into each of the new packets. ,
The packet detection unit uses the first and second packet identifiers as the identification code in addition to the sequence numbers of the first sequence and the second sequence.   8. The signal transmission system according to claim 7, wherein the first sequence and the second sequence are the same sequence. 9. The signal transmission method according to claim 1, wherein the reception device receives a first average reception time of the old packet received from the transmission device and the transmission device. A reception time measuring unit that measures a second average reception time of the new packet and determines whether a time difference between the first average reception time and the second average reception time exceeds an allowable value; Have
The reception controller controls the selector to select an output signal of the second reception buffer only when the time difference is equal to or less than the allowable value based on a determination result by the reception time measurement unit. Signal transmission method. A signal transmission system according to any one of claims 1 to 9,
The time division multiplexed signal comprises a transmission frame in which a plurality of fixed-length time slots and header signals are time division multiplexed,
The transmission processing unit
An interface unit for separating the channel signal inserted in the time slot from the transmission frame and the header signal;
A time slot other than an empty time slot to which an empty channel is allocated is selected from the time slots separated by the interface unit, and a channel signal of the selected time slot and a header signal separated by the interface unit are selected. A fragment generation unit that time-divides a signal sequence composed of a predetermined bit sequence in the fixed length unit, multiplexes the time-division signal sequence, and constitutes a data fragment;
A packet generator for accommodating the data fragment in a packet to be transmitted to the packet switched network;
A signal transmission system characterized by including:   11. The signal transmission system according to claim 10, wherein the fixed length is in units of 1 octet.   12. The signal transmission system according to claim 10, wherein the predetermined bit string includes the status bits. The signal transmission method according to claim 12,
The predetermined bit string includes a plurality of status frames each composed of the status bits of L bits (L is an integer of the fixed length),
The packet transmission unit includes a flag value for determining a phase of the status frame in the packet.   14. The signal transmission system according to claim 10, wherein the transmission controller includes a control memory for storing control data indicating the empty time slot. . A circuit emulation device for packetizing a time division multiplexed signal composed of a transmission frame in which a plurality of fixed-length time slots and header signals are time division multiplexed,
An interface unit for separating the channel signal inserted in the time slot from the transmission frame and the header signal;
A time slot other than an empty time slot to which an empty channel is allocated is selected from the time slots separated by the interface unit, and a channel signal of the selected time slot and a header signal separated by the interface unit are selected. A fragment generation unit that time-divides a signal sequence composed of a predetermined bit sequence in the fixed length unit, multiplexes the time-division signal sequence, and constitutes a data fragment;
A packet generator for accommodating the data fragment in a packet to be transmitted to the packet switched network;
A circuit emulation device comprising:   16. The circuit emulation device according to claim 15, wherein the fixed length is in units of 1 octet.   17. The circuit emulation apparatus according to claim 15, wherein the predetermined bit string is composed of a status bit indicating a transmission state of the time division multiplexed signal. The circuit emulation device according to claim 17,
The predetermined bit string includes a plurality of status frames each composed of the status bits of L bits (L is an integer of the fixed length),
The circuit emulation device, wherein the packet generation unit includes a flag value for determining a phase of the status frame in the packet.   19. The circuit emulation device according to claim 15, further comprising a control memory for storing control data indicating the empty time slot.

Images