JP2014107423A - Hetero junction field effect transistor and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an art which can inhibit damages on a semiconductor substrate surface in a manufacturing process of a hetero junction field effect transistor.SOLUTION: A manufacturing method of a hetero junction field effect transistor comprises: a process of forming a dielectric film 4 on a source electrode 2a, a drain electrode 2b, a semiconductor substrate 1 and a gate electrode body 3; a process of removing the dielectric film 4 on the gate electrode body 3; and a process of forming a field relaxation electrode 5 which projects laterally from a first gate electrode 3a on the dielectric film 4 around the first gate electrode 3a.

Description

  The present invention relates to a heterojunction field effect transistor including a nitride semiconductor and a method for manufacturing the same.

  In a heterojunction field effect transistor made of a semiconductor containing nitride, it is known that if the gate length is shortened, it is possible to cope with higher frequency signals, but the gate cross-sectional area is reduced and the gate resistance is increased. ing. In order to avoid this, a configuration has been proposed in which a protruding portion that protrudes to the side of the gate electrode is provided, that is, a configuration in which the gate electrode is formed in an umbrella shape (T-shape). According to such a configuration, the gate cross-sectional area can be increased while the gate length where the gate electrode is actually in contact with the semiconductor layer is shortened, so that the gate resistance can be reduced.

  Patent Document 1 discloses a configuration in which one of the above-described configurations is provided with a dielectric film in which one end is inserted into the gap between the protruding portion of the gate electrode and the semiconductor layer and the other end extends to the drain electrode. Has been. According to such a configuration, an electric field concentrated on the gate electrode end on the drain electrode side when a high voltage is applied to the drain electrode can be relaxed. This makes it possible to suppress a characteristic current collapse in a heterojunction field effect transistor made of a semiconductor containing nitride.

JP 2004-200248 A

  In the manufacturing process of the heterojunction field effect transistor including the gate electrode having the protruding portion and the dielectric film as described above, the gate electrode is formed after forming the dielectric film on the semiconductor layer before forming the gate electrode. The dielectric film in the region to be removed is removed by a dry etching method, and then the gate electrode is laminated on the semiconductor layer exposed by removing the dielectric film.

  However, in such a manufacturing process, there is a problem in that the semiconductor layer is damaged during the dry etching, and characteristics such as gate leakage current and current collapse are deteriorated. Further, even if an attempt is made to form a dielectric film after forming the gate electrode, it becomes difficult to insert the dielectric film into the gap between the protruding portion of the gate electrode and the semiconductor layer.

  In addition, after forming a rectangular partial electrode to be a part of the gate electrode, a dielectric film is formed so as to cover the partial electrode, and after further removing the dielectric film immediately above the partial electrode, an electrode connected to the upper part of the partial electrode Can also be considered. According to such a manufacturing process, damage to the semiconductor layer can be avoided, but usually the removal accuracy of the dielectric film is poor and the dielectric film is removed larger than planned. For this reason, there is a problem that it is necessary to perform lithography on the dielectric film with a higher resolution than that of the gate electrode, or that the gate electrode is longer than the design and high frequency characteristics cannot be obtained.

  Accordingly, the present invention has been made in view of the above-described problems, and an object thereof is to provide a technique capable of suppressing damage to the surface of a semiconductor substrate in a manufacturing process of a heterojunction field effect transistor. And

  The method of manufacturing a heterojunction field effect transistor according to the present invention includes: (a) a step of forming a source / drain electrode on a semiconductor substrate containing a nitride semiconductor; and (b) the semiconductor substrate between the source / drain electrodes. Forming a gate electrode body in which the first and second gate electrodes are laminated in this order; and (c) forming a dielectric film on the source / drain electrodes, the semiconductor substrate, and the gate electrode body; (D) removing the dielectric film on the gate electrode body; and (e) an electric field relaxation electrode protruding laterally from the first gate electrode on the dielectric film around the first gate electrode. Forming.

  According to the present invention, when the dielectric film on the gate electrode body is removed, the exposure of the surface of the semiconductor substrate is suppressed, so that damage to the surface of the semiconductor substrate can be suppressed.

1 is a cross-sectional view illustrating a configuration of a heterojunction field effect transistor according to a first embodiment. 10 is a cross-sectional view showing a method for manufacturing the heterojunction field effect transistor according to the second embodiment. FIG. 10 is a cross-sectional view showing a method for manufacturing the heterojunction field effect transistor according to the second embodiment. FIG. 10 is a cross-sectional view showing a method for manufacturing the heterojunction field effect transistor according to the second embodiment. FIG. 10 is a cross-sectional view showing a method for manufacturing the heterojunction field effect transistor according to the second embodiment. FIG. 10 is a cross-sectional view showing a method for manufacturing the heterojunction field effect transistor according to the second embodiment. FIG. FIG. 6 is a cross-sectional view illustrating a configuration of a heterojunction field effect transistor according to a third embodiment. 7 is a cross-sectional view illustrating a method for manufacturing a heterojunction field effect transistor according to Embodiment 3. FIG.

<Embodiment 1>
FIG. 1 is a cross-sectional view showing a configuration of a heterojunction field effect transistor according to Embodiment 1 of the present invention. As shown in FIG. 1, this heterojunction field effect transistor includes a semiconductor substrate 1, source / drain electrodes 2a and 2b, a gate electrode body 3, a dielectric film 4, and an electric field relaxation electrode 5. ing. Hereinafter, these components will be described in detail.

  The semiconductor substrate 1 is formed on the lowermost substrate 1a, the buffer layer 1b formed on the substrate 1a, the channel layer 1c made of a nitride semiconductor formed on the buffer layer 1b, and the channel layer 1c. And a barrier layer 1d made of a nitride semiconductor. The channel layer 1c and the barrier layer 1d form a heterojunction in the heterojunction field effect transistor.

  The source electrode 2a and the drain electrode 2b are made of, for example, one or a plurality of metal films, and are formed on the semiconductor substrate 1 (on the barrier layer 1d) so as to be separated from each other.

  The gate electrode body 3 is directly formed on the semiconductor substrate 1 (on the barrier layer 1d) between the source / drain electrodes 2a and 2b. The gate electrode body 3 is made of, for example, one or a plurality of metal films. In the first embodiment, the gate electrode body 3 includes the first gate electrode 3a. However, the present invention is not limited to this, and the second gate electrode described in the second and third embodiments described later is used. 3b may be further provided.

The dielectric film 4 is composed of, for example, a SiN _x surface protective film, and is provided between the gate electrode body 3 (first gate electrode 3a) and the source electrode 2a, and the gate electrode body 3 (first gate electrode 3a). And on the semiconductor substrate 1 (on the barrier layer 1d) between the drain electrode 2b and the drain electrode 2b.

  The electric field relaxation electrode 5 is formed on the dielectric film 4 around the first gate electrode 3a so as to be electrically connected to the first gate electrode 3a and protrudes laterally from the first gate electrode 3a. That is, one end of the dielectric film 4 formed between the first gate electrode 3a and the drain electrode 2b in the horizontal direction is inserted between the electric field relaxation electrode 5 and the semiconductor substrate 1 in the vertical direction.

  In the first embodiment, the electric field relaxation electrode 5 protrudes only from the first gate electrode 3a toward the drain electrode 2b. Note that the gate electrode body 3 (first gate electrode 3a) and the electric field relaxation electrode 5 may be made of the same metal or may be made of different metals as long as they are easy to handle later. The same metal may be used.

  According to the heterojunction field effect transistor according to the first embodiment configured as described above, the gate electrode body 3 directly formed on the semiconductor substrate 1 and the electric field projecting laterally from the upper portion of the gate electrode body 3. A relaxation electrode 5 is formed. Therefore, it is possible to increase the gate cross-sectional area and reduce the gate resistance in a state where the actual gate length is shortened. That is, it is possible to realize a heterojunction field effect transistor that can cope with high frequency signals and suppresses an increase in gate resistance.

  In the first embodiment, since the dielectric film 4 is inserted between the electric field relaxation electrode 5 connected to the gate electrode body 3 and the semiconductor substrate 1, the gate leakage current and current collapse are suppressed. Can do.

  Further, according to the first embodiment, since the electric field relaxation electrode 5 protrudes only on the drain electrode 2b side, the electric field relaxation electrode 5 is compared with the configuration in which the electric field relaxation electrode 5 protrudes also on the source electrode 2a side. 5 The capacity of the lower part can be reduced.

  Note that the semiconductor substrate 1 does not necessarily include three layers including the buffer layer 1b, the channel layer 1c, and the barrier layer 1d as long as the semiconductor substrate 1 can operate as a heterojunction field effect transistor. For example, the semiconductor substrate 1 may include N (N = 1, 2, 4,...) Semiconductor layers including a nitride semiconductor instead of these three semiconductor layers.

Further, the dielectric film 4 may not be composed of a surface protective film of SiN _x as long as the electric field applied to the ends of the gate electrode body 3 and the electric field relaxation electrode 5 on the drain electrode 2b side can be relaxed. _{x, SiO x N y, Al} x N y, AlO x N y, it may be composed of a surface protective film such as _HfO x _{N y.}

  Although only the minimum necessary elements to operate as a heterojunction field effect transistor are described above, the device is actually configured as a device in which wirings, via holes, etc. are formed in the heterojunction field effect transistor. .

<Embodiment 2>
In Embodiment 2 of the present invention, an example of a method for manufacturing the heterojunction field effect transistor described in Embodiment 1 will be described with reference to FIGS.

  First, as shown in FIG. 2, by applying an epitaxial growth method such as MOCVD (Metal Organic Chemical Vapor Deposition) method or MBE (Molecular Beam Epitaxy) method on the substrate 1a, a buffer layer 1b, a channel layer 1c, and a barrier. The layer 1d is epitaxially grown in this order.

  Next, on the semiconductor substrate 1, for example, a metal film such as Ti, Al, Nb, Hf, Zr, Sr, Ni, Ta, Au, Mo, and W, or a multilayer film of these metals is deposited or sputtered. The deposited film thus obtained is patterned by a lift-off method or the like. Thereafter, as shown in FIG. 3, the patterned deposited film is alloyed using an RTA (Rapid Thermal Annealing) method or the like to form source / drain electrodes 2a and 2b having ohmic characteristics.

  Then, as shown in FIG. 4, a metal multilayer film is deposited on the semiconductor substrate 1 between the source / drain electrodes 2a, 2b by using an evaporation method or a sputtering method, and the deposited film obtained thereby. Is patterned by a lift-off method or the like. By this step, the gate electrode body 3 in which the first and second gate electrodes 3a and 3b are stacked in this order is formed. In the second embodiment, the metal multilayer film is deposited so that the second gate electrode 3b is made of a metal having higher solubility in acid than the metal of the source / drain electrodes 2a and 2b. Since the lower surface of the first gate electrode 3a serves as a ground region with the surface of the semiconductor substrate 1, it is preferable to pattern the first gate electrode 3a so that the gate length is as short as possible.

Thereafter, as shown in FIG. 5, on the source / drain electrodes 2a and 2b, the semiconductor substrate 1, and the gate electrode body 3 (second gate electrode 3b), for example, SiN _x , SiO _x , SiO _x N _y , Al _{x N y, AlO x N y} , the surface protective film such as _HfO x _{N y,} is formed as a dielectric film 4. In the second embodiment, for example, a Cat-CVD (Catalytic Chemical Vapor Deposition) method having anisotropy in film formation or an ECR (Electron Cyclotron Resonance) sputtering method is used in a direction perpendicular to the surface of the semiconductor substrate 1. A dielectric film 4 is formed. According to such a manufacturing method, since it is possible to suppress the formation of the dielectric film 4 on the side surface of the second gate electrode 3b, it is possible to reliably remove the dielectric film 4 in the next step.

Next, as shown in FIG. 6, the dielectric film 4 on the gate electrode body 3 is removed. In the second embodiment, the gate electrode is formed by wet etching in which the second gate electrode 3b is dissolved in an acid such as HCl, HNO ₃ , H ₂ SO ₄ , aqua regia (HNO ₃ : HCl = 1: 3), for example. The dielectric film 4 on the body 3 is removed together with the second gate electrode 3b. According to such a manufacturing method, it is possible to suppress damage to the surface of the semiconductor substrate 1 and the other dielectric film 4 when the dielectric film 4 on the gate electrode body 3 is removed.

  Then, on the first gate electrode 3a and the dielectric film 4, for example, a metal film such as Ti, Al, Nb, Hf, Zr, Sr, Ni, Ta, Au, Mo, W, Pt, or a multilayer film of these metals Is deposited by vapor deposition or sputtering, and the resulting deposited film is patterned by a lift-off method or the like. By this step, the electric field relaxation electrode 5 protruding from the first gate electrode 3a is formed on the dielectric film 4 around the first gate electrode 3a. Thus, the heterojunction field effect transistor shown in FIG. 1 is completed.

  According to the heterojunction field effect transistor manufacturing method according to the second embodiment as described above, the heterojunction field effect transistor having the configuration and effects described in the first embodiment can be formed. In addition, since the exposure of the surface of the semiconductor substrate 1 is suppressed when the dielectric film 4 on the gate electrode body 3 is removed, damage to the surface of the semiconductor substrate 1 can be suppressed. Therefore, a heterojunction field effect transistor in which deterioration of characteristics such as gate leakage current and current collapse is suppressed can be realized.

  In the second embodiment, the second gate electrode 3b, which is more soluble in acid than the source / drain electrodes 2a and 2b, is dissolved in acid, so that the dielectric film 4 on the gate electrode body 3 is formed in the second state. It is removed together with the gate electrode 3b. Therefore, the dielectric film 4 on the gate electrode body 3 can be removed while leaving the desired dielectric film 4.

In addition, as a metal candidate for the second gate electrode 3b, when HF is used for the above-mentioned acid, for example, Nb, Ta, Ti, Zr, etc., which are easily soluble in this, are used, and HCl is used for the above-mentioned acid. If, for example, Cr, Fe, Ni or the like that is easily soluble in this is used and HNO ₃ is used for the above-mentioned acid, for example, Ag, Hg, Se, Zn or the like that is easily soluble in this is used, and H ₂ is used for the above-mentioned acid. In the case of using SO _4, for example, Be, As, Mo, Nb, Re, Sb and the like which are easily dissolved therein are used, and in the case where aqua regia is used as the above-mentioned acid, for example, Au, Mo and Pd which are easily soluble in this. , Pt, W, or the like may be used.

  In the above description, the second gate electrode 3b and the dielectric film 4 thereon are removed by dissolving the second gate electrode 3b in an acid. However, in the above description, alkali may be used instead of acid, and in this case, the same effect as described above can be obtained.

<Embodiment 3>
In the second embodiment, the second gate electrode 3b is removed during the manufacturing process of the heterojunction field effect transistor. On the other hand, in the third embodiment of the present invention, the second gate electrode 3b is not removed. That is, as shown in FIG. 7, in the third embodiment, the gate electrode body 3 includes a first gate electrode 3a and a second gate electrode 3b.

  FIG. 8 is a cross-sectional view showing a step of removing the dielectric film 4 on the gate electrode body 3 (step corresponding to FIG. 6) in the third embodiment. In the heterojunction field effect transistor according to the third embodiment, the same or similar components as those described in the first and second embodiments are denoted by the same reference numerals.

  In the third embodiment, substantially the same manufacturing process as in the second embodiment is performed. However, in the same process as that shown in FIGS. 3 and 4, in the third embodiment, the second gate electrode 3b (uppermost surface) is more than the metal of the source / drain electrodes 2a and 2b (uppermost surface). It is comprised from the metal with low adhesiveness with the dielectric film 4. For example, the uppermost surfaces of the source / drain electrodes 2a and 2b are made of Al, and the uppermost surface of the second gate electrode 3b is made of Au.

  Further, in the process shown in FIG. 8 corresponding to the process shown in FIG. 6, in the third embodiment, the dielectric film 4 on the gate electrode body 3 is peeled off from the second gate electrode 3b using ultrasonic waves. Then, the dielectric film 4 on the gate electrode body 3 is removed.

  According to the heterojunction field effect transistor manufacturing method according to the third embodiment as described above, when the dielectric film 4 on the gate electrode body 3 is removed, the surface of the semiconductor substrate 1 is removed as in the second embodiment. Since exposure is suppressed, damage to the surface of the semiconductor substrate 1 can be suppressed. Therefore, a heterojunction field effect transistor in which deterioration of characteristics such as gate leakage current and current collapse is suppressed can be realized.

  In the third embodiment, the second gate electrode 3b having lower adhesion to the dielectric film 4 than the source / drain electrodes 2a and 2b is formed, and the dielectric film 4 on the gate electrode body 3 is formed using ultrasonic waves. Remove and remove. Therefore, the dielectric film 4 on the gate electrode body 3 can be removed while leaving the desired dielectric film 4.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2a source electrode, 2b drain electrode, 3 gate electrode body, 3a 1st gate electrode, 3b 2nd gate electrode, 4 dielectric film, 5 electric field relaxation electrode

Claims (8)

(A) forming a source / drain electrode on a semiconductor substrate including a nitride semiconductor;
(B) forming a gate electrode body in which the first and second gate electrodes are stacked in this order on the semiconductor substrate between the source / drain electrodes;
(C) forming a dielectric film on the source / drain electrodes, the semiconductor substrate and the gate electrode body;
(D) removing the dielectric film on the gate electrode body;
(E) forming a field relaxation electrode projecting laterally from the first gate electrode on the dielectric film around the first gate electrode; and a method of manufacturing a heterojunction field effect transistor. A method of manufacturing a heterojunction field effect transistor according to claim 1,
The method of manufacturing a heterojunction field effect transistor, wherein the metal of the second gate electrode has higher solubility in acid or alkali than the metal of the source / drain electrode. A method of manufacturing a heterojunction field effect transistor according to claim 1,
The method of manufacturing a heterojunction field effect transistor, wherein the metal of the second gate electrode has lower adhesion to the dielectric film than the metal of the source / drain electrode. A method of manufacturing a heterojunction field effect transistor according to any one of claims 1 to 3,
A method of manufacturing a heterojunction field effect transistor, wherein the dielectric film is deposited using a Cat-CVD (Catalytic Chemical Vapor Deposition) method in the step (c). A method of manufacturing a heterojunction field effect transistor according to any one of claims 1 to 3,
A method of manufacturing a heterojunction field effect transistor, wherein in the step (c), the dielectric film is deposited using an ECR (Electron Cyclotron Resonance) sputtering method. A method of manufacturing a heterojunction field effect transistor according to claim 1 or claim 2,
In the step (d), the dielectric film on the gate electrode body and the second gate electrode are removed together with the second gate electrode by dissolving the second gate electrode in an acid or an alkali. A method of manufacturing a heterojunction field effect transistor according to claim 1 or 3,
In the step (d), the dielectric film on the gate electrode body is removed from the second gate electrode by peeling off the dielectric film on the gate electrode body using ultrasonic waves. A method for manufacturing a transistor. A heterojunction field effect transistor formed by the method of manufacturing a heterojunction field effect transistor according to any one of claims 1 to 7,
The field relaxation electrode is a heterojunction field effect transistor that protrudes only from the first gate electrode toward the drain electrode.

Images