JP2012174825A - Heterojunction field effect transistor and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide: a heterojunction field effect transistor (FET) having low resistance and capable of performing high-speed operation, without causing deterioration in withstand voltage characteristics and an increase in a gate leakage current; and a method for manufacturing the FET.SOLUTION: A method for manufacturing a heterojunction FET includes: (a) a step of preparing a channel layer 3 and a barrier layer 4 formed on the channel layer 3, as a nitride semiconductor layer; (b) a step of forming a ZnO film 9 on the nitride semiconductor layer as an impurity diffusion source; (c) a step of forming an oxide film 10 in a region other than a region where a drain electrode 6 and a source electrode 5 are to be formed, on the ZnO film 9; (d) a step of subjecting the nitride semiconductor layer to heat treatment so that Zn and O are selectively diffused from the ZnO film 9 into the channel layer 3 and the barrier layer 4 below a region where the oxide film 10 is not formed.

Description

  The present invention relates to a heterojunction field effect transistor made of a semiconductor containing nitride and a method for manufacturing the same.

  A heterojunction field effect transistor (hereinafter referred to as a “heterojunction FET (Field Effect Transistor)”) includes a channel layer that is an electron transit layer and a barrier layer that is an electron supply layer on a semi-insulating substrate. A drain electrode, a source electrode, and a gate electrode are provided on the layer. For example, the barrier layer is made of an AlGaN-based material and the channel layer is made of a GaN-based material (Non-Patent Document 1).

  In such a heterojunction FET, Patent Document 1 discloses a method of reducing resistance between an electrode and a barrier layer by forming a contact layer having a controlled band gap between the electrode and the barrier layer.

JP 2005-302916 A

Yasuhiro Okamoto, 5 others, "L-band high power AlGaN / GaN heterojunction FET on SiC substrate", IEICE Technical Report, The Institute of Electronics, Information and Communication Engineers, June 14, 2002, Volume 102, 118, pp.85-88

  As reported in Non-Patent Document 1, a conventional heterojunction FET has a non-doped barrier layer under a source / drain electrode. It is difficult to form source / drain electrodes having good ohmic characteristics, that is, low contact resistance, in a barrier layer having a low impurity concentration. However, when impurities are introduced into the barrier layer at a high concentration in order to obtain good ohmic characteristics, a high-concentration barrier layer also exists under the gate electrode, which causes deterioration of leakage current and breakdown voltage characteristics.

  As described above, in a conventional heterojunction FET, since a barrier layer having a constant impurity concentration exists under both the gate electrode and the source / drain electrodes, it is difficult to achieve both breakdown voltage characteristics and good ohmic characteristics. there were.

  Further, in Patent Document 1, a reduction in resistance is studied using a contact layer in which a band gap is controlled between the barrier layer and the ohmic electrode, and resistance reduction between the ohmic electrode and the barrier layer is possible. The resistance component between them cannot be reduced.

  Therefore, an object of the present invention is to provide a heterojunction FET that can operate at high speed with low resistance without causing deterioration in breakdown voltage characteristics and increase in gate leakage current, and a method for manufacturing the same.

  The heterojunction FET manufacturing method of the present invention includes (a) a step of preparing a channel layer and a barrier layer 4 formed on the channel layer as a nitride semiconductor layer, and (b) an impurity on the nitride semiconductor layer. A step of forming a ZnO film as a diffusion source, (c) a step of forming an oxide film in a region other than a region where a drain electrode and a source electrode are to be formed on the ZnO film, and (d) after the step (c), Heat-treating the nitride semiconductor layer, and selectively diffusing Zn and O from the ZnO film into the channel layer and the barrier layer below the region where the oxide film is not formed. .

  The heterojunction FET of the present invention includes a nitride semiconductor layer including a channel layer and a barrier layer on the channel layer, and a source electrode and a drain electrode formed on the nitride semiconductor layer, and the nitride The semiconductor layer includes a disordered region disordered from the barrier layer directly below the source electrode and the drain electrode to the channel layer, and at least one of O and Zn is introduced as an impurity into the disordered region. The

  In the method of manufacturing a heterojunction FET according to the present invention, the nitride semiconductor layer is subjected to a heat treatment, and a ZnO film and a ZnO film are selectively formed on a channel layer and a barrier layer below a region where no oxide film is formed. Therefore, the access resistance from the ohmic electrode to the channel can be reduced by reducing the band gap of the ohmic contact region and increasing the carrier concentration.

  Further, in the heterojunction FET of the present invention, the nitride semiconductor layer includes a disordered region disordered from the barrier layer immediately below the source electrode and the drain electrode to the channel layer, so that the band gap of the ohmic contact region is reduced, The access resistance from the ohmic electrode to the channel can be reduced. Furthermore, since O (oxygen), which is an n-type dopant, is introduced as an impurity in the disordered region, the carrier concentration increases and the access resistance from the ohmic electrode to the channel can be reduced.

It is sectional drawing which shows the structure of the heterojunction FET of this invention. FIG. 6 is a cross-sectional view showing a manufacturing process of the heterojunction FET of the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing process of the heterojunction FET of the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing process of the heterojunction FET of the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing process of the heterojunction FET of the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing process of the heterojunction FET of the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing process of the heterojunction FET of the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing process of the heterojunction FET of the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing process of the heterojunction FET of the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing process of the heterojunction FET of the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing process of the heterojunction FET of the first embodiment. It is a figure which shows the band gap and impurity concentration in the A-A 'cross section of FIG. It is a figure which shows the band gap and impurity concentration in the B-B 'cross section of FIG. It is a figure which shows the diffusion characteristic to Mg of GaN by heat processing. It is a figure which shows the diffusion characteristic to Zn of GaN and O by heat processing. It is a figure which shows the diffusion characteristic in the ZnO by heat processing. 7 is a cross-sectional view showing a manufacturing process of the heterojunction FET of Embodiment 2. FIG. 7 is a cross-sectional view showing a manufacturing process of the heterojunction FET of Embodiment 2. FIG. 7 is a cross-sectional view showing a manufacturing process of the heterojunction FET of Embodiment 2. FIG. 7 is a cross-sectional view showing a manufacturing process of the heterojunction FET of Embodiment 2. FIG.

(Embodiment 1)
<Configuration>
FIG. 1 is a cross-sectional view showing a heterojunction FET according to Embodiment 1 of the present invention. The heterojunction FET according to the first embodiment includes a buffer layer 2, a channel layer 3 as a carrier traveling layer, and a barrier layer as a carrier supply layer on a main surface of a substrate 1 made of sapphire, SiC, Si, GaN or the like. An epitaxial layer structure 4 is sequentially laminated. The barrier layer 4 forms a heterojunction with the channel layer 3.

The channel layer 3 is made of Al _x In _y Ga _1-xy N (0 ≦ x <1, 0 ≦ y <1, 0 ≦ x + y <1), and has a thickness (50 to 3000 nm) that allows electrons to flow. The impurity concentration does not matter.

The barrier layer 4 is made of Al _i In _j Ga _1-ij N (0 <i <1, 0 ≦ j <1, 0 <i + j ≦ 1), and has a larger band gap than the channel layer 3. As a combination of the channel layer 3 and the barrier layer 4, for example, GaN / AlGaN, AlInGaN / AlGaN, AlInGaN / AlInGaN, AlInGaN / AlInN, and the like are conceivable. Moreover, the barrier layer 4 should just be thickness (5-50 nm) of the grade which does not carry out a lattice relaxation. The impurity concentration of the barrier layer 4 is less than 1 × 10 ¹⁸ cm ⁻³ for the purpose of high breakdown voltage.

  Further, on the barrier layer 4, a source electrode 5 and a drain electrode 6 made of Ti / Al are formed as ohmic electrodes, and a gate electrode 7 made of Ni / Au is formed as a Schottky electrode.

  A disordered region 8 is formed in which impurities are thermally diffused from the barrier layer 4 below the source / drain electrodes 5 and 6 to the channel layer 3. In the disordered region 8, both Zn and O, or at least one of them is introduced as an impurity, and the impurity concentration is increased.

<Manufacturing process>
A manufacturing process of the heterojunction FET according to the first embodiment will be described with reference to FIGS. First, the buffer layer 2, the channel layer 3, and the barrier layer 4 are epitaxially grown in this order as nitride semiconductor layers on the main surface of the substrate 1 (FIG. 2). The substrate 1 is made of sapphire, SiC, Si, GaN or the like, and is laminated using, for example, MOCVD (Metal Organic Chemical Vapor Deposition) or MBE (Molecular Beam Epitaxy). .

The channel layer 3 is formed of Al _x In _y Ga _1-xy N (0 ≦ x <1, 0 ≦ y <1, 0 ≦ x + y <1). The channel layer 3 may be thick enough to allow electrons to flow (50 to 3000 nm), and the impurity concentration does not matter.

The barrier layer 4 formed as the carrier supply layer is formed of Al _i In _j Ga _1-ij N (0 <i <1, 0 ≦ j <1, 0 <i + j ≦ 1). The barrier layer 4 has a larger band gap than the channel layer 3. For example, the combination of the channel layer 3 and the barrier layer 4 may be GaN / AlGaN, AlInGaN / AlGaN, AlInGaN / AlInGaN, AlInGaN / AlInN, or the like. The thickness of the barrier layer 4 may be a thickness that does not relax the lattice (5 to 50 nm).

The impurity concentration of the barrier layer 4 is less than 1 × 10 ¹⁸ cm ⁻³ in order to achieve a high breakdown voltage. Here, the impurity is n-type. Note that even if a nitride semiconductor is intentionally not doped with impurities (non-doped), it becomes n-type when impurities enter the semiconductor from a growth furnace or atmospheric gas. Therefore, the present invention can be applied if the actual impurity concentration is less than 1 × 10 ¹⁸ cm ⁻³ even when the crystal growth is non-doped.

Next, a ZnO film 9 is formed as a solid phase diffusion source (impurity diffusion source) on the barrier layer 4, and an SiO ₂ film 10 is formed as a diffusion preventing film for selectively diffusing Zn and O from the ZnO film 9. It is formed on the ZnO film 9 (FIG. 3). The ZnO film 9 is formed by vapor deposition or sputtering, and the film thickness is 50 to 200 nm. The SiO ₂ film 10 is formed by vapor deposition or sputtering, and the film thickness is 50 to 200 nm.

Further, a resist pattern 11 is formed on the SiO ₂ film 10 using photolithography (FIG. 4). The resist pattern 11 is formed at the same position as the resist pattern for forming the source / drain electrodes 5 and 6. Alternatively, in consideration of superposition, the opening of the resist pattern 11 may be made larger or smaller than a region where the source / drain electrodes 5 and 6 are formed in a later step.

By etching the SiO ₂ film 10 using this resist pattern 11, the SiO ₂ film 10 is formed in a region other than the region where the source electrode 5 and the drain electrode 6 are to be formed in a later step on the ZnO film 9 (FIG. 5). .

In this state, selective impurity diffusion by heat treatment is performed on the nitride semiconductor layer, thereby disordering the regions of the barrier layer 4 and the channel layer 3 located below the opening of the SiO ₂ film 10. When the semiconductors are mixed, ideally, they have an average composition of both, resulting in a disordered region (composition change region) 8 with a changed band gap (FIG. 6). In this selective impurity diffusion, since the impurity (Zn, O) diffuses into the disordered region 8 from the portion of the ZnO film 9 exposed from the opening of the SiO ₂ film 10 as will be described later, the impurity concentration of the disordered region 8 increases. To do.

According to the method of manufacturing the heterojunction FET of the present embodiment, since the heat treatment is performed with the ZnO film 9 and the SiO ₂ film 10 formed on the barrier layer 4, the surface of the barrier layer 4 is made of resist or the like before the heat treatment. The surface of the barrier layer 4 is prevented from being contaminated by a residue such as an organic material without being exposed to the organic material.

In order to form the disordered region 8, it is necessary to diffuse impurities at a concentration of 5 × 10 ¹⁸ cm ⁻³ or more.

  In this embodiment, the ZnO film 9 is used as a solid phase diffusion source. However, a material containing an n-type dopant such as O is also used for the solid phase diffusion source or formed on the solid phase diffusion source. By performing the heat treatment, the n-type dopant diffuses at the same time as the band gap changes due to the disorder due to thermal diffusion. Therefore, in the disordered region 8, the band gap is reduced and a high-concentration n-type region is formed. It is possible to obtain a good ohmic characteristic.

The heat treatment may be performed at a temperature of about 800 ° C. to 1000 ° C. in an atmosphere containing oxygen, for example. The treatment at 800 ° C. or lower does not promote the diffusion of impurity elements, and the high temperature treatment at 1000 ° C. or higher deteriorates the crystallinity of the epitaxial layer. By performing heat treatment at 800 ° C. or more and 1000 ° C. or less, thermal diffusion is performed without adversely affecting the epitaxial layer such as deterioration of crystallinity, and the crystallinity of the disordered region 8 is maintained. As the gas containing oxygen, at least one of O ₂ , O ₃ , CO, CO ₂ , NO, N ₂ O, and NO ₂ or a mixed gas thereof, or a mixed gas of these gases and an inert gas is used. Can be processed. The oxygen content may be about 20% or more. By performing the heat treatment in an atmosphere containing oxygen, the reaction between the diffusion source and the nitride semiconductor is promoted on the semiconductor surface, and the impurity diffuses even in the low-temperature treatment, so that a region with a changed band gap can be formed.

  The treatment time may be set so as to obtain a desired diffusion depth, and the disordered region 8 is locally formed over a part of the barrier layer 4 and the channel layer 3. Specifically, it may be 100 nm or less.

  After the heat treatment, the solid phase diffusion source 9 and the diffusion preventing film 10 are removed (FIG. 7).

  Next, a resist layer is formed on the surface of the barrier layer 4, and a resist pattern 11 is formed in a portion where no ohmic contact is formed by photolithography (FIG. 8). At this time, an opening of the resist pattern 11 is provided so that the disordered region 8 is exposed. The opening may be formed so as to completely overlap the disordered region 8, or may be formed larger or smaller than the disordered region 8.

  Next, the source electrode 5 and the drain electrode 6 are formed using the resist pattern 11 (FIG. 9). An electrode material is deposited by vapor deposition or sputtering, and the source electrode 5 and drain electrode 6 are selectively formed in the electrode formation region by lift-off or the like. As a material for these electrodes, any material can be used as long as it can provide ohmic characteristics with the barrier layer. For example, there are a laminated film of Ti and Al, a laminated film of Ti, Al, Pt, and Au.

  Further, a resist pattern 12 having an opening in a region for forming the gate electrode 7 is formed by photolithography (FIG. 10), and the gate electrode 7 is formed (FIG. 11). An electrode material is formed by vapor deposition or sputtering, and the gate electrode 7 is selectively formed in the electrode formation region by lift-off or the like. The material of the gate electrode 7 may be any metal that forms a Schottky junction with the n-type nitride semiconductor, such as a metal having a high work function such as Pt or Ni, silicide, or WN (tungsten nitride). Metal nitride may also be used.

  By such a method, the heterojunction FET of the present embodiment is formed. Although not particularly illustrated, the element isolation region is formed by ion implantation in the same manner as the conventional transistor manufacturing method.

<Disordered area>
FIG. 12A shows a band gap distribution in the gate length direction in the section AA ′ in FIG. In the disordered region 8 in which the thermal diffusion is selectively performed, the semiconductors of the barrier layer 4 and the channel layer 3 are mixed to form a semiconductor region having an average composition of both. As a result, when viewed in the gate length direction cross section of the heterojunction FET, the band gap of the barrier layer 4 becomes smaller in the disordered region 8 below the ohmic electrode, so that the vicinity of the gate electrode 7 is reduced as shown in FIG. The distribution is as if sandwiched between regions with a small band gap. At this time, the channel layer 3 has a distribution in which the vicinity of the gate electrode 7 is sandwiched between regions having a large band gap, contrary to the barrier layer 4.

  FIG. 12B shows the impurity concentration distribution in the gate length direction in the AA ′ cross section of FIG. In the disordered region 8, the impurity concentration is high because impurities are introduced by selective thermal diffusion. Therefore, both the barrier layer 4 and the channel layer 3 have a distribution in which the impurity concentration is high in the disordered region 8 and the gate electrode 7 is sandwiched between regions having a high impurity concentration, as shown in FIG.

  FIG. 13A shows the band gap distribution in the BB ′ section of FIG. 1, and FIG. 13B shows the impurity distribution in the BB ′ section of FIG. 1. In the disordered region 8, since the semiconductors of the barrier layer 4 and the channel layer 3 are mixed, ideally, a semiconductor region having an average composition of both is formed. As shown in FIG. With an intermediate band gap. Further, as shown in FIG. 13B, since impurities are diffused from the ZnO film 9 in the disordered region 8, the impurity concentration is higher than the original value. The depth distribution of the disordered region 8 is determined from the heat treatment conditions, but reaches at least a part of the channel layer 3. This depth corresponds to the composition change of the barrier layer 4 and the channel layer 3.

  The possible band gap range of the disordered region 8 depends on the combination of semiconductor materials, but is smaller than the band gap of the material used for the barrier layer 4 and larger than the band gap of the material used for the channel layer 3.

  When a material containing In is used for at least one of the barrier layer 4 and the channel layer 3, mutual diffusion of constituent elements of both layers is promoted by In during heat treatment. For this reason, it is possible to obtain a desired diffusion depth while suppressing deterioration of crystallinity even by heat treatment at a low temperature for a short time. Furthermore, when interdiffusion is performed using a layer containing In, the lower limit value of the change amount (width) of the band gap can be changed to a smaller value. Therefore, the band gap approaches the band gap of InN of 0.8 eV due to an increase in the proportion of In contained in the interdiffused layers, and the band gap is greatly reduced compared to the case where In is not included (GaN, 3.4 eV). be able to. In particular, when a material having a large In composition is used for the channel layer, the effect of reducing the band gap is increased.

  14 to 16 show element diffusion profiles (SIMS analysis) by heat treatment in an atmosphere containing oxygen. The vertical axis and horizontal axis are each an arbitrary scale. FIG. 14 relates to the heat treatment condition dependency of Mg element, and no element diffusion is observed at a heat treatment temperature of 700 ° C. However, it can be seen that the elements are diffused by setting the heat treatment temperature to 800 ° C. It can also be seen that the diffusion depth is increased by increasing the processing time from 60 seconds to 180 seconds.

FIGS. 15A and 15B show the diffusion profiles of elements when heat treatment is performed at 850 ° C. in an oxygen-containing atmosphere for the case where the SiO ₂ film 10 is formed on the ZnO film 9 and the case where the SiO ₂ film 10 is not formed. Is shown. 15A shows a diffusion profile of Zn into GaN (barrier layer 4), and FIG. 15B shows a diffusion profile of O into GaN (barrier layer 4). Since any element does not form the SiO ₂ film 10, diffusion into GaN is promoted. Therefore, by selectively forming the SiO ₂ film 10, impurities can be selectively diffused. I understand that.

FIG. 16 shows a Ga diffusion profile when a heat treatment at 850 ° C. is performed in an atmosphere containing oxygen for each of the cases where the SiO ₂ film 10 is formed on the ZnO film 9 and the case where the SiO ₂ film 10 is not formed. From FIG. 16, when the SiO ₂ film 10 is not formed on the ZnO film 9, it is understood that the Ga absorption from the surface of the GaN layer (barrier layer 4) to the ZnO film 9 is promoted as compared with the case where it is formed. I understand.

<Effect>
The manufacturing process of the heterojunction FET of the present invention has the following effects. That is, the heterojunction FET of the present invention comprises (a) a step of preparing the channel layer 3 and the barrier layer 4 formed on the channel layer 3 as a nitride semiconductor layer, and (b) on the nitride semiconductor layer. A step of forming a ZnO film 9 as an impurity diffusion source; and (c) a step of forming an oxide film (SiO ₂ film 10) in a region other than the region where the drain electrode 6 and the source electrode 5 are to be formed on the ZnO film 9; (D) After the step (c), the nitride semiconductor layer is subjected to a heat treatment, and the channel layer 3 and the barrier layer 4 below the region where the SiO ₂ film 10 is not formed are selectively formed. And a step of diffusing Zn and O from the ZnO film 9. By forming the disordered region 8 under the drain electrode 6 and the source electrode 5 to reduce the band gap, the access resistance from the ohmic electrode to the channel can be reduced. As a result, there is an unprecedented remarkable effect that high-frequency operation is possible while maintaining the withstand voltage. Further, by simultaneously diffusing the n-type dopant during thermal diffusion, the carrier concentration in the disordered region 8 can be increased, and the access resistance can be further reduced.

  In addition, by performing heat treatment at a processing temperature of 800 ° C. or higher and 1000 ° C. or lower in the step (d), thermal diffusion is performed without adversely affecting the nitride semiconductor layer, such as deterioration of crystallinity. Crystallinity is maintained.

  In addition, by performing heat treatment in an atmosphere containing oxygen in the step (d), the reaction between the diffusion source and the barrier layer 4 is promoted on the semiconductor surface, and impurities are diffused even at low temperature treatment to form a region where the band gap is changed. can do.

  Further, in the step (d), it is possible to reduce the access resistance from the ohmic electrode to the channel by forming the local disordered region 8 from the barrier layer 4 to a part of the channel layer 3.

  The heterojunction FET of the present invention has the following effects. That is, the heterojunction FET of the present invention includes a nitride semiconductor layer including a channel layer 3 and a barrier layer 4 on the channel layer 3, and a source electrode 5 and a drain electrode 6 formed on the nitride semiconductor layer. The nitride semiconductor layer includes a disordered region 8 disordered from the barrier layer 4 immediately below the source electrode 5 and the drain electrode 6 to the channel layer 3, so that the access resistance from the ohmic electrode to the channel is reduced. As a result, there is an unprecedented remarkable effect that high-frequency operation is possible while maintaining the withstand voltage. Further, since the n-type dopant O is introduced as an impurity in the disordered region 8, the carrier concentration becomes high and the access resistance is further reduced.

  Although not particularly described in the present embodiment, this structure may be used even if a structure using a cap layer on the surface of the barrier layer 4, a recess gate structure, a structure in which an intermediate layer is provided between the channel layer and the barrier layer, or the like is used. The effect of the invention is exerted, and the effect of improving the characteristics of the heterojunction FET is exhibited.

In this embodiment, the SiO ₂ film 10 is used as the diffusion preventing film. However, the same effect can be obtained by using a material having a composition between SiO ₂ and SiN. Further, by changing the composition of the diffusion preventing film, the film stress changes, and the diffusion depth of the element can be controlled. Further, the distribution of the film thickness of the diffusion preventive film also distributes the film stress, and has the same effect. Furthermore, the same effect can be obtained even by a combination of two or more kinds of films.

(Embodiment 2)
17 to 20 are cross-sectional views illustrating the manufacturing steps of the heterojunction FET according to the second embodiment. The steps up to the formation of the ZnO film 9 are the same as the steps of the first embodiment described with reference to FIGS. 2 and 3, and the subsequent steps will be described.

  As shown in FIG. 17, after forming the ZnO film 9 on the barrier layer 4, a resist pattern 12 is formed for diffusing impurities under the source / drain electrode formation region (source / drain region). The resist pattern 12 is a pattern opposite to the resist pattern for forming the source / drain electrodes. The opening size of the resist pattern 12 may be set larger or smaller than the region where the source / drain electrodes are formed in consideration of the overlapping.

Next, using the resist pattern 12, an SiO ₂ film 10 serving as a diffusion preventing film is selectively formed outside the source / drain regions. After the SiO ₂ film 10 is deposited on the entire surface including the resist pattern 12, the unnecessary SiO ₂ film 10 and the resist pattern 12 are removed (FIG. 19). Thus, by selectively forming the SiO ₂ film 10 by lift-off, it becomes possible to suppress the formation of damage more than necessary with respect to the barrier layer 4.

After that, by performing heat treatment using the ZnO film 9 formed on the barrier layer 4 and the SiO ₂ film 10 formed in a region other than the source / drain regions, impurities are diffused from the ZnO film 9 into the source / drain regions. The formation region 8 is formed (FIG. 20).

  Thereafter, the heterojunction FET of the present invention is formed in the same manner as in the first embodiment described with reference to FIGS.

<Effect>
The method for manufacturing a heterojunction FET according to the present embodiment includes a step of forming the SiO ₂ film 10 by a lift-off method. By selectively forming the SiO2 film 10 in addition to the source / drain regions by the lift-off method, the disordered region 8 is formed only under the source / drain regions to reduce the band gap, so that from the ohmic electrode to the channel. It is possible to reduce the access resistance.

1 substrate, 2 buffer layer, 3 channel layer, 4 barrier layer, 5 source electrode, 6 drain electrode, 7 gate electrode, 8 disordered region, 9 ZnO film, 10 SiO ₂ film, 11, 12 resist pattern.

Claims (6)

(A) preparing a channel layer and a barrier layer formed on the channel layer as a nitride semiconductor layer;
(B) forming a ZnO film as an impurity diffusion source on the nitride semiconductor layer;
(C) forming an oxide film in a region other than the region where the drain electrode and the source electrode are to be formed on the ZnO film;
(D) After the step (c), the nitride semiconductor layer is subjected to heat treatment, and the ZnO film is selectively formed on the channel layer and the barrier layer below the region where the oxide film is not formed. Diffusing Zn and O from
A method of manufacturing a heterojunction field effect transistor. The step (d) is a step of performing heat treatment at a processing temperature of 800 ° C. or higher and 1000 ° C. or lower.
A method of manufacturing a heterojunction field effect transistor according to claim 1. The step (d) is a step of performing a heat treatment in an atmosphere containing oxygen.
A method for manufacturing a heterojunction field effect transistor according to claim 1.   4. The manufacture of a heterojunction field effect transistor according to claim 1, wherein the step (d) is a step of forming a local disordered region from the barrier layer to a part of the channel layer. Method. The step (c) is a step of forming the oxide film by a lift-off method.
The manufacturing method of the heterojunction field effect transistor in any one of Claims 1-4. A nitride semiconductor layer comprising a channel layer and a barrier layer on the channel layer;
A source electrode and a drain electrode formed on the nitride semiconductor layer,
The nitride semiconductor layer includes a disordered region disordered from the barrier layer directly below the source electrode and the drain electrode to the channel layer,
In the disordered region, at least one of O and Zn is introduced as an impurity,
Heterojunction field effect transistor.

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