JP2014099044A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of performing a stable operation when the power is turned on.SOLUTION: A semiconductor device of an embodiment includes: a clock buffer circuit 11 that generates an internal clock by receiving first and second clocks that have a complementary relationship with each other; and a clock detection circuit 12 that detects that the first and second clocks are at an identical level for a predetermined period of time. The clock buffer circuit 11 is constituted so as to operate with a first power supply VDDQ, and the clock detection circuit 12 is constituted so as to operate with a second power supply VDD.

Description

  The present invention relates to a semiconductor device, for example, a semiconductor device that operates with a clock having a complementary relationship.

  In recent years, with the increase in operating frequency of semiconductor devices, semiconductor devices operating with a clock having a complementary relationship (hereinafter also referred to as a complementary clock) have become widespread. By using a complementary clock, a high-frequency clock can be transmitted and the influence of noise can be reduced.

  Patent Document 1 discloses a technique related to a receiving apparatus capable of detecting an abnormality of a signal line in an LVDS receiver in data transmission using a low amplitude differential signal (LVDS) system. . Patent Document 2 discloses a technique for finding an abnormal part in real time when an abnormality occurs in a differential signal transmission line, and thereby quickly recovering from a system down caused by the abnormality of the transmission line. ing. Patent Document 3 discloses a technique for detecting disconnection of a transmission line in a transmission system using a balanced transmission line.

JP 2010-213246 A Japanese Patent Laid-Open No. 7-210410 JP-A-1-258512

  As described in the background art, some semiconductor devices operate with a complementary clock. In semiconductor devices that operate with a complementary clock, the complementary clock may not rise at the time of power-on, and both may be at the same level. In such a case, there is a problem that the operation of the semiconductor device becomes unstable.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  A semiconductor device according to an embodiment includes a clock buffer circuit that receives first and second clocks having a complementary relationship and generates an internal clock, and the first and second clocks are at the same level for a predetermined time. And a clock detection circuit for detecting a certain thing. The clock buffer circuit operates with a first power supply, and the clock detection circuit operates with a second power supply.

  According to the embodiment, it is possible to provide a semiconductor device capable of realizing a stable operation when power is turned on.

1 is a block diagram showing a semiconductor device according to a first embodiment; It is a circuit diagram which shows an example of a clock buffer circuit. It is a circuit diagram which shows an example of a clock comparison circuit. It is a truth table of a clock comparison circuit. It is a circuit diagram which shows an example of a filter circuit. 3 is a timing chart for explaining the operation of the semiconductor device according to the first embodiment; 1 is a block diagram for explaining a configuration example of a semiconductor device according to a first embodiment; 1 is a block diagram showing an example when a semiconductor device according to a first embodiment is applied to a memory device; 1 is a block diagram showing an example when a semiconductor device according to a first embodiment is applied to a memory device; It is a block diagram which shows the memory device concerning a comparative example. 6 is a timing chart for explaining the operation of the memory device according to the comparative example. 6 is a timing chart for explaining the operation of the memory device according to the comparative example. FIG. 6 is a block diagram showing a semiconductor device according to a second embodiment; It is a circuit diagram which shows an example of a clock buffer circuit and a level shift circuit. FIG. 6 is a block diagram showing a semiconductor device according to a third embodiment; FIG. 9 is a block diagram illustrating an example of a case where a semiconductor device according to a third embodiment is applied to a memory device. 6 is a timing chart for explaining the operation of the semiconductor device according to the third embodiment; FIG. 6 is a block diagram showing a semiconductor device according to a fourth embodiment; FIG. 6 is a block diagram showing an example of a semiconductor device according to a fourth embodiment applied to a memory device.

<Embodiment 1>
The first embodiment will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a semiconductor device according to the present embodiment. As shown in FIG. 1, the semiconductor device 1 according to the present embodiment includes a clock buffer circuit 11 and a clock detection circuit 12. The clock detection circuit 12 includes a clock comparison circuit 13 and a filter circuit 14. The clock buffer circuit 11 operates with the input / output power supply VDDQ (first power supply), and the clock detection circuit 12 operates with the internal power supply VDD (second power supply).

  The clock buffer circuit 11 receives the complementary clocks CK and CK # (first and second clocks) and generates an internal clock CLK_1. FIG. 2 is a circuit diagram showing an example of the clock buffer circuit 11. As shown in FIG. 2, the clock buffer circuit 11 includes PMOS transistors MP1 and MP2, NMOS transistors MN1 and MN2, and an inverter INV1.

  The source of the PMOS transistor MP1 is connected to the power supply VDDQ, and the gate and drain are connected to the node A. The source of the PMOS transistor MP2 is connected to the power supply VDDQ, the gate is connected to the node A, and the drain is connected to the node B. The drain of the NMOS transistor MN1 is connected to the node A, and the clock CK # is supplied to the gate. The source of the NMOS transistor MN1 is connected to a lower power supply (for example, ground potential). The drain of the NMOS transistor MN2 is connected to the node B, the clock CK is supplied to the gate, and the source is connected to the lower power supply (ground potential). A power supply VDDQ is supplied to the inverter INV1. The input of the inverter INV1 is connected to the node B.

  For example, when the high-level clock CK # and the low-level clock CK are supplied as the complementary clocks CK # and CK to the clock buffer circuit 11, the NMOS transistor MN1 is turned on and the NMOS transistor MN2 is turned off. When the NMOS transistor MN1 is turned on, the gates of the PMOS transistors MP1 and MP2 are grounded and become low level. As a result, the PMOS transistors MP1 and MP2 are turned on. Since the PMOS transistor MP2 is on and the NMOS transistor MN2 is off, the node B is at a high level. Therefore, the inverter INV1 outputs a low level signal as the internal clock CLK_1.

  Conversely, when the low-level clock CK # and the high-level clock CK are supplied to the clock buffer circuit 11 as the complementary clocks CK # and CK, the NMOS transistor MN1 is turned off and the NMOS transistor MN2 is turned on. When the NMOS transistor MN1 is turned off, the gates of the PMOS transistors MP1 and MP2 become high level. As a result, the PMOS transistors MP1 and MP2 are turned off. Since the PMOS transistor MP2 is off and the NMOS transistor MN2 is on, the node B is at the ground potential (low level). Therefore, the inverter INV1 outputs a high level signal as the internal clock CLK_1.

  When the complementary clocks CK # and CK are both at the low level, the NMOS transistors MN1 and MN2 are both turned off, and the node B is in an indefinite state (intermediate level). For this reason, the input of the inverter INV1 becomes unstable, and the inverter INV1 outputs the internal clock CLK_1 that changes irregularly.

  Further, when the complementary clocks CK # and CK are both at the high level, the NMOS transistor MN1 is turned on. As a result, the node A becomes low level, and the PMOS transistors MP1 and MP2 are turned on. However, when the complementary clocks CK # and CK are both at the high level, the NMOS transistor MN2 is also in the on state, and thus becomes indefinite (intermediate level). For this reason, the input of the inverter INV1 becomes unstable, and the inverter INV1 outputs the internal clock CLK_1 that changes irregularly.

  The clock detection circuit 12 is a circuit that detects that the complementary clocks CK # and CK are at the same level for a predetermined time. The clock detection circuit 12 includes a clock comparison circuit 13 that compares the complementary clocks CK # and CK, and a filter circuit 14 that detects that the output OUT_C of the clock comparison circuit 13 does not change for a predetermined time.

  FIG. 3 is a circuit diagram illustrating an example of the clock comparison circuit 13. As shown in FIG. 3, the clock comparison circuit 13 includes a reference potential generation circuit 21, a CK # detection circuit 22, and a CK detection circuit 23. The reference potential generation circuit 21 includes resistors R11 and R12 connected in series between the power supply VDD and the ground potential. A voltage VRQ divided by the resistors R11 and R12 is output to a node to which the resistors R11 and R12 are connected. For example, the set values of the resistors R11 and R12 are preferably set so that VRQ = ½ × VDDQ. The voltage VRQ generated by the reference potential generation circuit 21 is supplied to the CK # detection circuit 22 and the CK detection circuit 23.

  The CK # detection circuit 22 is a circuit for detecting the clock CK #. The CK # detection circuit 22 compares the voltage VRQ generated by the reference potential generation circuit 21 with the voltage of the clock CK #. When the voltage of the clock CK # is lower than the voltage VRQ, the output of the CK # detection circuit 22 A low level signal is output as OUT_A. On the other hand, when the voltage of the clock CK # is higher than the voltage VRQ, a high level signal is output as the output OUT_A.

  The CK # detection circuit 22 includes PMOS transistors MP11 and MP12, NMOS transistors MN11 and MN12, and an inverter INV11. The source of the PMOS transistor MP11 is connected to the power supply VDD, and the gate and drain are connected to the node C. The source of the PMOS transistor MP12 is connected to the power supply VDD, the gate is connected to the node C, and the drain is connected to the node D. The drain of the NMOS transistor MN11 is connected to the node C, the voltage VRQ generated by the reference potential generation circuit 21 is supplied to the gate, and the source is grounded. The drain of the NMOS transistor MN12 is connected to the node D, the clock CK # is supplied to the gate, and the source is grounded. A power supply VDD is supplied to the inverter INV11. The input of the inverter INV11 is connected to the node D.

  A voltage VRQ is supplied to the gate of the NMOS transistor MN11. Therefore, the NMOS transistor MN11 is in an on state at a level corresponding to the voltage VRQ. That is, the NMOS transistor MN11 passes a current corresponding to the voltage VRQ from the node C to the ground power supply. The PMOS transistors MP11 and MP12 are turned on at a level corresponding to the potential of the node C. That is, the transistor is turned on at a level corresponding to the amount of current flowing through the NMOS transistor MN11. The PMOS transistor MP12 supplies a current to the node D. In other words, the PMOS transistor MP12 supplies a current corresponding to the voltage VRQ to the node D.

  The NMOS transistor MN12 is turned on or off depending on the voltage level of the clock CK #. When the voltage of the clock CK # is lower than the voltage VRQ, since the amount of current flowing through the NMOS transistor MN12 is smaller than the amount of current flowing through the PMOS transistor MP12, the node D becomes high level. In this case, a low level signal is output as the output OUT_A of the inverter INV11. Further, when the voltage of the clock CK # is higher than the voltage VRQ, the amount of current flowing through the NMOS transistor MN12 is larger than the amount of current flowing through the PMOS transistor MP12, so that the node D becomes low level. In this case, a high level signal is output as the output OUT_A of the inverter INV11.

  FIG. 4 is a truth table of the clock comparison circuit 13. As shown in FIG. 4, when the clock CK # is at a low level (here, when the voltage is lower than the voltage VRQ), the node D is at a high level and the output OUT_A is at a low level. When the clock CK # is at a high level (here, when the voltage is higher than the voltage VRQ), the node D is at a low level and the output OUT_A is at a high level.

  The CK detection circuit 23 is a circuit for detecting the clock CK. The CK detection circuit 23 compares the voltage VRQ generated by the reference potential generation circuit 21 with the voltage of the clock CK. When the voltage of the clock CK is lower than the voltage VRQ, the CK detection circuit 23 outputs a low level as the output OUT_B of the CK detection circuit 23. Output a signal. On the other hand, when the voltage of the clock CK is higher than the voltage VRQ, a high level signal is output as the output OUT_B.

  The CK detection circuit 23 includes PMOS transistors MP13 and MP14, NMOS transistors MN13 and MN14, and an inverter INV12. Note that the configuration and operation of the CK detection circuit 23 are the same as the configuration and operation of the CK # detection circuit 22, and therefore a duplicate description is omitted.

  The output OUT_A of the CK # detection circuit 22 and the output OUT_B of the CK detection circuit 23 are supplied to the exclusive OR circuit EOR11. The exclusive OR circuit EOR11 calculates the exclusive OR of the output OUT_A and the output OUT_B, and outputs the calculation result as the output OUT_C of the clock comparison circuit 13. Further, the power source VDD is supplied to the exclusive OR circuit EOR11.

  As shown in FIG. 4, when both the output OUT_A (clock CK #) and the output OUT_B (clock CK) are at low level, the exclusive OR circuit EOR11 outputs a low level signal as the output OUT_C of the clock comparison circuit 13. . When the output OUT_A (clock CK #) is at a low level and the output OUT_B (clock CK) is at a high level, the exclusive OR circuit EOR11 outputs a high level signal as the output OUT_C of the clock comparison circuit 13. When the output OUT_A (clock CK #) is at a high level and the output OUT_B (clock CK) is at a low level, the exclusive OR circuit EOR11 outputs a high level signal as the output OUT_C of the clock comparison circuit 13. When both the output OUT_A (clock CK #) and the output OUT_B (clock CK) are at a high level, the exclusive OR circuit EOR11 outputs a low level signal as the output OUT_C of the clock comparison circuit 13.

  That is, when the clock CK # and the clock CK are at the same level, the clock comparison circuit 13 outputs a low level signal as the output OUT_C. When the level of the clock CK # and the level of the clock CK are different (that is, when the clock CK is a complementary clock), a high level signal is output as the output OUT_C.

  The filter circuit 14 is a circuit that detects that the output OUT_C of the clock comparison circuit 13 does not change for a predetermined time. FIG. 5 is a circuit diagram illustrating an example of the filter circuit 14. As shown in FIG. 5, the filter circuit 14 includes a delay circuit 25 and an OR circuit OR21. The delay circuit 25 delays the output OUT_C of the clock comparison circuit 13 and outputs the delayed output OUT_D to the OR circuit OR21. For example, the delay circuit 25 can be configured by a circuit in which a plurality of inverter circuits INV21 to INV24 are connected in series. The power supply VDD is supplied to the inverter circuits INV21 to INV24.

  The OR circuit OR21 inputs the output OUT_C of the clock comparison circuit 13 and the output OUT_D of the delay circuit 25, and outputs a logical sum of these. The power supply VDD is supplied to the OR circuit OR21. Immediately after the output OUT_C of the clock comparison circuit 13 changes from the high level to the low level, the output OUT_C supplied to one of the OR circuits OR21 becomes low level, but the delay circuit 25 supplied to the other of the OR circuits OR21. The output OUT_D from is kept at a high level. Therefore, the output OUT_E of the OR circuit OR21 maintains a high level. Thereafter, when the delay time set by the delay circuit 25 is passed, the output OUT_D changes from the high level to the low level. In this case, since the output OUT_C and the output OUT_D supplied to the OR circuit OR21 are at the low level, the OR circuit OR21 outputs a low level signal as the output OUT_E.

  Here, the case where the output OUT_C of the clock comparison circuit 13 changes from the high level to the low level is a case where the clock comparison circuit 13 detects that the clock CK # and the clock CK are at the same level.

  As shown in FIG. 1, the semiconductor device 1 according to the present embodiment includes a clock mask circuit 15 that masks the internal clock CLK_1 output from the clock buffer circuit 11 in accordance with the detection result of the clock detection circuit 12. Prepare. When the output OUT_E of the clock detection circuit 12 is at a high level, the clock CK and the clock CK # are in a complementary relationship, so the clock mask circuit 15 outputs the internal clock CLK_1 generated by the clock buffer circuit 11 as the internal clock CLK_2. To do.

  On the other hand, when the output OUT_E of the clock detection circuit 12 is at a low level, the clock CK and the clock CK # are at the same level for a predetermined time, so the clock mask circuit 15 uses the internal clock CLK_1 generated by the clock buffer circuit 11. Mask it. In this case, the internal clock CLK_2 is not output. The clock mask circuit 15 can be configured by an AND circuit, for example. The clock mask circuit 15 operates with the power supply VDD.

Next, the operation of the semiconductor device according to this embodiment will be described using the timing chart shown in FIG.
When power is turned on to the semiconductor device at timing t1, the power supply VDD and the power supply VDDQ start to rise. For example, after the timing t1, when the clock CK and the clock CK # supplied to the semiconductor device are both at the low level, the NMOS transistors MN1 and MN2 of the clock buffer circuit 11 illustrated in FIG. 2 are both turned off. For this reason, the node B which is the input of the inverter INV1 becomes indefinite (intermediate level), and the inverter INV1 outputs the internal clock CLK_1 that changes irregularly.

  When both the clock CK and the clock CK # supplied to the semiconductor device are at a low level, a low level signal is output from the clock comparison circuit 13 as an output OUT_C (see FIG. 4). In addition, when the output OUT_C of the clock comparison circuit 13 does not change for a predetermined time, the filter circuit 14 outputs a low level signal to the clock mask circuit 15 as the output OUT_E. Since the output OUT_E is at a low level, the clock mask circuit 15 masks the internal clock CLK_1 generated by the clock buffer circuit 11. In this case, as shown in FIG. 6, the internal clock CLK_2 is not output.

  After that, when the clock CK rises at timing t2, that is, when the clock CK and the clock CK # become complementary clocks, a high level signal is output from the clock comparison circuit 13 as the output OUT_C (see FIG. 4). The filter circuit 14 outputs a high level signal to the clock mask circuit 15 as an output OUT_E. At timing t3, the clock mask circuit 15 outputs the internal clock CLK_1 generated by the clock buffer circuit 11 as the internal clock CLK_2 because the output OUT_E is at the high level.

  As shown in FIG. 6, even when the clocks CK and CK # are operating normally as complementary clocks, cross points (see reference numerals 26 and 27) are generated during the transition of the clocks CK and CK #. . When a cross point occurs in this way, a short low-level pulse may be generated at the output OUT_C of the clock comparison circuit 13 in some cases. The filter circuit 14 described above is provided for the purpose of removing such a short low level pulse.

  Thus, in the semiconductor device according to this embodiment, the clock detection circuit 12 detects that the clock CK and the clock CK # are at the same level for a predetermined time. When the clock CK and the clock CK # are at the same level for a predetermined time, the internal clock CLK_1 generated by the clock buffer circuit 11 is masked by the clock mask circuit 15.

  That is, when both of the clocks CK and CK # are at the low level (or both are at the high level), the internal clock CLK_1 that changes irregularly is output from the clock buffer circuit 11. However, since the internal clock CLK_1 is masked in the semiconductor device according to the present embodiment, it is possible to prevent the operation of the semiconductor device to which the internal clock is supplied from becoming unstable.

  In the semiconductor device according to the present embodiment, the clock buffer circuit 11 operates with the input / output power supply VDDQ, and the clock detection circuit 12 operates with the internal power supply VDD. The effect obtained by such a configuration will be described in detail below.

  FIG. 7 is a block diagram for explaining a configuration example of the semiconductor device according to the present embodiment. As shown in FIG. 7, the semiconductor device according to the present embodiment includes an input stage 31, an internal circuit 32 disposed at the subsequent stage of the input stage 31, and an output disposed at the subsequent stage of the internal circuit 32. And a step 33. The input stage 31 and the output stage 33 operate with the input / output power supply VDDQ, and the internal circuit 32 operates with the internal power supply VDD.

  The input stage 31 includes, for example, a clock buffer circuit that receives clocks CK and CK # and generates an internal clock CLK, and an address buffer circuit that receives an address ADD and generates an internal address ADD_IN. Further, the input stage 31 includes a command buffer circuit that receives the command signal COM and generates internal command signals COM_0 to COM_2, an input data buffer circuit that receives the data DATA_1 and generates input data DATA_IN, and the like.

  The internal circuit 32 executes predetermined processing using the supplied internal clock CLK, internal address ADD_IN, internal command signals COM_0 to COM_2, and input data DATA_IN, and outputs a processing result (for example, output data DATA_OUT) to the output stage 33. Output. For example, the internal circuit 32 is configured by a logic circuit. The output stage 33 includes, for example, an output buffer circuit that receives the output data DATA_OUT and generates the data signal DATA_2.

  Thus, the input stage 31 and the output stage 33 are provided with input / output buffer circuits, and the internal circuit 32 is provided with transistors constituting a logic circuit. Therefore, the input stage 31 and output stage 33 and the internal circuit 32 may be driven with different voltages. For this reason, the input stage 31 and the output stage 33 are configured to operate with the power supply VDDQ, and the internal circuit 32 is configured to operate with the power supply VDD. Therefore, when the power supply VDDQ and the power supply VDD are raised when the semiconductor device is turned on, the power supply VDDQ and the power supply VDD are different power supplies, and thus the rising speed may be different.

  Further, for example, the internal circuit 32 includes a power-on reset circuit in order to prevent a malfunction at power-on. The power-on reset circuit is a circuit that detects a power-on and outputs a reset signal when the power supply VDD does not normally rise to prevent malfunction of the internal circuit 32.

  The semiconductor device according to the present embodiment is configured such that the clock buffer circuit 11 (corresponding to the input stage 31) operates with the input / output power supply VDDQ, and the clock detection circuit 12 operates with the internal power supply VDD. For example, when the power supply VDD has not risen, the internal circuit 32 is reset by the power-on reset circuit. Therefore, even if the clock detection circuit 12 does not function normally because the voltage of the power supply VDD is low, the internal circuit 32 will not malfunction. The case where the power supply VDD is not started up is a case where the voltage of the power supply VDD is low and the power supply VDD cannot operate the internal circuit 32.

  Here, when the clock detection circuit 12 is configured to operate with the same power supply VDDQ as that of the clock buffer circuit 11 (input stage 31), the following problem occurs. That is, when the power supply VDDQ rises after the power supply VDD rises, the clock detection circuit 12 may malfunction because the normal power supply VDDQ is not supplied to the clock detection circuit 12 immediately after the power supply VDD rises. On the other hand, in a state where the power supply VDD is rising, the power-on reset circuit included in the internal circuit 32 determines that the internal circuit 32 operates normally. For this reason, when an inappropriate internal clock CLK is supplied to the internal circuit 32, the internal clock CLK cannot be masked because the clock detection circuit 12 does not operate normally, and the internal circuit 32 may malfunction. .

  For the reasons described above, the semiconductor device 1 according to the present embodiment is configured such that the clock detection circuit 12 is operated with a power supply VDD different from the power supply VDDQ that operates the clock buffer circuit 11.

  Next, the case where the semiconductor device according to this embodiment is applied to a memory device will be described with reference to FIGS. When the semiconductor device according to this embodiment is applied to a memory device, the semiconductor device 1 is provided in the memory device 42 shown in FIG. An ASIC 41 (Application Specific Integrated Circuit) is configured to be accessible to the memory device 42. That is, the ASIC 41 outputs the complementary clocks CK and CK #, the address ADD, the command signal COM (chip selection signal CS # and the like), and the data DATA_1 to the memory device 42. Further, the ASIC 41 receives the data DATA_2 output from the memory device 42.

  FIG. 9 shows a detailed configuration of the memory device 42. As shown in FIG. 9, the memory device 42 includes the clock buffer circuit 11, the clock detection circuit 12, and the clock mask circuit 15 described above. The memory device 42 further includes an address buffer circuit 43, a command buffer circuit 44, a power-on reset circuit 45, a memory 46, and a data buffer circuit 47.

  The memory device 42 is supplied with an input / output power supply VDDQ and an internal power supply VDD. The clock buffer circuit 11 operates with the input / output power supply VDDQ, and the clock detection circuit 12, the clock mask circuit 15, and the power-on reset circuit 45 operate with the internal power supply VDD. As for the address buffer circuit 43, the command buffer circuit 44, and the data buffer circuit 47, the circuits provided in the input / output stage among the circuits constituting each buffer circuit operate with the input / output power supply VDDQ. The other circuits operate with the internal power supply VDD.

  Since the clock buffer circuit 11, the clock detection circuit 12, and the clock mask circuit 15 have been described above, redundant description will be omitted. The internal clock CLK_2 output from the clock mask circuit 15 is supplied to each of the address buffer circuit 43, the command buffer circuit 44, and the data buffer circuit 47.

  The address buffer circuit 43 receives the address ADD output from the ASIC 41, generates an internal address ADD_IN, and outputs it to the memory 46. The command buffer circuit 44 receives the command signal COM output from the ASIC 41, generates internal command signals COM_0 to COM_2, and generates the generated internal command signals COM_0 to COM_2, respectively, as the address buffer circuit 43, the memory 46, and the data The data is output to the buffer circuit 47. The power-on reset circuit 45 is a circuit that detects a power-on to the memory device 42 and outputs a reset signal Pon when the power supply VDD is not normally raised to prevent malfunction of the memory device 42. Here, the reset signal Pon is supplied to each circuit in the memory device 42.

  The data buffer circuit 47 receives the data DATA_1 output from the ASIC 41, generates input data DATA_IN, and outputs the generated input data DATA_IN to the memory 46. The output data DATA_OUT output from the memory 46 is received to generate output data DATA_2, and the generated output data DATA_2 is output to the ASIC 41. The memory 46 reads the output data DATA_OUT stored at the address corresponding to the internal address ADD_IN in accordance with the command signal (for example, read signal, write signal) output from the command buffer circuit 44, and also the internal address ADD_IN. The input data DATA_IN is written to the address corresponding to.

  Also in the memory device 42 illustrated in FIG. 9, the clock detection circuit 12 detects that the clock CK and the clock CK # are at the same level for a predetermined time. When the clock CK and the clock CK # are at the same level for a predetermined time, the clock mask circuit 15 masks the internal clock CLK_1 generated by the clock buffer circuit 11 (see FIG. 6). Therefore, it is possible to prevent the operation of the memory device 42 from becoming unstable when the power is turned on.

  Next, a comparative example of the semiconductor device according to the present embodiment will be described. FIG. 10 is a block diagram showing the memory device 142 according to the comparative example. A memory device 142 shown in FIG. 10 includes a clock buffer circuit 11, an address buffer circuit 43, a command buffer circuit 44, a power-on reset circuit 45, a memory 46, and a data buffer circuit 47. That is, the memory device 142 illustrated in FIG. 10 is different from the memory device 42 illustrated in FIG. 9 in that the clock detection circuit 12 and the clock mask circuit 15 are not provided. Except for this, it is the same as the memory device 42 shown in FIG.

  FIG. 11 is a timing chart for explaining the operation of memory device 142 (including ASIC 41) shown in FIG. FIG. 11 shows an operation recommended when the power is turned on. When the ASIC 41 and the memory device 142 are activated at the timing t11, the power supply VDD and the power supply VDDQ start to rise, and the clocks CK and CK # and the chip selection signal CS # transition to the initial state. Here, the clocks CK and CK # and the chip selection signal CS # are supplied from the ASIC 41. Further, since the clocks CK and CK # are complementary clocks, for example, the clock CK is set to the high level and the clock CK # is set to the low level.

  The chip selection signal CS # is set to a high level so that the memory device 142 is in a non-selected state in order to prevent malfunction at power-on. The power-on reset circuit 45 outputs a low-level reset signal Pon because the power supply VDD has not risen. As a result, the memory device 142 is initialized. Thereafter, when the power supply VDD rises, the power-on reset circuit 45 outputs a high-level reset signal Pon at timing t12. As a result, the memory device 142 becomes operable.

  Further, after the timing t13, when the clocks CK and CK # operate as complementary clocks, the clock buffer circuit 11 supplies the internal clock CLK_1 to each circuit in the memory device 142.

  On the other hand, when the ASIC 41 and the memory device 142 are activated, there are cases where the ASIC 41 and the memory device 142 cannot be activated normally as shown in FIG.

  FIG. 12 is a timing chart for explaining the operation of memory device 142 (including ASIC 41) shown in FIG. FIG. 12 shows the operation when the clocks CK and CK # do not rise normally when the power is turned on.

  When the ASIC 41 and the memory device 142 are activated at timing t21, the power supply VDD and the power supply VDDQ start to rise. However, in this case, the clocks CK and CK # and the chip selection signal CS # are at the low level until timing t23. That is, since the ASIC 41 does not rise, the clocks CK and CK # and the chip selection signal CS # remain at a low level.

  Thus, when both the clock CK and the clock CK # are at the low level, both the NMOS transistors MN1 and MN2 of the clock buffer circuit 11 shown in FIG. 2 are turned off. For this reason, the node B which is the input of the inverter INV1 becomes indefinite (intermediate level), and the inverter INV1 outputs the internal clock CLK_1 that changes irregularly.

  The power-on reset circuit 45 outputs a low-level reset signal Pon because the power supply VDD has not risen. As a result, the memory device 142 is initialized. Thereafter, when the power supply VDD rises, the power-on reset circuit 45 outputs a high-level reset signal Pon at timing t22. As a result, the memory device 142 becomes operable. However, at the timing t22, since the clocks CK and CK # are both at the low level, the internal clock CLK_1 that irregularly changes is supplied to the circuit inside the memory device 142. Further, since the chip selection signal CS # is at a low level, the memory device 142 is in a state of accepting a command signal from the outside, and there is a possibility of transition to an unexpected operation state.

  After the timing t23, when the clocks CK and CK # operate as complementary clocks, the clock buffer circuit 11 generates the normal internal clock CLK_1, and the memory device 142 operates with the normal internal clock CLK_1.

  In this manner, when the memory device 142 is powered on, if the appropriate clocks CK and CK # are not supplied to the memory device 142, the operation of the memory device may become unstable. Specifically, the operation of the memory device becomes unstable between the timing t22 at which the reset signal Pon becomes high level and the timing t23 at which the complementary clock starts to be supplied.

  Therefore, in the semiconductor device according to the present embodiment, the clock detection circuit 12 detects that the clock CK and the clock CK # are at the same level for a predetermined time. When the clock CK and the clock CK # are at the same level for a predetermined time, the internal clock CLK_1 generated by the clock buffer circuit 11 is masked by the clock mask circuit 15.

  That is, when both of the clocks CK and CK # are at the low level (or both are at the high level), the internal clock CLK_1 that changes irregularly is output from the clock buffer circuit 11. Therefore, in the semiconductor device according to the present embodiment, the internal clock CLK_1 is masked using the clock mask circuit 15. Therefore, it is possible to prevent the operation of the semiconductor device to which the internal clock is supplied from becoming unstable.

<Embodiment 2>
Next, a second embodiment will be described. FIG. 13 is a block diagram of the semiconductor device according to the second embodiment. As shown in FIG. 13, the semiconductor device 2 according to the present embodiment is different from the semiconductor device 1 according to the first embodiment in that a level shift circuit 51 is provided after the clock buffer circuit 11. Since other than this is the same as the semiconductor device 1 described in the first embodiment, the same components are denoted by the same reference numerals, and redundant description is omitted.

  The level shift circuit 51 is a circuit for shifting the level of the internal clock CLK_1 generated by the clock buffer circuit 11. That is, when the voltage of the input / output power supply VDDQ is different from the voltage of the internal power supply VDD, the level shift circuit 51 makes the level of the internal clock CLK_1 output from the clock buffer circuit 11 correspond to the voltage of the internal power supply VDD. shift. Here, the level shift circuit 51 operates with the internal power supply VDD.

  FIG. 14 is a circuit diagram showing an example of the clock buffer circuit 11 and the level shift circuit 51. The clock buffer circuit 11 shown in FIG. 14 is the same as the clock buffer circuit 11 described in FIG.

  The level shift circuit 51 includes PMOS transistors MP21 and MP22, NMOS transistors MN21 and MN22, and an inverter INV21. The source of the PMOS transistor MP21 is connected to the power supply VDD, the gate is connected to the node Q, and the drain is connected to the node P. The source of the PMOS transistor MP22 is connected to the power supply VDD, the gate is connected to the node P, and the drain is connected to the node Q. The drain of the NMOS transistor MN21 is connected to the node P, and the internal clock CLK_1 is supplied to the gate. The source of the NMOS transistor MN21 is grounded. The inverter INV21 receives the internal clock CLK_1 and outputs a signal obtained by inverting the internal clock CLK_1 to the gate of the NMOS transistor MN22. The drain of the NMOS transistor MN22 is connected to the node Q, and the source is grounded. The internal clock CLK_1 ′ after the level shift is output from the node Q.

  When the internal clock CLK_1 is at a high level, the NMOS transistor MN21 is turned on and the node P is at a low level. Further, the NMOS transistor MN22 is turned off. When the node P becomes low level, the PMOS transistor MP22 is turned on. At this time, since the NMOS transistor MN22 is in an off state, the node Q becomes a high level. Further, since the node Q is at the high level, the PMOS transistor MP21 is turned off. Therefore, a high level signal corresponding to the voltage of the power supply VDD is output from the node Q.

  On the other hand, when the internal clock CLK_1 is at a low level, the NMOS transistor MN21 is turned off. Further, the NMOS transistor MN22 is turned on. Therefore, the node Q becomes a low level. When the node Q becomes low level, the PMOS transistor MP21 is turned on. At this time, since the NMOS transistor MN21 is in an off state, the node P becomes a high level. Further, since the node P is at a high level, the PMOS transistor MP22 is turned off. Therefore, a low level (ground potential) signal is output from the node Q.

  As described above, since the level shift circuit 51 is provided after the clock buffer circuit 11 in the semiconductor device 2 according to the present embodiment, the voltage of the input / output power supply VDDQ is different from the voltage of the internal power supply VDD. However, the level of the internal clock can be matched with the voltage of the internal power supply VDD.

<Embodiment 3>
Next, Embodiment 3 will be described. FIG. 15 is a block diagram of the semiconductor device according to the third embodiment. As shown in FIG. 15, in the semiconductor device 3 according to the present embodiment, the reset signal Pon output from the power-on reset circuit 45 is masked according to the detection result of the clock detection circuit 12. Different from the semiconductor device 1 according to the first embodiment. Since other than this is the same as the semiconductor device 1 described in the first embodiment, the same components are denoted by the same reference numerals, and redundant description is omitted.

  As shown in FIG. 15, the semiconductor device 3 according to the present embodiment includes a clock buffer circuit 11, a clock detection circuit 12, a power-on reset circuit 45, and a reset signal mask circuit 61. The clock detection circuit 12 includes a clock comparison circuit 13 and a filter circuit 14. The clock buffer circuit 11 operates with the input / output power supply VDDQ (first power supply), and the clock detection circuit 12, the power-on reset circuit 45, and the reset signal mask circuit 61 operate with the internal power supply VDD (second power supply). . Note that the configurations and operations of the clock buffer circuit 11 and the clock detection circuit 12 are the same as those described in the first embodiment, and thus redundant description is omitted.

  The power-on reset circuit 45 is a circuit that detects a power-on to the semiconductor device 3 and outputs a reset signal Pon when the power supply VDD is not normally raised to prevent malfunction of the semiconductor device 3. For example, the power-on reset circuit 45 outputs a low-level reset signal Pon when the power supply VDD has not risen normally. On the other hand, when it is determined that the power supply VDD has risen normally, a high level reset signal Pon is output. The reset signal mask circuit 61 masks the reset signal Pon output from the power-on reset circuit 45 according to the detection result (output OUT_E) of the clock detection circuit 12. The reset signal mask circuit 61 can be configured by an AND circuit, for example.

  For example, when the output OUT_E of the clock detection circuit 12 is at a high level, the clock CK and the clock CK # are in a complementary relationship, and the semiconductor device 3 can operate normally. Therefore, the reset signal mask circuit 61 outputs the reset signal Pon_2 output from the power-on reset circuit 45 as the reset signal Pon_2 without masking.

  On the other hand, when the output OUT_E of the clock detection circuit 12 is at the low level, the semiconductor device 3 cannot operate normally because the clock CK and the clock CK # are at the same level for a predetermined time. Therefore, the reset signal mask circuit 61 masks the reset signal Pon output from the power-on reset circuit 45. That is, regardless of the output from the power-on reset circuit 45, a low level signal is always output as the reset signal Pon_2, and the semiconductor device (internal circuit) is reset.

  In other words, even when the power-on reset circuit 45 determines that the power supply VDD has risen normally, if the output OUT_E of the clock detection circuit 12 is at a low level, the detection result of the clock detection circuit 12 has priority. A low level signal is output as the reset signal Pon_2. Therefore, it is possible to suppress the operation of the semiconductor device from becoming unstable when the power is turned on.

  Next, a case where the semiconductor device 3 according to the present embodiment is applied to a memory device will be described with reference to FIG. As shown in FIG. 16, the memory device 42 ′ includes a clock detection circuit 12, a power-on reset circuit 45, and a reset signal mask circuit 61. The memory device 42 ′ further includes a clock buffer circuit 11, an address buffer circuit 43, a command buffer circuit 44, a memory 46, and a data buffer circuit 47. The clock buffer circuit 11 supplies the generated internal clock CLK_1 to the address buffer circuit 43, the command buffer circuit 44, the memory 46, and the data buffer circuit 47.

  In the present embodiment, the reset signal mask circuit 61 included in the memory device 42 ′ is configured to mask the reset signal Pon output from the power-on reset circuit 45 in accordance with the output OUT_E of the clock detection circuit 12. Yes. Other than this, since it is the same as the memory device 42 (see FIG. 9) described in the first embodiment, a duplicate description is omitted.

  FIG. 17 is a timing chart for explaining the operation of the memory device 42 ′ shown in FIG. FIG. 17 shows an operation when the clocks CK and CK # do not rise normally when the power is turned on.

  When the ASIC 41 (see FIG. 8 of the first embodiment) and the memory device 42 ′ are activated at the timing t31, the power supply VDD and the power supply VDDQ start to rise. However, in this case, the clocks CK and CK # and the chip selection signal CS # are at the low level until timing t33. That is, since the ASIC 41 does not rise, the clocks CK and CK # and the chip selection signal CS # remain at a low level.

  Thus, when both the clock CK and the clock CK # are at the low level, both the NMOS transistors MN1 and MN2 of the clock buffer circuit 11 shown in FIG. 2 are turned off. For this reason, the node B which is the input of the inverter INV1 becomes indefinite (intermediate level), and the inverter INV1 outputs the internal clock CLK_1 that changes irregularly.

  The power-on reset circuit 45 outputs a low-level reset signal Pon because the power supply VDD has not risen. As a result, the memory device 42 ′ is in an initialized state. Thereafter, when the power supply VDD rises, the power-on reset circuit 45 outputs a high-level reset signal Pon (indicated by a broken line) at timing t32. However, since the clocks CK and CK # remain at the low level, the clock detection circuit 12 outputs a low level signal as the output OUT_E. Therefore, the reset signal mask circuit 61 masks the high-level reset signal Pon output from the power-on reset circuit 45, and outputs a low-level signal as the reset signal Pon_2. Accordingly, since the memory device 42 ′ maintains the initialized state, malfunction of the memory device 42 ′ can be suppressed.

  Thereafter, when the clock CK rises at timing t33, that is, when the clock CK and the clock CK # become complementary clocks, a high level signal is output from the clock comparison circuit 13 as the output OUT_C (see FIG. 4). Further, the filter circuit 14 outputs a high level signal to the reset signal mask circuit 61 as the output OUT_E (timing t34). Since the output signal OUT_E is at the high level, the reset signal mask circuit 61 outputs the reset signal Pon output from the power-on reset circuit 45 as the reset signal Pon_2. As a result, the memory device 42 ′ becomes operable.

  Thus, in the semiconductor device according to this embodiment, the clock detection circuit 12 detects that the clock CK and the clock CK # are at the same level for a predetermined time. When the clock CK and the clock CK # are at the same level for a predetermined time, the reset signal mask circuit 61 masks the reset signal Pon output from the power-on reset circuit 45.

  That is, when both of the clocks CK and CK # are at the low level (or both are at the high level), the internal clock CLK_1 that changes irregularly is output from the clock buffer circuit 11. For this reason, the operation of the semiconductor device becomes unstable. However, in the semiconductor device according to the present embodiment, even when the high-level reset signal Pon indicating normality is output from the power-on reset circuit 45, the reset signal Pon is masked to initialize the semiconductor device. The state is maintained. Therefore, it is possible to suppress the operation of the semiconductor device from becoming unstable when the power is turned on.

<Embodiment 4>
Next, a fourth embodiment will be described. FIG. 18 is a block diagram of a semiconductor device according to the fourth embodiment. As shown in FIG. 18, in the semiconductor device 4 according to the present embodiment, the command signals CMD_0_B to CMD_n_B (n is a positive integer) output from the command buffer circuit 44 in accordance with the detection result of the clock detection circuit 12 are masked. This is different from the semiconductor device 1 according to the first embodiment. Since other than this is the same as the semiconductor device 1 described in the first embodiment, the same components are denoted by the same reference numerals, and redundant description is omitted.

  As shown in FIG. 18, the semiconductor device 4 according to the present embodiment includes a clock buffer circuit 11, a clock detection circuit 12, a command buffer circuit 44, and a command signal mask circuit 71. The clock detection circuit 12 includes a clock comparison circuit 13 and a filter circuit 14. The clock buffer circuit 11 operates with the input / output power supply VDDQ (first power supply), and the clock detection circuit 12, the command buffer circuit 44, and the command signal mask circuit 71 operate with the internal power supply VDD (second power supply). Note that the configurations and operations of the clock buffer circuit 11 and the clock detection circuit 12 are the same as those described in the first embodiment, and thus redundant description is omitted.

  The command buffer circuit 44 outputs command signals CMD_0_B to CMD_n_B to each circuit of the semiconductor device 4. The command signal mask circuit 71 masks the command signals CMD_0_B to CMD_n_B output from the command buffer circuit 44 according to the output OUT_E of the clock detection circuit 12. The command signal mask circuit 71 can be configured using, for example, AND circuits AND_0 to AND_n to which the output OUT_E of the clock detection circuit 12 is supplied on one side and the output of the command buffer circuit 44 on the other side.

  For example, when the output OUT_E of the clock detection circuit 12 is at a high level, the clock CK and the clock CK # are in a complementary relationship, and the semiconductor device 4 can operate normally. Therefore, the command signal mask circuit 71 outputs the command signals CMD_0 to CMD_n without masking the command signals CMD_0_B to CMD_n_B output from the command buffer circuit 44.

  On the other hand, when the output OUT_E of the clock detection circuit 12 is at a low level, the clock CK and the clock CK # are at the same level for a predetermined time, so that the semiconductor device 4 cannot operate normally. Therefore, the command signal mask circuit 71 masks the command signals CMD_0_B to CMD_n_B output from the command buffer circuit 44. That is, the command signals CMD_0_B to CMD_n_B are masked by the command signal mask circuit 71, so that the command signals CMD_0 to CMD_n are not supplied to each circuit of the semiconductor device 4. In other words, the command can be prevented from being validated, and the semiconductor device 4 can be prevented from operating. Therefore, it is possible to suppress the operation of the semiconductor device from becoming unstable when the power is turned on.

  Next, the case where the semiconductor device 4 according to the present embodiment is applied to a memory device will be described with reference to FIG. As shown in FIG. 19, the memory device 42 ″ includes a clock detection circuit 12, a command buffer circuit 44, and a command signal mask circuit 71. The memory device 42 ″ further includes a clock buffer circuit 11, an address buffer circuit 43, a power-on reset circuit 45, a memory 46, and a data buffer circuit 47. The clock buffer circuit 11 supplies the generated internal clock CLK_1 to the address buffer circuit 43, the command buffer circuit 44, the memory 46, and the data buffer circuit 47.

  In the present embodiment, the command signal mask circuit 71 included in the memory device 42 ″ is configured to mask the command signals CMD_0_B to CMD_n_B output from the command buffer circuit 44 in accordance with the output OUT_E of the clock detection circuit 12. doing. That is, the command signals CMD_0_B to CMD_n_B are masked by the command signal mask circuit 71 so that the command signal CMD_0 is not supplied to the address buffer circuit 43, the command signal CMD_1 is not supplied to the memory 46, and the command signal CMD_2 is not supplied to the data buffer circuit 47. can do. That is, since the command can be prevented from being validated, the semiconductor device 4 can be prevented from operating. Other than this, since it is the same as the memory device 42 (see FIG. 9) described in the first embodiment, a duplicate description is omitted.

  Thus, in the semiconductor device according to this embodiment, the clock detection circuit 12 detects that the clock CK and the clock CK # are at the same level for a predetermined time. When the clock CK and the clock CK # are at the same level for a predetermined time, the command signal mask circuit 71 masks the command signals CMD_0_B to CMD_n_B with the command signal mask circuit 71.

  That is, when both of the clocks CK and CK # are at the low level (or both are at the high level), the internal clock CLK_1 that changes irregularly is output from the clock buffer circuit 11. For this reason, the operation of the semiconductor device becomes unstable. However, in the semiconductor device according to the present embodiment, since the command signals CMD_0_B to CMD_n_B are masked by the command signal mask circuit 71, the semiconductor device can be prevented from operating. Therefore, it is possible to suppress the operation of the semiconductor device from becoming unstable when the power is turned on.

  In addition, you may combine the said Embodiment 2 and Embodiment 3, and the said Embodiment 2 and Embodiment 4 suitably, respectively. That is, the level shift circuit 51 may be provided after the clock buffer circuit 11 provided in the semiconductor device 3 according to the third embodiment. Further, the level shift circuit 51 may be provided after the clock buffer circuit 11 provided in the semiconductor device 4 according to the fourth embodiment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

1, 2, 3, 4 Semiconductor device 11 Clock buffer circuit 12 Clock detection circuit 13 Clock comparison circuit 14 Filter circuit 15 Clock mask circuit 21 Reference potential generation circuit 22 CK # detection circuit 23 CK detection circuit 25 Delay circuit 31 Input stage 32 Inside Circuit 33 Output stage 41 ASIC
42 memory device 43 address buffer circuit 44 command buffer circuit 45 power-on reset circuit 46 memory 47 data buffer circuit 51 level shift circuit 61 reset signal mask circuit 71 command signal mask circuit

Claims (13)

A clock buffer circuit which receives first and second clocks having a complementary relationship and generates an internal clock;
A clock detection circuit for detecting that the first and second clocks are at the same level for a predetermined time, and
The clock buffer circuit operates with a first power supply, and the clock detection circuit is configured to operate with a second power supply.
Semiconductor device. The semiconductor device includes an input stage, an internal circuit disposed in a subsequent stage of the input stage, and an output stage disposed in a subsequent stage of the internal circuit,
The input stage and the output stage operate with the first power supply, and the internal circuit is configured to operate with the second power supply.
The semiconductor device according to claim 1. The internal circuit further includes a power-on reset circuit that detects a power-on to the internal circuit and outputs a reset signal,
The power-on reset circuit is configured to operate with the second power source;
The semiconductor device according to claim 2.   The semiconductor device according to claim 1, further comprising a clock mask circuit that masks the internal clock output from the clock buffer circuit according to a detection result of the clock detection circuit.   The semiconductor device according to claim 4, wherein the clock mask circuit masks the internal clock when the first and second clocks are at the same level for a predetermined time.   5. The semiconductor according to claim 4, further comprising a level shift circuit that shifts a level of the internal clock output from the clock buffer circuit, wherein the level shift circuit is configured to operate with the second power supply. 6. apparatus.   The semiconductor device according to claim 6, wherein the level shift circuit shifts the level of the internal clock output from the clock buffer circuit so as to correspond to the voltage of the second power supply. Furthermore, a power-on reset circuit that detects power-on and outputs a reset signal;
A reset signal mask circuit that masks a reset signal output from the power-on reset circuit according to a detection result of the clock detection circuit,
The power-on reset circuit and the reset signal mask circuit are configured to operate with a second power supply.
The semiconductor device according to claim 1.   9. The semiconductor device according to claim 8, wherein the reset signal mask circuit masks the reset signal when the first and second clocks are at the same level for a predetermined time. A command buffer circuit for outputting a command signal;
A command signal mask circuit that masks a command signal output from the command buffer circuit in accordance with a detection result of the clock detection circuit;
The command signal mask circuit is configured to operate with the second power source;
The semiconductor device according to claim 1.   The semiconductor device according to claim 10, wherein the command signal masking circuit masks the command signal when the first and second clocks are at the same level for a predetermined time. The clock detection circuit includes:
A clock comparison circuit for comparing the first and second clocks;
A filter circuit for detecting that the output of the clock comparison circuit does not change for the predetermined time,
The semiconductor device according to claim 1. The filter circuit includes a delay circuit that delays an output of the clock comparison circuit;
A logical sum circuit that outputs a logical sum of the output of the clock comparison circuit and the output of the delay circuit;
The semiconductor device according to claim 12.

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