KR20080061737A - Input buffer circuit - Google Patents

Abstract

An input buffer circuit is provided to prevent degradation of an output signal in a high speed operation, by changing the intensity of a current of an input buffer according to operation speed. An input buffer part(100) buffers an input signal. A current sync part(200) changes the intensity of a current of the input buffer part according to a clock frequency signal. The current sync part is constituted with a transistor providing a current path of the input buffer part according to a first control signal and a transistor providing a current path of the input buffer part according to a second control signal.

Description

Input Buffer Circuit {Input Buffer Circuit}

1 is a detailed circuit diagram of an input buffer circuit according to the prior art;

2 is a block diagram of an input buffer circuit according to the present invention;

3 is a detailed circuit diagram illustrating an embodiment of the input buffer circuit of FIG. 2.

<Description of the symbols for the main parts of the drawings>

100: input buffer unit 200: current sink unit

210: first sink 220: second sink

The present invention relates to semiconductor integrated circuits, and more particularly, to input buffers.

The input buffer converts the signal of the transistor-transistor logic level into the signal of the CMOS level.

The semiconductor memory device is applied to various systems, and since the circuits inside the semiconductor integrated circuit are composed of CMOS circuits, when the level of a signal applied from the outside is different, it must be converted to the CMOS level.

Therefore, the semiconductor memory device has an input buffer at the address, data, clock signal, and driving signal input terminals, respectively.

1 is an embodiment of an input buffer according to the prior art.

As shown in the drawing, the input buffer according to the prior art is a first mirror that is turned on or turned off according to the driving signal EN and a second PMOS transistor PM2 and a current mirror that supplies current. The third PMOS transistor PM3 and the fourth PMOS transistor PM4, the first NMOS transistor NM1 and the second NMOS transistor NM2 to which the input signal IN and the reference voltage VREF are input. ), And a third NMOS transistor NM3 that connects the current path with the ground line.

In detail, the driving signal EN is applied to the gate and the supply voltage VDD is applied to the source of the first PMOS transistor PM1 and the second PMOS transistor PM2. A first node N1 is connected to a gate, the supply voltage VDD is applied to a source, and the first node N1 is connected to a drain of the third PMOS transistor PM3 and the fourth PMOS transistor PM4. ) Is connected. The first NMOS transistor NM1 and the second NMOS transistor NM2 receive an input signal IN and a reference voltage to a gate, respectively, and the second node N2 is connected to a source, and the first NMOS transistor NM2 is connected to a source. Node N1 is connected. In the third NMOS transistor NM3, the driving signal EN is applied to a gate, the second node N2 is connected to a drain, and a ground line is connected to a source.

The principle of operation is as follows. When the driving signal EN is low, the first PMOS transistor PM1 and the second PMOS transistor PM2 are turned on to fix the output signal OUT to a high level. The driving signal EN is a signal for driving the input buffer. When the driving signal EN is low, the driving signal EN does not operate as the input buffer but outputs a high level, and when the driving signal EN is high. It acts as the input buffer.

When the driving signal EN is high, the first PMOS transistor PM1 and the second PMOS transistor PM2 are turned off, and the third NMOS transistor NM3 is turned on. In this case, if the input signal IN is higher than the reference voltage VREF, the output signal OUT is at a low level, and if the input signal IN is lower than the reference voltage VREF, the output signal OUT Is high level. In this way, the input buffer converts the input signal IN to the supply voltage VDD level.

Prior art has not been able to cope with a change in the characteristics of the input buffer circuit according to the operating speed by designing the input buffer to have a constant operating characteristics irrespective of the operating speed (clock frequency).

If the input signal IN is higher than the reference voltage VREF, the output signal OUT is low. If the input signal IN is lower than the reference voltage VREF, the output signal OUT is high. The input signal IN and the output signal OUT are opposite in phase. Therefore, when the clock frequency increases, the gate potential and the drain potential of the first NMOS transistor NM1 to which the input signal IN is applied operate in an antiphase, so that the output is caused by parasitic capacitance between the gate and the drain. The deterioration of the signal OUT becomes remarkable. If the clock frequency is higher, the deterioration of the output signal OUT is more significant and, in severe cases, is almost indistinguishable from noise.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object of the present invention is to provide an input buffer circuit which does not deteriorate an output signal even at a high speed operation by varying an amount of current of an input buffer according to an operation speed.

In addition, another object of the present invention is to provide an input buffer circuit that efficiently consumes current by varying the amount of current according to the operation speed.

An input buffer circuit of the present invention for achieving the above technical problem is an input buffer unit for buffering an input signal; And a current sink unit for varying an amount of current of the input buffer unit according to a clock frequency signal.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2 is a block diagram of an input buffer circuit according to the present invention.

As shown, the input buffer circuit according to the present invention includes an input buffer unit 100 and a current sink unit 200.

The input buffer unit 100 buffers the input signal IN. The input buffer unit 100 outputs a low when the input signal IN is higher than the reference voltage VREF and outputs a high when the input signal IN is lower than the reference voltage VREF. Alternatively, the input buffer unit 100 outputs a high level when the input signal IN is higher than the reference voltage VREF and a low level when the input signal IN is lower than the reference voltage VREF. It may also output The input buffer unit 100 may be implemented as a general input buffer circuit.

The current sink 200 is configured by different transistors operating according to a clock frequency. The current sink 200 is an essential component of the present invention and changes the current path path from the input buffer unit 100 to the ground line according to a control signal CTRL. The control signal CTRL is a signal whose value varies depending on a range of clock frequencies that operate. The control signal CTRL may use, for example, a CAS Write Latency Address Bit. When the clock frequency is high, the current sink unit 200 increases the number of transistors that operate when the clock frequency is high, thereby increasing the current amount of the input buffer unit 100 to increase the operating speed, and when the clock frequency is low, The operation speed may be adjusted by reducing the number of currents and reducing the amount of current in the input buffer unit 100.

3 is a detailed circuit diagram illustrating an embodiment of the input buffer circuit of FIG. 2.

The input buffer unit 100 is a current mirror configured to supply current to the first PMOS transistor PM1 and the second PMOS transistor PM2 that are turned on or off according to the driving signal EN in the same manner as in the prior art. The third PMOS transistor PM3 and the fourth PMOS transistor PM4, the first NMOS transistor NM1 and the second NMOS transistor NM2 to which the input signal IN and the reference voltage VREF are input. ), And a third NMOS transistor NM3 that connects the current path with the ground line. As described above, the input buffer unit 100 may be implemented using a general input buffer circuit.

In detail, the driving signal EN is applied to a gate and the supply voltage VDD is applied to a source of the first PMOS transistor PM1 and the second PMOS transistor PM2. The third PMOS transistor PM3 and the fourth PMOS transistor PM4 are connected to a gate of the first node N1, a supply voltage VDD is applied to a source, and a drain of the first node (PM4). N1) is connected. The first NMOS transistor NM1 and the second NMOS transistor NM2 receive the input signal IN and the reference voltage VREF to a gate, respectively, and the second node N2 is connected to a source. The first node N1 is connected to a drain. The third NMOS transistor NM3 receives the driving signal EN at a gate, the second node N2 is connected to a drain, and a ground line is connected to a source.

The first PMOS transistor PM1 and the second PMOS transistor PM2 are configured to output a value in which the output signal OUT of the input buffer is fixed high when the driving signal EN is disabled. to be.

When the driving signal EN is at a high level, the input buffer unit 100 operates to buffer and output the input signal IN. The output signal OUT is low when the input signal IN is higher than the reference voltage VREF and the output signal OUT is high when the input signal IN is lower than the reference voltage VREF. Level.

The current sink 200 includes a first sink 210 including a fourth NMOS transistor NM4 and a fifth NMOS transistor NM5 that provide a current path path according to a first control signal CTRL1, The second sink 220 includes a sixth NMOS transistor NM6 and a seventh NMOS transistor NM7 that provide a current path path according to the second control signal CTRL2.

As described above, the first control signal CTRL1 and the second control signal CTRL2 are signals that vary in value depending on a range of clock frequencies in which they operate. The first and second control signals CTRL1 and CTRL2 may use a CAS WRITE Latency Address Bit.

That is, the first and second control signals CTRL1 and CTRL2 have values of 00, 01, 10 and 11 according to a range of clock frequencies. For example, when the clock period is 2.5 ns or more, the first and second control signals CTRL1 and CTRL2 are 00 and when the clock period is 2.5 ns to 1.875 ns, the first and second control signals CTRL1 and CTRL2. Is 01.

 The fourth NMOS transistor NM4 receives the first control signal CTRL1 at a gate thereof, the driving signal EN is applied at a drain thereof, and is connected to a gate of the fifth NMOS transistor NM5 at a source thereof. . The fifth NMOS transistor NM5 is connected to a source of the fourth NMOS transistor NM4 at a gate thereof, the first node N1 is connected to a drain thereof, and a ground line is connected to the source thereof.

Therefore, when the first control signal CTRL1 is high, the fourth NMOS transistor NM4 is turned on to transfer the driving signal EN to the gate of the fifth NMOS transistor NM5. Accordingly, since the fifth NMOS transistor NM5 is turned on so that the current path of the input buffer becomes the third NMOS transistor NM3 and the fifth NMOS transistor NM5, more current flows. The operation speed of the input buffer is increased.

In addition, the sixth NMOS transistor NM6 receives the second control signal CTRL2 at a gate thereof, the driving signal EN is applied at a drain thereof, and a gate of the seventh NMOS transistor NM7 is connected at a source thereof. do. In the seventh NMOS transistor NM7, a source of the sixth NMOS transistor NM6 is connected to a gate, the first node N1 is connected to a drain, and a ground line is connected to the source.

Therefore, as in the case where the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 operate, when the second control signal CTRL2 is high, the sixth NMOS transistor NM6 is turned on. The driving signal EN is transmitted to the gate of the seventh NMOS transistor NM7.

Therefore, since the seventh NMOS transistor NM7 is turned on so that the current path of the input buffer becomes the third NMOS transistor NM3 and the seventh NMOS transistor NM7, more current flows to the input. The buffer speeds up.

When both the first control signal CTRL1 and the second control signal CTRL2 are high, both the fourth NMOS transistor NM4 and the seventh NMOS transistor NM7 are turned on and the current of the input buffer is turned on. Since the pass path becomes the third NMOS transistor NM3, the fifth NMOS transistor NM5, and the seventh NMOS transistor NM7, the operation speed of the input buffer becomes higher.

That is, when the driving signal EN is low, the input buffer circuit has the first PMOS transistor PM1 and the second PMOS transistor PM2 turned on so that the output signal OUT has a high level. do.

When the driving signal EN is high and the first and second control signals CTRL1 and CTRL2 are low, the first PMOS transistor PM1 and the second PMOS transistor PM2 are turned off. The third NMOS transistor NM3 is turned on, and the fourth to seventh NMOS transistors are turned off. The output signal OUT outputs a low level when the input signal IN is higher than the reference voltage VREF. The output signal OUT is output when the input signal IN is lower than the reference voltage VREF. Outputs a high level. The current path path of the input buffer unit 100 is the third NMOS transistor NM3.

Even when the clock frequency (operation speed) is different, the operating principle is the same as above, but as described above, when the first or second control signals CTRL1 and CTRL2 become high, the fourth NMOS transistor NM4 or the fourth Since the six NMOS transistor NM6 is turned on and the fifth NMOS transistor NM5 or the seventh NMOS transistor NM7 is turned on, the current path path of the input buffer circuit is the third NMOS transistor PM3. In addition, the amount of current increases due to the fifth NMOS transistor PM5 or the seventh NMOS transistor PM7.

As a result, the degradation of the output signal OUT with respect to the input signal IN, which has been a problem in high-speed operation with a high clock frequency, is solved by increasing the current path path. The third to seventh NMOS transistors NM3, NM5, NM6, and NM7 may adjust the amount of current by adjusting a gate width or length.

In the exemplary embodiment illustrated in FIG. 3, when the current path path is provided by the third NMOS transistor NM3 according to the operating speed, the first sink 210 and the second sink 220 are provided. In the case of the MOS transistor NM3 and the fifth NMOS transistor NM5, in the case of the third NMOS transistor NM3 and the seventh NMOS transistor NM7, the third NMOS transistor NM3 and the fifth NMOS transistor NM5. Although different with the case of the NMOS transistor NM5 and the seventh NMOS transistor NM7, the sink may be further included if the current path path is to be varied according to the operation speed.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive.

The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The input buffer circuit according to the present invention is capable of outputting a signal corresponding to the input signal speed in the high speed operation mode, and has an effect of solving the degradation of the output signal during the high speed operation.

In addition, the current pass amount is adjusted according to the clock frequency, thereby effectively providing current consumption.

Claims (5)

An input buffer unit for buffering an input signal; And And a current sink for varying an amount of current in the input buffer according to a clock frequency signal. The method of claim 1, The current sink unit, And an input buffer circuit configured to provide a current path of the input buffer section according to a control signal. The method of claim 2, The current sink unit, A transistor providing a current path of the input buffer unit according to a first control signal; And And an input buffer circuit configured to provide a current path of the input buffer unit according to a second control signal. The method of claim 2, The current sink unit, A first NMOS transistor configured to receive the first control signal at a gate and apply a driving signal to a drain; And a second NMOS transistor connected to a source of the first NMOS transistor at a gate, to the input buffer unit at a drain, and to a ground line at a source thereof. The method of claim 4, wherein The current sink unit, A third NMOS transistor configured to receive the second control signal at a gate and apply the driving signal to a drain; And And a fourth NMOS transistor connected to a gate of the source of the third NMOS transistor, a drain thereof to the input buffer unit, and a source of the third NMOS transistor connected to a ground line.

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