JP2014093635A - Analog switch circuit and electric apparatus having the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an analog switch circuit that accurately transmits a signal between an input terminal and an output terminal while protecting a control electrode of a transistor from overvoltage.SOLUTION: An analog switch circuit 1 includes: an NMOS transistor M1 having a drain connected to an input terminal IN; a PMOS transistor SW1 having a source and a drain connected to a power supply node VDD and a gate of the NMOS transistor M1, respectively, and a gate connected to a control terminal CTRL; a PMOS transistor QP having a drain connected to a reference node VSS, and a gate connected to a source of the NMOS transistor M1; and a constant voltage circuit 21 connected to the gate of the NMOS transistor M1 and a source of the PMOS transistor QP to generate a constant voltage VC. The constant voltage VC is smaller than a difference between a gate-source withstanding voltage of the NMOS transistor M1 and a gate-source voltage VGS.

Description

  The present invention relates to an analog switch circuit and an electric device including the same.

  Various configurations have been proposed for analog switch circuits. For example, Japanese Unexamined Patent Application Publication No. 2007-295209 (Patent Document 1) discloses an analog switch circuit including two MOS transistors connected in series and a protection circuit for protecting the gates of the MOS transistors from overvoltage. .

  According to the analog switch circuit of Patent Document 1, the first and second MOS transistors are connected in series between the input terminal and the output terminal. The gates of the first and second MOS transistors are commonly connected to the first switch control terminal. The back gates of the first and second MOS transistors are connected to the second switch control terminal. The second switch control terminal is a connection point between the first and second MOS transistors. Impedance means (for example, a resistor) is connected between the first switch control terminal and the second switch control terminal. The control circuit controls the current flowing through the resistor so that the voltage between the terminals of the resistor does not exceed the gate-source breakdown voltage of each of the first and second MOS transistors.

JP 2007-295209 A

  However, in the analog switch circuit of Patent Document 1, a resistor is connected to a connection point (second switch control terminal) of the first and second MOS transistors. Therefore, the current flowing through the resistor is mixed with the current flowing through the first and second MOS transistors through the connection point. Thereby, the current value is different between the current input to the input terminal and the current output from the output terminal. Therefore, the analog switch circuit disclosed in Patent Document 1 may not be able to accurately transmit a signal between the input terminal and the output terminal.

  An object of the present invention is to provide an analog switch circuit capable of accurately transmitting a signal between an input terminal and an output terminal while protecting a control electrode of a transistor from an overvoltage.

  According to one aspect of the present invention, the analog switch circuit includes an input terminal, an output terminal, a control terminal, first to third transistors, and a constant voltage circuit. The first transistor of the first conductivity type has a first electrode electrically connected to the input terminal, a second electrode electrically connected to the output terminal, and a control electrode. A second transistor of the second conductivity type has a first and second electrodes electrically connected to the first voltage node and the control electrode of the first transistor, respectively, and a control electrically connected to the control terminal. Electrode. The third transistor of the second conductivity type includes a first electrode, a second electrode electrically connected to the second voltage node, and a control electrode electrically connected to the second electrode of the first transistor And have. The constant voltage circuit is electrically connected to the control electrode of the first transistor and the first electrode of the third transistor to generate a constant voltage. A potential difference exists between the first voltage node and the second voltage node. The constant voltage is determined to be smaller than the difference between the withstand voltage between the control electrode and the second electrode of the first transistor and the voltage between the control electrode and the first electrode of the third transistor.

  Preferably, the analog switch circuit further includes a fourth transistor of the first conductivity type. The fourth transistor includes first and second electrodes electrically connected to the output terminal and the second electrode of the first transistor, respectively, and a control electrode electrically connected to the control electrode of the first transistor Have

  Preferably, the analog switch circuit is electrically connected to the control electrode of the first transistor, and removes the charge of the control electrode of the first transistor when the second transistor is off. A circuit and a second charge removal circuit that is electrically connected to the control electrode of the third transistor and removes the charge of the control electrode of the third transistor when the second transistor is off. .

  Preferably, the analog switch circuit is electrically connected to the control electrode of the first transistor and the control electrode of the fourth transistor, and when the second transistor is off, A first charge removal circuit for removing the charge of the control electrode of the transistor 4 and the control of the third transistor when electrically connected to the control electrode of the third transistor and the second transistor is off And a second charge removal circuit for removing the charge of the electrode.

  Preferably, the first charge removal circuit includes a first conductivity type fifth transistor. The second charge removal circuit includes a sixth transistor of the first conductivity type. The analog switch circuit further includes fifth and sixth transistors each having a first conductivity type. The fifth transistor has first and second electrodes electrically connected to the second electrode and the second voltage node of the second transistor, respectively, and a control electrode electrically connected to the control terminal. . The sixth transistor has first and second electrodes electrically connected to the control electrode of the third transistor and the second voltage node, respectively, and a control electrode electrically connected to the control terminal.

  Preferably, the constant voltage circuit includes an n-type transistor and a series circuit having a first resistor and a second resistor connected in series. The n-type transistor has first and second electrodes electrically connected to the control electrode of the first transistor and the first electrode of the third transistor, respectively, and a control electrode. A series circuit is connected between the first and second electrodes of the n-type transistor. The control electrode of the n-type transistor is electrically connected to the connection point of the first and second resistors.

  Preferably, the constant voltage circuit includes a Zener diode. The zener diode has a cathode and an anode electrically connected to the control electrode of the first transistor and the first electrode of the third transistor, respectively.

  Preferably, the constant voltage circuit further includes a Zener diode. The zener diode has a cathode and an anode electrically connected to the control electrode of the first transistor and the first electrode of the third transistor, respectively.

  According to another aspect of the present invention, an electrical device includes an analog switch circuit, a transmission circuit that sends a signal to the analog switch circuit, a reception circuit that receives a signal from the analog switch circuit, and a control circuit that controls the analog switch circuit; Is provided. The analog switch circuit includes an input terminal electrically connected to the transmission circuit, an output terminal electrically connected to the reception circuit, a control terminal electrically connected to the control circuit, and first to third A transistor and a constant voltage circuit are provided. The first transistor of the first conductivity type includes a first electrode that is electrically connected to the input terminal, a second electrode, and a control electrode. A second transistor of the second conductivity type has a first and second electrodes electrically connected to the first voltage node and the control electrode of the first transistor, respectively, and a control electrically connected to the control terminal. Electrode. The third transistor of the second conductivity type includes a first electrode, a second electrode electrically connected to the second voltage node, and a control electrode electrically connected to the second electrode of the first transistor And have. The constant voltage circuit is electrically connected to the control electrode of the first transistor and the first electrode of the third transistor to generate a constant voltage. A potential difference exists between the first voltage node and the second voltage node. The constant voltage is determined to be smaller than the difference between the withstand voltage between the control electrode and the second electrode of the first transistor and the voltage between the control electrode and the first electrode of the third transistor.

  According to the present invention, it is possible to accurately transmit a signal between the input terminal and the output terminal while protecting the control electrode of the transistor from overvoltage.

It is a block diagram which shows the schematic structure of the electric equipment provided with the analog switch circuit based on this invention. 1 is a circuit diagram showing a configuration of an analog switch circuit according to a first embodiment of the present invention. 3 is a timing chart for explaining the operation of the analog switch circuit shown in FIG. 2. FIG. 3 is a circuit diagram showing another configuration of a constant voltage circuit included in the analog switch circuit shown in FIG. 2. FIG. 4 is a circuit diagram showing another configuration of a third transistor included in the analog switch circuit shown in FIG. 2. It is a circuit diagram which shows the structure of the analog switch circuit which concerns on Embodiment 2 of this invention. 7 is a timing chart for explaining the operation of the analog switch circuit shown in FIG. 6. It is a circuit diagram which shows the structure of the analog switch circuit which concerns on Embodiment 3 of this invention. FIG. 9 is a timing chart for explaining the operation of the analog switch circuit shown in FIG. 8. FIG. It is a circuit diagram which shows the structure of the analog switch circuit which concerns on Embodiment 4 of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same or equivalent part in a figure, and the description is not repeated.

[Embodiment 1]
FIG. 1 is a block diagram showing a schematic configuration of an electrical apparatus provided with an analog switch circuit according to the present invention. Referring to FIG. 1, electrical device 100 includes a motor M, an inverter circuit 101, a comparator circuit 102, a logic circuit 103, and analog switch circuits 1 to 3. Inverter circuit 101 includes switches Q1-Q6 and a resistor R. The inverter circuit 101, the comparator circuit 102, and the logic circuit 103 are examples of the “transmission circuit”, “reception circuit”, and “control circuit” according to the present invention, respectively. The configuration of the “electric device” according to the present invention is not limited to the configuration shown in FIG.

  The inverter circuit 101 is provided with a series circuit including a switch Q1 and a switch Q2 connected in series. This series circuit is connected between a voltage node that supplies power supply voltage VDD (hereinafter referred to as a power supply node) and a voltage node that applies reference potential VSS (hereinafter referred to as a reference node). The power supply voltage VDD is 24V, for example. Reference potential VSS is, for example, a ground potential. However, the voltage values of these voltage nodes are not limited to the above.

  Similarly, a series circuit including switches Q3 and Q4 connected in series and a series circuit including switches Q5 and Q6 connected in series are connected between the power supply node and the reference node. A resistor R is connected between the connection point of the switches Q2, Q4, Q6 and the reference node. Note that the resistor R may not be provided.

  The motor M is, for example, a three-phase brushless motor. The U-phase line, V-phase line, and W-phase line of the motor M are electrically connected to the midpoint between the switches Q1 and Q2, the midpoint between the switches Q3 and Q4, and the midpoint between the switches Q5 and Q6, respectively. Connected. Further, the input terminals IN (see FIG. 2) of the analog switch circuits 1 to 3 are electrically connected to the U-phase line, the V-phase line, and the W-phase line of the motor M, respectively. The output terminals OUT of the analog switch circuits 1 to 3 are all electrically connected to the non-inverting input terminal of the comparator circuit 102. The inverting input terminal of the comparator circuit 102 receives the midpoint potential COM of the motor M. The comparator circuit 102 compares the voltage at the non-inverting input terminal with the midpoint potential COM and outputs a control signal. This control signal is input to the logic circuit 103. Note that the input to the inverting input terminal and the input to the non-inverting input terminal in the comparator circuit 102 may be interchanged. Further, resistors may be connected between the U-phase line, the V-phase line, and the W-phase line of the motor M and the input terminals IN of the analog switch circuits 1 to 3, respectively.

  Based on the control signal from the comparator circuit 102, the logic circuit 103 outputs a control signal for controlling the switches Q1 to Q6 independently of each other to the inverter circuit 101. Inverter circuit 101 generates AC power by opening and closing switches Q <b> 1 to Q <b> 6 and outputs the generated AC power to motor M. The logic circuit 103 outputs the control signals G1 to G3 to the control terminals CTRL (see FIG. 2) of the analog switch circuits 1 to 3, respectively. Analog switch circuits 1 to 3 switch the connection between U-phase line, V-phase line, and W-phase line of motor M and comparator circuit 102 based on control signals G1 to G3, respectively. Hereinafter, the analog switch circuit 1 among the analog switch circuits 1 to 3 will be described representatively. The configuration of the analog switch circuits 2 and 3 is the same as the configuration of the analog switch circuit 1.

  FIG. 2 is a circuit diagram showing a configuration of the analog switch circuit 1 according to Embodiment 1 of the present invention. 1 and 2, the analog switch circuit 1 includes an input terminal IN, an output terminal OUT, a control terminal CTRL, an N (N-type) MOS transistor (first transistor) M1, and P ( P-type) MOS transistor (second transistor) SW1, PMOS transistor (third transistor) QP, NMOS transistor (fourth transistor) M2, constant voltage circuit 21, charge removal circuits 31, 32 Is provided. Diodes D1 and D2 are parasitic diodes of NMOS transistors M1 and M2, respectively.

  The input terminal IN is electrically connected to the midpoint between the switch Q1 and the switch Q2. The output terminal OUT is electrically connected to the non-inverting input terminal of the comparator circuit 102. The control terminal CTRL is electrically connected to the logic circuit 103 and receives the control signal G1.

  The source of the PMOS transistor SW1 is electrically connected to the power supply node. The gate of the PMOS transistor SW1 receives the control signal G1 from the control terminal CTRL.

  The gates of the NMOS transistors M1 and M2 are electrically connected to the drain of the PMOS transistor SW1. The sources of the NMOS transistors M1 and M2 are electrically connected to back gates (not shown) of the NMOS transistors M1 and M2, respectively. The drain of the NMOS transistor M1 is electrically connected to the input terminal IN. The drain of the NMOS transistor M2 is electrically connected to the output terminal OUT. The sources of the NMOS transistors M1 and M2 are electrically connected. Thereby, the anodes of the diodes D1 and D2 are electrically connected to each other, and the forward directions are opposite to each other. Therefore, it is possible to prevent a current from flowing between the input terminal IN and the output terminal OUT when each of the NMOS transistors M1 and M2 is off.

  The drain of the PMOS transistor QP is electrically connected to the reference node. The gate of the PMOS transistor QP is electrically connected to the source of the NMOS transistor M1. Charge removal circuits 31 and 32 are connected to the gates of the NMOS transistors M1 and M2 and the gate of the PMOS transistor QP. When the PMOS transistor SW1 is off, each of the charge removal circuits 31 and 32 removes the charge of the gate of the connected transistor. Thereby, the NMOS transistors M1 and M2 and the PMOS transistor QP can be turned off.

  One end of the constant voltage circuit 21 is electrically connected to the gate of the NMOS transistor M1. The other end of the constant voltage circuit 21 is electrically connected to the source of the PMOS transistor QP. The constant voltage circuit 21 generates a constant voltage VC between both ends. More specifically, the constant voltage circuit 21 includes an NMOS transistor Tr and resistors Ra and Rb. The drain-source voltage of the NMOS transistor Tr is determined by the ratio of the resistor Ra and the resistor Rb depending on the gate-source voltage. By adjusting the resistance values of the resistors Ra and Rb, the drain-source voltage and the gate-source voltage are determined in appropriate ranges.

  A constant voltage circuit 21 is provided between the gate and source of the NMOS transistors M1 and M2. Therefore, the gate-source voltages of the NMOS transistors M1 and M2 are clamped to the constant voltage VC by the constant voltage circuit 21. The constant voltage VC generated by the constant voltage circuit 21 is set to be smaller than the difference between the gate-source withstand voltage of each of the NMOS transistors M1 and M2 and the gate-source voltage VGS of the PMOS transistor QP. Therefore, even when the power supply voltage VDD fluctuates when the PMOS transistor SW1 is on or when the voltage VIN at the input terminal IN fluctuates when the NMOS transistor M1 is on, each of the NMOS transistors M1 and M2 The gate can be protected from overvoltage.

  In the first embodiment, the power supply node corresponds to the “first voltage node” according to the present invention, and the reference node corresponds to the “second voltage node”. The NMOS transistor and the PMOS transistor correspond to the “first conductivity type” and “second conductivity type” transistors according to the present invention, respectively. In the NMOS transistor, the drain and the source correspond to the “first electrode” and the “second electrode” according to the present invention, respectively. On the other hand, in the PMOS transistor, the source and the drain correspond to the “first electrode” and the “second electrode”, respectively. Regardless of the conductivity type of the transistor, the gate corresponds to the “control electrode” according to the present invention.

  FIG. 3 is a timing chart for explaining the operation of the analog switch circuit 1 shown in FIG. Referring to FIGS. 2 and 3, in control signal G <b> 1, an H (high) level period of 1/3 period corresponding to the rotation of a rotor (not shown) of motor M (see FIG. 1), The 2/3 period L (low) level period is repeated. A time at which a predetermined time has elapsed after the control signal G1 is input to the control terminal CTRL is represented by 0 as a start time.

  In the following description, the gate-source voltage refers to the gate potential with reference to the source potential in common for the NMOS transistor and the PMOS transistor. Therefore, the gate-source voltage in the NMOS transistor exceeds the gate threshold voltage when it is at the H level. On the other hand, the gate-source voltage in the PMOS transistor exceeds the gate threshold voltage when it is at the L level.

  At the time when t1 has elapsed from the start time, the potential of the control signal G1 switches from the L level to the H level. For this reason, the PMOS transistor SW1 is turned off. As a result, the power supply voltage VDD is not applied to the gates of the NMOS transistors M1 and M2. Therefore, the gate-source voltage of the NMOS transistors M1 and M2 is switched from the H level to the L level. Therefore, both NMOS transistors M1 and M2 are turned off. That is, the analog switch circuit 1 shifts from the conductive state to the non-conductive state.

  At this time, the voltage VIN of the input terminal IN is not applied to the gate of the PMOS transistor QP. Therefore, the gate-source voltage VGS of the PMOS transistor QP is lower than the gate threshold voltage (H level). Therefore, the PMOS transistor QP is turned off.

  At the time when t2 has elapsed from the start time, the level of the control signal G1 switches from the H level to the L level. For this reason, the PMOS transistor SW1 is turned on. As a result, the power supply voltage VDD is applied to the gates of the NMOS transistors M1 and M2. Therefore, the gate-source voltage of the NMOS transistors M1 and M2 is switched from the L level to the H level. Therefore, both NMOS transistors M1 and M2 are turned on. That is, the analog switch circuit 1 shifts from the non-conductive state to the conductive state.

  At this time, the voltage of the gate of the PMOS transistor QP becomes substantially equal to the voltage VIN of the input terminal IN. Therefore, the gate-source voltage VGS of the PMOS transistor QP becomes VDD-VC-VIN. This voltage value exceeds the gate threshold voltage of the PMOS transistor QP (L level). Therefore, the PMOS transistor QP is turned on. When the PMOS transistor QP is turned on, a current flowing from the power supply node to the constant voltage circuit 21 flows to the reference node. This prevents this current from being mixed with the current flowing between the NMOS transistors M1 and M2.

  At the time when t3 has elapsed from the start time, the level of the control signal G1 switches from the L level to the H level. Since the operation of the analog switch circuit 1 at this time is the same as the operation at the time when t1 has elapsed from the start time, detailed description will not be repeated.

  As described above, according to the present embodiment, the constant voltage circuit 21 is provided between the gates and the sources of the NMOS transistors M1 and M2. Therefore, the gates of the NMOS transistors M1 and M2 can be protected from overvoltage.

  As in the configuration disclosed in Patent Document 1, it is conceivable to use a resistor instead of the PMOS transistor QP. The resistor is connected in parallel to the constant voltage circuit 21 between the gate and source of the NMOS transistor M1. Even in this configuration, the gates of the NMOS transistors M1 and M2 can be protected from overvoltage. However, the current flowing through the resistor is mixed with the current flowing through the NMOS transistors M1 and M2. On the other hand, according to the present embodiment, the current flowing between the source and drain of the PMOS transistor QP is not mixed with the current flowing through the NMOS transistors M1 and M2. Therefore, according to the present embodiment, a signal can be accurately transmitted between the input terminal IN and the output terminal OUT.

  The case where the analog switch circuit 1 includes two NMOS transistors has been described. However, the present invention is applicable even when the analog switch circuit 1 is provided with only the NMOS transistor M1. In this case, the source of the NMOS transistor M1 is electrically connected to the output terminal OUT.

[Modification]
The configuration of each part of the analog switch circuit 1 is not limited to the configuration shown in FIG. Even when the analog switch circuit has a configuration different from that in FIG. 2, the same effects as those in the configuration shown in FIG. 2 can be obtained.

  FIG. 4 is a circuit diagram showing another configuration of the constant voltage circuit included in analog switching circuit 1 shown in FIG. Referring to FIG. 4A, the analog switch circuit 1 includes a constant voltage circuit 22 in place of the constant voltage circuit 21. The constant voltage circuit 22 includes a Zener diode ZD. Zener diode ZD has a cathode and an anode electrically connected to the gate of NMOS transistor M1 (see FIG. 2) and the source of PMOS transistor QP, respectively. The sum of the breakdown voltage VBR of the Zener diode ZD and the gate-source voltage VGS of the PMOS transistor QP is smaller than the withstand voltage between the gates and sources of the NMOS transistors M1 and M2. Also with this configuration, the gates of the NMOS transistors M1 and M2 can be protected from overvoltage.

  4B, the analog switch circuit 1 may include a constant voltage circuit 23 instead of the constant voltage circuit 21. In the constant voltage circuit 23, a Zener diode ZD is connected to the constant voltage circuit 21 in preparation for a rapid increase in the power supply voltage VDD.

  The constant voltage VC generated by the constant voltage circuit 21 is smaller than the breakdown voltage VBR of the Zener diode ZD. Therefore, each of the gate-source voltages of the NMOS transistors M1 and M2 is normally clamped to the constant voltage VC by the constant voltage circuit 21. On the other hand, the breakdown voltage VBR is lower than the withstand voltage between the drain and source of the NMOS transistor Tr. When the power supply voltage VDD increases rapidly, the Zener diode ZD breaks down. Thereby, the NMOS transistor Tr can be protected.

  FIG. 5 is a circuit diagram showing another configuration of the PMOS transistor QP included in the analog switch circuit 1 shown in FIG. Referring to FIG. 5A, the analog switch circuit 1 includes a PNP transistor Qa instead of the PMOS transistor QP. Also, referring to FIG. 5B, Darlington-connected PNP transistors Qa and Qb may be used. Even when the PNP transistor is used, it is possible to prevent the current flowing from the NMOS transistors M1 and M2 from being mixed with the current from other than the input terminal IN, similarly to the PMOS transistor.

[Embodiment 2]
According to the second embodiment, compared with the first embodiment, an analog switch circuit that shifts from a conductive state to a non-conductive state at high speed is realized.

  FIG. 6 is a circuit diagram showing a configuration of an analog switch circuit according to Embodiment 2 of the present invention. Referring to FIG. 6, the charge removal circuit 31 includes an NMOS transistor (fifth transistor) SW2 and a resistor R2. The charge removal circuit 32 includes an NMOS transistor (sixth transistor) SW3 and a resistor R3. In this respect, the analog switch circuit 12 is different from the analog switch circuit 1 (see FIG. 2) according to the first embodiment. The resistors R2 and R3 are current limiting resistors. Therefore, the resistors R2 and R3 need not be provided.

  The drain of the NMOS transistor SW2 is electrically connected to the drain of the PMOS transistor SW1. The sources of the NMOS transistors SW2 and SW3 are electrically connected to the reference node via resistors R2 and R3, respectively. The drain of the NMOS transistor SW3 is electrically connected to the gate of the PMOS transistor QP. The gates of the NMOS transistors SW2 and SW3 receive the control signal G1 from the control terminal CTRL. Since the other configuration of the analog switch circuit 12 is the same as that of the analog switch circuit 1, detailed description will not be repeated.

  FIG. 7 is a timing chart for explaining the operation of the analog switch circuit 12 shown in FIG. FIG. 7 is contrasted with FIG.

  6 and 7, the level of control signal G1 switches from the L level to the H level at the time when t1 has elapsed from the start time. For this reason, the PMOS transistor SW1 is turned off. On the other hand, the NMOS transistors SW2 and SW3 are both turned on. Therefore, the gates of the NMOS transistors M1 and M2 are pulled down to the reference potential VSS. This increases the switching speed of the NMOS transistors M1, M2 from on to off as compared with the first embodiment.

  At this time, the source and gate of the PMOS transistor QP are both pulled down to the reference potential VSS. Therefore, the gate-source voltage VGS of the PMOS transistor QP is lower than the gate threshold voltage. Therefore, the PMOS transistor QP is turned off.

  At the time when t2 has elapsed from the start time, the level of the control signal G1 switches from the H level to the L level. For this reason, the PMOS transistor SW1 is turned on. On the other hand, the NMOS transistors SW2 and SW3 are both turned off. As a result, the gates of the NMOS transistors M1 and M2 are pulled up to the power supply voltage VDD. Therefore, the gate-source voltages of the NMOS transistors M1 and M2 are switched from the L level to the H level. Therefore, both NMOS transistors M1 and M2 are turned on.

  At this time, the voltage of the gate of the PMOS transistor QP becomes substantially equal to the voltage VIN. Therefore, the gate-source voltage VGS of the PMOS transistor QP becomes VDD-VC-VIN. This voltage value exceeds the gate threshold voltage of the PMOS transistor QP. Therefore, the PMOS transistor QP is turned on.

  At the time when t3 has elapsed from the start time, the level of the control signal G1 switches from the L level to the H level. Since the operation of the analog switch circuit 12 at this time is the same as the operation at the time when t1 has elapsed from the start time, detailed description will not be repeated.

  According to the second embodiment, when the analog switch circuit 12 is switched from the conductive state to the non-conductive state, each of the NMOS transistors SW2 and SW3 is turned on. Therefore, the gates of the NMOS transistors M1 and M2 are pulled down to the reference potential VSS. This increases the switching speed of the NMOS transistors M1 and M2 from on to off. Further, the on-resistances of the NMOS transistors SW2 and SW3 are smaller than the on-resistance of the PMOS transistor of the same size. For this reason, the NMOS transistors SW2 and SW3 can remove charges faster than the PMOS transistors of the same size. Therefore, it is possible to turn off the NMOS transistors M1 and M2 at a higher speed than when using a PMOS transistor in the charge removal circuit. Therefore, according to the second embodiment, the analog switch circuit can be switched from the conductive state to the non-conductive state at a higher speed than in the first embodiment.

[Embodiment 3]
In the first and second embodiments, an NMOS transistor is used for switching between the conductive state and the non-conductive state of the analog switch circuit. However, a PMOS transistor may be used instead of the NMOS transistor.

  FIG. 8 is a circuit diagram showing a configuration of an analog switch circuit according to Embodiment 3 of the present invention. Referring to FIG. 8, analog switch circuit 13 includes PMOS transistors M3 and M4 in place of NMOS transistors M1 and M2. Diodes D3 and D4 are parasitic diodes of PMOS transistors M3 and M4, respectively. The analog switch circuit 13 includes NMOS transistors SW4 and QN instead of the PMOS transistors SW1 and QP. In the third embodiment, the PMOS transistors M3 and M4 correspond to the “first transistor” and the “fourth transistor” according to the present invention, respectively. The NMOS transistors SW4 and QN correspond to the “second transistor” and the “third transistor”, respectively.

  Further, in the third embodiment, contrary to the first embodiment, the reference node corresponds to the “first voltage node” according to the present invention, and the power supply node corresponds to the “second voltage node”. The PMOS transistor and the NMOS transistor correspond to the “first conductivity type” and “second conductivity type” transistors according to the present invention, respectively. In these points, the analog switch circuit 13 is different from the analog switch circuit 1 according to the first embodiment (see FIG. 2).

  The gates of the PMOS transistors M3 and M4 are electrically connected to the drain of the NMOS transistor SW4. The source of the NMOS transistor SW4 is electrically connected to the reference node. The source of the PMOS transistor M3 is electrically connected to the input terminal IN. The source of the PMOS transistor M4 is electrically connected to the output terminal OUT. The drains of the PMOS transistors M3 and M4 are electrically connected. Accordingly, the anodes of the diodes D3 and D4 are electrically connected to each other, and the forward directions are opposite to each other. Therefore, it is possible to prevent a current from flowing between the input terminal IN and the output terminal OUT when the PMOS transistors M3 and M4 are off.

  The drain of the NMOS transistor QN is electrically connected to the power supply node. The source of the NMOS transistor QN is electrically connected to one end of the constant voltage circuit 21. The gate of the NMOS transistor QN is electrically connected to the drain of the PMOS transistor M3. The other end of the constant voltage circuit 21 is electrically connected to the gate of the PMOS transistor M3. The other configuration of analog switch circuit 13 is the same as the configuration of analog switch circuit 1 according to Embodiment 1 (see FIG. 2), and thus detailed description will not be repeated.

  FIG. 9 is a timing chart for explaining the operation of the analog switch circuit 13 shown in FIG. FIG. 9 is contrasted with FIG.

  8 and 9, the level of control signal G1 switches from the L level to the H level at the time when t1 has elapsed from the start time. For this reason, the NMOS transistor SW4 is turned on. As a result, the voltage at the gate of each of the PMOS transistors M3 and M4 becomes substantially equal to the reference potential VSS. Therefore, the gate-source voltages of the PMOS transistors M3 and M4 are switched from the H level to the L level. Therefore, both the PMOS transistors M3 and M4 are turned on. That is, the analog switch circuit 13 shifts from the non-conductive state to the conductive state.

  At this time, the voltage of the gate of the NMOS transistor QN becomes substantially equal to the voltage VIN of the input terminal IN. Therefore, the gate-source voltage VGS of the NMOS transistor QN becomes VIN-VC-VSS. This voltage value exceeds the gate threshold voltage of the NMOS transistor QN (H level). Therefore, the NMOS transistor QN is turned on.

  At the time when t2 has elapsed from the start time, the level of the control signal G1 switches from the H level to the L level. For this reason, the NMOS transistor SW4 is turned off. As a result, the gate-source voltages of the PMOS transistors M3 and M4 are switched from the L level to the H level. Therefore, both the PMOS transistors M3 and M4 are turned off. That is, the analog switch circuit 13 shifts from the conductive state to the non-conductive state.

  At this time, the voltage VIN is not applied to the gate of the NMOS transistor QN. Therefore, the gate-source voltage VGS of the NMOS transistor QN is lower than the gate threshold voltage (L level). Therefore, the NMOS transistor QN is turned off.

  At the time when t3 has elapsed from the start time, the potential of the control signal G1 switches from the L level to the H level. Since the operation of the analog switch circuit 13 at this time is the same as the operation at the time when t1 has elapsed from the start time, detailed description will not be repeated.

  According to the third embodiment, even in an analog switch circuit using PMOS transistors, the gates of these PMOS transistors can be protected from overvoltage. In addition, it is possible to prevent current from other than the input terminal IN from being mixed with the current flowing through the PMOS transistors M3 and M4.

[Embodiment 4]
Also in the analog switch circuit using the PMOS transistor, as in the second embodiment, it is possible to shift from the conductive state to the non-conductive state at high speed.

  FIG. 10 is a circuit diagram showing a configuration of an analog switch circuit according to Embodiment 4 of the present invention. Referring to FIG. 10, charge removal circuit 31 includes a PMOS transistor SW5 and a resistor R5. The charge removal circuit 32 includes a PMOS transistor SW6 and a resistor R6. In the fourth embodiment, the PMOS transistors SW5 and SW6 correspond to the “fifth transistor” and the “sixth transistor” according to the present invention, respectively. In this respect, the analog switch circuit 14 is different from the analog switch circuit 13 according to the third embodiment (see FIG. 8).

  The drain of the PMOS transistor SW5 is electrically connected to the drain of the NMOS transistor SW4. The sources of the PMOS transistors SW5 and SW6 are electrically connected to the power supply node via resistors R5 and R6, respectively. The drain of the PMOS transistor SW6 is electrically connected to the gate of the NMOS transistor QN. The gates of the PMOS transistors SW5 and SW6 receive the control signal G1 from the control terminal CTRL. Since the other configuration of analog switch circuit 14 is the same as the configuration of analog switch circuit 13 according to Embodiment 3 (see FIG. 8), detailed description will not be repeated.

  The operation of the analog switch circuit 14 in comparison with the analog switch circuit 13 is the same as the operation of the analog switch circuit 12 in comparison with the analog switch circuit 1 (see FIG. 2) (see FIG. 7). Do not repeat the explanation.

  It should be noted that the second to fourth embodiments can be modified in the same manner as the modified example related to the first embodiment (see FIGS. 4 and 5). In this case, an NPN transistor or a PNP transistor can be appropriately employed as the bipolar transistor in FIG.

  The electric device 100 is, for example, a copying machine such as a printer, an air conditioner such as an air conditioner, a fan such as a vacuum cleaner, a washing dryer, or a fan. However, the electric device 100 is not limited to these. The analog switch circuit according to the present invention is not limited to the motor drive control described with reference to FIG.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1-3, 12-14 Analog switch circuit, IN input terminal, OUT output terminal, CTRL control terminal, M3, M4, QP, SW1, SW5, SW6 PMOS transistor, M1, M2, QN, SW2-SW4, Tr NMOS transistor , Qa, Qb PNP transistor, D1, D2 diode, 21-23 constant voltage circuit, R, Ra, Rb, R2, R3, R5, R6 resistor, ZD Zener diode, 31, 32 Charge removal circuit, 100 Electrical equipment, M Motor, 101 inverter circuit, 102 comparator circuit, 103 logic circuit, Q1-Q6 switch.

Claims (9)

An analog switch circuit,
An input terminal;
An output terminal;
A control terminal;
A first transistor of a first conductivity type having a first electrode electrically connected to the input terminal, a second electrode electrically connected to the output terminal, and a control electrode;
A second conductivity type having first and second electrodes electrically connected to a first voltage node and a control electrode of the first transistor, respectively, and a control electrode electrically connected to the control terminal A second transistor of
A first electrode; a second electrode electrically connected to a second voltage node; and a control electrode electrically connected to a second electrode of the first transistor. A third transistor;
A constant voltage circuit that is electrically connected to the control electrode of the first transistor and the first electrode of the third transistor to generate a constant voltage;
A potential difference exists between the first voltage node and the second voltage node,
The analog switch circuit, wherein the constant voltage is determined to be smaller than a difference between a withstand voltage between the control electrode and the second electrode of the first transistor and a voltage between the control electrode and the first electrode of the third transistor. . A fourth transistor of the first conductivity type;
The fourth transistor is electrically connected to the output terminal and the second electrode of the first transistor, respectively, and to the control electrode of the first transistor. The analog switch circuit according to claim 1, further comprising a control electrode. A first charge removal circuit that is electrically connected to the control electrode of the first transistor and removes the charge of the control electrode of the first transistor when the second transistor is off;
A second charge removal circuit that is electrically connected to the control electrode of the third transistor and removes the charge of the control electrode of the third transistor when the second transistor is off; The analog switch circuit according to claim 1. The control electrode of the first transistor and the fourth transistor when electrically connected to the control electrode of the first transistor and the control electrode of the fourth transistor and the second transistor is off A first charge removal circuit for removing the charge of the control electrode;
A second charge removal circuit that is electrically connected to the control electrode of the third transistor and removes the charge of the control electrode of the third transistor when the second transistor is off; The analog switch circuit according to claim 2. The first charge removal circuit includes a fifth transistor of the first conductivity type,
The second charge removal circuit includes a sixth transistor of the first conductivity type,
The fifth transistor includes a first electrode and a second electrode electrically connected to the second electrode of the second transistor and the second voltage node, respectively, and a control electrically connected to the control terminal. An electrode,
The sixth transistor includes first and second electrodes electrically connected to a control electrode of the third transistor and the second voltage node, respectively, and a control electrode electrically connected to the control terminal The analog switch circuit according to claim 4, comprising: The constant voltage circuit includes an n-type transistor, and a series circuit having a first resistor and a second resistor connected in series,
The n-type transistor has first and second electrodes electrically connected to a control electrode of the first transistor and a first electrode of the third transistor, respectively, and a control electrode,
The series circuit is connected between first and second electrodes of the n-type transistor,
The analog switch circuit according to claim 1, wherein a control electrode of the n-type transistor is electrically connected to a connection point of the first and second resistors. The constant voltage circuit includes a Zener diode,
6. The Zener diode according to claim 1, wherein the Zener diode has a cathode and an anode that are electrically connected to a control electrode of the first transistor and a first electrode of the third transistor, respectively. Analog switch circuit. The constant voltage circuit further includes a Zener diode,
The analog switch circuit according to claim 6, wherein the Zener diode has a cathode and an anode electrically connected to a control electrode of the first transistor and a first electrode of the third transistor, respectively. An analog switch circuit;
A transmission circuit for sending a signal to the analog switch circuit;
A receiving circuit for receiving a signal from the analog switch circuit;
An electric device comprising a control circuit for controlling the analog switch circuit,
The analog switch circuit is:
An input terminal electrically connected to the transmission circuit;
An output terminal electrically connected to the receiving circuit;
A control terminal electrically connected to the control circuit;
A first transistor of a first conductivity type having a first electrode electrically connected to the input terminal, a second electrode electrically connected to the output terminal, and a control electrode;
A second conductivity type having first and second electrodes electrically connected to a first voltage node and a control electrode of the first transistor, respectively, and a control electrode electrically connected to the control terminal A second transistor of
A first electrode; a second electrode electrically connected to a second voltage node; and a control electrode electrically connected to a second electrode of the first transistor. A third transistor;
A constant voltage circuit that is electrically connected to the control electrode of the first transistor and the first electrode of the third transistor to generate a constant voltage;
A potential difference exists between the first voltage node and the second voltage node,
The constant voltage is determined to be smaller than a difference between a withstand voltage between the control electrode and the second electrode of the first transistor and a voltage between the control electrode and the first electrode of the third transistor, .

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