JP2007295209A - Analog switch circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an analog switch circuit in which size reduction and low loss are attained. <P>SOLUTION: A first MOSFET and a second MOSFET, of which the voltage resistance between a gate and a source is smaller than voltage resistance between the gate and a back gate are connected in series between a first terminal and a second terminal. The gates of the first and second MOSFETs are connected to a third terminal, in common. The back gates of the first and second MOSFETs are connected to a fourth terminal which is a mutual connecting point of the first and second MOSFETs. An impedance means is connected between the third terminal and the fourth terminal. A control circuit controls a current allowed to flow between the third terminal, and the fourth terminal and voltage generated in the impedance means is set to a voltage which is larger or smaller than the threshold voltage of the first and second MOSFETs, to open/close a current path between the first terminal and the second terminal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an analog switch circuit, and more particularly to a technique effective when applied to a high-voltage analog switch circuit composed of a MOSFET (insulated gate field effect transistor).

In an analog switch using a MOSFET, a current path is formed by a parasitic diode (body diode) even when the MOSFET is turned off. Therefore, the source-drain paths of the two MOSFETs are connected in series, the back gate is connected to the interconnection point, and the parasitic diodes are used so that currents flow in opposite directions. As an example in which an analog switch using such a MOSFET is described, there is JP-A-2003-243613.
JP 2003-243613 A

  FIG. 5 shows a circuit diagram of an analog switch circuit studied prior to the present invention. This analog switch circuit has a high voltage range (about 0V to 20V). The N-channel MOSFETs DMN51 and DMN52 operating as the analog switch (5) have the source-drain paths connected in series as described above. The gates of the MOSFETs MDN51 and MDN52 are connected in common and supplied with a switch control signal. This switch control signal is set to a high voltage (VS) that is equal to or higher than the input voltage (Va) to transmit the input voltage (Va), and controls the MOSFETs MDN51 and MDN52 on / off. The high-gate breakdown voltage P-channel MOSFETs DMP1 and DMP2 constitute a current mirror circuit (2), and the source of the high-voltage VS is supplied to the gates of the N-channel MOSFETs DMN51 and DMN52 that operate as the analog switch (5). The supplied switch control signal is formed.

  A control signal is supplied to an input terminal IN of a CMOS inverter circuit composed of a P-channel MOSFET MP1 and an N-channel MOSFET MN1 that operates at a power supply voltage VDD as low as about 5 V, and a high gate breakdown voltage N-channel MOSFET MDN1 is switched by the output signal of the CMOS inverter circuit. Control. A current I1 is formed by a current source that operates at the power supply voltage VDD, and is used as an input current of a current mirror circuit (3) including N-channel MOSFETs MN4 and MN3. The output current of the current mirror circuit (3) is supplied to the input side of the current mirror circuit (2) through the MOSFET DMN2 having a high gate breakdown voltage which is constantly turned on by the supply voltage VDD being supplied to the gate. . The drain of the MOSFET DMN1 is connected to the output side of the current mirror circuit (2). When the MOSFET DMN1 is turned off by the high level of the input signal supplied to the input terminal IN, the current I1 forms an analog switch (5) through the current mirror circuits (3) and (2). Since the gate voltages of the MOSFETs DMN51 and DMN52 are charged up, the gate voltages of the MOSFETs DMN51 and DMN52 rise to the high voltage VS and are turned on. When the MOSFET DMN1 is turned on by the low level of the input signal supplied to the input terminal IN, the current I1 flowing from the current mirror circuit (2) flows to form an analog switch (5). And the gate voltage of the DMN 52 are discharged, so that the gate voltages of the MOSFETs DMN51 and DMN52 are reduced to 0V and turned off.

As described above, the N-channel MOSFETs DMN51 and DMN52 constituting the analog switch (5) need to have a gate-source breakdown voltage and a gate-back gate breakdown voltage (referred to as gate breakdown voltage) higher than the VS voltage which is a high voltage. And The on-resistance (RDSON) of the switch at this time can be approximated by the following formula (1).
RDSON = 1 / [μ × Cox × (W / L) × (VGS−VTH0)] (1) where μ: mobility Cox: gate capacitance per unit area, VGS: gate-source voltage , VTH0; threshold voltage, L; gate effective length W; gate effective width. Cox in the above equation decreases in inverse proportion to the voltage of the gate breakdown voltage, and the on-resistance RDSON of the analog switch used in the high voltage region increases as the gate breakdown voltage increases.

  FIG. 6 shows the input / output characteristic diagram of FIG. Voltage Va is the input voltage of one electrode of the switch, and Vb is the output voltage of the other electrode of the switch. A dotted line indicates when the current flowing when the analog switch (5) is on is 0, and a solid line indicates when the current Isw flows. When the input voltage Va of the switch is increased from 0V, the output voltage Vb also increases linearly and becomes constant when it exceeds the allowable input range of the switch. When the maximum input voltage is VINmax, the threshold voltage of the MOSFETs DMN51 and DMN52 is VTH0 (HG), and the effective voltage (voltage loss at the analog switch) is Veff (HG), VINmax = VS− (VTH0 (HG ) + Veff (HG)) and VGS = VS-Va. When current does not flow through the analog switch (5) (Isw = current off), Vb≈Va, and when current flows through the analog switch (5) (Isw = current on), Vb≈Va −2 × (Isw × RDSON) = Va−Veff (HG)

  The MOSFETs DMN51 and DMN52 constituting the analog switch (5) need to have a structure that can withstand a high voltage that has a gate-source breakdown voltage and a gate-back gate breakdown voltage (referred to as a gate breakdown voltage) that exceed the usage range. Therefore, it is necessary to increase the breakdown voltage as described above by increasing the thickness of the gate oxide film. When the gate breakdown voltage is increased in this way, the above-mentioned Cox is reduced and the on-resistances (RDSON) of the MOSFETs DMN51 and DMN52 are increased. Therefore, in an analog switch that requires a low on-resistance, the size of the MOSFETs DMN51 and DMN52 (the effective gate width) ) Had to be increased.

  An object of the present invention is to provide an analog switch circuit that achieves miniaturization and low loss. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. Between the first terminal and the second terminal, a first MOSFET and a second MOSFET whose breakdown voltage between the gate and the source is smaller than the breakdown voltage between the gate and the back gate are connected in series. The gates of the first and second MOSFETs are commonly connected to a third terminal. The back gates of the first and second MOSFETs are connected to a fourth terminal that is an interconnection point of the first and second MOSFETs. Impedance means is connected between the third terminal and the fourth terminal. The current flowing between the third terminal and the fourth terminal is controlled by the control circuit so that the voltage generated in the impedance means is larger or smaller than the threshold voltage of the first and second MOSFETs. Open and close the current path between the first terminal and the second terminal.

  An analog switch can be configured using a MOSFET having a small source-gate breakdown voltage, and downsizing and low loss can be realized.

  FIG. 1 shows a circuit diagram of an embodiment of an analog switch circuit according to the present invention. In this analog switch circuit, the operating voltage range is directed to a high voltage region (about 0V to 20V) as described above. The N-channel MOSFETs DMN11 and DMN12 operating as the analog switch (1) have source-drain paths connected in series as described above. The back gates of the MOSFETs DMN11 and DMN12 are connected to their interconnection points so that body diodes (not shown) flow currents in opposite directions. The gates of the MOSFETs DMN11 and DMN12 are commonly connected to serve as a first switch control terminal. The interconnection point is a second switch control terminal, and a resistor R1 is connected between them. Currents Ia and Ib from a control circuit described below flow through the first switch control terminal and the second switch control terminal.

  Similarly to the above, a control signal is supplied to the input terminal IN of a CMOS inverter circuit composed of a P-channel MOSFET MP1 and an N-channel MOSFET MN1 operating at a low power supply voltage VDD of about 5V, and an N-channel having a high gate breakdown voltage is output by the output signal of this CMOS inverter circuit. The MOSFET DMN1 is switch-controlled. A current I1 is formed by a current source that operates at the power supply voltage VDD, and is used as an input current of a current mirror circuit (3) including N-channel MOSFETs MN4, MN3, and MN2. In this current mirror circuit (3), the gate and drain of the MOSFET MN4 are connected in common to form an input-side MOSFET, the MOSFET MN3 and MN2 are connected in common to the MOSFET MN4 and the gate and source, and the drains of the MOSFETs MN3 and MN2 are connected. A current corresponding to the current I1 is output. These MOSFETs MP1, MN1 to MN4 are constituted by low breakdown voltage MOSFETs that operate at, for example, a 5V power supply voltage VDD.

  In order to transmit the input voltage (Va) through the analog switch (1), a current mirror circuit (DMP1 and DMP2) having a high gate breakdown voltage and a high voltage (VS) higher than the input voltage (Va) is used as an operating voltage. 2) is provided. The output current of the MOSFET MN2 of the current mirror circuit (3) passes through the current mirror circuit (2) through the high gate breakdown voltage MOSFET DMN1 which is supplied to the gate to control the output signal of the CMOS inverter circuit. The current Ia is supplied to the first switch control terminal. The output current of the MOSFET MN3 of the current mirror circuit (3) is supplied to the second switch control terminal as the current Ib through the high gate breakdown voltage MOSFET DMN2 which is constantly supplied with the power supply voltage VDD to the gate and constantly turned on. Supplied.

  When the MOSFET DMN1 is turned off by the high level of the input signal supplied to the input terminal IN, the current Ia is not supplied to the first switch control terminal. Therefore, the current Ib flows until the gates of the MOSFETs DMN11 and DMN12 constituting the analog switch (1) become 0V. Then, the gate-source voltage VGS of the MOSFETs DMN11 and DMN12 constituting the analog switch (1) becomes 0V and is turned off. Thus, the resistor R1 provided between the first switch control terminal and the second switch control terminal short-circuits the gates and sources of the MOSFETs DMN11 and DMN12 so that they have the same potential and turn them off.

  When the MOSFET DMN1 is turned on by the low level of the input signal supplied to the input terminal IN, the current Ia is supplied to the first switch control terminal. Therefore, the current Ia flows through the resistor R1 provided between the first switch control terminal and the second switch control terminal, and a voltage drop generated there is applied between the gates and sources of the MOSFETs DMN11 and DMN12. become. By setting the voltage Ia × R1 to be equal to or higher than the threshold voltage of the MOSFETs DMN11 and DMN12, the MOSFETs DMN11 and DMN12 are turned on. For example, when Ib> Ia, current Isw + (Ib−Ia) flows through MOSFET DMN11 as shown in FIG. Conversely, when Ib <Ia, the current flowing through MOSFET DMN 12 is Isw + (Ia−Ib). Therefore, when Ia = Ib, the current Isw flows through the MOSFETs DMN11 and DMN12.

  Only the voltage set by the resistor R1 × Ia, which is set to the threshold voltage or higher, is applied between the gates and sources of the MOSFETs DMN11 and DMN12 constituting the analog switch (1). Thereby, a low breakdown voltage MOSFET having a gate-source breakdown voltage corresponding to the threshold voltage can be obtained. Such a MOSFET having a low breakdown voltage between the gate and the source can be formed thinner than the MOSFETs DMN51 and DMN52 whose gate insulating film has a high breakdown voltage as shown in FIG. . As a result, the gate-source voltage VGS, the gate capacitance Cox, and the threshold voltage VTH0 can be reduced as shown in the equation (1). With the circuit configuration shown in FIG. 1, the gate-source voltage VGS of the MOSFETs DMN11 and DMN12 constituting the analog switch (1) can be controlled so as not to exceed a low breakdown voltage gate breakdown voltage. ) Having a low gate breakdown voltage can be used. As a result, the analog switch (1) of FIG. 1 can have the same performance with a device smaller than the analog switch (5) of FIG.

  FIG. 2 shows the input / output characteristic diagram of FIG. As in FIG. 6, the voltage Va is the input voltage of one electrode of the switch, and Vb is the output voltage of the other electrode of the switch. A dotted line indicates when the current flowing when the analog switch (1) is on is 0, and a solid line indicates when the current Isw flows. When the input voltage Va of the analog switch (1) is increased from 0V, the output voltage Vb also increases linearly and becomes constant when the input allowable range VINMIN of the switch is exceeded. The gate-source voltage VGS of the MOSFETs DMN11 and DMN12 constituting the analog switch (1) becomes VGS = Ia.times.R1 due to the output current Ia of the high breakdown voltage current mirror (2) and the resistor R1. In this input / output characteristic, the current Ib that is connected to the other electrode of the resistor R1 and flows into the N-channel MOSFET DMN2 has the same current value as the current Ia, so that the current that flows into the sources of the MOSFETs DMN11 and DMN12 of the analog switch (1). Is lost. Since a high voltage is applied to the drains of the MOSFETs DMN11 and DMN12 and MOSFETs DMP1, DMP2 and DMN1, DMN2, a high voltage MOSFET is used between the gate, drain and gate-back gate. For example, the gate-source breakdown voltage is a low breakdown voltage of about 5V, but the gate-back gate and the gate and drain are set to a high breakdown voltage of 50 to 100V.

  The MOSFETs DMN11 and DMN12 of the analog switch (1) when the input / output voltage has linearity characteristics within the input allowable range operate in the saturation region. In a region where the input allowable range of the switch is exceeded and the input / output voltage loses linearity, VGS ≧ Veff (LG), and the MOSFET DMN 12 operates in the specific saturation region. Therefore, the MOSFET DMN12 has a constant current even when the drain-source voltage increases, and the output voltage Vb of the analog switch (1) becomes a constant voltage. In this embodiment, the maximum input voltage is VINmax, the threshold voltage of the gate high voltage device used in the embodiment is VTH0 (LG), and the effective voltage (voltage loss or drive voltage in the analog switch) is Veff (LG). Then, VINmax = VS− (VTH0 (LG) + Veff (LG)), and VGS = Ia × R1. When current does not flow through the analog switch (1) (Isw = current off), Vb≈Va, and current mirror circuit (3) (2) sets Ia≈Ib, so that current flows through the analog switch (1). Is flowing (Isw = current on), Vb≈Va−2 × (Isw × RDSON).

  Since the gate capacitance Cox of the gate low breakdown voltage MOSFETs DMN11 and DMN12 is larger than that of the gate high breakdown voltage MOSFETs DMN51 and DMN52 shown in FIG. 5, in the case of the same gate effective width W, the characteristic Isw = current off shown by the dotted line The characteristic Isw shown by the solid line = (Veff (LG)) corresponding to the difference of current on can be reduced. In other words, when this difference is made the same (Veff (HG) = Veff (LG)), the gate effective width W of the MOSFETs DMN11 and DMN12 having low gate breakdown voltage can be reduced. Furthermore, since the gate low breakdown voltage MOSFETs DMN11 and DMN12 can reduce the threshold voltage VTH0 by thinning the gate oxide film, etc., under the same voltage VS, it is based on (VTH0 (LG)). The input allowable range VINmax can be widened by the voltage difference.

  The MOSFETs DMP1 and DMP2 and the N-channel MOSFETs DMN1 and DMN2 constituting the current mirror circuit (2) have a small gate-source voltage, and a high voltage is applied to the drain and back gate. The one having a breakdown voltage structure similar to the MOSFETs DMN11 and DMN12 constituting 1) can be used. When the analog switch circuit is formed on one semiconductor substrate, MOSFETs DMN51 and DMN52 in which both the gate-source and the gate-back gate have a high breakdown voltage compared to the case where the analog switch circuit as shown in FIG. 5 is used. Thus, it is not necessary to form a MOSFET having a thick gate insulating film, and the manufacturing process can be simplified.

  FIG. 3 is a circuit diagram showing another embodiment of the analog switch circuit according to the present invention. In this embodiment, the current mirror circuits (2) and (3) are constituted by cascade connection circuits. That is, in the current mirror circuit (3), similar current mirror type MOSFETs MN5 to MN7 are cascade-connected to the current mirror type MOSFETs MN2 to MN4. Similarly, in the current mirror circuit (2), the current mirror type MOSFETs DMP3 and DMP4 are cascade-connected to the current mirror type MOSFETs DMP1 and DMP2. By adding such cascaded MOSFETs, it is possible to reduce voltage dependency errors of the power supply voltages VDD and VS due to the channel length modulation effect of the currents Ia and Ib. In particular, the influence when the signal current Isw flowing through the analog switch (1) is very small can be reduced.

  FIG. 4 is a circuit diagram showing still another embodiment of the analog switch circuit according to the present invention. In this embodiment, a Zener diode ZD1 is used instead of the resistor R1. In this embodiment, in order to stabilize the gate-source voltage VGS of the MOSFETs DMN11 and DMN12 constituting the analog switch (1), the Zener voltage of the Zener diode ZD1 is used to reduce the noise current generated when switching is switched. On the other hand, the voltage can be clamped. A resistor R1 may be connected in parallel to the Zener diode ZD1. Further, as in the embodiment of FIG. 3, the current mirror circuits (2) and (3) may be formed of a cascade connection circuit.

  The analog switch circuit of this embodiment can be used for an airbag squib diagnostic circuit. The airbag deployment layer sequentially selects a plurality of squibs using a high-current driver switch, supplies an ignition voltage to each squib, and performs airbag deployment processing. When an automobile engine is started, the resistance value of the squib is detected via the analog switch, and a diagnosis is made as to whether or not the squib is in a normal state. At the time of diagnosis, the analog switch supplies a small current to the squib.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, the resistor R1 can take various embodiments such as one using a diffusion layer or one using a polysilicon layer. In response to the input signal, the configuration of the control circuit for causing the currents Ia and Ib to flow through the resistor R1 and the Zener diode provided in the analog switch (1) can take various embodiments. The present invention can be widely used in analog switch circuits that transmit high-voltage analog signals.

1 is a circuit diagram showing an embodiment of an analog switch circuit according to the present invention. FIG. 2 is an input / output characteristic diagram of FIG. 1. It is a circuit diagram which shows another Example of the analog switch circuit based on this invention. It is a circuit diagram which shows another Example of the analog switch circuit based on this invention. FIG. 3 is a circuit diagram of an analog switch circuit studied prior to the present invention. FIG. 6 is an input / output characteristic diagram of FIG. 5.

Explanation of symbols

  (1), (5) ... Analog switch, (2), (3) ... Current mirror circuit, MP1, MN1-MN7 ... Low voltage MOSFET, DMN1-DMN12 ... Gate, Source low voltage MOSFET, DMP1-DMP4 ... Gate, Source low breakdown voltage MOSFET, R1... Resistor, ZD1... Zener diode, DMN51, DMN52.

Claims (6)

A first MOSFET and a second MOSFET having a gate-source breakdown voltage smaller than the gate-back gate breakdown voltage;
A first terminal and a second terminal;
Impedance means;
A control circuit,
The source-drain paths of the first MOSFET and the second MOSFET are connected in series between the first terminal and the second terminal,
The gate of the first MOSFET and the gate of the second MOSFET are commonly connected to form a third terminal,
The back gates of the first MOSFET and the second MOSFET are connected to a fourth terminal which is an interconnection point between the first MOSFET and the second MOSFET,
The impedance means is connected between the third terminal and the fourth terminal;
The control circuit controls a current flowing between the third terminal and the fourth terminal so that a voltage generated in the impedance means is larger or smaller than a threshold voltage of the first MOSFET and the second MOSFET. An analog switch circuit for opening and closing a current path between the first terminal and the second terminal. In claim 1,
The first terminal has a first supply voltage that is larger than the breakdown voltage between the gate and the source and smaller than the breakdown voltage between the gate and the back gate.
The control circuit is
A first current mirror comprising a third MOSFET and a fourth MOSFET having a second voltage that is greater than the threshold voltage with respect to the first voltage as an operating voltage and having a gate-back gate breakdown voltage greater than or equal to the second voltage. Circuit,
A first circuit that operates at an operating voltage smaller than the first and second voltages and selectively forms a first current in response to a switch control signal; and a second current that is constantly equivalent to the first current A second circuit forming
A voltage generated in the impedance means by supplying the first current to the third terminal or the fourth terminal through the first current mirror circuit and supplying the second current to the fourth or third terminal. Is an analog switch circuit in which the voltage is higher or lower than the threshold voltage of the first MOSFET and the second MOSFET. In claim 2,
The control circuit includes a reference current source that forms a reference current corresponding to the first current,
The first circuit includes:
A second current mirror circuit to which the reference current is input;
A switch MOSFET controlled by the switch control signal,
The switch MOSFET selectively transmits the output current of the second current mirror circuit to the input terminal of the first current mirror circuit according to the switch control signal.
The second circuit is
A third current mirror circuit to which the reference current is input;
An analog switch circuit in which the output current of the third current mirror circuit is the second current. In claim 3,
The first to third current mirror circuits are analog switch circuits each provided with a current mirror type MOSFET cascaded. In claim 4,
The impedance means is a resistance element, and an analog switch circuit in which a voltage generated when the first current flows through the resistance element is larger than a threshold voltage of the first MOSFET and the second MOSFET. In claim 4,
The impedance means is a Zener diode, and the Zener voltage is an analog switch circuit whose voltage is larger than the threshold voltage of the first MOSFET and the second MOSFET.

Images