JP2014072481A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an opening failure of a cylinder for forming a capacitor element.SOLUTION: A manufacturing method of a semiconductor device 100 comprises: forming an insulation film on a semiconductor substrate 1 having a memory cell part 2 and a peripheral circuit part 3; forming a hard mask 8 on the insulation film; and preliminarily etching only the hard mask at the peripheral circuit part 3 by a predetermined thickness and etching the insulation film by using the hard mask at the memory cell part 2 and the peripheral circuit part 3 in a state where a first residual film thickness of the hard mask at the memory cell part 2 and a second residual film thickness of the hard mask at the peripheral circuit part 3 are substantially the same with each other to form a plurality of openings (cylinders 11) which penetrate the insulation film.

Description

  The present invention relates to a method for manufacturing a semiconductor device such as a DRAM element.

  In recent years, with the miniaturization of semiconductor devices such as DRAM elements, elements having an MIM (Metal-Insulator-Metal) structure have been adopted as capacitor elements having a large capacitance.

  As a technology related to this, there is, for example, Japanese Patent Application Laid-Open No. 2011-192801 (Patent Document 1).

  Patent Document 1 discloses a technique for realizing both a reduction in leakage current of a capacitor element and an increase in capacitance.

JP 2011-192801 A

  However, the above-mentioned patent document 1 is intended to realize both reduction of the leakage current of the capacitor element and increase of the capacitance, and recognizes that it prevents the opening failure of the cylinder for forming the capacitor element. It has not been.

  The present invention provides a method of manufacturing a semiconductor device capable of preventing a defective opening of a cylinder for forming a capacitor element.

A method for manufacturing a semiconductor device according to one embodiment of the present invention includes:
Forming an insulating film on a semiconductor substrate having a memory cell portion and a peripheral circuit portion;
Forming a hard mask on the insulating film;
Only a predetermined thickness of the peripheral circuit hard mask is etched in advance,
Using the hard masks of the cell portion and the peripheral circuit portion, the first residual film thickness of the hard mask of the cell portion and the second residual film thickness of the hard mask of the peripheral circuit portion are substantially equal And etching the insulating film to form a plurality of openings that penetrate the insulating film.

  According to the present invention, it is possible to prevent a defective opening of a cylinder for forming a capacitor element.

It is a top view which shows the structure of the semiconductor device by embodiment of this invention. FIG. 7 is a cross-sectional view taken along the line BB of FIG. FIG. 7 is a cross-sectional view taken along the line BB of FIG. 1 showing one manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 7 is a cross-sectional view taken along the line BB of FIG. 1 showing one manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 7 is a cross-sectional view taken along the line BB of FIG. 1 showing one manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 7 is a cross-sectional view taken along the line BB of FIG. 1 showing one manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 7 is a cross-sectional view taken along the line BB of FIG. 1 showing one manufacturing process of the semiconductor device according to the embodiment of the present invention. It is a top view which shows the structure of the semiconductor device by related technology. It is BB sectional drawing of FIG. 8 which shows one manufacturing process of the semiconductor device by related technology. It is BB sectional drawing of FIG. 8 which shows one manufacturing process of the semiconductor device by related technology.

  First, a semiconductor device according to related art will be described so that the features of the present invention become clearer.

(Related technology)
8-10 is a figure which shows the structure of the semiconductor device 100 by related technology. 8 is a plan view of a cylinder opening etching process of the memory cell portion and the peripheral circuit portion of the DRAM, and FIGS. 9 to 10 are cross-sectional views taken along line BB of FIG.

  First, the related-art semiconductor device 100 will be described with reference to the plan view of FIG.

The semiconductor device 100 constitutes a memory cell portion 2 and a peripheral circuit portion 3 of a DRAM. On a semiconductor substrate 1 on which a semiconductor element such as a transistor (not shown) is formed, a diffusion layer (not shown) of the semiconductor substrate 1 and a capacitor lower electrode (not shown) formed in the cylinder 11 in the future are provided. A capacitive contact plug 5 to be connected is installed.

  A silicon oxide film 7 for forming a cylinder is provided so as to cover the capacitor contact plug 5, and a silicon hard mask 8 for cylinder etching is patterned thereon with a mask separation width Xnm and a mask opening Ynm. For example, X can be 20 nm and Y can be 60 nm.

  Thereafter, using the silicon hard mask 8 as a mask, the stopper silicon nitride film 6 and the cylinder-forming silicon oxide film 7 are passed through and etched to form a cylinder (cylinder hole) 11.

  In the related art, at the time of cylinder etching, the silicon hard mask 8 in the memory cell unit 2 is quickly etched because the mask is also etched from the lateral direction, but the silicon hard mask 8 of the peripheral circuit unit 3 that does not form the cylinder 11 is Etching is only possible from above. Therefore, the remaining film of the silicon hard mask 8 remains thicker in the peripheral circuit portion 3 than in the memory cell portion 2 2.

  For this reason, since the silicon hard mask 8 having a thick residual film remains on the peripheral circuit portion 3 side in the cylinder 11 at the cell end, the cylinder 11 is blocked by the deposition 15 during the etching, and the cylinder 11a having a defective opening. Will be formed.

  A method for manufacturing the semiconductor device 100 according to the related technique shown in FIG. 8 will be described below with reference to FIGS. 9 to 10 show BB cross-sectional views in FIG.

  First, as shown in FIG. 9, an interlayer insulating film 4 is formed on a semiconductor substrate 1 on which a semiconductor element (not shown) such as a transistor is formed, penetrates the interlayer insulating film 4, and is formed on the semiconductor substrate 1. A capacitor contact 5a to be connected is formed. Thereafter, polysilicon or the like is deposited on the interlayer insulating film 4 so as to embed the capacitor contact 5a, and etched back to form the capacitor contact plug 5.

  Then, a stopper silicon nitride film 6 is formed so as to cover the capacitor contact plug 5.

  Further, a cylinder forming silicon oxide film 7 is deposited on the stopper silicon nitride film 6.

  Thereafter, a silicon hard mask 8 for forming a cylinder is deposited to a thickness of A nm and patterned using a lithography technique and a dry etching technique. For example, the film thickness A is 100 nm. Further, the dimension X of the hard mask 8 at this time can be set to 20 nm, for example, and the dimension Y of the space can be set to 60 nm, for example.

  Next, as shown in FIG. 10, a cylinder 11 is formed by etching through the stopper silicon nitride film 6 and the silicon oxide film 7 for cylinder formation using the silicon hard mask 8 as a mask.

  At this time, the film thickness of the silicon hard mask 8 before etching is set to Anm, the etching amount Bnm of the silicon hard mask 8 in the peripheral circuit portion 3 and the etching amount difference between the silicon hard mask 8 in the memory cell portion 2 and the peripheral circuit portion 3 are In the case of Cnm, the residual film D2 of the silicon hard mask in the cell part 2 after etching and the residual film D3 of the silicon hard mask in the peripheral circuit part 3 are D2 = ABC in the cell and the peripheral circuit part, respectively. D3 = A−B. For example, when A is 100 nm, B is 20 nm, and C is 50 nm, D2 = 30 nm and D3 = 80 nm.

  As described above, in the related art, during the cylinder etching, the silicon hard mask 8 in the memory cell portion 2 can be quickly removed because the silicon hard mask 8 is also etched from the lateral direction, but the peripheral circuit portion 3 that does not form the cylinder 11. The silicon hard mask 8 is etched only from above. Therefore, the remaining film of the silicon hard mask 8 remains thicker in the peripheral circuit portion 3 than in the memory cell portion 2.

  For this reason, in the cylinder 11 at the cell end, the silicon hard mask 8 having a thick residual film remains on the peripheral circuit portion 3 side, so that the cylinder 11 (cylinder hole) is blocked by the deposition 15 during the etching, and the opening is defective. There is a problem that the cylinder 11a is formed.

  The present invention solves the above-described problems of the related art, and provides a method for manufacturing a semiconductor device capable of preventing defective opening of a cylinder for forming a capacitor element.

(Embodiment of the present invention)
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

  1 to 6 are views showing a structure of a semiconductor device 100 according to a preferred embodiment of the present invention. 1 is a plan view of a cylinder opening etching process of a memory cell portion and a peripheral circuit portion of a DRAM, FIGS. 2 to 6 are BB cross-sectional views of FIG. 1, and FIG. 7 is a BB cross-sectional view of a DRAM after capacitance formation. Is shown.

  First, the semiconductor device 100 of this embodiment will be described with reference to the plan view of FIG.

  The semiconductor device 100 constitutes a memory cell portion 2 and a peripheral circuit portion 3 of a DRAM. On a semiconductor substrate 1 on which a semiconductor element (not shown) such as a transistor is formed, a diffusion layer (not shown) of the semiconductor substrate 1 and a capacitor lower electrode (not shown) formed in the cylinder 11 in the future are connected. A capacitive contact plug 5 is installed. A stopper silicon nitride film 6 and a cylinder forming silicon oxide film 7 are provided so as to cover the capacitor contact plug 5, and a cylinder etching silicon hard mask 8 is formed on the mask contact width Xnm and mask opening Ynm. Patterned. For example, X can be 20 nm and Y can be 60 nm.

  A silicon hard mask etching region 9 in which the silicon hard mask 8 for cylinder etching is etched to a depth E in advance is formed in the peripheral circuit portion 3 while leaving the width Z from the boundary 3a with the memory cell portion 2.

  Thereafter, using the silicon hard mask 8 as a mask, the stopper 11 is formed through the stopper silicon nitride film 6 and the cylinder forming silicon oxide film 7 to form the cylinder 11.

  As described above, in the embodiment of the present invention, the silicon hard mask 8 of the peripheral circuit portion 3 is etched in advance, so that the remaining film of the silicon hard mask 8 in the memory cell 2 and the peripheral circuit portion 3 at the time of cylinder etching. The thickness can be made approximately equal. As a result, it is possible to prevent the cylinder opening failure at the cell edge, which is a problem in the related art. Further, it becomes possible to delete the dummy cylinder at the cell edge necessary for countermeasures against the defective opening, and the chip area can be reduced.

  A method for manufacturing the semiconductor device 100 according to the embodiment of the present invention shown in FIG. 1 will be described below with reference to FIGS. 2-6 has shown BB sectional drawing in FIG.

  First, as shown in FIG. 2, an interlayer insulating film 4 is formed on a semiconductor substrate 1 on which a semiconductor element (not shown) such as a transistor is formed, passes through the interlayer insulating film 4, and is formed on the semiconductor substrate 1. A capacitor contact 5a to be connected is formed. Thereafter, polysilicon or the like is deposited on the interlayer insulating film 4 so as to embed the capacitor contact 5a, and etched back to form the capacitor contact plug 5.

  Then, a stopper silicon nitride film 6 is formed so as to cover the capacitor contact plug 5.

  Further, a cylinder forming silicon oxide film 7 is deposited on the stopper silicon nitride film 6.

  Thereafter, a silicon hard mask 8 for forming a cylinder is deposited to a thickness of Anm and patterned using a lithography technique and a dry etching technique. For example, the film thickness A is 100 nm. Further, the dimension X of the hard mask 8 at this time can be set to 20 nm, for example, and the dimension Y of the space can be set to 60 nm, for example.

  Next, as shown in FIG. 3, the resist 10 is patterned so as to cover the silicon hard mask 8 from the memory cell portion 2 and the memory cell portion 2 to the region that has entered the width Znm peripheral circuit portion 3.

  When the dimension of the silicon hard mask 8 for cylinder formation is X nm and the dimension of the space is Y nm, Z at this time can be set to X nm or more and X + Y nm or less. For example, when X is 20 nm and Y is 60 nm, Z can be 20 nm or more and 80 nm or less.

  Next, as shown in FIG. 4, using the resist 10 as a mask, the silicon hard mask 8 is etched using a dry etching technique. The film thickness of the silicon hard mask 8 before etching is Anm, the etching amount Bnm of the silicon hard mask 8 of the peripheral circuit portion 3 generated by the related technique shown in FIG. 10, the silicon hard mask 8 of the memory cell portion 2 and the peripheral circuit portion 3 When the difference in etching amount is Cnm, the etching amount Enm of the silicon hard mask 8 at this time can be set to C or more and AB or less.

  For example, when A is 100 nm, B is 20 nm, and C is 50 nm, the etching amount Enm of the silicon hard mask 8 in the peripheral circuit section 3 can be 50 nm or more and 80 nm or less. As a result, a cylinder hard mask etching region 9, which is a region where the silicon hard mask 8 is etched by the nm, is formed in the peripheral circuit portion 3.

  Next, the resist 10 is removed as shown in FIG.

  Next, as shown in FIG. 6, using the silicon hard mask 8 as a mask, a cylinder 11 is formed through the stopper silicon nitride film 6 and the cylinder forming silicon oxide film 7 by using a dry etching technique.

  After the cylinder etching, the remaining film D2 of the silicon hard mask 8 in the memory cell portion 2 after the cylinder etching and the remaining film D3 of the silicon hard mask in the peripheral circuit portion 3 are respectively in-cell D2 = A−B−C, peripheral circuit For example, D2 = 30 nm and D3 = 0 to 30 nm.

  In the embodiment of the present invention, since the silicon hard mask 8 of the peripheral circuit portion 3 is previously etched to have a film thickness, the remaining film thickness D3 of the silicon hard mask 8 of the peripheral circuit portion 3 during the cylinder etching and the memory cell portion. The remaining film thickness D2 of the second silicon hard mask 8 becomes substantially equal, and the cylinder opening defect at the cell edge, which is a problem in the related art, can be prevented.

  Next, as shown in FIG. 7, the lower electrode 12 of the capacitor element is formed on the capacitor contact plug 5 with titanium nitride or the like.

  Then, after forming the capacitive insulating film 13 so as to cover the surface of the lower electrode 12, the upper electrode 14 of the capacitor element is formed of titanium nitride or the like.

  Thereafter, although not shown, the wiring formation process is repeated to form a multilayer wiring, and the semiconductor device 100 is formed.

  In the method of manufacturing a semiconductor device according to the embodiment of the present invention, the silicon hard mask 8 of the peripheral circuit portion 3 is etched in advance, so that the silicon hard mask 8 of the memory cell portion 2 and the peripheral circuit portion 3 of the peripheral circuit portion 3 are etched. The remaining film thicknesses D2 and D3 can be made substantially equal. As a result, it is possible to prevent the cylinder opening failure at the cell edge, which is a problem in the related art. Further, it becomes possible to delete the dummy cylinder at the cell edge necessary for countermeasures against the defective opening, and the chip area can be reduced.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in the embodiment of the present invention, the formation of the cylinder of the DRAM has been described. However, the present invention is not limited to this, and the present invention can also be applied to other high-aspect ratio dense contact holes.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Memory cell part 3 Peripheral circuit part 3a Boundary 4 Interlayer insulating film 5 Capacitor contact plug 6 Stopper silicon nitride film 7 Silicon oxide film 8 Silicon hard mask 9 Silicon hard mask etching area 10 Resist 11 Cylinder 12 Lower electrode 13 Capacitance insulation Film 14 Upper electrode 15 Deposition 100 Semiconductor device

Claims (9)

Forming an insulating film on a semiconductor substrate having a memory cell portion and a peripheral circuit portion;
Forming a hard mask on the insulating film;
Only a predetermined thickness of the peripheral circuit hard mask is etched in advance,
Using the hard mask of the memory cell portion and the peripheral circuit portion, a first remaining film thickness of the hard mask of the memory cell portion and a second remaining film thickness of the hard mask of the peripheral circuit portion are substantially A method of manufacturing a semiconductor device, wherein a plurality of openings penetrating the insulating film are formed by etching the insulating film in an equal state.   Etching the insulating film in a state where the first remaining film thickness and the second remaining film thickness are substantially equal, thereby preventing an opening defect in the opening located at the cell edge of the memory cell portion. The method of manufacturing a semiconductor device according to claim 1.   The hard mask of the peripheral circuit portion maintains the original thickness in a portion that falls within a predetermined width from the boundary between the memory cell portion and the peripheral circuit portion, and the portion other than the predetermined width has the predetermined thickness. The method of manufacturing a semiconductor device according to claim 1, wherein the etching is performed in advance. Patterning a resist so as to cover the hard mask from the memory cell part and the boundary to a region including the predetermined width;
4. The method of manufacturing a semiconductor device according to claim 3, wherein only the hard mask of the peripheral circuit portion is etched in advance by the predetermined thickness by etching the hard mask using the resist as a mask.   5. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is a silicon oxide film formed on a capacitor contact plug. 6.   6. The method of manufacturing a semiconductor device according to claim 5, wherein a lower electrode is formed on the capacitor contact plug in the opening of the memory cell portion.   The method of manufacturing a semiconductor device according to claim 6, wherein the upper electrode is formed after forming the capacitive insulating film so as to cover the surface of the lower electrode. The semiconductor device is a DRAM;
The opening is a cylinder;
8. The method of manufacturing a semiconductor device according to claim 7, wherein a capacitor element is constituted by the lower electrode, the capacitive insulating film, and the upper electrode.   The method of manufacturing a semiconductor device according to claim 1, wherein the opening is a contact hole.

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