KR100819674B1 - Method for forming semiconductor devices - Google Patents

Method for forming semiconductor devices Download PDF

Info

Publication number
KR100819674B1
KR100819674B1 KR1020060047563A KR20060047563A KR100819674B1 KR 100819674 B1 KR100819674 B1 KR 100819674B1 KR 1020060047563 A KR1020060047563 A KR 1020060047563A KR 20060047563 A KR20060047563 A KR 20060047563A KR 100819674 B1 KR100819674 B1 KR 100819674B1
Authority
KR
South Korea
Prior art keywords
layer
forming
hard mask
storage electrode
mask layer
Prior art date
Application number
KR1020060047563A
Other languages
Korean (ko)
Other versions
KR20070113805A (en
Inventor
구선영
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020060047563A priority Critical patent/KR100819674B1/en
Publication of KR20070113805A publication Critical patent/KR20070113805A/en
Application granted granted Critical
Publication of KR100819674B1 publication Critical patent/KR100819674B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 반도체소자의 형성방법에 관한 것으로, The present invention relates to a method of forming a semiconductor device,

반도체소자의 고집적화에 따른 리소그래피의 해상도 증가 필요성에 따라 최소선폭 패턴보다 작은 크기의 패턴을 형성할 수 있도록 하기 위하여, 피식각층이 형성된 반도체기판 상부에 n 개의 하드마스크층 적층구조를 형성하고 상기 적층구조의 최상층인 제n층 하드마스크층을 패터닝한 다음, 상기 제n층 하드마스크층 사이에 에치 트리밍 공정을 이용하여 패터닝된 마스크층을 형성하고 상기 제n층 하드마스크층과 마스크층을 마스크로 하여 (n-1)층의 하드마스크층을 패터닝한 다음, 이들의 단계를 반복하여 상기 피식각층 상부의 제1하드마스크층까지 패터닝하고 상기 피식각층 상부의 구조물을 마스크로 하여 상기 피식각층을 패터닝함으로써 최소 피치 크기 보다 작은 크기의 미세패턴을 형성하고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.In order to form a pattern having a size smaller than the minimum line width pattern according to the necessity of increasing the resolution of lithography due to the high integration of semiconductor devices, n stacked hard mask layer structures are formed on the semiconductor substrate on which an etched layer is formed, After patterning the n-th layer hard mask layer, which is the uppermost layer of, a patterned mask layer is formed between the n-th layer hard mask layers using an etch trimming process, and the n-th layer hard mask layer and the mask layer are used as masks. patterning the hard mask layer of the (n-1) layer, and then repeating these steps to pattern the first hard mask layer on the etched layer and patterning the etched layer using the structure on the etched layer as a mask. It is possible to form a fine pattern of a size smaller than the minimum pitch size and to thereby enable high integration of the semiconductor device. The technology.

Description

반도체소자의 형성방법{Method for forming semiconductor devices}Method for forming semiconductor devices

도 1a 내지 도 1g 는 종래기술의 실시예에 따른 반도체소자의 형성방법을 도시한 단면도.1A to 1G are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the prior art.

도 2a 내지 도 2g 는 본 발명의 실시예에 따른 반도체소자의 형성방법을 도시한 단면도.2A to 2G are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.

본 발명은 반도체소자의 형성방법에 관한 것으로, 특히 삼차원적 구조를 갖는 캐패시터를 형성하여 반도체소자의 고집적화에 충분한 정전용량을 확보하는데 있어 저장전극 콘택 플러그 간의 브릿지를 방지할 수 있도록 하는 기술에 관한 것이다. The present invention relates to a method of forming a semiconductor device, and more particularly, to a technology for forming a capacitor having a three-dimensional structure to prevent a bridge between storage electrode contact plugs in securing a sufficient capacitance for high integration of the semiconductor device. .

반도체소자가 고집적화되어 셀 크기가 감소됨에 따라 저장전극의 표면적에 비례하는 정전용량을 충분히 확보하기가 어려워지고 있다.As semiconductor devices are highly integrated and cell sizes are reduced, it is difficult to secure a capacitance that is proportional to the surface area of the storage electrode.

특히, 단위 셀이 하나의 모스 트랜지스터와 캐패시터로 구성되는 디램 소자는 칩에서 많은 면적을 차지하는 캐패시터의 정전용량을 크게 하면서, 면적을 줄이는 것이 디램 소자의 고집적화에 중요한 요인이 된다.In particular, in a DRAM device having a unit cell composed of one MOS transistor and a capacitor, it is important to reduce the area while increasing the capacitance of a capacitor, which occupies a large area on a chip, which is an important factor for high integration of the DRAM device.

그래서, ( Eo × Er × A ) / T ( 단, 상기 Eo 는 진공유전율, 상기 Er 은 유전막의 유전율, 상기 A 는 캐패시터의 면적 그리고 상기 T 는 유전막의 두께 ) 로 표시되는 캐패시터의 정전용량을 증가시키기 위하여, 하부전극인 저장전극의 표면적을 증가시켜 캐패시터를 형성하거나, 유전체막의 두께를 감소시켜 캐패시터를 형성하였다.Thus, the capacitance of the capacitor represented by (Eo × Er × A) / T (wherein Eo is the vacuum dielectric constant, Er is the dielectric constant of the dielectric film, A is the area of the capacitor and T is the thickness of the dielectric film) is increased. In order to do this, the surface area of the storage electrode, which is a lower electrode, is increased to form a capacitor, or the thickness of the dielectric film is reduced to form a capacitor.

도 1a 내지 도 1g 는 종래기술에 따른 반도체소자의 형성방법을 도시한 단면도로서, 저장전극 콘택 플러그 형성공정을 도시한 것이다. 1A to 1G are cross-sectional views illustrating a method of forming a semiconductor device according to the related art, and illustrating a storage electrode contact plug forming process.

도 1a를 참조하면, 소자분리막(미도시), 게이트전극(미도시), 랜딩플러그(미도시) 및 비트라인(13)과 같은 하부구조물이 구비되는 반도체기판(11) 상에 하부절연층(15)을 형성한다. Referring to FIG. 1A, a lower insulating layer (not shown) may be formed on a semiconductor substrate 11 having lower structures such as an isolation layer (not shown), a gate electrode (not shown), a landing plug (not shown), and a bit line 13. 15).

그 다음, 하부절연층(15) 상에 하드마스크층(17)을 형성하고 그 상부에 감광막패턴(19)을 형성한다. Next, a hard mask layer 17 is formed on the lower insulating layer 15, and a photosensitive film pattern 19 is formed on the top of the hard mask layer 17.

이때, 하드마스크층(17)은 폴리실리콘으로 형성한 것이다. At this time, the hard mask layer 17 is formed of polysilicon.

도 1b를 참조하면, 감광막패턴(19)을 마스크로 하여 상기 하드마스크층(17)을 식각하고 감광막패턴(19)을 제거함으로써 하드마스크층(17) 패턴을 형성한다. Referring to FIG. 1B, the hard mask layer 17 pattern is formed by etching the hard mask layer 17 and removing the photoresist pattern 19 using the photoresist pattern 19 as a mask.

도 1c를 참조하면, 하드마스크층(17) 패턴을 마스크로 하여 하부절연층(15)을 식각하여 랜딩플러그(미도시)를 노출시키는 저장전극 콘택홀(21)을 형성한다.Referring to FIG. 1C, the lower insulating layer 15 is etched using the hard mask layer 17 pattern as a mask to form a storage electrode contact hole 21 exposing a landing plug (not shown).

이때, 하부절연층(15)의 식각공정은 플라즈마를 이용한 에치백 공정으로 실시한 것이다. YIn this case, the etching of the lower insulating layer 15 is performed by an etch back process using plasma. Y

도 1d를 참조하면, 저장전극 콘택홀(21)을 포함한 전체표면상부에 질화 막(23)을 일정두께 형성한다. Referring to FIG. 1D, a nitride film 23 is formed on the entire surface including the storage electrode contact hole 21 at a predetermined thickness.

이때, 질화막(23)은 저압화학기상증착 ( LPCVD ) 방법으로 형성한다. In this case, the nitride film 23 is formed by low pressure chemical vapor deposition (LPCVD).

도 1e를 참조하면, 상기 질화막(23)을 이방성식각하여 저장전극 콘택홀(21)의 측벽에 질화막(23) 스페이서를 형성한다. Referring to FIG. 1E, the nitride layer 23 is anisotropically etched to form a nitride layer 23 spacer on a sidewall of the storage electrode contact hole 21.

도 1f를 참조하면, 전체표면상부에 저장전극 콘택홀(21)을 매립하는 플러그용 도전층(25)인 폴리실리콘을 전체표면상부에 형성한다.Referring to FIG. 1F, polysilicon, which is a plug conductive layer 25 for filling the storage electrode contact hole 21, is formed on the entire surface.

도 1g를 참조하면, 플러그용 도전층(25)을 에치백하여 저장전극 콘택 플러그(27)를 형성한다. Referring to FIG. 1G, the storage conductive contact plug 27 is formed by etching back the plug conductive layer 25.

이때, 비트라인(13) 상측이 뾰족하게 구성되어, 후속 공정인 저장전극 형성공정시 브릿지가 유발될 수 있다. At this time, the upper side of the bit line 13 is sharply formed, which may cause a bridge in a subsequent process of forming a storage electrode.

상기한 바와 같이, 종래기술에 따른 반도체소자의 형성방법은, 비트라인 상측의 구조가 뾰족하게 형성되어 후속 공정으로 형성되는 저장전극이 이웃하는 저장전극과 브릿지(bridge)되는 경우가 유발되고 그에 따른 반도체소자의 페일이 유발될 수 있는 문제점이 있다. As described above, in the method of forming a semiconductor device according to the related art, a structure in which an upper portion of a bit line is sharply formed causes a case in which a storage electrode formed in a subsequent process is bridged with a neighboring storage electrode, and accordingly There is a problem that may cause a failure of the semiconductor device.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 비트라인 상부를 평탄하게 형성하여 후속 공정시 브릿지를 억제할 수 있도록 하는 반도체소자의 형성방법을 제공하는데 그 목적이 있다. In order to solve the above problems of the prior art, an object of the present invention is to provide a method for forming a semiconductor device to flatten the bit line to suppress the bridge during subsequent processing.

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 형성방법은,
랜딩플러그 및 비트라인이 형성된 반도체기판 상에 하부절연층을 형성하는 공정과,
상기 하부절연층 상부에 저장전극 콘택 영역을 노출시키는 하드마스크층을 패터닝하는 공정과,
상기 하드마스크층을 마스크로 하여 하부절연층을 등방성식각하고 이방성식각하여 저장전극 콘택홀을 형성하되, 상기 하드마스크층의 저부로 언더컷을 형성하는 공정과,
상기 저장전극 콘택홀 측벽에 질화막 스페이서를 형성하여 상기 언더컷을 매립하는 공정과,
상기 저장전극 콘택홀에 저장전극 콘택플러그를 형성하는 공정을 포함하는 것을 특징으로 한다.
한편, 본 발명은 원리는, In order to achieve the above object, a method of forming a semiconductor device according to the present invention,
Forming a lower insulating layer on the semiconductor substrate on which the landing plug and the bit line are formed;
Patterning a hard mask layer exposing a storage electrode contact region on the lower insulating layer;
Forming a storage electrode contact hole by isotropically etching and anisotropically etching the lower insulating layer using the hard mask layer as a mask, and forming an undercut under the hard mask layer;
Embedding the undercut by forming a nitride film spacer on sidewalls of the storage electrode contact hole;
And forming a storage electrode contact plug in the storage electrode contact hole.
On the other hand, the present invention is a principle,

삭제delete

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2g 는 본 발명에 따라 형성된 반도체소자의 형성방법을 도시한 것이다. 2A to 2G illustrate a method of forming a semiconductor device formed in accordance with the present invention.

도 2a 를 참조하면, 소자분리막(미도시), 게이트전극(미도시), 랜딩플러그(미도시) 및 비트라인(33)과 같은 하부구조물이 구비되는 반도체기판(31) 상에 하부절연층(35)을 형성한다. Referring to FIG. 2A, a lower insulating layer (not shown) may be formed on a semiconductor substrate 31 including lower structures such as an isolation layer (not shown), a gate electrode (not shown), a landing plug (not shown), and a bit line 33. 35).

그 다음, 하부절연층(35) 상에 하드마스크층(37)을 형성하고 그 상부에 감광막패턴(미도시)을 형성한다. Next, a hard mask layer 37 is formed on the lower insulating layer 35 and a photoresist pattern (not shown) is formed thereon.

이때, 하드마스크층(37)은 폴리실리콘으로 형성한 것이다. At this time, the hard mask layer 37 is formed of polysilicon.

도 2b를 참조하면, 감광막패턴을 마스크로 하여 상기 하드마스크층(37)을 식각하고 감광막패턴을 제거함으로써 하드마스크층(37) 패턴을 형성한다. Referring to FIG. 2B, the hard mask layer 37 is etched by using the photoresist pattern as a mask and the hard mask layer 37 is removed by removing the photoresist pattern.

그 다음, 하드마스크층(37) 패턴을 마스크로 하여 하부절연층(35)을 소정두께 등방성식각하여 하드마스크층(37) 패턴 하부로 언더컷(39)을 형성한다. Subsequently, an undercut 39 is formed under the hard mask layer 37 pattern by isotropically etching the lower insulating layer 35 using the hard mask layer 37 pattern as a mask.

이때, 등방성 식각 공정은 HDP 산화막의 식각률이 200 초당 0.8 - 0.9 Å 을 식각할 수 있도록 순수와 HF 용액의 혼합비가 280 - 320 : 1 인 BOE 용액을 이용하여 실시한 것이다. At this time, the isotropic etching process was performed using a BOE solution having a mixing ratio of 280-320: 1 of pure water and HF solution so that the etching rate of the HDP oxide film can be etched 0.8-0.9 kPa per 200 seconds.

도 2c를 참조하면, 하드마스크층(37) 패턴을 마스크로 하여 하부절연층(35)을 식각하여 랜딩플러그(미도시)를 노출시키는 저장전극 콘택홀(41)을 형성한다.Referring to FIG. 2C, the lower insulating layer 35 is etched using the hard mask layer 37 pattern as a mask to form a storage electrode contact hole 41 exposing a landing plug (not shown).

이때, 하부절연층(35)의 식각공정은 이방성식각공정으로 실시하되, 플라즈마 를 이용한 에치백 공정으로 실시한 것이다. At this time, the etching process of the lower insulating layer 35 is performed by an anisotropic etching process, an etching back process using a plasma.

도 2d를 참조하면, 저장전극 콘택홀(41)을 포함한 전체표면상부에 질화막(43)을 일정두께 형성하되, 질화막(43)은 언더컷(39) 부분을 매립하게 된다. Referring to FIG. 2D, the nitride film 43 is formed on the entire surface including the storage electrode contact hole 41, but the nitride film 43 fills the undercut 39.

이때, 질화막(43)은 저압화학기상증착 ( LPCVD ) 방법으로 형성한다. At this time, the nitride film 43 is formed by low pressure chemical vapor deposition (LPCVD).

도 2e를 참조하면, 상기 질화막(43)을 이방성식각하여 저장전극 콘택홀(41)의 측벽에 질화막(43) 스페이서를 형성한다. Referring to FIG. 2E, the nitride layer 43 is anisotropically etched to form a nitride layer 43 spacer on the sidewall of the storage electrode contact hole 41.

도 2f를 참조하면, 전체표면상부에 저장전극 콘택홀(41)을 매립하는 플러그용 도전층(45)인 폴리실리콘을 전체표면상부에 형성한다.Referring to FIG. 2F, polysilicon, which is a plug conductive layer 45 for filling the storage electrode contact hole 41, is formed over the entire surface.

도 2g를 참조하면, 플러그용 도전층(45)을 에치백하여 저장전극 콘택 플러그(47)를 형성하되, 언더컷(39) 부분에 매립된 질화막(43)이 식각장벽 역할을 하게 된다. 이로 인하여, 비트라인(33) 상측이 종래기술의 도 1g 보다 평탄하게 형성되어 후속 공정인 저장전극 형성공정시 브릿지를 종래보다 억제할 수 있다. Referring to FIG. 2G, the storage electrode contact plug 47 is formed by etching back the plug conductive layer 45, and the nitride film 43 embedded in the undercut 39 serves as an etch barrier. As a result, the upper side of the bit line 33 is formed to be flatter than that of FIG. 1G of the prior art, so that the bridge can be suppressed in the subsequent step of forming the storage electrode.

이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 형성방법은, 비트라인 상측에서의 브릿지 현상을 억제할 수 있도록 하여 반도체소자의 고집적화에 따른 캐패시터를 용이하게 형성할 수 있도록 하는 효과를 제공한다. As described above, the method of forming a semiconductor device according to the present invention can suppress the bridge phenomenon on the upper side of the bit line, thereby providing an effect of easily forming a capacitor according to high integration of the semiconductor device.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (7)

랜딩플러그 및 비트라인이 형성된 반도체기판 상에 하부절연층을 형성하는 공정과,Forming a lower insulating layer on the semiconductor substrate on which the landing plug and the bit line are formed; 상기 하부절연층 상부에 저장전극 콘택 영역을 노출시키는 하드마스크층을 패터닝하는 공정과,Patterning a hard mask layer exposing a storage electrode contact region on the lower insulating layer; 상기 하드마스크층을 마스크로 하여 하부절연층을 등방성식각하고 이방성식각하여 저장전극 콘택홀을 형성하되, 상기 하드마스크층의 저부로 언더컷을 형성하는 공정과,Forming a storage electrode contact hole by isotropically etching and anisotropically etching the lower insulating layer using the hard mask layer as a mask, and forming an undercut under the hard mask layer; 상기 저장전극 콘택홀 측벽에 질화막 스페이서를 형성하여 상기 언더컷을 매립하는 공정과,Embedding the undercut by forming a nitride film spacer on sidewalls of the storage electrode contact hole; 상기 저장전극 콘택홀에 저장전극 콘택플러그를 형성하는 공정을 포함하는 것을 특징으로 하는 반도체소자의 형성방법.And forming a storage electrode contact plug in the storage electrode contact hole. 제 1 항에 있어서, The method of claim 1, 상기 하드마스크층은 폴리실리콘으로 형성하는 것을 특징으로 하는 반도체소자의 형성방법.The hard mask layer is a method of forming a semiconductor device, characterized in that formed of polysilicon. 제 1 항에 있어서, The method of claim 1, 상기 하드마스크층은 저장전극 콘택마스크를 이용한 사진식각공정으로 형성한 것을 특징으로 하는 반도체소자의 형성방법.And the hard mask layer is formed by a photolithography process using a storage electrode contact mask. 제 1 항에 있어서,The method of claim 1, 상기 등방성 식각 공정은 HDP 산화막의 식각률이 200 초당 0.8 - 0.9 Å 인 식각용액을 이용하여 실시하는 것을 특징으로 하는 반도체소자의 형성방법.The isotropic etching process is a method of forming a semiconductor device, characterized in that using the etching solution of the etching rate of the HDP oxide film 0.8 ~ 0.9 Å / 200 per second. 제 1 항에 있어서,The method of claim 1, 상기 등방성 식각 공정은 순수와 HF 용액의 혼합비가 280 - 320 : 1 인 BOE 용액을 이용하여 실시하는 것을 특징으로 하는 반도체소자의 형성방법.The isotropic etching process is a method of forming a semiconductor device, characterized in that performed using a BOE solution with a mixing ratio of 280-320: 1 of pure water and HF solution. 제 1 항에 있어서, The method of claim 1, 상기 이방성 식각 공정은 플라즈마를 이용한 에치백 공정인 것을 특징으로 하는 반도체소자의 형성방법.The anisotropic etching process is a method of forming a semiconductor device, characterized in that the etching back process using a plasma. 제 1 항에 있어서, The method of claim 1, 상기 질화막 스페이서는 상기 저장전극 콘택홀을 포함한 전체표면상부에 질화막을 형성하고 이를 이방성식각하여 형성하는 것을 특징으로 하는 반도체소자의 형성방법.The nitride film spacer is formed by forming a nitride film on the entire surface including the storage electrode contact hole and anisotropically etching it.
KR1020060047563A 2006-05-26 2006-05-26 Method for forming semiconductor devices KR100819674B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020060047563A KR100819674B1 (en) 2006-05-26 2006-05-26 Method for forming semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060047563A KR100819674B1 (en) 2006-05-26 2006-05-26 Method for forming semiconductor devices

Publications (2)

Publication Number Publication Date
KR20070113805A KR20070113805A (en) 2007-11-29
KR100819674B1 true KR100819674B1 (en) 2008-04-04

Family

ID=39091571

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020060047563A KR100819674B1 (en) 2006-05-26 2006-05-26 Method for forming semiconductor devices

Country Status (1)

Country Link
KR (1) KR100819674B1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0529282A (en) * 1991-07-23 1993-02-05 Sony Corp Dry etching method
KR20000003342A (en) * 1998-06-27 2000-01-15 김영환 Self-align contact hole forming method of semiconductor apparatus
KR20020061942A (en) * 2001-01-19 2002-07-25 삼성전자 주식회사 Wiring of semiconductor device for forming a self-aligned contact and Method of manufacturing the same
KR20030022951A (en) * 2001-09-11 2003-03-19 삼성전자주식회사 Method of manufacturing the electric wiring and method of manufacturing the semiconductor device the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0529282A (en) * 1991-07-23 1993-02-05 Sony Corp Dry etching method
KR20000003342A (en) * 1998-06-27 2000-01-15 김영환 Self-align contact hole forming method of semiconductor apparatus
KR20020061942A (en) * 2001-01-19 2002-07-25 삼성전자 주식회사 Wiring of semiconductor device for forming a self-aligned contact and Method of manufacturing the same
KR20030022951A (en) * 2001-09-11 2003-03-19 삼성전자주식회사 Method of manufacturing the electric wiring and method of manufacturing the semiconductor device the same

Also Published As

Publication number Publication date
KR20070113805A (en) 2007-11-29

Similar Documents

Publication Publication Date Title
US8338304B2 (en) Methods to reduce the critical dimension of semiconductor devices and related semiconductor devices
US10991596B2 (en) Semiconductor structure and method for forming same
US20080160759A1 (en) Method for fabricating landing plug contact in semiconductor device
WO2022160629A1 (en) Manufacturing method for semiconductor structure and semiconductor structure
KR100819674B1 (en) Method for forming semiconductor devices
KR100457161B1 (en) A method for forming a storage node of a semiconductor device
KR100819636B1 (en) A method for forming a storage node of a semiconductor device
KR101031471B1 (en) semiconductor device and method for forming the same
KR101204919B1 (en) Semiconductor device and method for fabricating the same
US7517755B2 (en) Method for fabricating semiconductor device
KR20040060317A (en) A method for forming a storage node of a semiconductor device
KR0166491B1 (en) Capacitor fabrication method of semiconductor device
KR100400321B1 (en) A method for forming of a semiconductor device
KR100772077B1 (en) A method for forming contact hole of semiconductor device
KR20050066192A (en) A method for forming a contact of a semiconductor device
KR20120064841A (en) Method for manufcaturing the semiconductor device
KR101046755B1 (en) Landing plug manufacturing method of semiconductor device
KR20050073635A (en) A method for forming a contact of a semiconductor device
KR20120055153A (en) Method for fabricating semiconductor device
KR20070017593A (en) Method for manufacturing recess gate transitor
KR20050002441A (en) A method for forming a storage node of a semiconductor device
KR20050002356A (en) A method for forming a storage node of a semiconductor device
KR20060036729A (en) Forming method of contact hole in semiconductor device
KR20050063051A (en) Method for forming capacitor of semiconductor device
JP2004186379A (en) Manufacturing method for semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110222

Year of fee payment: 4

LAPS Lapse due to unpaid annual fee