JP2014067819A - Component-embedded substrate mounting body, method of manufacturing the same, and component-embedded substrate - Google Patents

Component-embedded substrate mounting body, method of manufacturing the same, and component-embedded substrate Download PDF

Info

Publication number
JP2014067819A
JP2014067819A JP2012211089A JP2012211089A JP2014067819A JP 2014067819 A JP2014067819 A JP 2014067819A JP 2012211089 A JP2012211089 A JP 2012211089A JP 2012211089 A JP2012211089 A JP 2012211089A JP 2014067819 A JP2014067819 A JP 2014067819A
Authority
JP
Japan
Prior art keywords
component
electronic component
substrate
mounting
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2012211089A
Other languages
Japanese (ja)
Inventor
Hirotaka Ueda
啓貴 上田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujikura Ltd
Original Assignee
Fujikura Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujikura Ltd filed Critical Fujikura Ltd
Priority to JP2012211089A priority Critical patent/JP2014067819A/en
Publication of JP2014067819A publication Critical patent/JP2014067819A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a component-embedded substrate mounting body that allows being downsized, has high degree of freedom in layout of an electronic component to be embedded, and allows improving the heat dissipation characteristics of the electronic component embedded in a component-embedded substrate and an electronic component being surface mounted.SOLUTION: A component-embedded substrate mounting body 100 is composed of a component-embedded substrate 1 and a mounting substrate 2 on which the component-embedded substrate 1 is mounted. The component-embedded substrate 1 has a single-step stacked structure of first to fourth printed wiring base materials 10 to 40 by thermocompression bonding. A first electronic component 90 is embedded in an opening 29 formed in a second resin base material 21 of the second printed wiring base material 20. A first bump 49 is formed on a mounting surface 2a side of the first printed wiring base material 10, and a second bump 97 is formed on a surface side of the fourth printed wiring base material 40. The heat of the first electronic component 90 and a second electronic component 98 passes through vias and wiring lines of each layer, is transmitted from the first bump 49 to the mounting substrate 2, and is dissipated at the mounting substrate 2.

Description

この発明は、電子部品が内蔵されると共に表面実装された部品内蔵基板を実装基板に実装した部品内蔵基板実装体及びその製造方法並びに部品内蔵基板に関する。   The present invention relates to a component built-in substrate mounting body in which an electronic component is embedded and a surface-mounted component built-in substrate is mounted on a mounting substrate, a manufacturing method thereof, and a component built-in substrate.

近年、半導体などの電子部品は小型化や高集積化が求められており、ＣｏＣ（Ｃｈｉｐ ｏｎ Ｃｈｉｐ）やＰｏＰ（Ｐａｃｋａｇｅ ｏｎ Ｐａｃｋａｇｅ）等の三次元パッケージ技術や電子部品を内蔵する部品内蔵基板の採用が拡大化する傾向にある。これらのパッケージ技術等においては、搭載される電子部品の放熱特性を十分に考慮した構造設計が重要となる。   In recent years, electronic components such as semiconductors have been required to be downsized and highly integrated, and three-dimensional package technology such as CoC (Chip on Chip) and PoP (Package on Package) and the use of a component-embedded substrate that incorporates electronic components. Tend to expand. In these package technologies and the like, it is important to design a structure that sufficiently considers the heat dissipation characteristics of the electronic components to be mounted.

一般的に用いられるシリコン半導体からなる電子部品では、例えばＴｊ温度（半導体素子温度）が１７５℃以上になると、半導体素子自体が破壊されてしまう可能性があり、Ｔｊ温度が８０℃〜１００℃の範囲内となるように熱設計が行われている。特に、部品内蔵基板においては、内蔵された電子部品（ＩＣチップや受動部品）の周囲が配線金属材料（例えば、熱伝導係数が約３７０Ｗ／ｍｋの銅）に比べて、熱伝導係数が約１／１０００倍の絶縁樹脂材料（例えば、熱伝導係数が約０．２Ｗ／ｍｋのエポキシ樹脂やポリイミド樹脂）により覆われていることから、放熱特性を考慮した構造設計が必要である。   In an electronic component made of a silicon semiconductor that is generally used, for example, when the Tj temperature (semiconductor element temperature) is 175 ° C. or higher, the semiconductor element itself may be destroyed, and the Tj temperature is 80 ° C. to 100 ° C. The thermal design is made to be within the range. In particular, in the component-embedded substrate, the heat conduction coefficient is about 1 in the periphery of the built-in electronic component (IC chip or passive component) compared to a wiring metal material (for example, copper having a heat conduction coefficient of about 370 W / mk). Since it is covered with an insulating resin material (for example, an epoxy resin or a polyimide resin having a thermal conductivity coefficient of about 0.2 W / mk), a structural design considering heat dissipation characteristics is required.

このように放熱特性を考慮した部品内蔵基板として、下記特許文献１に開示された電子部品内蔵型配線基板が知られている。この電子部品内蔵型配線基板は、内蔵された電子部品の電極形成面とは反対側の面にサーマルビアを形成することで、このサーマルビアから表層の放熱基板を介して電子部品の熱を外気に放熱する構造となっている。   As such a component-embedded substrate in consideration of heat dissipation characteristics, an electronic component-embedded wiring substrate disclosed in Patent Document 1 below is known. In this electronic component built-in wiring board, a thermal via is formed on the surface opposite to the electrode forming surface of the built-in electronic component, so that the heat of the electronic component is externally discharged from the thermal via via the surface heat dissipation substrate. It has a structure that dissipates heat.

特開２００８−２０５１２４号公報JP 2008-205124 A

しかしながら、上記特許文献１に開示された電子部品内蔵型配線基板では、サーマルビア及び放熱基板を介して熱を外気にのみ放熱する構造であるため、電子部品の放熱特性を十分に向上させているとは言い難く、更なる放熱特性の向上を図る余地がある。また、放熱基板の厚さ分だけ基板全体の厚さが増してしまうため、例えば実装基板に実装した場合には全体の高さが増えてしまい、小型化などの要求に十分に応えられる構造とは言い難い。更に、放熱基板を電子部品の近傍に配置する必要があるため、電子部品のレイアウトの自由度が制限されてしまうという問題がある。   However, the electronic component built-in wiring board disclosed in Patent Document 1 has a structure in which heat is radiated only to the outside air through the thermal via and the heat radiating substrate, so that the heat dissipation characteristics of the electronic component are sufficiently improved. However, there is room for further improvement in heat dissipation characteristics. In addition, since the thickness of the entire board increases by the thickness of the heat dissipation board, for example, when mounted on a mounting board, the overall height increases, and a structure that can sufficiently meet demands for miniaturization, etc. Is hard to say. Furthermore, since it is necessary to arrange the heat dissipation board in the vicinity of the electronic component, there is a problem in that the degree of freedom in the layout of the electronic component is limited.

この発明は、上述した従来技術による問題点を解消し、小型化が可能であると共に内蔵される電子部品のレイアウトの自由度が高く、部品内蔵基板に内蔵された電子部品及び表面実装された電子部品の放熱特性の向上を図ることができる部品内蔵基板実装体及びその製造方法並びに部品内蔵基板を提供することを目的とする。   The present invention solves the above-described problems caused by the prior art, and can be downsized and has a high degree of freedom in the layout of the electronic components incorporated therein. The electronic components incorporated in the component-embedded substrate and the surface-mounted electronics It is an object of the present invention to provide a component built-in board mounting body, a manufacturing method thereof, and a component built-in board capable of improving the heat dissipation characteristics of the component.

本発明に係る部品内蔵基板実装体は、樹脂基材に配線パターン及びビアが形成されたプリント配線基材を複数積層すると共に第１の電子部品を内蔵し、第２の電子部品を表面実装してなる部品内蔵基板を、実装基板の実装面上に実装した部品内蔵基板実装体であって、前記部品内蔵基板は、前記複数のプリント配線基材の少なくとも一部が、前記配線パターンにサーマル配線を含み、前記ビアにサーマルビアを含み、一方の表層に形成された第１バンプを介して前記実装基板に実装されると共に、他方の表層に形成された第２バンプを介して前記第２の電子部品が表面実装され、前記第１の電子部品の電極が前記ビア及び前記配線パターンを介して前記第２バンプに接続されると共に、前記電極の形成面と反対側の面が前記サーマルビア及び前記サーマル配線を介して前記第１バンプに接続され、前記第１の電子部品及び前記第２の電子部品が、前記ビア、前記配線パターン、前記サーマル配線、前記サーマルビア、前記第１バンプ及び前記第２バンプを介して前記実装基板に熱的に接続されていることを特徴とする。   The component-embedded board mounting body according to the present invention includes a plurality of printed wiring substrates each having a wiring pattern and a via formed on a resin substrate, and includes a first electronic component, and a second electronic component is surface-mounted. A component built-in board mounting body in which the component built-in board is mounted on a mounting surface of the mounting board, wherein the component built-in board has at least a part of the plurality of printed wiring bases and thermal wiring on the wiring pattern. The vias include thermal vias and are mounted on the mounting substrate via first bumps formed on one surface layer, and the second bumps are formed via second bumps formed on the other surface layer. The electronic component is surface-mounted, the electrode of the first electronic component is connected to the second bump via the via and the wiring pattern, and the surface opposite to the electrode formation surface is the thermal via and The first electronic component and the second electronic component are connected to the first bump via the thermal wiring, and the via, the wiring pattern, the thermal wiring, the thermal via, the first bump, and the It is thermally connected to the mounting substrate through a second bump.

本発明に係る部品内蔵基板実装体によれば、部品内蔵基板に内蔵された第１の電子部品の電極の形成面とは反対側の面が、サーマルビア、サーマル配線及び部品内蔵基板の一方の表層に形成された第１バンプを介して実装基板に接続され、第１の電子部品の電極が、ビア、配線パターン及び部品内蔵基板の他方の表層に形成された第２バンプを介して表面実装された第２の電子部品と接続されている。このため、内蔵された第１の電子部品の熱がサーマルビア、サーマル配線及び第１バンプを放熱経路として伝わって、効率よく確実に実装基板に放熱される。また、表面実装された第２の電子部品の熱が主に第２バンプ、配線パターン、ビア、第１の電子部品、サーマルビア、サーマル配線及び第１バンプを放熱経路として伝わって、同じく効率よく確実に実装基板に放熱される。これにより、第２の電子部品の放熱経路を第１の電子部品の周囲に迂回させて形成する必要がなく放熱経路の短縮化を図ることができると共に、配線設計の自由度を向上させることができる。なお、実装基板は各電子部品や部品内蔵基板と比べると十分に面積が広いので、放熱媒体としては放熱基板よりも良好であり、従来のような放熱基板を設ける必要がない。従って、小型化が可能であると共に電子部品のレイアウトの自由度を高めつつ、内蔵された第１の電子部品及び表面実装された第２の電子部品の放熱特性の向上を図ることができる。   According to the component built-in board mounting body according to the present invention, the surface opposite to the electrode formation surface of the first electronic component built in the component built-in substrate is one of the thermal via, the thermal wiring, and the component built-in substrate. The first electronic component electrode is connected to the mounting substrate via the first bump formed on the surface layer, and the surface mounting is performed via the via, the wiring pattern, and the second bump formed on the other surface layer of the component built-in substrate. Connected to the second electronic component. For this reason, the heat of the built-in first electronic component is transmitted through the thermal via, the thermal wiring, and the first bump as a heat dissipation path, and is efficiently and reliably radiated to the mounting substrate. In addition, the heat of the second electronic component mounted on the surface is mainly transmitted through the second bump, the wiring pattern, the via, the first electronic component, the thermal via, the thermal wiring, and the first bump as a heat dissipation path, so that it is also efficient. Heat is reliably radiated to the mounting board. As a result, it is not necessary to form the heat dissipation path of the second electronic component around the first electronic component, so that the heat dissipation path can be shortened and the degree of freedom in wiring design can be improved. it can. Since the mounting substrate has a sufficiently large area compared to each electronic component and component-embedded substrate, the heat dissipation medium is better than the heat dissipation substrate, and there is no need to provide a conventional heat dissipation substrate. Therefore, it is possible to improve the heat dissipation characteristics of the built-in first electronic component and the surface-mounted second electronic component while reducing the size and increasing the flexibility of the layout of the electronic component.

本発明に係る部品内蔵基板実装体の製造方法は、樹脂基材に配線パターン及びビアが形成されたプリント配線基材を複数積層すると共に第１の電子部品を内蔵し、第２の電子部品を表面実装してなる部品内蔵基板を、実装基板の実装面上に実装した部品内蔵基板実装体の製造方法であって、複数の樹脂基材にサーマル配線を含む前記配線パターン及びサーマルビアを含む前記ビアを形成すると共に、前記複数の樹脂基材のうちの少なくとも一つに前記第１の電子部品を内蔵する開口部を形成して複数のプリント配線基材を形成する工程と、前記開口部に内蔵される前記第１の電子部品の電極が前記ビアを介して前記配線パターンと接続され、前記電極の形成面と反対側の面が前記サーマルビアを介して前記サーマル配線と接続されるように前記複数のプリント配線基材を熱圧着して一括積層し前記部品内蔵基板を形成する工程と、前記部品内蔵基板の一方の表層に前記電極の形成面と反対側の面側の前記サーマル配線と接続される第１バンプを形成すると共に、他方の表層に前記電極側の前記配線パターンと接続される第２バンプを形成する工程と、前記第２バンプを介して前記第２の電子部品を前記部品内蔵基板に実装すると共に、前記第１バンプを介して前記部品内蔵基板を前記実装基板の実装面上に実装する工程とを備えたことを特徴とする。   The method for manufacturing a component-embedded board mounting body according to the present invention includes stacking a plurality of printed wiring substrates each having a wiring pattern and a via formed on a resin substrate, incorporating the first electronic component, and incorporating the second electronic component. A method of manufacturing a component built-in board mounting body in which a component built-in board formed by surface mounting is mounted on a mounting surface of a mounting board, the wiring pattern including thermal wiring on a plurality of resin base materials and the thermal via Forming a via and forming an opening containing the first electronic component in at least one of the plurality of resin substrates to form a plurality of printed wiring substrates; and The electrode of the built-in first electronic component is connected to the wiring pattern through the via, and the surface opposite to the electrode formation surface is connected to the thermal wiring through the thermal via. Previous A step of thermo-compressing a plurality of printed wiring substrates to form a component-embedded substrate, and connecting the thermal wiring on one surface layer of the component-embedded substrate to the surface opposite to the surface on which the electrodes are formed; Forming a first bump to be formed, forming a second bump connected to the wiring pattern on the electrode side on the other surface layer, and connecting the second electronic component to the component via the second bump And mounting the component-embedded substrate on the mounting surface of the mounting substrate via the first bump.

本発明に係る部品内蔵基板実装体の製造方法によれば、部品内蔵基板に内蔵された第１の電子部品の電極の形成面とは反対側の面が、サーマルビアを介してサーマル配線及び第１バンプに接続され、第１の電子部品の電極が、ビアを介して配線パターン及び第２バンプに接続され、部品内蔵基板に表面実装された第２の電子部品が第２バンプに接続された上で、第１バンプを介して部品内蔵基板を実装基板に実装するので、上記と同様の作用効果を奏することができる。   According to the manufacturing method of the component built-in board mounting body according to the present invention, the surface opposite to the electrode formation surface of the first electronic component built in the component built-in substrate is connected to the thermal wiring and the second via the thermal via. Connected to one bump, the electrode of the first electronic component was connected to the wiring pattern and the second bump via the via, and the second electronic component surface-mounted on the component-embedded substrate was connected to the second bump Since the component-embedded substrate is mounted on the mounting substrate via the first bumps, the same effects as described above can be obtained.

本発明に係る部品内蔵基板は、樹脂基材に配線パターン及びビアが形成されたプリント配線基材を複数積層すると共に第１の電子部品を内蔵し、第２の電子部品を表面実装してなる部品内蔵基板であって、前記複数のプリント配線基材の少なくとも一部が、前記配線パターンにサーマル配線を含み、前記ビアにサーマルビアを含み、一方の表層に形成された第１バンプを介して前記実装基板に実装されると共に、他方の表層に形成された第２バンプを介して前記第２の電子部品が表面実装され、前記第１の電子部品の電極が前記ビア及び前記配線パターンを介して前記第２バンプに接続されると共に、前記電極の形成面と反対側の面が前記サーマルビア及び前記サーマル配線を介して前記第１バンプに接続されていることを特徴とする。   The component-embedded substrate according to the present invention is formed by laminating a plurality of printed wiring substrates in which a wiring pattern and vias are formed on a resin substrate, incorporating a first electronic component, and surface-mounting a second electronic component. The component-embedded substrate, wherein at least a part of the plurality of printed wiring substrates includes a thermal wiring in the wiring pattern, a thermal via in the via, and a first bump formed on one surface layer The second electronic component is mounted on the surface via the second bump formed on the other surface layer, and the electrode of the first electronic component is connected to the via and the wiring pattern. And a surface opposite to the electrode forming surface is connected to the first bump via the thermal via and the thermal wiring.

本発明に係る部品内蔵基板によれば、内蔵された第１の電子部品の電極の形成面と反対側の面が、サーマルビア及びサーマル配線を介して一方の表層の第１バンプに接続され、第１の電子部品の電極が、ビア及び配線パターンを介して他方の表層の第２の電子部品が表面実装された第２バンプに接続されており、第１バンプを介して実装基板に熱的に接続されることにより、内蔵された第１の電子部品及び表面実装された第２の電子部品の放熱特性の向上を図ることができる。   According to the component-embedded substrate according to the present invention, the surface opposite to the electrode formation surface of the built-in first electronic component is connected to the first bump on one surface layer via the thermal via and the thermal wiring, The electrode of the first electronic component is connected to the second bump on which the second electronic component on the other surface layer is surface-mounted via the via and the wiring pattern, and is thermally applied to the mounting substrate via the first bump. As a result, the heat dissipation characteristics of the built-in first electronic component and the surface-mounted second electronic component can be improved.

本発明によれば、小型化が可能であると共に内蔵される電子部品のレイアウトの自由度を高めつつ、内蔵された電子部品及び表面実装された電子部品の放熱特性の向上を図ることができる。   ADVANTAGE OF THE INVENTION According to this invention, while improving the freedom degree of the layout of the electronic component incorporated while being miniaturizable, the improvement of the thermal radiation characteristic of the electronic component incorporated and the surface mounted electronic component can be aimed at.

本発明の一実施形態に係る部品内蔵基板実装体の構造を示す断面図である。It is sectional drawing which shows the structure of the component built-in board mounting body which concerns on one Embodiment of this invention. 同部品内蔵基板実装体の製造工程を示すフローチャートである。It is a flowchart which shows the manufacturing process of the same board | substrate with a built-in component. 同部品内蔵基板実装体を製造工程毎に示す断面図である。It is sectional drawing which shows the said component built-in board mounting body for every manufacturing process. 同部品内蔵基板実装体の他の構造を示す断面図である。It is sectional drawing which shows the other structure of the same component built-in board mounting body. 本発明の実施例に係る部品内蔵基板実装体と比較例の部品内蔵基板実装体との放熱特性の解析結果を示す図である。It is a figure which shows the analysis result of the thermal radiation characteristic of the component built-in board mounting body which concerns on the Example of this invention, and the component built-in board mounting body of a comparative example.

以下、添付の図面を参照して、この発明の実施の形態に係る部品内蔵基板実装体及びその製造方法並びに部品内蔵基板を詳細に説明する。   Hereinafter, a component built-in board mounting body, a method for manufacturing the same, and a component built-in board according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

図１は、本発明の一実施形態に係る部品内蔵基板実装体の構造を示す断面図である。図１に示すように、本実施形態に係る部品内蔵基板実装体１００は、部品内蔵基板１と、この部品内蔵基板１が実装面２ａ上に実装された実装基板２とからなる。   FIG. 1 is a cross-sectional view showing a structure of a component built-in board mounting body according to an embodiment of the present invention. As shown in FIG. 1, a component built-in board mounting body 100 according to the present embodiment includes a component built-in board 1 and a mounting board 2 on which the component built-in board 1 is mounted on a mounting surface 2a.

部品内蔵基板１は、第１プリント配線基材１０と、第２プリント配線基材２０と、第３プリント配線基材３０と、第４プリント配線基材４０とを熱圧着により一括積層した構造を備えている。また、部品内蔵基板１は、第２プリント配線基材２０の第２樹脂基材２１に形成された開口部２９内に、第１及び第３プリント配線基材１０，３０に挟まれた状態で内蔵された第１の電子部品９０を備えている。   The component-embedded substrate 1 has a structure in which a first printed wiring substrate 10, a second printed wiring substrate 20, a third printed wiring substrate 30, and a fourth printed wiring substrate 40 are collectively laminated by thermocompression bonding. I have. The component-embedded substrate 1 is sandwiched between the first and third printed wiring substrates 10 and 30 in the opening 29 formed in the second resin substrate 21 of the second printed wiring substrate 20. A built-in first electronic component 90 is provided.

更に、部品内蔵基板１は、第１プリント配線基材１０の実装面２ａ側に形成された第１バンプ４９を備えると共に、第４プリント配線基材４０の表面側に形成された第２バンプ９７を備え、この第２バンプ９７を介して第２の電子部品９８が表面実装された構造を備えている。   Further, the component-embedded substrate 1 includes first bumps 49 formed on the mounting surface 2a side of the first printed wiring substrate 10 and second bumps 97 formed on the surface side of the fourth printed wiring substrate 40. , And a structure in which the second electronic component 98 is surface-mounted through the second bump 97 is provided.

第１〜第４プリント配線基材１０〜４０は、それぞれ第１〜第４樹脂基材１１，２１，３１，４１と、これら第１〜第４樹脂基材の少なくとも片面に形成された信号用配線１２，２２，３２，４２と、例えば第１樹脂基材１１の少なくとも片面に形成されたサーマル配線１３とを備える。なお、上記信号用配線１２，２２，３２，４２は、サーマル配線としても機能する。   The first to fourth printed wiring base materials 10 to 40 are the first to fourth resin base materials 11, 21, 31 and 41, respectively, and signal signals formed on at least one side of the first to fourth resin base materials. Wirings 12, 22, 32, and 42 and, for example, a thermal wiring 13 formed on at least one surface of the first resin substrate 11 are provided. The signal wirings 12, 22, 32, and 42 also function as thermal wirings.

また、第１〜第４プリント配線基材１０〜４０は、それぞれ第１〜第４樹脂基材１１〜４１に形成されたビアホール内に充填形成された信号用ビア１５，２５，３５，４５を備える。なお、第１プリント配線基材１０は、同様にビアホール内に充填形成されたサーマルビア１４を備える。   In addition, the first to fourth printed wiring base materials 10 to 40 include the signal vias 15, 25, 35, and 45 filled in the via holes formed in the first to fourth resin base materials 11 to 41, respectively. Prepare. In addition, the 1st printed wiring board 10 is equipped with the thermal via 14 similarly filled and formed in the via hole.

これら第１〜第４プリント配線基材１０〜４０は、例えば片面銅張積層板（片面ＣＣＬ）や両面銅張積層板（両面ＣＣＬ）などを用いて構成される。本実施形態においては、第２プリント配線基材２０が両面ＣＣＬに基づき形成され、それ以外の第１、第３及び第４プリント配線基材１０，３０，４０が片面ＣＣＬに基づき形成されている。   These 1st-4th printed wiring base materials 10-40 are comprised using a single-sided copper clad laminated board (single-sided CCL), a double-sided copper clad laminated board (double-sided CCL), etc., for example. In this embodiment, the 2nd printed wiring base material 20 is formed based on double-sided CCL, and the other 1st, 3rd and 4th printed wiring base materials 10, 30, and 40 are formed based on single-sided CCL. .

従って、第２プリント配線基材２０の信号用配線２２は第２樹脂基材２１の両面に形成され、信号用ビア２５はこれら両面の信号用配線２２を層間接続している。この場合、信号用ビア２５は、例えばスルーホールにめっきを施した構造からなるもので構成されている。   Accordingly, the signal wiring 22 of the second printed wiring substrate 20 is formed on both surfaces of the second resin substrate 21, and the signal via 25 connects the signal wirings 22 on both surfaces with each other. In this case, the signal via 25 is composed of, for example, a structure in which a through hole is plated.

第１〜第４樹脂基材１１〜４１は、それぞれ例えば厚さ２５μｍ程度の樹脂フィルムにより構成されている。樹脂フィルムとしては、例えば熱可塑性のポリイミド、ポリオレフィン、液晶ポリマー等からなる樹脂フィルムや、熱硬化性のエポキシ樹脂からなる樹脂フィルムなどを用いることができる。   The 1st-4th resin base materials 11-41 are each comprised by the resin film about 25 micrometers thick, for example. As the resin film, for example, a resin film made of thermoplastic polyimide, polyolefin, liquid crystal polymer, or the like, a resin film made of a thermosetting epoxy resin, or the like can be used.

第１及び第２の電子部品９０，９８は、例えばＩＣチップ等の半導体部品や受動部品などであり、図１における第１及び第２の電子部品９０，９８は、再配線を施したＷＬＰ（Ｗａｆｅｒ Ｌｅｖｅｌ Ｐａｃｋａｇｅ）を示している。第１及び第２の電子部品９０，９８のそれぞれの電極形成面９１ｂ，９９ｂには、複数の再配線電極９１，９９が形成されている。   The first and second electronic components 90 and 98 are, for example, semiconductor components such as IC chips or passive components, and the first and second electronic components 90 and 98 in FIG. Wafer Level Package). A plurality of rewiring electrodes 91 and 99 are formed on the electrode formation surfaces 91b and 99b of the first and second electronic components 90 and 98, respectively.

信号用配線１２，２２，３２，４２及びサーマル配線１３は、銅箔などの導電材をパターン形成してなる。信号用ビア１５，３５，４５及びサーマルビア１４は、ビアホール内にそれぞれ充填された導電ペーストからなり、信号用ビア２５は、上述したようにめっきにより形成される。信号用配線及び信号用ビアは、一部を除いて第１の電子部品９０の外周側に配置されるように形成され、サーマル配線及びサーマルビアは、第１の電子部品９０の電極形成面９１ｂとは反対側の裏面９１ａ側に配置されるように形成される。   The signal wirings 12, 22, 32, and the thermal wiring 13 are formed by patterning a conductive material such as copper foil. The signal vias 15, 35, 45 and the thermal via 14 are each made of a conductive paste filled in the via hole, and the signal via 25 is formed by plating as described above. The signal wiring and the signal via are formed so as to be arranged on the outer peripheral side of the first electronic component 90 except for a part, and the thermal wiring and the thermal via are formed on the electrode forming surface 91b of the first electronic component 90. It is formed so as to be arranged on the back surface 91a side opposite to the side.

導電ペーストは、例えばニッケル、金、銀、亜鉛、アルミニウム、鉄、タングステン等から選択される少なくとも１種類の低電気抵抗の金属粒子と、ビスマス、インジウム、鉛等から選択される少なくとも１種類の低融点の金属粒子とを含む。そして、導電ペーストは、これらの金属粒子に錫を成分として含有させ、エポキシ、アクリル、ウレタン等を主成分とするバインダ成分を混合したペーストからなる。   The conductive paste is, for example, at least one kind of low electrical resistance metal particles selected from nickel, gold, silver, zinc, aluminum, iron, tungsten, etc., and at least one kind selected from bismuth, indium, lead, etc. Metal particles having a melting point. The conductive paste is made of a paste in which tin is contained as a component in these metal particles and a binder component mainly composed of epoxy, acrylic, urethane or the like is mixed.

このように構成された導電ペーストは、含有された錫と低融点の金属が２００℃以下で溶融し合金を形成することができ、特に銅や銀等とは金属間化合物を形成することができる特性を備える。なお、導電ペーストは、例えば粒子径がナノレベルの金、銀、銅、ニッケル等のフィラーが、上記のようなバインダ成分に混合されたナノペーストで構成することもできる。   In the conductive paste thus configured, the contained tin and the low melting point metal can be melted at 200 ° C. or less to form an alloy, and particularly an intermetallic compound can be formed with copper, silver, or the like. With characteristics. Note that the conductive paste can also be formed of a nanopaste in which fillers such as gold, silver, copper, and nickel having a nanometer particle size are mixed with the binder component as described above.

その他、導電ペーストは、上記ニッケル等の金属粒子が、上記のようなバインダ成分に混合されたペーストで構成することもできる。この場合、導電ペーストは、金属粒子同士が接触することで電気的接続が行われる特性となる。導電ペーストのビアホールへの充填方法としては、例えば印刷工法、スピン塗布工法、スプレー塗布工法、ディスペンス工法、ラミネート工法、及びこれらを併用した工法等を用いることができる。   In addition, the conductive paste can also be composed of a paste in which metal particles such as nickel are mixed with the binder component as described above. In this case, the conductive paste has a characteristic that electrical connection is made when metal particles come into contact with each other. As a method for filling the via holes with the conductive paste, for example, a printing method, a spin coating method, a spray coating method, a dispensing method, a laminating method, a method using these in combination, or the like can be used.

第１及び第２バンプ４９，９７は、半田等からなり、第１バンプ４９は第１プリント配線基材１０の第１樹脂基材１１の実装面２ａ側に形成された信号用配線１２及びサーマル配線１３上のソルダーレジスト４８が被覆していない部分に形成されている。第２バンプ９７は、同様に第４プリント配線基材の信号用配線４２上のソルダーレジスト４８が被覆していない部分に形成されている。   The first and second bumps 49 and 97 are made of solder or the like, and the first bump 49 is the signal wiring 12 formed on the first resin base 11 on the mounting surface 2a side of the first printed wiring base 10 and the thermal. The solder resist 48 on the wiring 13 is formed in a portion not covered. Similarly, the second bump 97 is formed in a portion not covered with the solder resist 48 on the signal wiring 42 of the fourth printed wiring board.

第２の電子部品９８は、この第２バンプ９７を介して再配線電極９９が信号用配線４２に接続され、電極形成面９９ｂとソルダーレジスト４８との間に充填形成されたアンダーフィル９６を介して部品内蔵基板１に表面実装されている。また、部品内蔵基板１は、第１バンプ４９を介して実装基板２の実装面２ａ上に実装されている。   In the second electronic component 98, the rewiring electrode 99 is connected to the signal wiring 42 via the second bump 97, and the underfill 96 is formed between the electrode forming surface 99 b and the solder resist 48. And mounted on the component-embedded substrate 1. The component built-in substrate 1 is mounted on the mounting surface 2 a of the mounting substrate 2 via the first bumps 49.

なお、第１〜第４プリント配線基材１０〜４０は、接着層９を介して積層されている。接着層９は、例えばエポキシ系やアクリル系接着剤など、揮発成分が含まれた有機系接着剤等からなる。   In addition, the 1st-4th printed wiring base materials 10-40 are laminated | stacked through the contact bonding layer 9. As shown in FIG. The adhesive layer 9 is made of an organic adhesive containing a volatile component, such as an epoxy adhesive or an acrylic adhesive.

このように構成された部品内蔵基板実装体１００では、部品内蔵基板１に内蔵された第１の電子部品９０の熱及び部品内蔵基板１に表面実装された第２の電子部品９８の熱は、それぞれ次のような放熱経路を辿って実装基板２に伝えられる。まず、第１の電子部品９０については、主に熱が裏面９１ａから、この裏面９１ａに接続された第１プリント配線基材１０のサーマルビア１４に伝わる。   In the component built-in substrate mounting body 100 configured as described above, the heat of the first electronic component 90 built in the component built-in substrate 1 and the heat of the second electronic component 98 surface-mounted on the component built-in substrate 1 are: Each is transmitted to the mounting substrate 2 by following the following heat dissipation path. First, for the first electronic component 90, heat is mainly transmitted from the back surface 91a to the thermal via 14 of the first printed wiring board 10 connected to the back surface 91a.

サーマルビア１４に伝わった熱は、第１プリント配線基材１０のサーマル配線１３を介して第１バンプ４９に伝わり、この第１バンプ４９に伝わった熱は、第１バンプ４９を介して部品内蔵基板１よりも面積の大きな実装基板２に伝わって、実装基板２から放熱される。   The heat transferred to the thermal via 14 is transferred to the first bump 49 via the thermal wiring 13 of the first printed wiring board 10, and the heat transferred to the first bump 49 is built into the component via the first bump 49. The heat is transmitted to the mounting substrate 2 having a larger area than the substrate 1 and is radiated from the mounting substrate 2.

これと同時に、第１の電子部品９０の熱は、再配線電極９１から、この再配線電極９１に接続された第３プリント配線基材３０信号用ビア３５に伝わる。信号用ビア３５に伝わった熱は、第３プリント配線基材３０の信号用配線３２から、第４プリント配線基材４０の信号用ビア４５に伝わり、更に信号用配線４２に伝わる。   At the same time, the heat of the first electronic component 90 is transmitted from the rewiring electrode 91 to the third printed wiring board 30 signal via 35 connected to the rewiring electrode 91. The heat transmitted to the signal via 35 is transmitted from the signal wiring 32 of the third printed wiring substrate 30 to the signal via 45 of the fourth printed wiring substrate 40 and further transmitted to the signal wiring 42.

そして、信号用配線４２に伝わった熱は、第１の電子部品９０の外周側に形成された信号用ビア４５を伝わって、第３プリント配線基材３０の信号用配線３２及び信号用ビア３５を介し、第２プリント配線基材２０の信号用配線２２及び信号用ビア２５に伝わる。その後、第１プリント配線基材１０の信号用ビア１５を通って信号用配線１２に伝わり、第１バンプ４９から実装基板２に伝えられ、放熱される。   Then, the heat transmitted to the signal wiring 42 is transmitted through the signal via 45 formed on the outer peripheral side of the first electronic component 90, and the signal wiring 32 and the signal via 35 of the third printed wiring substrate 30. The signal is transmitted to the signal wiring 22 and the signal via 25 of the second printed wiring board 20 via the. Thereafter, the signal is transmitted to the signal wiring 12 through the signal via 15 of the first printed wiring substrate 10, transmitted from the first bump 49 to the mounting substrate 2, and radiated.

次に、第２の電子部品９８については、例えば裏面９９ａ等から外気に放熱される以外の熱が電極形成面９９ｂ側の再配線電極９９から、この再配線電極９９に接続された第２バンプ９７に伝わって、第４プリント配線基材４０の信号用配線４２に伝わる。この信号用配線４２に伝わった熱は、例えば上記のように第１の電子部品９０の外周側に形成された各プリント配線基材の信号用配線４２，３２，２２，１２及び信号用ビア４５，３５，２５，１５を介して第１バンプ４９から実装基板２に伝えられて放熱される。   Next, for the second electronic component 98, for example, the second bump connected to the redistribution electrode 99 from the redistribution electrode 99 on the electrode formation surface 99b side except for heat radiated from the back surface 99a to the outside air. 97 and transmitted to the signal wiring 42 of the fourth printed wiring board 40. The heat transmitted to the signal wiring 42 is, for example, the signal wirings 42, 32, 22, 12 and the signal via 45 of each printed wiring board formed on the outer peripheral side of the first electronic component 90 as described above. , 35, 25, 15 are transmitted from the first bump 49 to the mounting substrate 2 to be dissipated.

これと同時に、第２の電子部品９８の熱は、主に第１の電子部品９０との間に配置された信号用配線４２，３２及び信号用ビア４５，３５を伝わって第１の電子部品９０に伝わる。そして、第１の電子部品９０を介し、サーマルビア１４及びサーマル配線１３に伝わって、第１バンプ４９から実装基板２に伝えられ、放熱される。   At the same time, the heat of the second electronic component 98 is mainly transmitted through the signal wirings 42 and 32 and the signal vias 45 and 35 arranged between the first electronic component 90 and the first electronic component. 90. Then, the heat is transmitted to the thermal via 14 and the thermal wiring 13 through the first electronic component 90, transmitted from the first bump 49 to the mounting substrate 2, and radiated.

このような構造により、部品内蔵基板１に内蔵された第１の電子部品９０で発生した熱の殆ど、及び表面実装された第２の電子部品９８で発生した熱の一部が、従来のような放熱基板が不要な構造の部品内蔵基板１から実装基板２に伝わって放熱されることとなる。これにより、第２の電子部品９８の放熱経路を第１の電子部品９０の周囲に迂回させて形成する必要がなく、放熱経路の短縮化を図ることができる。   With such a structure, most of the heat generated in the first electronic component 90 built in the component-embedded substrate 1 and part of the heat generated in the second electronic component 98 mounted on the surface are as in the conventional case. Thus, heat is transmitted from the component-embedded substrate 1 having a structure that does not require a heat dissipation substrate to the mounting substrate 2. Thereby, it is not necessary to form the heat dissipation path of the second electronic component 98 around the first electronic component 90, and the heat dissipation path can be shortened.

また、上記のように放熱経路に制限が少ないため配線設計の自由度を向上させることができる。このため、部品内蔵基板実装体１００の小型化が可能であると共に、第１の電子部品９０のレイアウト自由度を高めることができ、部品内蔵基板１に内蔵された第１の電子部品９０及び表面実装された第２の電子部品９８の放熱特性の向上を図ることができる。   Moreover, since there are few restrictions on a heat radiation path as mentioned above, the freedom degree of wiring design can be improved. Therefore, it is possible to reduce the size of the component built-in substrate mounting body 100 and to increase the degree of freedom in layout of the first electronic component 90. The first electronic component 90 and the surface built in the component built-in substrate 1 can be increased. The heat dissipation characteristics of the mounted second electronic component 98 can be improved.

また、第１及び第２の電子部品９０，９８間の信号経路を短く構成して信号伝送特性（例えば、信号伝送速度）を向上させることができると共に、電子部品の内蔵や表面実装による配置効率を放熱特性を低下させることなく高めることができる。   In addition, the signal path between the first and second electronic components 90 and 98 can be shortened to improve the signal transmission characteristics (for example, signal transmission speed), and the placement efficiency due to the built-in electronic components and surface mounting. Can be improved without deteriorating the heat dissipation characteristics.

次に、本実施形態に係る部品内蔵基板実装体１００の製造方法について説明する。
図２は、部品内蔵基板実装体の製造工程を示すフローチャートである。図３は、部品内蔵基板実装体を製造工程毎に示す断面図である。まず、例えば一方の面に導体層が形成された、片面ＣＣＬ等の樹脂基材を複数準備し（ステップＳ１００）、各樹脂基材にエッチング等を行って、それぞれに信号用配線やサーマル配線等の配線パターンを形成する（ステップＳ１０２）。 Next, a method for manufacturing the component built-in substrate mounting body 100 according to the present embodiment will be described.
FIG. 2 is a flowchart showing a manufacturing process of the component built-in board mounting body. FIG. 3 is a cross-sectional view showing the component built-in board mounting body for each manufacturing process. First, for example, a plurality of resin base materials such as a single-sided CCL having a conductor layer formed on one surface are prepared (step S100), and each resin base material is etched to provide signal wiring, thermal wiring, etc., respectively. The wiring pattern is formed (step S102).

次に、樹脂基材に接着剤を貼り付けるなどして接着層を形成し（ステップＳ１０４）、レーザ加工機等によってビアホールを形成する（ステップＳ１０６）。そして、ビアホールに導電ペーストを充填して信号用ビアやサーマルビアを形成する（ステップＳ１０８）。ここまでの処理で、図３（ａ）に示すような第１プリント配線基材１０や、図３（ｃ）に示すような第３プリント配線基材３０、或いは第４プリント配線基材４０等の、配線パターン及びビアを有する基本的なプリント配線基材を複数作製する。なお、図３（ａ），（ｃ）においては、図１に示したものと上下位置を逆さにして図示している。   Next, an adhesive layer is formed by sticking an adhesive on the resin base material (step S104), and a via hole is formed by a laser processing machine or the like (step S106). Then, via holes are filled with a conductive paste to form signal vias and thermal vias (step S108). By the processing so far, the first printed wiring substrate 10 as shown in FIG. 3A, the third printed wiring substrate 30 as shown in FIG. 3C, the fourth printed wiring substrate 40, or the like. A plurality of basic printed wiring substrates having wiring patterns and vias are prepared. In FIGS. 3A and 3C, the vertical position is inverted from that shown in FIG.

一方、図３（ｂ）に示すような第２プリント配線基材２０は、例えば両面ＣＣＬ等の第２樹脂基材２１に、一方の信号用配線２２（詳細には信号用配線２２に接続するランド部）を貫通させないように他方の信号用配線２３（詳細には信号用配線２２に接続するランド部）側から貫通孔を形成し、貫通孔内にめっき処理を施して信号用ビア２５を形成した後、開口部２９を形成する（ステップＳ１１０）。こうして、第１〜第４プリント配線基材１０〜４０が準備される。   On the other hand, a second printed wiring substrate 20 as shown in FIG. 3B is connected to a second resin substrate 21 such as a double-sided CCL, for example, and one signal wiring 22 (in detail, to the signal wiring 22). A through hole is formed from the other signal wiring 23 side (specifically, a land portion connected to the signal wiring 22) side so as not to penetrate the land portion, and plating is performed in the through hole to form the signal via 25. After the formation, the opening 29 is formed (step S110). In this way, the 1st-4th printed wiring base materials 10-40 are prepared.

そして、第１の電子部品９０の再配線電極９１を、第３プリント配線基材３０の信号用ビア３５に、例えば電子部品用実装機を用いて位置合わせして、第３プリント配線基材３０の接着層９及び信号用ビア３５の導電ペーストの硬化温度以下の温度で加熱することによって、第１の電子部品９０を仮留め接着する（ステップＳ１１２）。   Then, the rewiring electrode 91 of the first electronic component 90 is aligned with the signal via 35 of the third printed wiring substrate 30 by using, for example, an electronic component mounting machine, and the third printed wiring substrate 30. The first electronic component 90 is temporarily bonded by heating at a temperature lower than the curing temperature of the conductive paste of the adhesive layer 9 and the signal via 35 (step S112).

その後、第１〜第４プリント配線基材１０〜４０を、それぞれ位置合わせして例えば加熱温度２００℃以下の温度で熱圧着する（ステップＳ１１４）ことにより一括積層し、部品内蔵基板１を作製する。そして、図３（ｄ）に示すように、部品内蔵基板１における第１プリント配線基材１０の信号用配線１２及びサーマル配線１３側の第１樹脂基材１１上、及び第４プリント配線基材４０の信号用配線４２側の第４樹脂基材４１上に、それぞれソルダーレジスト４８をパターン形成する（ステップＳ１１６）。   Thereafter, the first to fourth printed wiring substrates 10 to 40 are aligned and thermo-compression bonded at, for example, a heating temperature of 200 ° C. or less (step S114) to produce the component built-in substrate 1. . And as shown in FIG.3 (d), on the signal wiring 12 of the 1st printed wiring base material 10 in the component built-in board | substrate 1, the 1st resin base material 11 by the side of the thermal wiring 13, and the 4th printed wiring base material A solder resist 48 is formed on the fourth resin base 41 on the 40 signal wiring 42 side (step S116).

そして、ソルダーレジスト４８がない部分の各配線１２，１３，４２上に、半田等を充填して第１バンプ４９及び第２バンプ９７をそれぞれ形成した上で（ステップＳ１１８）、例えば部品内蔵基板１を実装基板２に実装する（ステップＳ１２０）。部品内蔵基板１を実装基板２に実装したら、図３（ｅ）に示すように、第２の電子部品９８を部品内蔵基板１に表面実装し（ステップＳ１２２）、アンダーフィル９６を施して、図１に示すような部品内蔵基板実装体１００を製造する。   Then, the first bump 49 and the second bump 97 are respectively formed by filling solder, etc., on the wirings 12, 13, and 42 where the solder resist 48 is not provided (step S118). Is mounted on the mounting board 2 (step S120). When the component-embedded substrate 1 is mounted on the mounting substrate 2, as shown in FIG. 3E, the second electronic component 98 is surface-mounted on the component-embedded substrate 1 (step S122), and an underfill 96 is applied. 1 is manufactured. As shown in FIG.

図４は、部品内蔵基板実装体の他の構造を示す断面図である。図４に示すように、第２の電子部品９８の再配線電極９９の電極形成面９９ｂ側に設けられたアンダーフィル９６の代わりに、部品内蔵基板１の第４プリント配線基材４０の第２の電子部品９８の表面十層側の全体を、例えばモールド樹脂９５で覆うようにして、実装基板２に実装し、部品内蔵基板実装体２００を構成するようにしても良い。   FIG. 4 is a cross-sectional view showing another structure of the component built-in board mounting body. As shown in FIG. 4, instead of the underfill 96 provided on the electrode forming surface 99b side of the rewiring electrode 99 of the second electronic component 98, the second printed wiring substrate 40 of the fourth printed wiring board 40 of the component-embedded substrate 1 is used. The entire surface 10 layers of the electronic component 98 may be covered with, for example, a mold resin 95 and mounted on the mounting substrate 2 to constitute the component built-in substrate mounting body 200.

以下、実施例により本発明に係る部品内蔵基板実装体を具体的に説明する。
図５は、本発明の実施例に係る部品内蔵基板実装体と比較例の部品内蔵基板実装体との放熱特性の解析結果を示す図である。図５の縦軸はＴｊ温度を示している。実施例及び比較例共に、上述したような４層構造の部品内蔵基板を実装基板に実装した部品内蔵基板実装体を用いた。 Hereinafter, the component built-in board mounting body according to the present invention will be described in detail by way of examples.
FIG. 5 is a diagram showing an analysis result of heat radiation characteristics of the component built-in board mounting body according to the example of the present invention and the component built-in board mounting body of the comparative example. The vertical axis in FIG. 5 indicates the Tj temperature. In both the examples and comparative examples, the component built-in board mounting body in which the component built-in board having the four-layer structure as described above was mounted on the mounting board was used.

比較例１は、電子部品の裏面側にサーマルビアを形成せず、電子部品の電極が実装基板側に配置された構造の部品内蔵基板を実装基板に実装した部品内蔵基板実装体である。実施例１は、部品内蔵基板実装体１００と同様の構造とした。   Comparative Example 1 is a component built-in substrate mounting body in which a component built-in substrate having a structure in which an electrode of an electronic component is arranged on the mounting substrate side without mounting a thermal via on the back surface side of the electronic component is mounted on the mounting substrate. In Example 1, a structure similar to that of the component built-in substrate mounting body 100 was used.

Ｔｊ温度の解析は、汎用ソフトウェア「ＡＮＳＹＳ（登録商標）」を用い、解析の境界条件は次のようなものとした。すなわち、比較例１及び実施例１について、部品内蔵基板に内蔵された電子部品及び表面実装された電子部品それぞれに１ワット（Ｗ）の発熱量を与え、部品内蔵基板実装体の外気との接触面には外気の対流がない静止状態として、４．５Ｗ／ｍ２ｋの熱伝達係数で雰囲気温度２５℃の環境下にて解析を行った。 For the analysis of the Tj temperature, general-purpose software “ANSYS (registered trademark)” was used, and the boundary conditions of the analysis were as follows. That is, in Comparative Example 1 and Example 1, a heat generation amount of 1 watt (W) is given to each of the electronic component built in the component built-in substrate and the surface-mounted electronic component, and contact with the outside air of the component built-in substrate mounting body. The surface was analyzed in an environment where the ambient temperature was 25 ° C. with a heat transfer coefficient of 4.5 W / m 2 k in a static state where there was no convection of outside air.

図５に示すように、解析結果によれば、比較例１はＴｊ温度が１１５℃近辺となったのに対し、実施例１ではＴｊ温度は９４℃程度となった。このことから、比較例１のようにサーマルビアがないものは部品内蔵基板実装体の放熱特性を向上させることはできないことが判明した。   As shown in FIG. 5, according to the analysis result, the Tj temperature was around 115 ° C. in Comparative Example 1, whereas the Tj temperature was about 94 ° C. in Example 1. From this, it was found that the heat dissipation characteristic of the component built-in board mounting body cannot be improved if there is no thermal via as in Comparative Example 1.

一方、実施例１のように、ビア、配線パターン、サーマルビアやサーマル配線を介して部品内蔵基板に内蔵された電子部品及び表面実装された電子部品の熱を実装基板にて放熱するタイプの部品内蔵基板実装体では、比較例１に比べて明らかに放熱特性が向上していることが判明した。特に、実施例１のように、発熱源と放熱体との実装方向の距離が近く、電子部品同士の配線距離が短い構造であれば、放熱特性を更に向上させることができる結果となった。   On the other hand, as in the first embodiment, electronic components built into the component-embedded substrate and via-mounting heat are radiated from the mounting substrate via vias, wiring patterns, thermal vias and thermal wiring. It was found that the heat dissipation characteristics were clearly improved in the built-in substrate mounting body as compared with Comparative Example 1. In particular, as in Example 1, if the structure in which the distance between the heat generation source and the heat dissipator is short and the wiring distance between the electronic components is short, the heat dissipation characteristics can be further improved.

１ 部品内蔵基板
２ 実装基板
２ａ 実装面
９ 接着層
１０ 第１プリント配線基材
１１ 第１樹脂基材
１２ 信号用配線
１３ サーマル配線
１４ サーマルビア
１５ 信号用ビア
２０ 第２プリント配線基材
２９ 開口部
３０ 第３プリント配線基材
４０ 第４プリント配線基材
４８ ソルダーレジスト
４９ 第１バンプ
９０ 第１の電子部品
９１ａ 裏面
９７ 第２バンプ
９８ 第２の電子部品
１００，２００ 部品内蔵基板実装体 DESCRIPTION OF SYMBOLS 1 Component built-in board 2 Mounting board 2a Mounting surface 9 Adhesive layer 10 1st printed wiring base material 11 1st resin base material 12 Signal wiring 13 Thermal wiring 14 Thermal via 15 Signal via 20 20 Second printed wiring base material 29 Opening part 30 3rd printed wiring base material 40 4th printed wiring base material 48 Solder resist 49 1st bump 90 1st electronic component 91a Back surface 97 2nd bump 98 2nd electronic component 100,200 Component built-in board mounting body

Claims (3)

樹脂基材に配線パターン及びビアが形成されたプリント配線基材を複数積層すると共に第１の電子部品を内蔵し、第２の電子部品を表面実装してなる部品内蔵基板を、実装基板の実装面上に実装した部品内蔵基板実装体であって、
前記部品内蔵基板は、前記複数のプリント配線基材の少なくとも一部が、前記配線パターンにサーマル配線を含み、前記ビアにサーマルビアを含み、
一方の表層に形成された第１バンプを介して前記実装基板に実装されると共に、他方の表層に形成された第２バンプを介して前記第２の電子部品が表面実装され、
前記第１の電子部品の電極が前記ビア及び前記配線パターンを介して前記第２バンプに接続されると共に、前記電極の形成面と反対側の面が前記サーマルビア及び前記サーマル配線を介して前記第１バンプに接続され、
前記第１の電子部品及び前記第２の電子部品が、前記ビア、前記配線パターン、前記サーマル配線、前記サーマルビア、前記第１バンプ及び前記第２バンプを介して前記実装基板に熱的に接続されている
ことを特徴とする部品内蔵基板実装体。 Mounting a printed circuit board having a wiring pattern and vias formed on a resin substrate, mounting a first electronic component and mounting a second electronic component on the surface of the mounting substrate A component built-in board mounting body mounted on a surface,
In the component-embedded substrate, at least a part of the plurality of printed wiring substrates includes a thermal wiring in the wiring pattern, and includes a thermal via in the via,
The first electronic component is mounted on the mounting substrate via the first bump formed on one surface layer, and the second electronic component is surface-mounted via the second bump formed on the other surface layer,
The electrode of the first electronic component is connected to the second bump via the via and the wiring pattern, and the surface opposite to the electrode forming surface is connected to the second via the thermal via and the thermal wiring. Connected to the first bump,
The first electronic component and the second electronic component are thermally connected to the mounting substrate through the via, the wiring pattern, the thermal wiring, the thermal via, the first bump, and the second bump. A component built-in board mounting body characterized by being made. 樹脂基材に配線パターン及びビアが形成されたプリント配線基材を複数積層すると共に第１の電子部品を内蔵し、第２の電子部品を表面実装してなる部品内蔵基板を、実装基板の実装面上に実装した部品内蔵基板実装体の製造方法であって、
複数の樹脂基材にサーマル配線を含む前記配線パターン及びサーマルビアを含む前記ビアを形成すると共に、前記複数の樹脂基材のうちの少なくとも一つに前記第１の電子部品を内蔵する開口部を形成して複数のプリント配線基材を形成する工程と、
前記開口部に内蔵される前記第１の電子部品の電極が前記ビアを介して前記配線パターンと接続され、前記電極の形成面と反対側の面が前記サーマルビアを介して前記サーマル配線と接続されるように前記複数のプリント配線基材を熱圧着して一括積層し前記部品内蔵基板を形成する工程と、
前記部品内蔵基板の一方の表層に前記電極の形成面と反対側の面側の前記サーマル配線と接続される第１バンプを形成すると共に、他方の表層に前記電極側の前記配線パターンと接続される第２バンプを形成する工程と、
前記第２バンプを介して前記第２の電子部品を前記部品内蔵基板に実装すると共に、前記第１バンプを介して前記部品内蔵基板を前記実装基板の実装面上に実装する工程とを備えた
ことを特徴とする部品内蔵基板実装体の製造方法。 Mounting a printed circuit board having a wiring pattern and vias formed on a resin substrate, mounting a first electronic component and mounting a second electronic component on the surface of the mounting substrate A method of manufacturing a component-embedded board mounting body mounted on a surface,
The wiring pattern including thermal wiring and the via including thermal via are formed in a plurality of resin base materials, and an opening for incorporating the first electronic component in at least one of the plurality of resin base materials is provided. Forming and forming a plurality of printed wiring substrates; and
The electrode of the first electronic component built in the opening is connected to the wiring pattern through the via, and the surface opposite to the electrode formation surface is connected to the thermal wiring through the thermal via. Forming the component-embedded substrate by thermally laminating and laminating the plurality of printed wiring substrates as described above,
Formed on one surface layer of the component-embedded substrate is a first bump connected to the thermal wiring on the surface opposite to the electrode formation surface, and connected to the wiring pattern on the electrode side on the other surface layer. Forming a second bump,
Mounting the second electronic component on the component-embedded substrate via the second bump, and mounting the component-embedded substrate on the mounting surface of the mounting substrate via the first bump. A method of manufacturing a component-embedded board mounting body, wherein: 樹脂基材に配線パターン及びビアが形成されたプリント配線基材を複数積層すると共に第１の電子部品を内蔵し、第２の電子部品を表面実装してなる部品内蔵基板であって、
前記複数のプリント配線基材の少なくとも一部が、前記配線パターンにサーマル配線を含み、前記ビアにサーマルビアを含み、
一方の表層に形成された第１バンプを介して前記実装基板に実装されると共に、他方の表層に形成された第２バンプを介して前記第２の電子部品が表面実装され、
前記第１の電子部品の電極が前記ビア及び前記配線パターンを介して前記第２バンプに接続されると共に、前記電極の形成面と反対側の面が前記サーマルビア及び前記サーマル配線を介して前記第１バンプに接続されている
ことを特徴とする部品内蔵基板。 A component-embedded substrate in which a plurality of printed wiring substrates each having a wiring pattern and vias formed on a resin substrate are stacked and a first electronic component is embedded, and a second electronic component is surface-mounted,
At least some of the plurality of printed wiring substrates include thermal wiring in the wiring pattern, and include thermal vias in the vias,
The first electronic component is mounted on the mounting substrate via the first bump formed on one surface layer, and the second electronic component is surface-mounted via the second bump formed on the other surface layer,
The electrode of the first electronic component is connected to the second bump via the via and the wiring pattern, and the surface opposite to the electrode forming surface is connected to the second via the thermal via and the thermal wiring. A component-embedded board connected to the first bump.
JP2012211089A 2012-09-25 2012-09-25 Component-embedded substrate mounting body, method of manufacturing the same, and component-embedded substrate Pending JP2014067819A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2012211089A JP2014067819A (en) 2012-09-25 2012-09-25 Component-embedded substrate mounting body, method of manufacturing the same, and component-embedded substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012211089A JP2014067819A (en) 2012-09-25 2012-09-25 Component-embedded substrate mounting body, method of manufacturing the same, and component-embedded substrate

Publications (1)

Publication Number Publication Date
JP2014067819A true JP2014067819A (en) 2014-04-17

Family

ID=50743938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012211089A Pending JP2014067819A (en) 2012-09-25 2012-09-25 Component-embedded substrate mounting body, method of manufacturing the same, and component-embedded substrate

Country Status (1)

Country Link
JP (1) JP2014067819A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017086095A1 (en) * 2015-11-17 2017-05-26 株式会社村田製作所 Multilayer substrate and electronic apparatus
JP2020053524A (en) * 2018-09-26 2020-04-02 日亜化学工業株式会社 Circuit board and component mounting board, and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009158742A (en) * 2007-12-27 2009-07-16 Shinko Electric Ind Co Ltd Electronic apparatus
JP2009164287A (en) * 2007-12-28 2009-07-23 Fujikura Ltd Multilayer printed wiring board and manufacturing method thereof
JP2010118589A (en) * 2008-11-14 2010-05-27 Shinko Electric Ind Co Ltd Method of manufacturing wiring board with electronic component incorporated therein
JP2010123632A (en) * 2008-11-17 2010-06-03 Shinko Electric Ind Co Ltd Method for manufacturing wiring board with built-in electronic component

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009158742A (en) * 2007-12-27 2009-07-16 Shinko Electric Ind Co Ltd Electronic apparatus
JP2009164287A (en) * 2007-12-28 2009-07-23 Fujikura Ltd Multilayer printed wiring board and manufacturing method thereof
JP2010118589A (en) * 2008-11-14 2010-05-27 Shinko Electric Ind Co Ltd Method of manufacturing wiring board with electronic component incorporated therein
JP2010123632A (en) * 2008-11-17 2010-06-03 Shinko Electric Ind Co Ltd Method for manufacturing wiring board with built-in electronic component

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017086095A1 (en) * 2015-11-17 2017-05-26 株式会社村田製作所 Multilayer substrate and electronic apparatus
JPWO2017086095A1 (en) * 2015-11-17 2018-07-05 株式会社村田製作所 Multilayer substrate and electronic device
US10354939B2 (en) 2015-11-17 2019-07-16 Murata Manufacturing Co., Ltd. Multilayer board and electronic device
JP2020053524A (en) * 2018-09-26 2020-04-02 日亜化学工業株式会社 Circuit board and component mounting board, and manufacturing method thereof
US10887988B2 (en) 2018-09-26 2021-01-05 Nichia Corporation Circuit substrate, component-mounted substrate, and methods of manufacturing circuit substrate and component-mounted substrate
US11864317B2 (en) 2018-09-26 2024-01-02 Nichia Corporation Sn—Bi and copper powder conductive paste in through hole of insulating substrate

Similar Documents

Publication Publication Date Title
JP5100878B1 (en) Component built-in board mounting body, manufacturing method thereof, and component built-in board
JP4277036B2 (en) Semiconductor embedded substrate and manufacturing method thereof
TWI529878B (en) Hybrid thermal interface material for ic packages with integrated heat spreader
JP5167516B1 (en) Component-embedded substrate, manufacturing method thereof, and component-embedded substrate mounting body
JP6669586B2 (en) Semiconductor device and method of manufacturing semiconductor device
KR20110085481A (en) Stacked semiconductor package
KR20090071386A (en) Electronic apparatus
KR20070010915A (en) Substrate having heat spreading layer and semiconductor package using the same
US9269685B2 (en) Integrated circuit package and packaging methods
CN115884499A (en) Semiconductor package and printed circuit board
JP2007158279A (en) Semiconductor device and electronic controller using the same
JP5760260B2 (en) Printed circuit board with built-in component and manufacturing method thereof
JP2006295119A (en) Multilayered semiconductor device
TWI531283B (en) Connecting substrate and package on package structure
US9105562B2 (en) Integrated circuit package and packaging methods
US20240030089A1 (en) Semiconductor package
US9425116B2 (en) Integrated circuit package and a method for manufacturing an integrated circuit package
US20060108146A1 (en) Structure of electronic package and method for fabricating the same
US11450597B2 (en) Semiconductor package substrate having heat dissipating metal sheet on solder pads, method for fabricating the same, and electronic package having the same
JP3944898B2 (en) Semiconductor device
JP2014067819A (en) Component-embedded substrate mounting body, method of manufacturing the same, and component-embedded substrate
JP2008243966A (en) Printed circuit board mounted with electronic component and manufacturing method therefor
JP2010219554A (en) Semiconductor device and electronic controller using the same
JP2001168226A (en) Semiconductor package and semiconductor device
JP2012199283A (en) Semiconductor device

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140204

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20140624