JP2010118589A - Method of manufacturing wiring board with electronic component incorporated therein - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To remarkably reduce waste of material and the like caused by trouble to contribute to improvement of a yield even when the trouble occurs in a process of manufacturing a wiring board with an electronic component such as a semiconductor incorporated therein. <P>SOLUTION: An electronic component 20 with projecting terminals 24 formed on one surface thereof is prepared; a first structure 28 formed by mounting the electronic component 20 on a base material 27 in a face-up form is manufactured; and a second structure 30 with through-holes TH for inserting the projecting terminals 24 of the electronic component 20 therein formed therein is manufactured by laminating wiring layers 31, 34 in a required number of layers. The projecting terminals 24 and the through-holes TH are positioned with respect to each other, an adhesive member 40 is interposed between the respective structures 28, 30, and the respective structures 28, 30 are laminated and integrated to expose end faces of the projecting terminals 24 to the front surface of the second structure 30 by penetrating the adhesive member 40. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a technique for manufacturing a wiring board to be used for mounting electronic components such as semiconductor elements, and more particularly to electronic components such as semiconductor elements in order to cope with higher density and higher functionality. The present invention relates to a method of manufacturing a wiring board (wiring board with built-in electronic components) having a built-in multilayer structure.

  Since such a wiring board also plays a role of surface mounting electronic components such as semiconductor elements, it is also referred to as “semiconductor package” or simply “package” in the following description for convenience.

  Conventionally, a build-up method has been widely used as a technique for manufacturing a wiring board having a multilayer structure. A wide variety of wiring boards using this build-up method can be produced by combining the material of the interlayer insulating layer (typically resin) and the via hole formation process. A wiring layer (wiring) including the formation of a resin layer (insulating layer), formation of a via hole in the resin layer, filling of the via hole (formation of a via) on one or both sides of the base material (core substrate) Pattern) is sequentially repeated and stacked.

In addition, there is a multi-layered wiring board in which electronic components such as semiconductor elements are incorporated so as to cope with higher density and higher functionality. One example thereof is described in Patent Document 1 below. This Patent Document 1 discloses a method of manufacturing a multilayer printed wiring board with a built-in semiconductor element, and the process is to arrange a device (IC chip) in a core part → encapsulate with resin → for planarization Polishing (exposing the electrode surface of the chip) → Forming an insulating layer on it → Forming a via hole in this insulating layer → Forming a wiring layer by the semi-additive method → After that, alternating between the insulating layer and the wiring layer until the required number of layers is reached It includes a series of processes such as forming.
JP 2002-246757 A

  As described above, in the manufacturing technology of a package (wiring board) incorporating an electronic component, as illustrated in Patent Document 1 above, a required number of wiring layers are formed after a device is mounted (arranged in the core portion). Until then, a series of processing is performed in time series. That is, since one product is manufactured through these series of processes, the yield is determined by the yield through all the processes.

  For this reason, if a defect occurs in one of all the processes, or if a defect occurs in two or more processes, the final product cannot be shipped as a “defective product”. Become. For example, if a wiring or the like becomes defective in the process of forming each layer after embedding a non-defective device, the product becomes a defective product, so that a built-in device (non-defective product) is wasted. That is, there is a problem in that all the materials used and the man-hours (manufacturing period) used until the product in which the defect occurs are wasted, resulting in a decrease in yield. In particular, when a problem occurs in a process close to the final stage in all processes, the cost is further disadvantageous.

  The present invention has been created in view of the problems in the prior art, and even when a failure occurs in the process of manufacturing a wiring board incorporating an electronic component such as a semiconductor element, the waste of materials generated by the failure is wasted. An object of the present invention is to provide a method of manufacturing a wiring board with a built-in electronic component that can greatly reduce and contribute to the improvement of yield.

  In order to solve the above-described problems of the prior art, according to the present invention, an electronic component having a protruding terminal formed on one surface is prepared, and the electronic component is mounted on a substrate in a face-up manner. A first structure body is manufactured, and a second structure body is formed by laminating wiring layers in a required number of layers and forming through holes for inserting the protruding terminals of the electronic component. Aligning the projecting terminal of the first structure and the through hole of the second structure, interposing an adhesive member between the structures, and the end surface of the projecting terminal being the adhesive member And a step of stacking and integrating the structures so as to be exposed on the surface of the second structure.

  According to the method for manufacturing a wiring board with a built-in electronic component according to the present invention, an electronic component in which a protruding terminal is previously formed on one surface (for example, a semiconductor in which a conductive post is provided on an electrode pad on the circuit forming surface side) (Element) mounted on a base material in a face-up manner (first structure) and a wiring layer are stacked in a required number of layers, and a through-hole for inserting the protruding terminal into the required location A structure in which holes are formed (second structure) is prepared separately, and the protruding terminals and through-holes of each structure are aligned, and an adhesive member is interposed therebetween to form protrusions. Each structure is laminated so that the end face of the terminal penetrates the adhesive member and is exposed on the surface of the second structure, thereby forming an integrated structure.

  As described above, in the conventional technique (a method in which a series of steps of sequentially stacking wiring layers connected to a device after the device is incorporated in a substrate is connected in time series) Even if a defect occurs in one process, the finally obtained product becomes a “defective product” that cannot be shipped, resulting in a decrease in yield as a product. In addition, all the materials used before the product with the defect is wasted, especially when a defect occurs near the final stage of the entire process, which is further disadvantageous in terms of cost. It was.

  On the other hand, in the method of the present invention, even if a failure occurs in any of the steps of manufacturing the first structure and the second structure, the member in which the failure occurs (this In this case, it is only necessary to discard only the first structure or the second structure and substitute a non-defective product having the same function. That is, even when one member is defective, if the other member is a non-defective product, the use of the non-defective product can eliminate the waste (material and man-hour). As a result, the yield can be significantly improved as compared with the prior art.

  Other structural features of the manufacturing method of the electronic component built-in wiring board according to the present invention and advantageous advantages based thereon will be described in detail with reference to embodiments of the invention described later.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the accompanying drawings.

  FIG. 1 is a cross-sectional view showing a configuration of an electronic component built-in wiring board (semiconductor package) according to an embodiment of the present invention.

  The semiconductor package (electronic component built-in wiring substrate 10) according to the present embodiment is basically configured to include a post-mounted chip mounting substrate 28 and a laminated wiring sheet 30 each configured as a single member. Each single member 28, 30 has a structure integrated through an adhesive member (thermosetting resin sheet 40) as will be described later.

  The post-mounted chip mounting substrate 28 is provided with protruding terminals (three posts 24 in the illustrated example) on the circuit forming surface side (upper in the illustrated example) of the silicon (Si) chip 20 as an electronic component. A post-attached chip 25 and an insulating base material 27 on which the post-attached chip 25 is mounted are provided. The post-attached chip 25 is mounted on the base material 27 with a die attach film 26 bonded to the surface opposite to the circuit forming surface side interposed. That is, the post-attached chip 25 is mounted in a face-up manner. Further, the post 24 provided on the chip 20 has a pad portion 41P (on the outermost wiring layer 41 on the side (in the illustrated example) on the side where an electronic component (external chip) such as an external semiconductor element is mounted). It functions as a connection terminal that conducts to an external connection pad.

  The laminated wiring sheet 30 is a wiring board (a so-called coreless board) that does not include a support base material (core material), and a required number of wiring layers (in the illustrated example, the wiring layers 31 and 34) have the insulating layers 32 and 35. It has a structure in which layers are interposed and connected to each other through conductors (vias 33 and 36) filled in via holes formed in the insulating layers 32 and 35. However, with respect to the outermost insulating layer 35, a via 36 embedded in a required portion is exposed. Further, through holes TH through which the posts 24 on the chip 20 are inserted are formed at required locations (three locations in the illustrated example) of the laminated wiring sheet 30.

  As will be described later, the post 24 of the chip 20 is inserted into the through hole TH, and the gap is filled with an adhesive member (a part of the molten resin sheet 40) and cured, so that it is laminated with the post-mounted chip mounting substrate 28. The wiring sheet 30 can be integrated. In this integrated structure, the end surface of the post 24 and the end surface of the via 36 are exposed on the same surface (the same height) as the upper surface of the laminated wiring sheet 30.

  Further, an outermost wiring layer 41 is patterned and formed in a required shape on one surface (external chip mounting surface side) of the integrated structure, and a pad portion 41P is defined at the required location. Has been. Each pad portion 41P is formed so as to be connected to the end face of the post 24 and the end face of the via 36 as shown. Furthermore, an insulating layer (solder resist layer) 42 as a protective film is formed on the laminated wiring sheet 30 (excluding the region of the pad portion 41P). In the illustrated example, the “outermost layer” wiring layer 41 is used for the sake of simplicity of explanation, but a build-up layer that can be appropriately formed on the external chip mounting surface side according to the function required for the package 10 and the like. One of the wiring layers may be used. That is, the outermost wiring layer 41 may be formed after forming a required number of build-up layers as necessary.

  Similarly, the outermost wiring layer 44 is patterned and formed in a required shape on the surface opposite to the external chip mounting surface, and a pad portion 44P is defined at the required location. Each pad portion 44P is formed so as to be connected to the end face of the conductor (via 43) filled in the via hole VH formed through the base material 27 and the resin sheet 40 of the post-mounted chip mounting substrate 28 as shown in the figure. Has been. Furthermore, an insulating layer (solder resist layer) 45 as a protective film is formed on the base material 27 (excluding the region of the pad portion 44P). Similarly, in this case as well, the “outermost” wiring layer 44 is used for the sake of simplicity of explanation. However, after forming the required number of buildup layers as necessary, the outermost wiring layer 44 is formed. Also good.

  The pad portions 41P and 44P exposed from the solder resist layers 42 and 45 have external chip electrode terminals and external connection terminals used when the package 10 is mounted on a mounting board such as a mother board. Since they are joined, it is desirable to apply nickel (Ni) plating and gold (Au) plating to the pad portion in this order. This is to improve the contact property when the terminals are joined, to improve the adhesion with the metal (typically copper (Cu)) constituting the pad portion, and to prevent Cu from diffusing into the Au layer. This is to prevent it.

  Furthermore, in this embodiment, pre-solder is applied to the pad portion 41P on the external chip mounting surface side (deposition of the solder 46). This is to make it easier to connect to the electrode terminal when mounting the external chip in consideration of the convenience of the shipping destination. Further, the pad portion 44P on the external connection terminal bonding surface side is left exposed so that the external connection terminals can be bonded as necessary at the shipping destination (LGA (Land Grid Array)). Of course, solder balls (see FIGS. 6 and 7), pins or the like may be bonded to the pad portion in advance according to the demand of the shipping destination (BGA (ball grid array), PGA (pin grid). ·array)).

  Specific materials, sizes, and the like of the members constituting the electronic component built-in wiring board 10 (FIG. 1) according to the present embodiment will be described in relation to the processes described below.

  Hereinafter, a method of manufacturing the electronic component built-in wiring board 10 according to the present embodiment will be described with reference to FIGS.

  First, in the first step (see FIG. 2A), a basic single member (a post-mounted chip mounting substrate 28 and a laminated wiring sheet 30) constituting the electronic component built-in wiring substrate 10 of this embodiment is prepared.

(1) Production of Post-Mounted Chip Mounting Substrate First, the chip 20 with the post 24 is fabricated, and the post-mounted chip 25 is mounted on the base material 27.

  The post-attached chip 25 can be manufactured as follows, for example. First, a silicon wafer having a required size (diameter of 8 inches or 12 inches) is subjected to a required device process on one side to form a plurality of devices in an array, and the devices are formed. A passivation film 22 made of silicon nitride (SiN), phosphorous glass (PSG), or the like is formed on the surface on the side facing (see an enlarged view of a portion surrounded by a broken line in FIG. 2A), and a required film is formed on each device. A portion of the passivation film 22 corresponding to the electrode pad 21 defined in a part of the aluminum (Al) wiring layer formed in a pattern is removed by a laser or the like (that is, the part is opened to expose the electrode pad 21). ).

  Further, after an insulating film (not shown) such as a polyimide resin is formed on the passivation film 22 by photolithography, a metal thin film 23 is formed by sputtering on the entire surface on which the insulating film is formed. The metal thin film 23 has a two-layer structure of a titanium (Ti) layer or a chromium (Cr) layer for improving adhesion to the electrode pad (Al) 21 and a copper (Cu) layer laminated thereon. Have.

  Further, a plating resist (not shown) patterned to have the same thickness as the post 24 to be formed and to have an opening corresponding to the shape is formed on the metal thin film 23. As the resist material, a liquid photoresist or a photosensitive dry film is used. Next, a Cu post 24 is formed on the electrode pad 21 (metal thin film 23) exposed from the opening of the plating resist layer by electrolytic Cu plating using the metal thin film 23 as a seed layer. In this embodiment, the height of the Cu post 24 is selected to be about 60 μm.

  Next, the back surface of the wafer (the surface opposite to the side on which the device is formed) is ground using a suitable grinding apparatus, and thinned to a predetermined thickness (about 50 μm, which is the same as the thickness of the chip 20 finally obtained). After that, the plating resist layer is removed. When a liquid photoresist is used, it is removed using a stripping solution containing an organic solvent. When a photosensitive dry film is used, an alkaline solution such as sodium hydroxide (NaOH) or monoethanolamine is used. Strip and remove using chemicals.

  Further, the exposed metal thin film 23 is removed by wet etching. In this case, the upper layer Cu layer is first removed with an etchant that dissolves Cu, and then the lower layer Ti layer or Cr layer is removed with an etchant that dissolves Ti or Cr. As a result, the passivation film 22 is exposed as illustrated. Thereafter, predetermined surface cleaning or the like is performed.

  And each chip | tip 20 (chip 25 with a post | mailbox) with which the Cu post 24 was formed in one surface can be obtained by cutting and dividing | segmenting into each device (chip | chip) unit with a dicer etc. FIG. When individual devices are separated, the wafer is bonded to the back surface of the wafer with a die attach film (thickness of about 15 μm) interposed on a dicing tape supported by a dicing frame. The wafer is cut and divided along a line defining each device region by a dicer blade, and each divided post-attached chip 25 is picked up. At that time, a die attach film 26 is attached to each chip 25 as shown in FIG.

  Next, an epoxy resin or a polyimide resin is used in the face-up mode in which the chip-with-post 25 thus prepared is face-up with the electrode pad 21 (Cu post 24) formed side up. It mounts on the sheet-like base material 27 which consists of etc. (die attachment). At this time, since the die attach film 26 is attached to the back surface of the chip 25, the chip 25 can be fixed at a predetermined position on the base material 27 by utilizing the adhesiveness.

  One single member (the post-mounted chip mounting substrate 28) is manufactured through the above steps.

  In the example shown in FIG. 2A, only one post-attached chip 25 is arranged on the base material 27 for the sake of simplicity of illustration. A plurality of post-attached chips 25 are arranged in an array on the base material 27 in accordance with the number to be divided into product (electronic component built-in wiring board) units.

(2) Production of Laminated Wiring Sheet The laminated wiring sheet 30 can be produced using, for example, a coreless substrate manufacturing technique (JP 2007-158174 A) previously proposed by the applicant of the present application. An example of the method is as follows.

  First, a temporary substrate made of copper (Cu) is prepared, and a plating resist having an opening corresponding to the shape of a required wiring pattern to be formed is formed on the temporary substrate, and then this plating resist layer For example, a wiring layer 31 (pad portion 31P) having a two-layer structure of an Au plating layer and a Ni plating layer is formed on the temporary substrate (Cu) exposed from the opening. Next, after removing the plating resist layer, an insulating layer 32 such as an epoxy resin is formed on the temporary substrate and the wiring layer 31 (pad portion 31P), and a required portion of the insulating layer 32 (corresponding to the pad portion 31P). A via hole is formed in the portion).

  Next, the via hole is filled with a conductive paste such as copper (Cu) or silver (Ag) by screen printing or filled with Cu plating (formation of the via 33), and then this via hole is formed by a semi-additive method or the like. The wiring layer 34 is formed in a required shape on the insulating layer 32 by being connected to the insulating layer 32. Thereafter, the insulating layers and the wiring layers are alternately stacked until the required number of layers is stacked, and the vias 36 embedded in the required portions of the outermost insulating layer 35 are exposed.

  Next, through holes TH through which the posts 24 on the chip 20 are inserted are formed at required locations (three locations in the illustrated example) of the stacked structures. The through hole TH can be formed by, for example, drilling with a CO2 gas laser, excimer laser, YAG laser, or the like, drilling with a mechanical drill, or the like.

  And the laminated wiring sheet 30 which is another single member can be obtained by selectively etching the temporary substrate (Cu) with respect to the wiring layer 31 and the insulating layer 32. In the present embodiment, the thickness of the laminated wiring sheet 30 is selected to be about 50 μm.

  In the next step (see FIG. 2B), the laminated wiring sheet 30 and the post-mounted chip mounting substrate 28 produced in the previous step are placed above the posts 24 of the post-mounted chip mounting substrate 28. The two are aligned so that the through hole TH is positioned, and the two are overlapped with a thermosetting resin sheet 40 interposed therebetween. As a material of the resin sheet 40, an epoxy resin widely used as a buildup resin is preferably used.

  In the next step (see FIG. 3A), the post-mounted chip mounting substrate 28, the thermosetting resin sheet 40, and the laminated wiring sheet 30 that are aligned and overlapped in the previous step are placed on the lower press hot platen. 51 and an upper press hot platen 52 (with a protective film 53 made of polyester resin or the like attached to the inner surface), and heating and pressurization (hot press) from both the upper and lower sides by a vacuum press or the like And laminated to form an integral structure. In the course of the hot pressing process, the post 24 on the chip 20 passes through the resin material (resin sheet 40) and is inserted into the through hole TH of the laminated wiring sheet 30, and a part of the molten resin is formed between the post 24 and the through hole. The gap in TH is filled.

  The protective film 53 affixed on the upper press heat platen 52 prevents a part of the molten resin from adhering to the press heat platen 52 and leaks to the external chip mounting surface side of the laminated wiring sheet 30. It is for preventing it from taking out. If the resin leaks onto the laminated wiring sheet 30, the resin adheres to the post 24 and the via 36 in some cases, and conduction with the wiring layer 41 (see FIG. 3B) formed thereon is established. It is because it is damaged. The protective film 53 does not necessarily have to be stuck on the press hot platen 52, and may be disposed only between the press hot platen 52 and the laminated wiring sheet 30. That is, when the chip mounting substrate with post 28, the thermosetting resin sheet 40, and the laminated wiring sheet 30 are aligned and superimposed in the previous step, the protective film 53 is also superimposed on the laminated wiring sheet 30, The superposed structures (28, 40, 30, 53) may be disposed between the press hot plates 51 and 52.

  When the required hot pressing process is completed in this manner, the integrated structure is taken out from between the press hot plates 51 and 52. As a result, a structure in which the end surface of the post 24 and the end surface of the via 36 are exposed on the same plane as the upper surface of the laminated wiring sheet 30 (that is, at the same height) is produced.

  At this time, the thickness of the thermally cured resin layer (resin sheet 40) is 75 μm (= the thickness of the chip 20 (50 μm) + the thickness of the die attach film 26 (15 μm) + the height of the post 24 ( 60 μm) —approximately the thickness (50 μm) of the laminated wiring sheet 30. Part of the resin melted during thermosetting is a gap between the post 24 on the chip 20 and the through hole TH of the laminated wiring sheet 30. In view of this filling amount, the resin sheet 40 to be prepared in the step of FIG. 2B needs to be selected to an appropriate thickness of 75 μm or more.

  In addition, depending on the state of the protective film 53 at the time of hot pressing in this step, it may be assumed that the end surfaces of the post 24 and the via 36 are not reliably exposed. In that case, since a thin resin skin is deposited on each end face, after hot pressing, the upper surface of the laminated wiring sheet 30 is appropriately ground to expose the end faces of the post 24 and the via 36.

  In the next step (see FIG. 3B), the outermost insulating layer 35 of the laminated wiring sheet 30 is formed into a required shape so as to be connected to the post 24 and the via 36 by a semi-additive method or the like. An outer wiring layer 41 (pad portion 41P) is formed. The wiring layer 41 is “outermost layer” for simplicity of explanation, but as described above, one wiring of the build-up layers that can be appropriately formed on the external chip mounting surface side as necessary. It may be a layer.

  In the next step (see FIG. 3C), a solder resist layer 42 (outermost insulating layer) covering the surface so that the pad portion 41P of the wiring layer 41 formed on the laminated wiring sheet 30 is exposed. Form. The solder resist layer 42 can be formed, for example, by laminating a photosensitive solder resist film or applying a liquid photoresist and patterning the resist into a required shape. Further, Ni / Au plating is applied to the pad portion 41P exposed from the solder resist layer.

  The insulating layer 42 formed in this step is also the “outermost layer” for simplicity of explanation. However, as described above, the build-up layer that can be appropriately formed on the external chip mounting surface side as necessary. One of them may be an insulating layer. In this case, the solder resist layer 42 is formed after the required number of build-up layers are formed.

  In the next step (see FIG. 4 (a)), on the surface opposite to the external chip mounting surface side (the lower side in the illustrated example), the required positions (four locations in the illustrated example) of the base material 27 A via hole VH that passes through the base material 27 and the resin sheet 40 in order and reaches the lowermost wiring layer 31 (pad portion 31P) of the laminated wiring sheet 30 is formed. This via hole VH can be formed by a CO2 gas laser, an excimer laser or the like.

  Alternatively, the via hole VH can be formed using other methods. For example, when both the base material 27 and the resin sheet 40 are made of a photosensitive material, the via hole VH can be formed by photolithography. As another method, sandblasting can be used. In this method, since the target surface is scraped off by sand injection, in order to protect the surface to which the sand is sprayed (in this case, the base material 27), the portion corresponding to the via hole formation location on the base material 27 is excluded. It is necessary to apply a masking process (such as attaching a protective tape).

  In the next step (see FIG. 4B), the via hole VH is filled by screen printing using a conductive paste such as copper (Cu) or silver (Ag), or filled by Cu plating (via). 43 formation). Further, in the same manner as the process performed in the step of FIG. 3B, the outermost wiring layer 44 (pad portion 44P) is connected to the via 43 and formed into a required shape on the base material 27 by a semi-additive method or the like. Form.

  Similarly, the wiring layer 44 is also the “outermost layer” for simplification of description, but as described above, among the build-up layers that can be appropriately formed on the external connection terminal joint surface side as necessary. One wiring layer may be used.

  In the next step (see FIG. 4C), the pad portion 44P of the wiring layer 44 formed on the substrate 27 is exposed in the same manner as the processing performed in the step of FIG. A solder resist layer 45 (outermost insulating layer) covering the surface is formed. Further, Ni / Au plating is applied to the pad portion 44P exposed from the solder resist layer 45.

  Similarly, the insulating layer 45 is also the “outermost layer” for simplification of description, but among the build-up layers that can be appropriately formed on the external connection terminal joint surface side as described above, as described above. One insulating layer may be used. In this case, the solder resist layer 45 is formed after the required number of build-up layers are formed.

  In the last step (see FIG. 4 (d)), after pre-soldering (depositing the solder 46) on the pad portion 41P on the external chip mounting surface side, each package unit (one piece) required by a dicer or the like is used. The post-attached chip 25 and the necessary laminated wiring region (a portion including a via, an external connection pad, etc.) around it are cut and divided.

  In the illustrated example, the pad portion 44P on the external connection terminal joining surface side is left exposed, but external connection terminals (solder balls, pins, etc.) are joined to the pad portion 44P as necessary. It may be left. In this case, before dicing, after applying flux as a surface treatment agent to the pad portion 44P, a solder ball as an external connection terminal is mounted and reflowed at a temperature of about 240 to 260 ° C. to form a bump. To do. Thereafter, the surface is washed to remove the flux.

  Through the above steps, the electronic component built-in wiring board 10 (FIG. 1) of this embodiment is manufactured.

  As described above, according to the manufacturing method (FIGS. 2 to 4) of the electronic component built-in wiring board 10 according to the present embodiment, the laminated wiring sheet 30 in which wiring layers are laminated in advance with the required number of layers, A chip 20 having a post 24 inserted through a through hole TH provided in the laminated wiring sheet 30 (chip 25 with post) mounted on a predetermined base material 27 (chip mounting substrate 28 with post) is separately provided. These single members 28 and 30 are overlapped with a thermosetting resin sheet 40 interposed therebetween, and have an integrated structure by a vacuum press or the like. Further, after forming a required number of buildup layers on one surface (external chip mounting surface side) of the stacked structure, the outermost wiring layer 41 and the solder resist layer 42 are formed. Further, via holes VH reaching the lowermost wiring layer 31 of the laminated wiring sheet 30 are formed on the other surface (external connection terminal bonding surface side), and a necessary number of buildup layers are formed as necessary. An outer wiring layer 44 and a solder resist layer 45 are formed to obtain a semiconductor package (electronic component built-in wiring board 10).

  In the conventional process as exemplified in Patent Document 1 described above (a method in which a series of steps of sequentially stacking wiring layers connected to a device after the device is incorporated in a substrate is connected in time series) Even if a defect occurs in one of all the processes, the finally obtained product (semiconductor package) becomes a “defective product” that cannot be shipped, resulting in a problem that the yield of the product is lowered. In addition, all the materials used and the man-hours (manufacturing period) used until a defective product is obtained are wasted, especially when a failure occurs in a process close to the final stage in all processes. Was further disadvantageous in terms of cost.

  On the other hand, in the manufacturing method according to the present embodiment, there is a problem in any process (especially, any process of manufacturing the post-mounted chip mounting substrate 28 and the laminated wiring sheet 30 which is a basic single member). Even if it occurs, only the member (in this case, the post-mounted chip mounting substrate 28 or the laminated wiring sheet 30) in which the defect has occurred may be discarded and a good product having the same function may be substituted. In other words, even if one member (for example, the laminated wiring sheet 30) becomes a defective product, if the other member (the chip-mounted substrate 28 with post) is a non-defective product, this non-defective product can be used. Waste can be eliminated. Thereby, compared with a prior art, a yield can be improved significantly and it can also contribute to shortening of a manufacturing period.

  In the embodiment described above, the case where the base material 27 on which the post-attached chip 25 is mounted is made of an insulating material such as an epoxy resin has been described as an example, but the material constituting the base material is an insulating material. Of course, it is not limited to. Since the die attach film 26 (insulating member) is interposed between the post-attached chip 25 and the base material 27 as shown in FIG. 2A, the material constituting the base material is It is also possible to use a conductive material in relation to the chip 25.

  FIG. 5 shows an example of this, and shows a step (part) of a method of manufacturing a semiconductor package according to another embodiment of the present invention in the form of a sectional view. In the figure, the processes performed in the steps (a), (b), and (c) correspond to the processes performed in the steps of FIGS. 2 (b), 3 (a), and 4 (a), respectively. ing. Moreover, about the process which should be performed from the process of FIG.5 (b) to the process of FIG.5 (c), and the process performed after the process of FIG.5 (c), respectively, FIG.3 (b), (c), And since it is the same as the process performed by each process of FIG.4 (b)-(d), the description is abbreviate | omitted.

  In the present embodiment, as shown in FIG. 5A, a sheet member 27a made of a conductive material (for example, copper (Cu)) is used as a base material on which the post-mounted chip 25 constituting the post-mounted chip mounting substrate 28a is mounted. A plate having a two-layer structure in which an insulating layer 27b made of epoxy resin or the like is formed on one surface (the surface opposite to the side to which the die attach film 26 is bonded) is used. Further, the two-layer base materials 27a and 27b are formed with openings OP having a predetermined size at required positions (four positions in the illustrated example). The opening OP is formed at a location corresponding to the position of the via hole VH1 formed in a later step (see FIG. 5C), and the size thereof is selected to be larger than the diameter of the via hole VH1. Yes.

  The reason why the two-layer base materials 27a and 27b are used and the opening OP is formed in the base material with a predetermined size is as follows. That is, if a base material made only of a conductive material is used, a via hole is formed in a later step, and the via hole is filled with a conductor to form a via 43 (see FIG. 4B). This is because when the pad portion 44P is formed by being connected to the via 43, the adjacent pad portion 44P is electrically short-circuited through the conductive base material. If the opening OP is not formed in a predetermined size, when the via hole is formed, the conductive member 27a is exposed on the inner wall, and the conductive member 27a is adjacent to the via hole 43. This is because it is connected to the pad portion 44P.

  In the present embodiment, the post-mounted chip mounting substrate 28a, the resin sheet 40, and the laminated wiring sheet 30 are superposed and placed between the press hot plates 51 and 52 to perform hot pressing (FIG. 5B). )), A similar protective film 54 is also attached to the inner surface of the lower press hot platen 51. This protective film 54 prevents the resin melted during hot pressing (a part of the resin sheet 40) from leaking onto the lower press hot platen 51 through the opening OP provided in the base materials 27a and 27b. Is to do.

  Further, after performing the same processing as the processing performed in the steps of FIGS. 3B and 3C, a predetermined surface on the surface opposite to the external chip mounting surface side (the lower side in the example of FIG. 5C) is provided. The lowermost wiring layer 31 (pad portion 31P) of the laminated wiring sheet 30 penetrating the resin sheet 40 at a location (a portion corresponding to the inside of the opening OP provided in the base materials 27a and 27b of the resin sheet 40). A via hole VH1 reaching to is formed. About the formation method, it is the same as the process performed at the process of Fig.4 (a).

  Since the via hole VH1 is thus formed at a predetermined location, the via hole VH1 is filled with a conductor in the subsequent process to form the via 43 (see FIG. 4B), and the pad portion 44P is further formed. Sometimes, the via 43 and the pad portion 44P are insulated from the conductive member 27a via the resin sheet 40 and the insulating layer 27b. That is, the inconvenience that the adjacent pad portions 44P are electrically short-circuited can be avoided.

  Thereafter, the semiconductor package (not shown) of the present embodiment is obtained through the same processing as that performed in the steps of FIGS. 4C and 4D. The semiconductor package of this embodiment is basically the same as the configuration of the semiconductor package (electronic component built-in wiring board 10) shown in FIG. 1, and is a portion of the base material (27a, 27b) on which the post-attached chip 25 is mounted. Are only different.

  According to the present embodiment, in addition to the effects obtained by the manufacturing method according to the above-described embodiment (FIGS. 2 to 4), a part of the base material on which the post-attached chip 25 is mounted has a relatively high rigidity. Since the conductive member 27a such as a Cu plate is included, it can function as a reinforcing material for this package.

  FIG. 6 is a cross-sectional view showing a configuration example (semiconductor device 60) in the case where a semiconductor element as an electronic component (external chip) is surface-mounted on the semiconductor package (wiring substrate with built-in electronic component 10) shown in FIG. It is a thing.

  In the illustrated semiconductor device 60, the external chip (semiconductor element 61) is bonded onto the electrode pad of the semiconductor element 61 to the pad portion 41 </ b> P exposed from the upper protective film (solder resist layer 42) of the semiconductor package 10. Further, flip-chip mounting is performed so that electrode terminals 62 such as gold bumps are connected via solder 46. An underfill resin (for example, epoxy resin) 63 is filled between the mounted semiconductor element 61 and the protective film 42, and the semiconductor element 61 is fixed to the package 10 by thermosetting.

  On the other hand, on the surface opposite to the external chip mounting surface side, solder balls 65 as external connection terminals are reflowed on the pad portion 44P exposed from the lower protective film (solder resist layer 45) of the package 10. It is joined. The apparatus 60 is mounted on a mounting board such as a mother board via the solder balls 65.

  In the illustrated example, the BGA form is used. However, a PGA form may be used by joining pins instead of the solder balls, or an LGA form in which no external connection terminal is connected to the pad portion 44P. Good.

  In each of the above-described embodiments, the case where one post-attached chip 25 is incorporated in the semiconductor package (electronic component built-in wiring substrate 10) has been described as an example. However, as is apparent from the gist of the present invention, the chip is incorporated. Of course, the number of posts with posts is not limited to one. Two or more post-attached chips can be appropriately incorporated depending on functions required for a semiconductor device obtained using the package.

  In the configuration example of the semiconductor device 60 shown in FIG. 6, only one external chip (semiconductor element 61) is surface-mounted on the semiconductor package 10, but depending on the function required for the semiconductor device, the chip Passive elements such as capacitors may also be surface mounted. FIG. 7 shows an example of the configuration.

  In the configuration of the semiconductor device 60a shown in FIG. 7, as compared with the semiconductor device 60 shown in FIG. 6, another post-attached chip 25a (chip 20a, post 24a) is added to the semiconductor package 10a as the wiring board together with the original post-attached chip 25. The semiconductor package 10a is different from the semiconductor chip 10a in that a required number (two in the illustrated example) of chip capacitors 66 are mounted on the surface together with the external chip (semiconductor element 61). Each chip capacitor 66 is connected to a pad portion 41P exposed from the upper protective film 42 via a pair of electrode terminals 67. The other configuration is basically the same as the configuration of the semiconductor device 60 shown in FIG.

  In the semiconductor device 60a shown in the figure, the chip capacitor 66 is provided for reducing the inductance of the wiring in the package 10a and performing the required “decoupling”. For example, when the chip 61 mounted on the package 10a is a microprocessor (CPU), such a CPU is required to operate at high speed. Therefore, it is necessary to reduce an increase in inductance due to the wiring length of the signal line. In this case, “decoupling” can be effectively performed by providing a required number of chip capacitors 66 as one means for realizing it as shown in the figure.

  In each of the above-described embodiments, the case where the Cu posts 24 and 24a (protruding terminals) are provided on the chips 20 and 20a incorporated in the packages 10 and 10a has been described as an example, but the protruding terminals provided on the chips are described. Of course, the form is not necessarily limited to “post”, as can be seen from its function (can be connected to the external connection pad 41P through the through hole TH of the laminated wiring sheet 30). As other forms, conductive bumps such as gold (Au) bumps and solder bumps, solder balls and copper core balls (copper is used as a core, and the periphery thereof is covered with a different metal (for example, solder or nickel / gold). It is also possible to use conductive balls such as composite structure balls) and resin core balls (composite structure balls having a resin as a core and surrounding the periphery with metal (mainly solder or nickel / gold)). .

  For example, in the case where a protruding Au bump is provided, an electroplating method using a photo process or a transfer in which an Au bump is once formed on a temporary substrate for bump formation and is thermocompression bonded onto the electrode pad of each chip 20. A conductive paste containing an appropriate amount of conductive particles such as Au, Ag, and solder in an epoxy-based, polyester-based, polyimide-based resin or the like is supplied onto the electrode pads of each chip 20 by screen printing. A method of curing by heating to form a bump can be used.

  In each of the above-described embodiments, the surface on which the posts 24 and 24a of the chips 20 and 20a are formed in the packages 10 and 10a is referred to as an “external chip mounting surface”, and the opposite surface is referred to as “external connection”. Although the case of “terminal joint surface” has been described, it is needless to say that the present invention is not limited to such a use form. Depending on the environment in which the package is used and the functions required for the semiconductor device obtained by using the package, the external chip mounting surface and the external connection terminal joint surface are used with the upper and lower sides appropriately upside down. It is also possible.

It is sectional drawing which shows the structure of the electronic component built-in wiring board (semiconductor package) which concerns on one Embodiment of this invention. FIG. 8 is a cross-sectional view showing a process (No. 1) of the method for manufacturing the electronic component built-in wiring board (semiconductor package) of FIG. FIG. 3 is a cross-sectional view showing a process (No. 2) following the manufacturing process of FIG. 2. FIG. 4 is a cross-sectional view showing a process (No. 3) following the manufacturing process of FIG. 3. It is sectional drawing which shows the process of the manufacturing method which concerns on other embodiment of this invention. FIG. 2 is a cross-sectional view showing a configuration example (semiconductor device) when electronic components are surface-mounted on the electronic component built-in wiring board (semiconductor package) of FIG. 1. FIG. 7 is a cross-sectional view showing a configuration according to a modification of the semiconductor device of FIG. 6.

Explanation of symbols

10, 10a ... Electronic component built-in wiring board (semiconductor package),
20, 20a ... chip (internal electronic component),
21 ... Electrode pad,
24, 24a ... posts (protruding terminals),
25, 25a ... chip with post,
27, 27a, 27b ... (substrate with post-mounted chip),
28, 28a ... post-mounted chip mounting substrate (first structure),
30 ... laminated wiring sheet (second structure),
31, 34, 41, 44 ... wiring layers,
32, 35 ... Resin layer (insulating layer),
33, 36, 43 ... vias,
40: Resin sheet (adhesive member),
42, 45 ... Solder resist layer (protective film / insulating layer),
41P, 44P ... external connection pads,
60, 60a ... semiconductor device,
61, 66 ... external chips (surface-mounted electronic components),
TH ... Through hole,
VH, VH1 ... via hole.

Claims (5)

Preparing an electronic component having a protruding terminal formed on one surface, and producing a first structure formed by mounting the electronic component on a substrate in a face-up manner;
A step of producing a second structure formed by laminating a wiring layer with a required number of layers and forming a through hole for inserting the protruding terminal of the electronic component;
The protruding terminals of the first structure and the through holes of the second structure are aligned, an adhesive member is interposed between the structures, and the end surface of the protruding terminal penetrates the adhesive member. And a step of stacking and integrating the structures so as to be exposed on the surface of the second structure. A step of forming a wiring layer connected to the end face of the protruding terminal on the second structure;
Forming an insulating layer on the wiring layer and the second structure so that a pad portion of the wiring layer is exposed;
On the base material, a step of forming a via hole that penetrates the base material and the adhesive member in order and reaches the wiring layer of the second structure,
Filling the via hole with a conductor and forming a wiring layer connected to the conductor;
The method of manufacturing a wiring board with built-in electronic components according to claim 1, further comprising: forming an insulating layer on the wiring layer and the base material so that a pad portion of the wiring layer is exposed.   In the step of laminating and integrating each of the first and second structures, the first structure, the adhesive member, and the second structure that are aligned and overlapped are placed between a pair of press hot plates. The wiring board with a built-in electronic component according to claim 1, wherein the wiring board is disposed and laminated by a heating / pressurizing process, and an end face of the protruding terminal is exposed to the same height as a surface of the second structure. Manufacturing method.   4. The method of manufacturing a wiring board with built-in electronic components according to claim 3, wherein a heating / pressurizing process is performed with a protective film interposed between the second structure and one of the press hot plates. In the step of manufacturing the first structure, an insulating layer is formed on one surface of a sheet member made of a conductive material as a base material on which the electronic component is mounted, and a predetermined size is provided at a required location. Using a base material having a two-layer structure in which openings are formed,
In the step of laminating and integrating the first and second structures, a heating / pressurizing process is performed with a protective film interposed between the base material having the two-layer structure and the other press hot platen. 5. The method of manufacturing an electronic component built-in wiring board according to claim 4, wherein the method is performed.

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