JP2014060190A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device including a photo detector having good high-frequency response characteristic.SOLUTION: A semiconductor device SD1 includes a photo detector PD1. The photo detector PD1 includes a semiconductor substrate SS1, first conductivity type first through third semiconductor layers SL1-SL3 and a second conductivity type fourth semiconductor layer SL4 formed on the third semiconductor layer SL3. The second through fourth semiconductor layers SL2-SL4 form a mesa structure MS1. The photo detector PD1 includes a second conductivity type fifth semiconductor layer (second conductivity type region SL5) formed on a side wall of the mesa structure MS1. A first impurity as a second conductivity type impurity of the fourth semiconductor layer SL4 and a second impurity as a second conductivity type impurity of the fifth semiconductor layer are elements different from each other. A diffusion constant of the second impurity in the fifth semiconductor layer is larger than a diffusion constant of the first impurity in the fourth semiconductor layer SL4.

Description

  The present invention relates to a semiconductor device including a light receiving element having a mesa structure and a method for manufacturing the semiconductor device.

In the semiconductor light-receiving element described in Patent Document 1, an n ⁺ -type InP buffer layer, an n ⁻ -type InP buffer layer, an n ⁺ -type InP electric field relaxation layer, an undoped InAlGaAs / InAlAs on an n ⁺ -type InP substrate. A superlattice multiplication layer, a p ⁺ type InP electric field relaxation layer, a p ⁻ type InGaAs light absorption layer, a p type InP cap layer, and a p + type InGaAs contact layer are sequentially formed. These stacked structures on the n ⁺ -type InP substrate constitute a mesa structure.

  In Patent Document 1, there is no description about impurities in the p-type semiconductor layer (p-type InP cap layer) at the top of the mesa structure.

JP-A-8-181349

  When the modulated light enters the light receiving element, photoelectric conversion is performed by the light receiving element, and a current is output from the light receiving element. A characteristic indicating how much the current output waveform follows the input optical waveform is called a high frequency response characteristic. In recent years, there has been an increasing demand for manufacturing a semiconductor device including a light receiving element having good high frequency response characteristics.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the first impurity that is the second conductivity type impurity of the fourth semiconductor layer and the second impurity that is the second conductivity type impurity of the fifth semiconductor layer are different elements. The diffusion constant of the second impurity in the fifth semiconductor layer is larger than the diffusion constant of the first impurity in the fourth semiconductor layer.

  According to the one embodiment, a semiconductor device including a light receiving element having good high frequency response characteristics can be obtained.

It is sectional drawing which shows the structure of the semiconductor device which concerns on 1st Embodiment. 1 is a plan view showing a structure of a semiconductor device according to a first embodiment. It is a figure which shows the example of the profile of the impurity concentration in the depth direction of the 4th semiconductor layer which comprises the top part of the mesa structure of the light receiving element of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the effect of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 2nd Embodiment. It is a top view which shows the structure of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. In all the drawings, the same components are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

[First Embodiment]
FIG. 1 is a cross-sectional view showing the structure of the semiconductor device SD1 according to the first embodiment. FIG. 2 is a plan view showing the structure of the semiconductor device SD1. 1 is a cross-sectional view taken along line AA in FIG.

The semiconductor device SD1 according to this embodiment includes a light receiving element PD1 (semiconductor light receiving element). The light receiving element PD1 includes a semiconductor substrate SS1, a first semiconductor layer SL1, a second semiconductor layer SL2, a third semiconductor layer SL3, a fourth semiconductor layer SL4, and a fifth semiconductor layer (second conductivity type region SL5). And having. The first semiconductor layer SL1 is stacked on the semiconductor substrate SS1, the second semiconductor layer SL2 is stacked on the first semiconductor layer SL1, and the third semiconductor layer SL3 is stacked on the second semiconductor layer SL2. The fourth semiconductor layer SL4 is stacked on the third semiconductor layer SL3. A mesa structure MS1 is configured by the second semiconductor layer SL2, the third semiconductor layer SL3, and the fourth semiconductor layer SL4. The fifth semiconductor layer (second conductivity type region SL5) is formed on the side wall of the mesa structure MS1. The first semiconductor layer SL1, the second semiconductor layer SL2, and the third semiconductor layer SL3 are of the first conductivity type (for example, n-type).
The fourth semiconductor layer SL4 and the fifth semiconductor layer (second conductivity type region SL5) are of the second conductivity type (for example, p-type). However, the first impurity that is the second conductivity type impurity of the fourth semiconductor layer SL4 and the second impurity that is the second conductivity type impurity of the fifth semiconductor layer (second conductivity type region SL5) are different from each other. It is an element. The diffusion constant of the second impurity in the fifth semiconductor layer (second conductivity type region SL5) is larger than the diffusion constant of the first impurity in the fourth semiconductor layer SL4.
Details will be described below.

  The semiconductor substrate SS1 is, for example, an InP substrate. The semiconductor substrate SS1 is, for example, semi-insulating type. The semi-insulating semiconductor substrate SS1 has a deep level formed by doping Fe or the like into the InP substrate, and has a high resistance.

The first semiconductor layer SL1 is, for example, an n ⁺ type InP layer.

The second semiconductor layer SL2 is, for example, an n ⁻ type InP layer. Alternatively, the second semiconductor layer SL2 is, n ^- the type of InP layer n ^- or may be constructed by laminating type InAlAs layer.

The third semiconductor layer SL3 is, for example, an n ⁻ type InGaAs layer. The third semiconductor layer SL3 functions as a light absorption layer.

  The fourth semiconductor layer SL4 is, for example, a p-type InGaAs layer. That is, the first impurity is a p-type impurity.

  For example, the n-type impurity of the first semiconductor layer SL1, the second semiconductor layer SL2, and the third semiconductor layer SL3 is Si.

  For example, the p-type impurity (first impurity) of the fourth semiconductor layer SL4 is Be, C, or Mg.

  For example, the p-type impurity (second impurity) of the fifth semiconductor layer (second conductivity type region SL5) is Zn.

  As described above, the mesa structure MS1 is configured by the second semiconductor layer SL2, the third semiconductor layer SL3, and the fourth semiconductor layer SL4.

  The mesa structure MS1 is formed, for example, so as to widen the bottom. That is, the mesa structure MS1 is formed in a shape in which the plane cross-sectional area of the mesa structure MS1 increases from the top to the bottom, and the inclination angle of the side wall of the mesa structure MS1 is less than 90 °. That is, the mesa structure MS1 is a trapezoidal portion in front sectional shape. The top surface of the mesa structure MS1 is substantially horizontal.

  The mesa structure MS1 includes a first mesa MS11 configured by the third semiconductor layer SL3 and the fourth semiconductor layer SL4, and a second mesa MS12 configured by the second semiconductor layer SL2. The second mesa MS12 has a larger planar dimension than the first mesa MS11. In plan view, the outline of the second mesa MS12 is located outside the outline of the first mesa MS11.

  As shown in FIG. 2, the mesa structure MS1 is formed in a circular shape in a plan view, for example. The first mesa MS11 and the second mesa MS12 are each formed in a circular shape in plan view, and are arranged concentrically with each other in plan view.

  On both sides of the mesa structure MS1, mesa structures MS2 and MS3 are formed, each forming a protrusion shape serving as a base for the second electrode EL2. The mesa structure MS2, MS3 and the second electrode EL2 formed on the mesa structure MS2, MS3 constitute an electrode pad.

  The mesa structures MS2 and MS3 have the same stacked structure as the mesa structure MS1. That is, the mesa structures MS2 and MS3 are configured by the second semiconductor layer SL2, the third semiconductor layer SL3, and the fourth semiconductor layer SL4, similarly to the mesa structure MS1. The mesa structures MS2 and MS3 are each formed, for example, in a rectangular shape in plan view (specifically, in a rectangular shape in plan view).

  Similar to the mesa structure MS1, the mesa structure MS2 includes a first mesa MS21 and a second mesa MS22 having a larger planar dimension than the first mesa MS21, and the second mesa MS22 in plan view. The outer contour line is located outside the outer contour line of the first mesa MS21. The first mesa MS21 and the second mesa MS22 are each formed in a rectangular shape in plan view, and are arranged concentrically and in the same direction (so that each side is parallel to each other).

  Similarly, the mesa structure MS3 includes a first mesa MS31 and a second mesa MS32 having a larger planar dimension than the first mesa MS31. In the plan view, the outline of the second mesa MS32 is , Located outside the outline of the first mesa MS31. The first mesa MS31 and the second mesa MS32 are each formed in a rectangular shape in plan view, and are arranged concentrically and in the same direction (so that each side is parallel to each other).

  For example, the mesa structures MS2 and MS3 are formed to spread out like the mesa structure MS1. That is, the mesa structures MS2 and MS3 are formed in a shape in which the plane cross-sectional area of the mesa structures MS2 and 3 is enlarged from top to bottom, and the inclination angle of the side walls of the mesa structures MS2 and MS3 is less than 90 °. . The mesa structures MS2 and MS3 are portions in which the front sectional shape and the side sectional shape are trapezoidal. The top surfaces of the mesa structures MS2 and MS3 are almost horizontal.

  In the semiconductor device SD1, the light receiving element PD1 is configured by the formation region of the mesa structures MS1, MS2, and MS3 and the region therebetween. In the light receiving element PD1, the uppermost semiconductor layer is the first semiconductor layer SL1 in the non-formation regions of the mesa structures MS1, MS2, and MS3.

  As described above, the second conductivity type region SL5 as the fifth semiconductor layer is formed on the side wall of the mesa structure MS1. For example, the second conductivity type region SL5 is formed continuously from the side wall of the first mesa MS11 to the upper surface of the second mesa MS12.

  Note that the second conductivity type region SL5 may or may not be formed on the sidewalls of the mesa structures MS2 and MS3. In the case of the present embodiment, for example, the second conductivity type region SL5 is continuously formed from the side wall of the first mesa MS21 to the upper surface of the second mesa MS22, and from the side wall of the first mesa MS31 to the second side. It is continuously formed over the upper surface of the mesa MS32.

  The semiconductor device SD1 further includes a first insulating film IF1, a second insulating film IF2, a first contact CNT1, a first electrode EL1, a second contact CNT2, and a second electrode EL2. The first contact CNT1 constitutes a p contact, and the second contact CNT2 constitutes an n contact.

  The first insulating film IF1 functions as a surface protective film, and is made of, for example, an inorganic film such as a SiN film or an organic film such as polyimide. The first insulating film IF1 covers the mesa structures MS1, MS2, and MS3 and the upper surface of the first semiconductor layer SL1. The first insulating film IF1 covers the fifth semiconductor layer (second conductivity type region SL5) formed on the sidewalls of the mesa structures MS1, MS2, and MS3 together with the mesa structures MS1, MS2, and MS3.

  At the top of the mesa structure MS1, an opening IF1a is formed in the first insulating film IF1. The opening IF1a is formed in a circular shape in plan view, for example, and is arranged concentrically with the top surface of the mesa structure MS1.

  In the opening IF1a, the first contact CNT1 is formed on the top surface of the fourth semiconductor layer SL4 (that is, on the top surface of the mesa structure MS1). That is, the first contact CNT1 is electrically connected to the top surface of the mesa structure MS1.

  A first electrode EL1 is formed on the first contact CNT1. The first electrode EL1 is electrically connected to the upper surface of the first contact CNT1 through the opening IF1a, and is also formed on the upper surface of the first insulating film IF1 at the peripheral edge of the opening IF1a.

  The first contact CNT1 and the first electrode EL1 are each formed in a circular shape in plan view.

  The second insulating film IF2 is formed on the back surface of the semiconductor substrate SS1. The second insulating film IF2 functions as a non-reflective film and is made of, for example, an inorganic film such as a SiN film.

  Around the mesa structure MS1, an arc-shaped (for example, C-shaped) ring-shaped opening IF1b concentric with the mesa structure MS1 is formed in the first insulating film IF1 on the first semiconductor layer SL1 in a plan view.

  In the opening IF1b, an arc-shaped (for example, C-shaped) ring-shaped second contact CNT2 concentric with the mesa structure MS1 is formed on the first semiconductor layer SL1. That is, the second contact CNT2 is in contact with the upper surface of the first semiconductor layer SL1 around the mesa structure MS1.

  The opening IF1b and the second contact CNT2 are spaced from the mesa structure MS1 and are disposed around the mesa structure MS1 in plan view. The opening IF1b and the second contact CNT2 are also separated from the mesa structures MS2 and MS3 in a plan view, and are disposed between the mesa structure MS2 and the mesa structure MS3.

  A second electrode EL2 is connected to the second contact CNT2.

The second electrode EL2 is continuously formed from the second contact CNT2 to the top surface of the mesa structure MS2, and continuously formed from the second contact CNT2 to the top surface of the mesa structure MS3. Further, it is continuously formed over the mesa structure MS2 to the mesa structure MS3. More specifically, the second electrode EL2 includes the entire second contact CNT2, the entire mesa structure MS2, the entire mesa structure MS3, and the first semiconductor layer SL1 between the mesa structure MS2 and the mesa structure MS3. And covering.
However, the second electrode EL2 is arranged avoiding the mesa structure MS1. In the second electrode EL2, for example, a keyhole-shaped cutout portion CO1 is formed. And the edge part of notch shape part CO1 in 2nd electrode EL2 is connected to the upper surface of 2nd contact CNT2.

  The first contact CNT1, the first electrode EL1, the second contact CNT2, and the second electrode EL2 are each made of metal. In the present embodiment, the first contact CNT1 is a p-contact, the first electrode EL1 is a p-electrode, the second contact CNT2 is an n-contact, and the second electrode EL2 is an n-electrode (n lead electrode). .

  The light receiving element PD1 of the semiconductor device SD1 according to the present embodiment is a back-illuminated type. That is, when incident light IR1 enters from the back side of the light receiving element PD1, a current flows between the first electrode EL1 and the second electrode EL2.

FIG. 3A and FIG. 3B are diagrams showing examples of impurity concentration profiles in the depth direction of the fourth semiconductor layer SL4. In each of FIG. 3A and FIG. 3B, the horizontal axis represents depth (μm), and the vertical axis represents p-type impurity concentration (cm ⁻³ ). 3A and 3B, the range from the depth of 0.1 μm to 0.5 μm indicates the concentration of the first impurity in the fourth semiconductor layer SL4. The concentration of the p-type impurity in the fourth semiconductor layer SL4 can be, for example, in the range of 1.5 × 10 ¹⁹ cm ⁻³ to 1.0 × 10 ¹⁷ cm ⁻³ .

As shown in FIGS. 3A and 3B, the concentration of the first impurity in the fourth semiconductor layer SL4 decreases in the depth direction of the fourth semiconductor layer SL4. More specifically, for example, there is a region where the concentration of the first impurity decreases from the upper end to the lower end of the fourth semiconductor layer SL4, and there is no region where the concentration of the first impurity increases. .
For example, as shown in FIG. 3A, the concentration of the first impurity in the fourth semiconductor layer SL4 decreases stepwise in the depth direction of the fourth semiconductor layer SL4. Alternatively, as illustrated in FIG. 3B, the concentration of the first impurity in the fourth semiconductor layer SL4 continuously decreases in the depth direction of the fourth semiconductor layer SL4. That is, the fourth semiconductor layer SL4 is a stepped or graded doping layer formed by crystal growth junction.

Next, a method for manufacturing the semiconductor device according to the present embodiment will be described.
This manufacturing method is a method of manufacturing the semiconductor device SD1 including the light receiving element PD1, and includes the following steps (1) to (6).
(1) Step of forming first conductive type first semiconductor layer SL1 on semiconductor substrate SS1 (2) Step of forming first conductive type second semiconductor layer SL2 on first semiconductor layer SL1 (3) First Step of forming first conductive type third semiconductor layer SL3 on second semiconductor layer SL2 (4) Step of forming second conductive type fourth semiconductor layer SL4 on third semiconductor layer SL3 (5) Second semiconductor Step of forming mesa structure MS1 by processing layer SL2, third semiconductor layer SL3, and fourth semiconductor layer SL4 into a mesa shape (6) Second semiconductor layer of second conductivity type (second second) on the side wall of mesa structure MS1 Step of Forming Conductive Type Region SL5) Here, the first impurity that is the second conductive type impurity of the fourth semiconductor layer SL4 and the second conductive type impurity of the fifth semiconductor layer (second conductive type region SL5) Is a different element from the second impurity A. The diffusion constant of the second impurity in the fifth semiconductor layer (second conductivity type region SL5) is larger than the diffusion constant of the first impurity in the fourth semiconductor layer SL4.
Details will be described below.

  Each of FIGS. 4 to 6 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

  First, a semiconductor substrate SS1 that is a semi-insulating InP substrate is prepared. Next, the first semiconductor layer SL1, the second semiconductor layer SL2, the third semiconductor layer SL3, and the fourth semiconductor layer SL4 are sequentially grown on the semiconductor substrate SS1 by, for example, MBE (Molecular Beam Epitaxy) (FIG. 4 (a)).

Here, the first semiconductor layer SL1 is, for example, an n ⁺ -type InP layer having a thickness of about 0.1 μm to 2.0 μm.
The second semiconductor layer SL2 is, for example, an n ⁻ type InP layer having a thickness of about 0.8 μm to 1.5 μm. The second semiconductor layer SL2 may have a two-layer structure of a lower n ⁻ type InP layer and an upper n ⁻ type InAlAs layer.
The third semiconductor layer SL3 is, for example, an n ⁻ type InGaAs layer having a thickness of about 0.7 μm to 1.5 μm.
For example, the fourth semiconductor layer SL4 is a p-type InGaAs layer having a thickness of about 0.2 μm to 1.5 μm.
Here, Si is used as the n-type impurity, and Be is used as the p-type impurity (first impurity).
The doping profile of the p-type impurity in the fourth semiconductor layer SL4 is decreased stepwise or continuously in the depth direction of the fourth semiconductor layer SL4 (FIGS. 3A and 3B). ).

Next, after a film such as a resist film or a SiO ₂ film is formed on the fourth semiconductor layer SL4, this film is processed into an etching mask MSK1 for the first mesa by performing normal photolithography. (FIG. 4B). The mask MSK1 is formed in regions corresponding to the mesa structures MS1, MS2, and MS3 in the fourth semiconductor layer SL4. Of these, the mask MSK1 in a region corresponding to the mesa structure MS1 is formed in a circle having a diameter of about 10 μm to 45 μm. The mask MSK1 in the region corresponding to the mesa structures MS2 and MS3 is formed in a rectangular shape.

  Next, the fourth semiconductor layer SL4 and the third semiconductor layer SL3 are etched through the mask MSK1. This etching may be wet etching or dry etching. Thereby, the first mesa MS11 of the mesa structure MS1, the first mesa MS21 of the mesa structure MS2, and the first mesa MS31 of the mesa structure MS3 are formed in the fourth semiconductor layer SL4 and the third semiconductor layer SL3 ( FIG. 4 (b)). Next, the mask MSK1 is removed (FIG. 4C).

Next, a film FLM1 such as a SiO ₂ film is formed on the first mesa MS11, the first mesa MS21, the first mesa MS31, and the second semiconductor layer SL2 (FIG. 4D).

  Next, the film FLM1 is processed into a diffusion mask MSK2 by performing normal photolithography on the film FLM1 (FIG. 5A). Masks MSK2 are formed in regions corresponding to mesa structures MS1, MS2, and MS3, respectively. Of these, the mask MSK2 in a region corresponding to the mesa structure MS1 is formed in a circular shape having a diameter of about 5 μm to 40 μm. The masks MSK2 in the regions corresponding to the mesa structures MS2 and MS3 are each formed in a rectangular shape. The mask MSK2 in the region corresponding to the mesa structure MS1 is arranged concentrically with the mask MSK1 in the region corresponding to the mesa structure MS1. The mask MSK2 in the region corresponding to the mesa structure MS2 is arranged concentrically and in the same direction (so that the sides are parallel to each other) of the mask MSK1 in the region corresponding to the mesa structure MS2. Similarly, the mask MSK2 in the region corresponding to the mesa structure MS3 is arranged concentrically and in the same direction (so that the sides are parallel to each other) of the mask MSK1 in the region corresponding to the mesa structure MS3.

  Next, Zn (second impurity) is diffused by the solid phase diffusion method or the vapor phase diffusion method using the diffusion mask MSK2 as a mask. Thereby, the fifth semiconductor layer (second conductivity type region SL5) is formed on the side wall of the first mesa MS11, the side wall of the first mesa MS21, the side wall of the first mesa MS31, and the second semiconductor layer SL2. FIG. 5B). Here, the Zn diffusion depth (thickness of the second conductivity type region SL5) is a depth (thickness) at which the second semiconductor layer SL2 is not p-type over the entire thickness. The diffusion depth of Zn is, for example, about 0.05 μm or more and 0.7 μm or less.

Next, a film such as a resist film or a SiO ₂ film is formed on the mask MSK2 and the second conductivity type region SL5, and then this film is used for etching the second mesa by performing normal photolithography. The mask MSK3 is processed (FIG. 5C). The mask MSK3 covers the top surface of the first mesa MS11, the top surface of the first mesa MS21, and the top surface of the first mesa MS31 via the mask MSK2, and over the second conductivity type region SL5. The side wall of the first mesa MS11, the side wall of the first mesa MS21, and the side wall of the first mesa MS31 are covered. Among these, the mask MSK3 covering the top surface and the side wall of the first mesa MS11 is formed in a circular shape having a diameter of about 15 μm to 47 μm and is arranged concentrically with the first mesa MS11. Mask MSK3 covering the top surface and the side wall of mesa structure MS2 is arranged concentrically and in the same direction as first mesa MS21 (each side is parallel to each other). Similarly, the mask MSK3 covering the top surface and the side wall of the mesa structure MS3 is arranged concentrically and in the same direction as the first mesa MS31 (each side is parallel to each other).

  Next, the second semiconductor layer SL2 (the second semiconductor layer SL2 that has become the second conductivity type region SL5 due to the p-type upper layer) is wet-etched or dry-etched through the mask MSK3. This etching is performed to a depth reaching the first semiconductor layer SL1. Thereby, the second mesa MS12 of the mesa structure MS1, the second mesa MS22 of the mesa structure MS2, and the second mesa MS32 of the mesa structure MS3 are formed by the remaining second semiconductor layer SL2 (FIG. 5D). ). The second conductivity type region SL5 is also present on the upper surfaces of the second mesas MS12, MS22, and MS32. The second mesa MS12 is located below the first mesa MS11 and is arranged concentrically with the first mesa MS11. The second mesa MS22 is located below the first mesa MS21 and is concentric with the first mesa MS21 and arranged in the same direction (so that each side is parallel to each other). Similarly, the second mesa MS32 is located below the first mesa MS31 and is concentric with the first mesa MS31 and arranged in the same direction (so that the sides are parallel to each other).

  Thus, the mesa structure MS1 includes the first mesa MS11 configured by the third semiconductor layer SL3 and the fourth semiconductor layer SL4, and the second mesa configured by the second semiconductor layer SL2 having a larger planar dimension than the first mesa MS11. MS12. Similarly, the mesa structure MS2 has a first mesa MS21 constituted by the third semiconductor layer SL3 and the fourth semiconductor layer SL4, and a second mesa structure having a larger planar dimension than the first mesa MS21 and constituted by the second semiconductor layer SL2. And mesa MS22. Similarly, the mesa structure MS3 includes a first mesa MS31 constituted by the third semiconductor layer SL3 and the fourth semiconductor layer SL4, and a second mesa structure having a larger planar dimension than the first mesa MS31 and constituted by the second semiconductor layer SL2. And mesa MS32.

  Further, as a result of performing the etching through the mask MSK3, the fifth semiconductor layer (second conductivity type region SL5) is formed in the mesa structures MS1, MS2, and MS3 from the side walls of the first mesa MS11, MS21, and MS31. It remains in the region extending over the top surfaces of the two mesas MS12, MS22, and MS32.

  Next, the mask MSK3 and the mask MSK2 are removed (FIG. 5D).

  Next, a first insulating film IF1 made of, for example, SiN is formed on the entire surface (FIG. 6A).

  Next, the first contact CNT1 and the second contact CNT2 are formed.

For this purpose, a film such as a resist film is first formed on the entire surface, and then this film is processed into an etching mask by performing normal photolithography. Openings corresponding to the first contact CNT1 and the second contact CNT2 are formed in the mask. Next, the first insulating film IF1 is wet-etched or dry-etched through this mask. Thus, an opening IF1a for forming the first contact CNT1 therein and an opening IF1b for forming the second contact CNT2 therein are formed in the first insulating film IF1 (FIG. 6B). )).
Among these, the opening IF1a is formed in a circular shape concentric with the top surface of the mesa structure MS1 in a portion on the top surface of the mesa structure MS1 in the first insulating film IF1. The opening IF1a is formed to a depth reaching the fourth semiconductor layer SL4.
The opening IF1b is formed in an arc shape (for example, C-shape) concentric with the mesa structure MS1 in a portion around the mesa structure MS1 in the first insulating film IF1 (see FIG. 2). The opening IF1b is formed to a depth reaching the first semiconductor layer SL1.

  Next, a metal film constituting the first contact CNT1 and the second contact CNT2 is formed on the entire surface. This metal film is also formed on the fourth semiconductor layer SL4 and the first semiconductor layer SL1 through the openings IF1a and IF1b. Next, after a film such as a resist film is formed on the entire surface, this film is processed into an etching mask by performing normal photolithography. This mask is located on the formation region of the first contact CNT1 (on the opening IF1a) and on the formation region of the second contact CNT2 (on the opening IF1b). Next, wet etching or dry etching is performed through this mask to leave the opening IF1a and the metal film in the opening IF1a, and remove other portions of the metal film. As a result, the first contact CNT1 is formed in the opening IF1a, and the second contact CNT2 is formed in the opening IF1b.

  Next, the first electrode EL1 and the second electrode EL2 are formed.

  For this purpose, first, a metal film constituting the first electrode EL1 and the second electrode EL2 is formed on the entire surface. Next, after a film such as a resist film is formed on the metal film, the film is processed into an etching mask by performing normal photolithography. The mask is formed in a region corresponding to the first electrode EL1 and a region corresponding to the second electrode EL2. Next, the first electrode EL1 and the second electrode EL2 are formed by etching the metal film through this mask (FIG. 6B).

  Next, the back surface of the semiconductor substrate SS1 is mirror-polished so that the thickness of the semiconductor substrate SS1 is about 100 μm or more and 200 μm or less. Next, a second insulating film IF2 is formed on the back surface of the semiconductor substrate SS1 by CVD or sputtering (FIG. 6C).

  Thus, the semiconductor device SD1 having the light receiving element PD1 is obtained.

  In the above process, the fourth semiconductor layer SL4 may be formed by a MOVPE (Metal Organic Vapor Phase Epitaxy) method. As an impurity of the fourth semiconductor layer SL4, C or Mg may be used instead of Be.

According to the first embodiment as described above, in the mesa PIN photodiode structure having an epi junction, the p-type region (second conductivity type region SL5) is provided in a part of the side wall of the mesa structure MS1. More specifically, a part of the side wall of the mesa structure MS1 is p ⁺ . As a result, the depletion layers of the semiconductors having the small band gap (the third semiconductor layer SL3 and the fourth semiconductor layer SL4 made of InGaAs) can be prevented from being exposed on the side walls of the mesa structure MS1, and the depletion layer can be prevented from being exposed to the surface protection film A light receiving element PD1 having a structure not in direct contact with the insulating film IF1) is obtained. That is, the interface between the unstable surface protective film (first insulating film IF1) and the depleted undoped InGaAs can be prevented. Thereby, the dark current is stabilized and the high reliability characteristic of the semiconductor device SD1 is obtained.

  The second conductivity type provided on the side wall portion of the mesa structure MS1 is larger than the thermal diffusion constant of the p-type impurity element (first impurity) of the fourth semiconductor layer SL4 constituting the top portion (light receiving portion) of the mesa structure SM1. The thermal diffusion constant of the p-type impurity element (second impurity) in region SL5 is larger. With such an element structure, the doping profile of the p-type impurity at the top (fourth semiconductor layer SL4) of the mesa structure MS1 is destroyed in the thermal process of diffusing the p-type impurity into the side wall of the mesa structure MS1. This can be suppressed. That is, since the diffusion constant of the first impurity in the fourth semiconductor layer SL4 that forms the top of the mesa structure MS1 is small, it is possible to suppress the doping profile of the fourth semiconductor layer SL4 from collapsing. In addition, since the diffusion constant of the second impurity in the second conductivity type region SL5 provided on the side wall portion of the mesa structure MS1 is large, the side wall of the mesa structure MS1 is promptly maintained so as not to destroy the doping profile of the fourth semiconductor layer SL4. A second impurity can be introduced into the part. Thereby, the light receiving element PD1 having good high frequency response characteristics is obtained.

FIG. 7 is a diagram for explaining the effect of the light receiving element PD1 included in the semiconductor device SD1 according to the embodiment. In FIG. 7, the horizontal axis represents the modulation frequency of the modulated light incident on the light receiving element PD1 as the incident light IR1, and the vertical axis represents the relative intensity (in dB) of the output current from the light receiving element PD1.
In FIG. 7, a curve L1 (solid line) indicates the characteristic (high frequency response characteristic) of the light receiving element PD1 in the semiconductor device SD1 according to the embodiment, and a curve L2 (dotted line) indicates the characteristic of the light receiving element of the semiconductor device according to the comparative example. (High frequency response characteristics). When the modulated light enters the light receiving element, photoelectric conversion is performed by the light receiving element, and a current is output from the light receiving element. A characteristic indicating how much the current output waveform follows the input optical waveform is called a high frequency response characteristic.
The semiconductor device according to the comparative example is in the embodiment only in that the thermal diffusion constant of the p-type impurity element of the fourth semiconductor layer SL4 and the thermal diffusion constant of the p-type impurity element of the second conductivity type region SL5 are equal to each other. The semiconductor device SD1 is different from the semiconductor device SD1 and is otherwise configured in the same manner as the semiconductor device SD1 according to the embodiment.
As shown in FIG. 7, the high frequency response characteristic (curve L1) of the light receiving element PD1 of the semiconductor device SD1 according to the embodiment is better than the high frequency response characteristic (curve L2) of the light receiving element of the semiconductor device according to the comparative example. It is.

As described above, the concentration of the p-type impurity in the fourth semiconductor layer SL4 is, for example, in the range of 1.5 × 10 ¹⁹ cm ⁻³ to 1.0 × 10 ¹⁷ cm ⁻³ , and within this concentration range, Loss due to non-radiative recombination can be reduced and can contribute to quantum efficiency. Furthermore, by appropriately designing the p-concentration profile, a pseudo electric field with respect to electrons can be used, so that the light receiving element PD1 with good high-speed response characteristics can be obtained.

  According to the present embodiment, the semiconductor device SD1 including the light receiving element PD1 having a low operating voltage, high speed, high quantum efficiency, and high reliability can be manufactured with a simple element structure and high yield. More specifically, for example, a light receiving element PD1 having an operating speed of 10 Gb / s or higher, particularly a low operating voltage of 25 to 40 Gb / s in a wavelength range of 1.3 to 1.5 μm, high speed, high quantum efficiency, and high reliability is obtained. It is done.

  In addition, the concentration of the first impurity in the fourth semiconductor layer SL4 decreases in the depth direction of the fourth semiconductor layer SL4. As a result, the p-type impurity doping profile of the fourth semiconductor layer SL4 constituting the top of the mesa structure MS1 is destroyed in the thermal process of diffusing the p-type impurity into the side wall of the mesa structure MS1. It can suppress suitably.

[Second Embodiment]
FIG. 8 is a cross-sectional view showing the structure of the semiconductor device SD2 according to the second embodiment. FIG. 9 is a plan view showing the structure of the semiconductor device SD2. 8 is a cross-sectional view taken along line AA in FIG.

  The semiconductor device SD2 according to this embodiment includes a front-illuminated light receiving element PD2. The semiconductor device SD2 according to the present embodiment is different from the semiconductor device SD1 according to the first embodiment in the points described below, and is configured in the same manner as the semiconductor device SD1 in other points.

  Also in the present embodiment, the first contact CNT1 is formed in the opening IF1a of the first insulating film IF1 on the top surface of the mesa structure MS1 (on the fourth semiconductor layer SL4). However, in the first embodiment, the first contact CNT1 is circular in plan view. In the present embodiment, the first contact CNT1 is formed in a ring shape (doughnut shape) in plan view.

  In the case of this embodiment, the first electrode EL1 has a ring-shaped portion EL11, a lead-out portion EL12, and a rectangular portion EL13.

  The ring-shaped portion EL11 has a ring shape (doughnut shape) in plan view, and is formed on the first contact CNT1 and on the peripheral edge portion of the opening IF1a in the first insulating film IF1.

  The rectangular portion EL13 has a rectangular shape in plan view, and is formed on the top surface of the mesa structure MS3 via the first insulating film IF1.

  The lead portion EL12 is formed in a linear shape (long rectangular shape) having a predetermined width in plan view. The lead portion EL12 functions as a lead wiring that connects the ring-shaped portion EL11 and the rectangular portion EL13 to each other. The lead portion EL12 is formed on the top surface of the mesa structure MS1, on the sidewall of the mesa structure MS1, on the semiconductor substrate SS1 between the mesa structure MS1 and the mesa structure MS3, and on the sidewall of the mesa structure MS3. It is formed via IF1.

  Also in the present embodiment, the second contact CNT2 is formed in the opening IF1b of the first insulating film IF1 around the mesa structure MS1, and is disposed on the first semiconductor layer SL1. Also in the present embodiment, the second contact CNT2 is formed in an arc-shaped (for example, C-shaped) ring shape concentric with the mesa structure MS1, and on the upper surface of the first semiconductor layer SL1 around the mesa structure MS1. It touches.

  In the case of this embodiment, the second electrode EL2 has an arc-shaped portion EL21, a lead-out portion EL22, and a rectangular portion EL23.

  The arc-shaped portion EL21 is formed on the second contact CNT2 so as to be substantially the same shape as the second contact CNT2 in a plan view and overlaps the second contact CNT2 in a plan view. Are electrically connected.

  The rectangular portion EL23 has a rectangular shape in plan view, and is formed on the top surface of the mesa structure MS2 via the first insulating film IF1.

  The lead portion EL22 is formed in a linear shape (for example, a wide and short rectangular shape) having a predetermined width in a plan view. The lead portion EL22 functions as a lead wire that connects the arc-shaped portion EL21 and the rectangular portion EL23 to each other. The lead portion EL22 is disposed on the side wall of the mesa structure MS3 and on the first semiconductor layer SL1 (on the third mesa MS13 to be described later) between the mesa structure MS2 and the second contact CNT2 via the first insulating film IF1. Is formed.

  Furthermore, the semiconductor device SD2 according to the present embodiment includes a third mesa MS13 and a third mesa MS33 described below. In the light receiving element PD2, the first to fifth semiconductor layers SL1 to SL5 do not exist in the non-formation regions of the third mesa MS13 and the third mesa MS33, and the semiconductor substrate SS1 is formed via the first insulating film IF1. The semiconductor substrate SS1 is exposed through the first insulating film IF1 and the lead portion EL12 of the first electrode EL1.

  As shown in FIG. 9, the third mesa MS13 is configured by a part of the first semiconductor layer SL1. The third mesa MS13 has a rectangular shape including a formation region of the mesa structure MS1, a formation region of the mesa structure MS2, and a formation region of the second electrode EL2 (including the formation region of the second contact CNT2) in plan view. Is formed. Therefore, the mesa structure MS1 and the mesa structure MS2 are arranged on the third mesa MS13.

  The third mesa MS13 is formed to spread out at the bottom. That is, the third mesa MS13 is formed in a shape in which the plane cross-sectional area of the third mesa MS13 increases from top to bottom, and the inclination angle of the side wall of the third mesa MS13 is less than 90 °. The third mesa MS13 is a trapezoidal part in front sectional shape and side sectional shape.

  The third mesa MS13 is formed with a notch-shaped portion CO2 having a trapezoidal shape or a rectangular shape in plan view, and the third mesa MS13 does not exist in the formation region of the notch-shaped portion CO2 in plan view. The notch-shaped part CO2 is formed between the mesa structure MS1 and the mesa structure MS3 in the formation area of the lead part EL12 and the surrounding area.

  On the other hand, the third mesa MS33 is composed of the first semiconductor layer SL1 and constitutes the lower part of the mesa structure MS3. The third mesa MS33 has a larger planar dimension than the second mesa MS32, and the outline of the third mesa MS33 is located outside the outline of the second mesa MS32 in plan view. The third mesa MS33 is formed in a rectangular shape in plan view. The third mesa MS33 and the second mesa MS32 (and the first mesa MS31) are arranged concentrically and in the same direction (so that each side is parallel to each other).

  In the case of this embodiment, since the semiconductor light receiving element detects incident light IR1 incident from the front surface side, the first contact CNT1 and the first electrode EL1 formed on the top of the mesa structure each have a ring shape. . That is, a ring-shaped opening IF1a is formed in the first insulating film IF1 on the top of the mesa structure, and a ring-shaped first contact CNT1 is formed in the opening IF1a. In addition, a circular opening EL1a is formed in a portion on the top of the mesa structure in the first electrode EL1. The peripheral edge of the opening EL1a in the first electrode EL1 is connected to the upper surface of the first contact CNT1.

  The first electrode EL1 is formed from the top of the mesa structure to the top of the surrounding frame-like portion.

  In addition, a portion of the doughnut-shaped valley portion around the mesa structure (the right portion in FIG. 3) reaches the surface of the semiconductor substrate SS1, and the first insulating film IF1 is formed on the portion. .

  Further, the second insulating film IF2 (FIG. 1) is not formed on the back surface of the semiconductor substrate SS1.

Next, a method for manufacturing a semiconductor device according to the second embodiment will be described.
FIG. 10 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment.

  First, the steps from FIG. 4A to FIG. 5D are performed as in the first embodiment.

Next, the third mesa MS13 and the third mesa MS33 are formed. For this purpose, first, a film such as a resist film or a SiO ₂ film is formed on the entire surface, and then this film is processed into an etching mask by performing normal photolithography. This mask includes a region corresponding to the third mesa MS13 (a rectangular region having a notch-shaped portion CO2 as shown in FIG. 9) and a region corresponding to the third mesa MS33 (a rectangular region as shown in FIG. 9). In the shape area). Next, the first semiconductor layer SL1 is etched (wet etching or dry etching) through this mask. This etching is performed to a depth that reaches the semiconductor substrate SS1. Thereby, the third mesa MS13 and the third mesa MS33 made of the first semiconductor layer SL1 are formed (FIG. 10A).

  Next, a first insulating film IF1 made of, for example, SiN is formed on the entire surface (FIG. 10B).

  Next, the first contact CNT1 and the second contact CNT2 are formed.

For this purpose, a film such as a resist film is first formed on the entire surface, and then this film is processed into an etching mask by performing normal photolithography. Openings corresponding to the first contact CNT1 and the second contact CNT2 are formed in the mask. Next, the first insulating film IF1 is wet-etched or dry-etched through this mask. As a result, an opening IF1a for forming the first contact CNT1 therein and an opening IF1b for forming the second contact CNT2 therein are formed in the first insulating film IF1 (FIG. 10B). )).
Among these, the opening IF1a is formed in a ring-like shape concentric with the top surface of the mesa structure MS1 in a portion on the top surface of the mesa structure MS1 in the first insulating film IF1. The opening IF1a is formed to a depth reaching the fourth semiconductor layer SL4.
The opening IF1b is formed in an arc shape (for example, C-shape) concentric with the mesa structure MS1 in a portion around the mesa structure MS1 in the first insulating film IF1 (see FIG. 8). The opening IF1b is formed to a depth reaching the first semiconductor layer SL1.

  Next, a metal film constituting the first contact CNT1 and the second contact CNT2 is formed on the entire surface. This metal film is also formed on the fourth semiconductor layer SL4 and the first semiconductor layer SL1 through the openings IF1a and IF1b. Next, after a film such as a resist film is formed on the entire surface, this film is processed into an etching mask by performing normal photolithography. This mask is located on the formation region of the first contact CNT1 (on the opening IF1a) and on the formation region of the second contact CNT2 (on the opening IF1b). Next, wet etching or dry etching is performed through this mask to leave the opening IF1a and the metal film in the opening IF1a, and remove other portions of the metal film. As a result, the first contact CNT1 is formed in the opening IF1a, and the second contact CNT2 is formed in the opening IF1b.

  Next, the first electrode EL1 and the second electrode EL2 are formed.

  For this purpose, first, a metal film constituting the first electrode EL1 and the second electrode EL2 is formed on the entire surface. Next, after a film such as a resist film is formed on the metal film, the film is processed into an etching mask by performing normal photolithography. The mask is formed in a region corresponding to the first electrode EL1 and a region corresponding to the second electrode EL2. Next, the first electrode EL1 and the second electrode EL2 are formed by etching the metal film through this mask (FIG. 10B).

  Next, the back surface of the semiconductor substrate SS1 is mirror-polished so that the thickness of the semiconductor substrate SS1 is about 100 μm or more and 200 μm or less (FIG. 10C).

  Thus, the semiconductor device SD2 having the light receiving element PD2 is obtained.

  According to the second embodiment as described above, the same effect as in the first embodiment can be obtained.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

CNT1 First contact CNT2 Second contact CO1 Notch shape portion CO2 Notch shape portion EL1 First electrode EL1a Opening EL11 Ring shape portion EL12 Lead portion EL13 Rectangular portion EL2 Second electrode EL21 Arc portion EL22 Lead portion EL23 Rectangular portion IF1 First Insulating film IF1a Opening IF1b Opening IF2 Second insulating film IR1 Incident light IR2 Incident light MS1 Mesa structure MS11 First mesa MS12 Second mesa MS13 Second mesa MS2 Mesa structure MS21 First mesa MS22 Second mesa MS3 Mesa structure MS31 First mesa MS32 Second mesa MS33 Second mesa MSK1 Mask MSK2 Mask MSK3 Mask FLM1 Film PD1 Light receiving element PD2 Light receiving element SD1 Semiconductor device SD2 Semiconductor device SL1 First semiconductor layer SL2 Second semiconductor layer SL3 Third semiconductor layer SL4 Four semiconductor layer SL5 second conductivity type region (fifth semiconductor layer)
SS1 semiconductor substrate

Claims (13)

Having a light receiving element,
The light receiving element is
A semiconductor substrate;
A first semiconductor layer of a first conductivity type formed on the semiconductor substrate;
A second semiconductor layer of a first conductivity type formed on the first semiconductor layer;
A third semiconductor layer of a first conductivity type formed on the second semiconductor layer;
A fourth semiconductor layer of a second conductivity type formed on the third semiconductor layer;
Have
A mesa structure is constituted by the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer,
The light receiving element further includes a fifth semiconductor layer of a second conductivity type formed on a side wall of the mesa structure,
A first impurity that is a second conductivity type impurity of the fourth semiconductor layer and a second impurity that is a second conductivity type impurity of the fifth semiconductor layer are elements different from each other;
A semiconductor device, wherein a diffusion constant of the second impurity in the fifth semiconductor layer is larger than a diffusion constant of the first impurity in the fourth semiconductor layer.   2. The semiconductor device according to claim 1, wherein a concentration of the first impurity in the fourth semiconductor layer decreases in a depth direction of the fourth semiconductor layer.   3. The semiconductor device according to claim 2, wherein the concentration of the first impurity in the fourth semiconductor layer decreases stepwise in the depth direction of the fourth semiconductor layer.   The semiconductor device according to claim 2, wherein the concentration of the first impurity in the fourth semiconductor layer continuously decreases in the depth direction of the fourth semiconductor layer. The mesa structure is
A first mesa composed of the third semiconductor layer and the fourth semiconductor layer;
A second mesa composed of the second semiconductor layer;
Including
2. The semiconductor device according to claim 1, wherein the outline of the second mesa is located outside the outline of the first mesa in plan view. The fifth semiconductor layer is
The semiconductor device according to claim 5, wherein the semiconductor device is continuously formed from a side wall of the first mesa to an upper surface of the second mesa.   2. The semiconductor device according to claim 1, wherein the mesa structure is formed in a shape in which a plane cross-sectional area of the mesa structure increases from top to bottom, and an inclination angle of a side wall is less than 90 °.   The semiconductor device according to claim 1, wherein the mesa structure is circular in a plan view. The semiconductor substrate is an InP substrate;
The first semiconductor layer is an n-type InP layer;
The second semiconductor layer is an n-type InP layer, or an n-type InAlAs layer is stacked on the n-type InP layer,
The third semiconductor layer is an n-type InGaAs layer;
The semiconductor device according to claim 1, wherein the fourth semiconductor layer is a p-type InGaAs layer. The n-type impurity of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer is Si,
The semiconductor device according to claim 9, wherein the first impurity is Be, C, or Mg.   The semiconductor device according to claim 1, wherein the second impurity is Zn. Forming a first semiconductor layer of a first conductivity type on a semiconductor substrate;
Forming a first conductivity type second semiconductor layer on the first semiconductor layer;
Forming a first conductivity type third semiconductor layer on the second semiconductor layer;
Forming a fourth semiconductor layer of the second conductivity type on the third semiconductor layer;
Forming a mesa structure by processing the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer into a mesa shape;
Forming a second conductivity type fifth semiconductor layer on the side wall of the mesa structure;
Have
A first impurity that is a second conductivity type impurity of the fourth semiconductor layer and a second impurity that is a second conductivity type impurity of the fifth semiconductor layer are elements different from each other;
A method of manufacturing a semiconductor device including a light receiving element, wherein a diffusion constant of the second impurity in the fifth semiconductor layer is larger than a diffusion constant of the first impurity in the fourth semiconductor layer.   13. The method of manufacturing a semiconductor device according to claim 12, wherein the fifth semiconductor layer is formed by diffusing the second impurity by a solid phase diffusion method or a vapor phase diffusion method with respect to the side wall of the mesa structure.

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