JP2014021634A - Rush current suppression circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a rush current suppression circuit that suppresses a rush current in an ON state by using a small number of components.SOLUTION: In a circuit that is inserted between a DC power supply BT1 and a load and that controls on/off of power supply from the DC power supply BT1 to the load by a gate potential of a semiconductor switching element Q1, a potential difference detection circuit is provided, which is a negative feedback circuit that connects a rise voltage of an output voltage to an anode of a reverse-flow blocking diode D1 via a capacitor C1 and feeds back a cathode of the diode D1 to a gate of the semiconductor switching element Q1 and in which if the semiconductor switching element Q1 is off, an emitter of a PNP transistor Q2 connected to a source and a base of the PNP transistor Q2 connected to a drain detect a potential difference and a collector of the PNP transistor Q2 is connected so as to make a potential of the anode of the reverse-flow blocking diode D1 the same potential as that of the source of the semiconductor switching element Q1.

Description

  The present invention relates to an inrush current suppression circuit that copes with a problem caused by an inrush current immediately after application of a DC voltage to a load in accordance with ON / OFF control of power supply from a DC power supply to a load by a semiconductor switching element.

  In recent years, switching regulators and storage batteries have been used in various electronic devices, lighting fixtures, and power devices as DC power sources for electronic devices.

  A semiconductor switching element configured as shown in FIG. 1 is frequently used for on / off control of power supply from a DC power source to a load. In the circuit example shown in FIG. 1, the gate voltage of a Pch power MOSFET is used. Is reduced from the DC power source by a predetermined voltage Vth (threshold voltage), so that DC can be supplied to the load with high speed and low resistance switching characteristics.

  In particular, when the DC power supply is a switching regulator, the output voltage once drops due to the inrush current due to load connection, and then overshoot and ringing occur due to the response of the output voltage stabilization circuit of the switching regulator, and the circuit operation and element reliability May be affected.

  When the DC power source is a storage battery, excessive discharge due to an inrush current when a load is connected accelerates deterioration of the storage battery in addition to an abnormal decrease in output voltage.

  When it is required to cope with the above-mentioned problems and to suppress inrush current mainly as a load-side application and specification, the supply voltage to the load is moderated by applying a control voltage generated by PWM etc. to the semiconductor switching element. To suppress the inrush current.

P3772318 (Japanese Patent Laid-Open No. 9-233806) P3155342 (Japanese Patent Laid-open No. 5-336737)

  However, in the inrush current suppression circuit having such a configuration, it is necessary to separately provide an inrush current suppression signal generation circuit for the semiconductor switching element. In addition to the dedicated element, the inrush current suppression signal generation circuit has a reference clock or a reference voltage. There are various problems such as the increase in circuit components, the associated cost increase, and the difficulty in reducing the board area due to the increase in the number of components.

  In addition, for example, a CPU or logic IC as a system control circuit is connected to a DC power supply, and the same DC power supply enters a load via a semiconductor switching element that performs on / off operation based on a signal from the control circuit described above. When on / off control of a capacitive load with a large current is performed, a semiconductor switching element or the like is turned on based on an on signal according to a command from the control circuit. When the load is connected steeply, the voltage of the DC power supply is increased due to an excessive inrush current. There is also a problem that a problem arises that the operating voltage of the CPU or logic IC falls below the operating voltage of the CPU or logic IC for a very short time, and the system circuit is reset, resulting in a loop in which the system cannot be activated forever.

  For example, in Patent Document 1, a dedicated soft start PWM generation circuit is provided to solve the problem. For this reason, there has been a problem that the cost of the soft star PWM generation circuit components and the printed circuit board mounting area of the soft start PWM generation circuit are large, and the apparatus cannot be downsized.

  In Patent Document 2, a simple operation delay circuit configured by RC is provided at the gate of the power MOSFET for turning on / off the power source to suppress the inrush current. Since a bias diode is connected, an inrush current suppression effect cannot be obtained unless a voltage higher than Vf of the reverse bias diode is applied to the operation delay circuit. There was a problem that the effect could not be obtained.

  The present invention aims to solve the above-mentioned problems of the prior art. For example, if an ON signal is input to a semiconductor switching element, an inrush current can be suppressed by a few active components, and an external inrush current suppression signal can be obtained. If the DC power supply is a switching power supply, the transient response phenomenon of the power supply voltage due to the load connection can be suppressed, and the stability of the circuit operation and the deterioration of the circuit elements can be prevented. it can.

  If the DC power supply is a storage battery, the deterioration of the storage battery can be protected by limiting an excessive inrush current to the load.

In order to achieve this object, an inrush current suppression circuit according to the present invention is inserted between a DC power supply and a load, and on / off of power supply from the DC power supply to the load is controlled by a gate potential of the semiconductor switching element. In the circuit.
A negative feedback circuit for connecting a rising voltage of an output voltage from a drain of a semiconductor switching element to a load via a capacitor to an anode of a reverse current blocking diode and feeding back the cathode of the diode to a gate of the semiconductor switching element. If the element is off, the emitter of the PNP transistor connected to the source and the base of the PNP transistor connected to the drain detect a potential difference, and the collector of the PNP transistor detects the potential of the anode of the reverse current blocking diode as a semiconductor. An inrush current suppression circuit comprising a potential difference detection circuit connected to have the same potential as the source of a switching element.

  If the overcurrent detection resistor element is connected in series with the load and the current flowing through the load is an overcurrent, the base potential of the control transistor is turned off based on the potential difference between the terminals of the overcurrent detection resistor element. An inrush current suppression circuit comprising an overcurrent detection circuit that drops the potential to a negative current.

  As described above, according to the present invention, when a load is connected to a DC power supply, the on / off control having an inrush current suppressing function is configured by the semiconductor switching element, thereby achieving downsizing and cost reduction.

It is a circuit diagram which shows the structure of the DC power supply on / off circuit by a semiconductor switching element which has the inrush current suppression function of this invention. It is a waveform of the output voltage at the time of load connection (off to on) by a semiconductor switching element having no inrush current suppression function. It is a waveform of the output voltage at the time of load connection (OFF to ON) by a semiconductor switching element by the inrush current suppression circuit of the present invention. It is a figure which shows the transition of the inrush current suppression function of this invention. It is a waveform showing an erroneous output power supply rise when the DC power supply BT1 is connected later to a circuit that does not add a backflow prevention diode to the inrush current suppression circuit. This is a circuit example in which a discharging diode of a feedback capacitor is connected from a GND potential without adding a potential difference detection circuit. FIG. 7 is a rising waveform of an output voltage when the power is turned on and a voltage waveform of the DC power supply BT1 according to the circuit example of FIG. FIG. 2 is a circuit diagram illustrating a configuration of a circuit example in which an overcurrent detection resistance element is added to the circuit diagram of FIG. 1.

  The inrush current suppression circuit of the present invention will be described below with reference to the drawings. The same or equivalent components shown in the drawings are denoted by the same reference numerals, and repeated description is appropriately omitted. Further, the embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the present invention.

This inrush current suppression circuit, as shown in FIG.
-BT1 as a power source for supplying DC voltage;
A control element transistor Q3 for controlling on / off of the power supply based on the TTL signal;
A Pch power MOSFET Q1 of a semiconductor switching element that is turned on when the gate drops due to the output of the control element Q3 and turns on / off the power supply to the load;
An emitter of a PNP transistor Q2 connected to the source of the semiconductor switching element Q1, a base of Q2 also connected to the drain of Q1,
A load resistance RL and a capacitive load CL are connected to the drain of the semiconductor switching element Q1 as a load.
The capacitor C1 is connected to the drain of the semiconductor switching element Q1, the other terminal of C1 is connected to the anode of the reverse current blocking diode D1, and the cathode of D1 is connected to the gate of Q1 to form a negative feedback circuit. ing.
The collector of the transistor Q2 is connected to the connection point between the capacitor C1 and the anode of the reverse current blocking diode D1, and if the semiconductor switching element Q1 is off, a potential difference occurs between the emitter and base of Q2 and Q2 is on. Therefore, a bias voltage having the same potential as the source of the semiconductor switching element Q1 is applied from the collector of the transistor Q2 to the connection point between the capacitor C1 and the anode of the reverse current blocking diode D1.

In addition, a waveform is shown in FIG. 2 as an example in which inrush current suppression is not performed.
The condition of the case where inrush current suppression is not performed will be described based on the circuit diagram of FIG.
・ Commercial power supply AC100V input to DC power supply BT1 and rated output DC12V 0.9A general-purpose switching regulator (unit) is used.
The load resistance RL is 27Ω, and therefore, a load resistance through which 0.44 A, a current that is approximately 50% of the rated current of the switching regulator (unit), flows.
・ Capacitive load CL is 1000uF
-In order to prevent inrush current suppression from functioning, delete inrush current suppression circuit components from the circuit diagram of (Fig. 1) (Q2, D1, C1, etc.)
It is.

  The waveform of the case where the inrush current is not suppressed (FIG. 2) is turned on (load connection) in the waveform center, and as a result, the voltage of the DC power source BT1 of ch2 on the lower side of the waveform is once about half of the rated voltage. The voltage dropped to 6.2V, and the voltage returned after about 15mse. The upper ch1 of the waveform is the waveform of the supply voltage to the loads RL and CL, and the supply voltage to the loads RL and CL rises with the voltage recovery of the DC power supply BT1 and stabilizes after about 15 ms.

  Examples of the present invention will be described below.

Example 1
As an example, the inrush current suppression circuit in the circuit diagram of FIG. 1 is a circuit diagram showing the basic function of the present invention.

In the circuit diagram of FIG. 1, for example, when the DC power supply BT1 is + 12V (hereinafter abbreviated as 12V) and the power supply to the load is off, the voltage of each semiconductor element is as follows. is there.
・ Control transistor Q3 (base 0V, collector 12V, emitter 0V)
Switching element Pch power MOSFET Q1 (source 12V, gate 12V, drain 0V)
-Potential difference detection transistor Q2 (base 11.4V, collector 12V, emitter 12V)
・ Backflow prevention diode D4 (Anode 12V, Cathode 12V)

Similarly, in the circuit diagram of FIG. 1, when the DC power supply BT1 is 12V and the power supply to the load is on, the voltages of the respective semiconductor elements are as follows.
・ Control transistor Q3 (base 0.6V, collector 0V, emitter 0V)
Switching element Pch power MOSFET Q1 (source 12V, gate approximately 0V, drain 12V)
-Potential difference detection transistor Q2 (base 12V, collector about 0V, emitter 12V)
・ Backflow prevention diode D4 (Anode approximately 0V, cathode approximately 0V)

  Then, during the transition period from the power supply OFF to ON, which is a feature of the present invention, a reverse potential change voltage is applied between the anode and the cathode of the reverse current blocking diode D1 to turn on the load from the power supply OFF. In the early stage of transition to, a voltage exceeding Vf is applied to the reverse current blocking diode D1 at high speed, thereby enabling the function of the negative feedback circuit for suppressing the inrush current.

  In detail, based on (FIG. 4), inrush current suppression is performed during the transition period in the process of shifting from OFF to ON. In particular, the Pch power MOSFET Q1 of the switching element is a high resistance semiconductor element in the off state, and functions as a low resistance semiconductor in the saturation region in the on state.

  Inrush current suppression is achieved by operating the Pch power MOSFET Q1 in the non-saturation region and operating Q1 as a semiconductor element having a high resistance to a low resistance in the process of switching from off to on. Yes.

  Specifically, based on the TTL control signal, the control transistor Q3 is turned on by turning off (0V) to on (5V), and when the collector of Q3 becomes 0V, the gate of the Pch power MOSFET Q1 and the cathode of the reverse current blocking diode D1 are connected. The connection point begins to gradually decrease from 12V, which is the same potential as the power supply voltage, to 0V at (delta) Vth. Therefore, Q1 starts to shift from OFF to ON, and the drain potential of Q1 increases from 0V to 12V. Begin. Since one terminal of the negative feedback capacitor C1 is connected to the drain of Q1, an increase in potential is obtained, and the remaining terminal of C1 is connected to the anode of the reverse current element diode D1 to which a potential of 12 V has been applied in advance. An attempt is made to convey the rise in drain potential, but the cathode of D1 is connected to the gate of Q1, and the anode potential of diode D1 is a negative feedback circuit that functions while maintaining the potential of (delta) Vth + (Vf of D1). Therefore, it falls while being pulled down to the potential of the gate of Q1, and since the collector of Q3 is 0V, the connection point between the gate of Q1 and the cathode of D1 finally becomes a potential around 0V by the time constant of R4 and C1. At the same time, the anode potential of the diode D1 also drops to near 0V, and the switching power MOSFET Q1 exceeds the applied voltage of Vth, A semiconductor element for supplying electric power to a load of low resistance in the saturation region of the all-on.

  Therefore, a voltage less than Vth is applied to the gate of Q1 in the transition period, and during the period until Vth is exceeded, the resistance value between the source and gate of Q1 is gradually decreased from OFF to ON, and finally It functions as a semiconductor that turns on (operates as a low resistance). At this time, in the embodiment of the present invention, the inrush current to the load is suppressed by the change of the on-resistance of Q1 during the transition period.

  In the inrush current suppressing circuit of the present invention, the time required for transition from output OFF to complete ON can be determined by the capacitance value of the feedback capacitor C2 and the resistance element R4, but the power supply impedance and load resistance RL of the DC power supply BT1. Therefore, the time required for transition from the output off state to the complete on state may be appropriately adjusted by the capacitance value of the feedback capacitor C2 and the resistance value of the resistance element R4.

  Further, the operation of the reverse current blocking diode D1 described in the circuit diagram of FIG. 1 will be described. When the DC power supply BT1 is connected (later connected) to the circuit of FIG. 1 in a short circuit state in which D1 is not inserted, Although the TTL control signal is turned off, the gate voltage of the Pch power MOSFET Q1 of the switching element forms a charging circuit by C1, RL, and CL, and the gate potential of Q1 becomes lower than the source potential, so that Q1 is turned on. , There occurs a problem that power is supplied to the load during the time of the C1 charging period.

  Then, the potential of the connection point between the negative feedback capacitor C1 and the anode of the reverse current blocking diode D1, which is a feature of the present invention, is not set to the same potential as the source of the switching power MOSFET Q1, and the discharge of C1 is made GND as shown in FIG. When the potentials of the anodes of C1 and D1 are set close to GND, the inrush current suppression circuit does not function, and the power supply voltage of BT1 decreases significantly simultaneously with the load connection. Note that the voltage waveform when the power supply is turned off is as shown in FIG. 7. The lower ch2 of the waveform is the voltage waveform of BT1, and the upper ch1 of the waveform is the supply voltage waveform to the load.

  In the operation from on to off in the present invention, when the potential of the collector of Q3 rises from 0V to 12V based on the control signal of TTL, the control transistor Q3 is turned off by on (5V) to off (0V). Since the potential at the connection point between the gate of the Pch power MOSFET Q1 and the cathode of the reverse current blocking diode D1 also rises from 0V to 12V, Q1 starts to shift from the on state to the off state, and the drain potential of Q1 begins to fall from 12V to 0V. . Then, the base potential of Q2 connected to the drain of Q1 falls, and when the potential difference between the emitter and the base exceeds 0.6V, Q2 is turned on. As a result, 12V is output to the collector of Q2, 12V is charged to C1 via R2, and 12V is applied from the anode of D1 to the cathode, thereby further assisting in raising the gate potential of Q1. Accordingly, it is possible to shorten the transition time from the ON state to the OFF state of Q1 and cut off the power supply at high speed.

(Example 2)
In (Embodiment 1) of the present invention, an example in which the positive output of the direct current power supply BT1 is turned on / off has been described. Easy. For example, the Pch power MOSFET Q1 of the switching control element is replaced with an Nch element, the potential detection transistor Q2 is replaced with NPN, and the connection direction of the backflow blocking element diode D1 is switched.

(Example 3)
It is easy to add an overcurrent protection function or the like to (Embodiment 1) of the present invention based on the circuit diagram of (FIG. 5).

Example 4
In the present invention, when the load resistor RL is detachable and when the load resistor RL is not connected, the path of the bias current of the potential difference detection transistor Q2 is lost. Therefore, as shown in FIG. The path of the bias current of the potential difference detection transistor Q2 may be secured by always connecting the resistance element RLD.

(Example 5)
In the inrush current suppression circuit of the present invention, when it is desired to change the rise time from OFF to ON at any time according to the load specification or to combine the slopes, a plurality of different resistance values are provided in the resistance element portion of R4. By switching the resistance value of R4 with an analog switch or the like, it is possible to perform operations such as rising time or changing the slope from the middle of rising.

  Also, the voltage change of the DC power supply BT1 due to the load connection is monitored by a comparator or the like, and the voltage of the DC power supply BT1 greatly fluctuates due to the new load connection, and the influence of the voltage fluctuation on other loads connected in advance is considered. When the voltage of the DC power supply BT1 is monitored, the output of the comparator that monitors the voltage of the BT1 is connected to the analog switch, and the resistance value of R4 is switched to control the rise time and to the load. It is also possible to control the rise of the supply voltage of the power supply and suppress the voltage fluctuation of the DC power supply BT1.

  The inrush current suppression circuit according to the present invention suppresses an inrush current by a semiconductor switching element at the time of transition from off to on to supply a DC voltage to a load, and a DC power source such as a switching regulator in a no load or light load state. It can be used as a means to supply DC voltage load by suppressing excessive current flow from the battery, extending the life of storage batteries, and protecting various electronic devices, lighting fixtures, and power equipment from deterioration and damage. It is.

BT1 DC power supply Q1 Semiconductor switching element, Pch power MOSFET
Q2 Potential difference detection transistor Q3 Control transistor D1 Backflow blocking diode D2 Discharge diode C1 Feedback capacitor RL Load resistance CL Capacitive load RLD Bias current resistance R7 of potential difference detection transistor Q2 Overcurrent detection resistance Q4 Overcurrent detection amplification Transistor

Claims (2)

In a circuit that is inserted between a DC power supply and a load, and on / off of power supply from the DC power supply to the load is controlled by the gate potential of the semiconductor switching element.
A negative feedback circuit for connecting a rising voltage of an output voltage from a drain of a semiconductor switching element to a load via a capacitor to an anode of a reverse current blocking diode and feeding back the cathode of the diode to a gate of the semiconductor switching element. If the element is off, the emitter of the PNP transistor connected to the source and the base of the PNP transistor connected to the drain detect a potential difference, and the collector of the PNP transistor detects the potential of the anode of the reverse current blocking diode as a semiconductor. An inrush current suppression circuit comprising a potential difference detection circuit connected to have the same potential as the source of the switching element. If the overcurrent detection resistor element is connected in series with the load and the current flowing through the load is an overcurrent, the base potential of the control transistor is turned off based on the potential difference between the terminals of the overcurrent detection resistor element. The inrush current suppression circuit according to claim 1, further comprising an overcurrent circuit that drops the current to