JP2013512509A5 - - Google Patents

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JP2013512509A5
JP2013512509A5 JP2012541131A JP2012541131A JP2013512509A5 JP 2013512509 A5 JP2013512509 A5 JP 2013512509A5 JP 2012541131 A JP2012541131 A JP 2012541131A JP 2012541131 A JP2012541131 A JP 2012541131A JP 2013512509 A5 JP2013512509 A5 JP 2013512509A5
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memory
processing nodes
memory initialization
subtask
processing
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JP2012541131A
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Japanese (ja)
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JP5646644B2 (ja
JP2013512509A (ja
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Priority claimed from US12/624,626 external-priority patent/US8307198B2/en
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JP2012541131A 2009-11-24 2010-11-22 分散型多重コアメモリ初期化 Active JP5646644B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/624,626 US8307198B2 (en) 2009-11-24 2009-11-24 Distributed multi-core memory initialization
US12/624,626 2009-11-24
PCT/US2010/057561 WO2011066202A1 (en) 2009-11-24 2010-11-22 Distributed multi-core memory initialization

Publications (3)

Publication Number Publication Date
JP2013512509A JP2013512509A (ja) 2013-04-11
JP2013512509A5 true JP2013512509A5 (enExample) 2014-01-16
JP5646644B2 JP5646644B2 (ja) 2014-12-24

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JP2012541131A Active JP5646644B2 (ja) 2009-11-24 2010-11-22 分散型多重コアメモリ初期化

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US (2) US8307198B2 (enExample)
EP (1) EP2504761A1 (enExample)
JP (1) JP5646644B2 (enExample)
KR (1) KR101623892B1 (enExample)
CN (1) CN102648453B (enExample)
WO (1) WO2011066202A1 (enExample)

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