JP2013246129A - Inspection device and inspection method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate inspecting a failure of an internal signal of a semiconductor device constituted by laminating semiconductor chips.SOLUTION: An inspection device 1A includes; a measurement interposer 11 in which signal measurement probes 12 are arranged at an interval corresponding to each TSV 53 of a semiconductor device 100A; a signal measurement pad 13 which is arranged at, preferably an end of, the measurement interposer 11; and a probe 14 of a measuring instrument (not illustrated) that is connected to the signal measurement pad 13. In this case, each of the probes 12 and the signal measurement pad 13 are electrically connected each other via a signal line arranged within the measurement interposer 11. The signal measurement probes 12 are, for example, of a spring type so that when being brought into contact with the TSVs 53, the probes are retracted within the measurement interposer 11 so as to prevent the TSVs 53 from being damaged even if they are pressed.

Description

  The present invention relates to an inspection apparatus and an inspection method for a semiconductor device.

  With respect to measuring an internal signal of a semiconductor device and analyzing the defect, the internal signal of a semiconductor device in which one chip is assembled in a package can be measured via an external terminal.

On the other hand, in recent years, a semiconductor device in which a large number of chips (memory and controller) are stacked using a TSV and housed in one package has been manufactured. FIG. 9A is a cross-sectional view of such a semiconductor device. The semiconductor device 100P shown in the figure, the interposer 51, the first to fifth semiconductor chip ₅₂ 1-52 ₅ laminated on the interposer 51, first to fifth semiconductor chip ₅₂ 1-52 ₅ through the A TSV 53 that electrically connects them, an underfill 54 that seals these components, and a solder ball 55 provided on the lower surface of the interposer 51 are configured.

JP 2004-233155 A JP 2008-286657 A

  However, in such a semiconductor device, since various signals are closed between the memory and the controller, there is no externally exposed probe point and measurement of the internal waveform signal even if the failure analysis is performed after assembly. It is difficult.

As a means to solve it, first, the top layer of the chip, i.e. the TSV53 electrode of the fifth semiconductor chip 52 ₅ and exposed, it is conceivable to apply the probe 14. However, while a plurality of electrodes having a size of 20 to 50 μm are usually arranged at the same interval, the size of the probe 14 is usually as large as 800 μm and the tip size is about 200 μm. As shown to 9B, it is difficult to apply the probe 14 to a specific electrode without short-circuiting with another electrode.

  As another solution, it is conceivable to assign each signal to the terminal of each solder ball 55 and measure the waveform signal of those terminals. However, since the signal is closed between the memory and the controller, only a limited signal can be assigned.

  On the other hand, Patent Document 1 discloses disposing a decoupling capacitor for cutting high-frequency noise in a probe card for testing electrical characteristics of an electronic circuit by bringing a probe needle into contact with an electrode of a semiconductor wafer or chip. Yes. However, there is no disclosure regarding the relationship between the size of the probe needle and the size of the electrode to be inspected. There is no mention of exposing the electrode to be inspected.

  Patent Document 2 discloses that in an electronic component testing apparatus for testing an electronic component formed on a wafer, an elastically deformable needle portion and a substrate to which the needle portion is fixed are integrally formed. ing. However, there is no disclosure regarding the relationship between the size of the needle and the size of the electrode to be inspected.

  The inspection apparatus according to the present invention is an inspection apparatus for a semiconductor device in which a plurality of chips are stacked using a through electrode, and a needle that is in contact with the through electrode exposed on the top of the semiconductor device. An interposer for measurement, a signal measurement pad provided in the measurement interposer to which an electrical signal from the needle is supplied, and a measuring instrument terminal that comes into contact with the signal measurement pad. This is the gist.

  According to the inspection apparatus of the present invention, it is possible to easily inspect a defect in an internal signal of a semiconductor device configured by stacking semiconductor chips.

It is sectional drawing for demonstrating the structure of the inspection apparatus of the semiconductor device which concerns on the basic form of 1st Embodiment of this invention. It is a top view for demonstrating the structure of the test | inspection apparatus of the semiconductor device which concerns on the modification [1] of 1st Embodiment of this invention. It is sectional drawing for demonstrating the structure of the test | inspection apparatus of the semiconductor device which concerns on the modification [1] of 1st Embodiment of this invention. It is a top view for demonstrating the structure of the test | inspection apparatus of the semiconductor device which concerns on the modification [2] of 1st Embodiment of this invention. It is sectional drawing for demonstrating the structure of the test | inspection apparatus of the semiconductor device which concerns on the modification [2] of 1st Embodiment of this invention. It is sectional drawing for demonstrating the structure of the inspection apparatus of the semiconductor device which concerns on the basic form of 2nd Embodiment of this invention. It is sectional drawing for demonstrating the structure of the test | inspection apparatus of the semiconductor device which concerns on the modification [1] of 2nd Embodiment of this invention. It is a perspective view for demonstrating the structure of the test | inspection apparatus of the semiconductor device which concerns on the modification [1] of 2nd Embodiment of this invention. It is a figure for demonstrating the structure of the test | inspection apparatus of the semiconductor device which concerns on the modification [2] of 2nd Embodiment of this invention. It is sectional drawing for demonstrating the structure of the inspection apparatus of the semiconductor device which concerns on 3rd Embodiment of this invention. It is a figure which shows the example of a selector circuit. It is sectional drawing for demonstrating the prior art. It is a perspective view for demonstrating the prior art.

Hereinafter, an inspection apparatus and an inspection method for a semiconductor device of the present invention will be described in detail with reference to the drawings.
In addition, in the drawings used in the following description, in order to make the features easy to understand, there are cases where the portions that become the features are enlarged for the sake of convenience, and the dimensional ratios of the respective components are not always the same as the actual ones. Absent. In addition, the materials, dimensions, and the like exemplified in the following description are merely examples, and the present invention is not necessarily limited thereto, and can be appropriately modified and implemented without departing from the scope of the invention. .

<First Embodiment>
The semiconductor device inspection apparatus and method according to the first embodiment of the present invention employ a measurement interposer. The basic form, modification [1], and modification [2] will be described below.

(Basic form of the first embodiment)
FIG. 1 is a cross-sectional view for explaining the configuration of a semiconductor device inspection apparatus according to the basic form of the first embodiment of the present invention.
The inspection apparatus 1A shown in the figure includes a measurement interposer 11 in which the signal measuring needles 12 are arranged at intervals corresponding to the TSVs 53 of the semiconductor device 100A, and preferably an end portion of the measurement interposer 11. And a probe (measuring instrument terminal) 14 of a measuring instrument (not shown) connected to the signal measuring pad 13. Here, each needle 12 and the signal measurement pad 13 are electrically connected via a signal line arranged in the measurement interposer 11. Note that the signal measuring needle 12 is, for example, a spring type so as to be retracted into the measuring interposer 11 even when pressed, so as not to damage the TSV 53 when contacting the TSV 53.

Next, an inspection method using the inspection apparatus 1A will be described.
The measurement interposer 11 is placed so that each needle 12 abuts each corresponding TSV 53 against the upper surface of the semiconductor device 100A placed on the substrate 101 where the end of each TSV 53 is exposed. In this state, by bringing the probe 14 into contact with the signal measurement pad 13, each TSV 53 and the probe 14 are electrically connected, and waveform measurement, state measurement, or the like can be performed.

  Thus, according to the basic form of the first embodiment, since the electrical signal is acquired from each TSV 53 by the needle 12 corresponding to each TSV 53, the semiconductor device 100A can be inspected without causing a short circuit.

(Modification [1] of the first embodiment)
2A and 2B are diagrams for explaining the configuration of a semiconductor device inspection apparatus according to Modification [1] of the first embodiment of the present invention. The same components as those in the basic form shown in FIG.

  The semiconductor device inspection apparatus 1B according to the modified example [1] illustrated in FIGS. 2A and 2B further includes a frame 15 for alignment adjustment in addition to the inspection apparatus 1A according to the basic form illustrated in FIG. It has become. Specifically, the frame 15 is a hollow cylindrical member, and the cross-sectional shape perpendicular to the central axis matches the shape viewed from above the semiconductor device 100A. More precisely, the inner wall dimension of the frame 15 matches the outer wall dimension of the semiconductor device 100A. Further, the frame 15 has a protruding portion 15a protruding in the axial direction from a part of the inner wall.

  FIG. 2A is a plan view showing a state in which the frame 15 is fitted to the semiconductor device 100A. FIG. 2B is a cross-sectional view. As shown in FIG. 2B, the frame 15 is placed on the semiconductor device 100A by the projection 15a of the frame 15 engaging with the upper surface of the semiconductor device 100A.

  In this state, as shown in FIG. 2B, when the measurement interposer 11 is guided into the frame 15 and lowered along the inner wall, each needle 12 of the measurement interposer 11 is moved to each TSV 53 of the semiconductor device 100A. Can be brought into contact with each other. The outer dimensions of the measurement interposer 11 are also matched with the inner wall dimensions of the frame 15.

  According to this modification [1], in addition to the effects of the basic shape, the measurement interposer 11 can be brought into contact with the TSV 53 of the semiconductor device 100A in an easily positioned state.

(Modification [1] of the first embodiment)
3A and 3B are diagrams for explaining the configuration of a semiconductor device inspection apparatus according to Modification [2] of the first embodiment of the present invention. The same components as those in the basic form shown in FIG.

  The semiconductor device inspection apparatus 1C according to the modification [2] shown in FIGS. 3A and 3B is further provided at four corners on the upper surface of the semiconductor device 100A with respect to the inspection apparatus 1A according to the basic form shown in FIG. The pins 16a to 16d are provided. Specifically, as for each pin 16a-16d, the principal part is a column shape and the upper part predetermined length part has comprised the taper shape. In addition, the measurement interposer 11C is provided with a hole having a dimension that approximately matches the outer dimension of the main part of each pin 16a to 16d.

  FIG. 3A is a plan view of the semiconductor device 100A in which the pins 16a to 16d are erected. Therefore, as shown in the cross-sectional view of FIG. 3B, each needle 12 of the measurement interposer 11 is moved by lowering the measurement interposer 11 with respect to the semiconductor device 100A so as to penetrate each hole of the measurement interposer 11. The semiconductor device 100A can be brought into contact with each TSV 53.

  Of the pins 16a to 16d, for example, as shown in FIG. 3A, only the pin 16a is biased with respect to the other pins 16b to 16d, and the corresponding holes of the measurement interposer 11C are also correspondingly changed. Accordingly, the two-dimensional orientation of the measurement interposer 11 with respect to the semiconductor device 100A can be fixed.

According to this modification [2], in addition to the effect of the basic shape, the measurement interposer 11 can be brought into contact with the TSV 53 of the semiconductor device 100A in an easily positioned state. In addition, by biasing only the specific pin 16a, there is an advantage that the orientation of the measurement interposer 11 with respect to the semiconductor device 100A is not mistaken.
Note that the cross-sectional shape of the pin 16 is not necessarily circular, and may be square.

Second Embodiment
The second embodiment of the inspection apparatus and inspection method for a semiconductor device of the present invention is a form in which a TSV side signal measurement pad corresponding to each TSV is employed. The basic form, modification [1], and modification [2] will be described below.

(Basic form of the second embodiment)
FIG. 4 is a cross-sectional view for explaining the configuration of the semiconductor device inspection apparatus according to the basic form of the second embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same structure part as the basic form of 1st Embodiment shown in FIG. 1, and the description is abbreviate | omitted.

  The semiconductor device inspection apparatus according to the basic form of the second embodiment shown in FIG. 4 is provided to be electrically connected to the upper end portion of each TSV 53 of the semiconductor device 100B, and the upper portion thereof is exposed from the underfill 54. At least the signal measurement pads 13B are provided, and when measuring waveforms, a probe (not shown) of a measuring instrument is brought into contact with the signal measurement pads 13B.

  According to the basic form of the second embodiment, similarly to the first embodiment, there is an advantage that the signal waveform can be easily measured, and an advantage that the configuration is simplified as compared with the first embodiment. is there.

(Modification [2] of the second embodiment)
FIG. 5A and FIG. 5B are diagrams for explaining the configuration of a semiconductor device inspection apparatus according to Modification [1] of the second embodiment of the present invention. Note that the same components as those in the basic form shown in FIG.

  The semiconductor device inspection apparatus according to the modification [1] shown in FIG. 5A and FIG. 5B is provided with a signal measuring pad as in the basic type. However, as shown in FIG. It is characterized in that a signal measuring pad 13C that is entirely covered with the fill 54 is provided.

  When measuring the signal waveform, as shown in FIG. 5B, the underfill 54 around the signal measurement pad 13C is melted with a solvent or the like to expose the upper part of the pad 13C, and the probe of the measuring instrument there is used. Do by hitting.

  According to the modification [1] of the second embodiment, there is an advantage that the configuration is simplified as in the case of the basic form, and further, there is an advantage that the risk of short-circuiting during measurement can be eliminated. .

(Modification [2] of the second embodiment)
FIG. 6 is a diagram for explaining the configuration of a semiconductor device inspection apparatus according to Modification [2] of the second embodiment of the present invention. Note that the same components as those in the basic form shown in FIG.

  The semiconductor device inspection apparatus according to the modified example [2] shown in FIG. 6 is provided with the signal measurement pad 13B whose upper portion is exposed from the underfill 54, as in the basic type. A feature is that a signal measurement chip 17 is provided between the measurement pad 13 </ b> B and each TSV 53.

  According to the modification [2] of the second embodiment, there is an advantage that the configuration is simplified as in the case of the basic form, and the pressure on the chip 52 in the semiconductor device 100D can be further reduced, Furthermore, when a selector circuit described later is incorporated, there is an advantage that all signals can be taken out regardless of the number of signal measuring pads 13B.

  Note that the modification [2] can be combined with the structure of the modification [1], that is, the structure covering the entire signal measurement pad.

<Third Embodiment>
FIG. 7 is a cross-sectional view for explaining the configuration of a semiconductor device inspection apparatus according to the third embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same structure part as the basic form of 1st Embodiment shown in FIG. 1, and the description is abbreviate | omitted.

  The semiconductor device inspection apparatus 1D according to the basic form of the third embodiment shown in FIG. 7 electrically connects the connection substrate 18 disposed at the end of the upper surface of the semiconductor device 100A, the connection substrate 18 and each TSV 53. And a signal measuring pad 13 provided on the connection substrate 18 and in contact with a probe (not shown) of a measuring instrument or the like.

  According to the third embodiment, as in the first embodiment, there is an advantage that the signal waveform can be easily measured without causing a short circuit.

<Configuration for Extracting All Signals in Each Embodiment>
Finally, a configuration for extracting all signals in each of the above-described embodiments will be described. For example, this is incorporated in the signal measurement chip 17 in the modification [2] of the second embodiment, or is incorporated in the connection substrate 18 in the third embodiment.

FIG. 8 is a diagram showing an example thereof, which is a configuration that can be adopted when one signal measurement pad is provided. That is, the selector circuit 30 shown in the figure has two states of transmitting or blocking the corresponding signals [0] to [7] (bit 0 signal to bit 7 signal) to the signal measurement pad 13. a switching element _(FET) 31 0-31 ₇ can take, has three input terminals and one output terminal, an output terminal, logical product elements are respectively connected to the gate terminal of the switching element ₃₁ 0-31 ₇ 32 and ₀ to 32 _7, and a. Here, the control signals C0, C1, and C2 shown in the figure are signals that can take values of high level (1) or low level (0), respectively, and the control signals C0_b, C1_b, and C2_b are respectively This is an inverted signal of the control signals C0_t, C1_t, and C2_t. By the combination of these signals and AND gate 32 ₀ to 32 ₇ input signals, from one of the logical product element 32, a circuit that can output a high level signal. Specifically, the AND gate 32 _0, the control signal C0_b, C1_b, C2_b is entered, the logical product element 32 _1, the control signal C0_t, C1_b, C2_b are input to the AND gate 32 ₂ , the control signal C0_b, C1_t, C2_b is inputted, the aND gate 32 _3, the control signal C0_t, C1_t, C2_b is input, the control aND gate 32 _4, the control signal C0_b, C1_b, C2_t is input , the aND gate 32 _5, the control signal C0_t, C1_b, C2_t is inputted, the aND gate _{32. 6,} the control signal C0_b, C1_t, C2_t are input to the aND gate 32 _7, the control signal C0_t , C1_t, C2_t are input.

  With such a configuration, by switching the control signals C0, C1, and C2, the output of any one of the AND elements 32 becomes a high level, so that the corresponding switching element 31 is turned on, and the signal measurement pad 13 is turned on. Will reach the signal input to the switching element 31 in the on state.

  The present invention can be applied to a semiconductor device in which a large number of chips (memory and controller) are stacked using a TSV and housed in one package.

DESCRIPTION OF SYMBOLS 1 ... Inspection apparatus 11 ... Measurement interposer 12 ... Needle 13 ... Signal measurement pad 14 ... Probe 15 ... Frame 16 ... Pin 17 ... Signal measurement chip 18 ... Connection board 19 ... Bonding wire 30 ... Selector circuit 31 ... Switching element 32 ... AND element 51 ... Interposer 52 ... Semiconductor chip 53 ... TSV
100..Semiconductor device

Claims (11)

An inspection apparatus for a semiconductor device in which a plurality of chips are stacked using a through electrode,
An interposer for measurement comprising a needle that is in contact with the through electrode exposed at the top of the semiconductor device;
A signal measuring pad provided in the measuring interposer and supplied with an electrical signal from the needle;
A measuring instrument terminal abutting on the signal measuring pad;
An inspection apparatus comprising:   Further comprising a frame having a closed wall surface corresponding to the outer periphery of the semiconductor device and fitted to the semiconductor device, and the measurement interposer is guided along the inner wall toward the semiconductor device, The inspection apparatus according to claim 1, wherein a needle abuts on the electrode.   The measurement interposer further includes a plurality of pins erected on the semiconductor device, the measurement interposer having a hole corresponding to each pin and having a dimension corresponding to a cross-sectional dimension of each pin, and each hole of the measurement interposer 2. The inspection apparatus according to claim 1, wherein the needle is brought into contact with the electrode when the measurement interposer is guided toward the semiconductor device in a state of being inserted into each pin.   4. The inspection apparatus according to claim 3, wherein one of the plurality of pins is erected at an offset position on an upper surface of the semiconductor device with respect to the other pins. An inspection apparatus for a semiconductor device in which a plurality of chips are stacked using a through electrode,
A signal measuring pad incorporated in the semiconductor device in a state of being in electrical contact with the upper end of the through electrode;
A measuring instrument terminal abutting on the signal measuring pad;
An inspection apparatus comprising:   The inspection apparatus according to claim 5, wherein the signal measurement pad is exposed from the semiconductor device.   The inspection apparatus according to claim 5, wherein the signal measurement pad is embedded in the semiconductor device.   The inspection apparatus according to claim 6, further comprising a signal measurement chip electrically interposed between the through electrode and the signal measurement pad. An inspection apparatus for a semiconductor device in which a plurality of chips are stacked using a through electrode,
A connection substrate disposed on an upper surface of the semiconductor device;
A bonding wire for electrically connecting the connection substrate and the through electrode;
A signal measuring pad formed on the connection substrate and supplied with a signal from the bonding wire;
A measuring instrument terminal abutting on the signal measuring pad;
An inspection apparatus comprising: A plurality of through electrodes,
The signal measuring pad is arranged between the plurality of through electrodes and the signal measuring pad, and selects one signal from the plurality of signals from the plurality of through electrodes in accordance with a control signal, to the signal measuring pad. The inspection apparatus according to claim 1, further comprising a selector circuit to be supplied. A semiconductor device comprising: a plurality of chips; a through electrode that is electrically connected by penetrating the plurality of chips; and a signal measurement pad that is electrically connected to and embedded in an upper end of the through electrode. An inspection method,
Preparing the semiconductor device;
Melting the upper surface of the semiconductor device to expose the signal measuring pad;
Bringing a detector terminal into contact with the signal measuring pad;
Inspecting the signal input to the detector;
The inspection method characterized by including.

Images