JP2013209226A - Method of manufacturing semiconductor bulk crystal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor bulk crystal in which a crystal crack at processing molding treatment of a compound semiconductor single crystal layer formed by an epitaxial growth method is prevented, and a yield is improved.SOLUTION: A method of manufacturing a semiconductor bulk crystal manufactures the semiconductor bulk crystal such that a compound semiconductor single crystal layer 2 is made to grow epitaxially on a groundwork substrate 1, wherein a crystalline complex (a crystal that is in such a state that the groundwork substrate 1 and the compound semiconductor single crystal layer 2 are combined) is prepared so that a cavity 3 is formed in a vicinity of a boundary of the groundwork substrate 1 and the compound semiconductor single crystal layer 2, the crystalline complex is heated at a temperature of at least 1,000°C, and thereby the groundwork substrate 1 and the compound semiconductor single crystal layer 2 can be separated without causing a crystal crack.

Description

  The present invention relates to a method for manufacturing a semiconductor bulk crystal, and more particularly to a method for manufacturing a semiconductor bulk crystal by epitaxial growth.

  An epitaxial growth method using a semiconductor crystal as a base substrate and growing a compound semiconductor single crystal layer on the base substrate is widely used as a method for manufacturing a semiconductor bulk crystal. For example, a group III represented by gallium nitride (GaN) is used. Studies are also progressing as a manufacturing technique of nitride semiconductor crystals. Group III nitride semiconductor crystals have been put into practical use as light emitting elements on the relatively short wavelength side such as light emitting diodes and semiconductor lasers such as ultraviolet and blue, etc., but the same type of material, that is, group III nitride semiconductor crystals are used as substrates. Epitaxial growth methods such as halide vapor phase epitaxy (HVPE) and metal organic chemical vapor deposition (MOCVD) are actively researched as techniques for producing Group III nitride semiconductor crystals that can be used as substrates. Has been.

  Various problems have been reported with respect to a method for producing a semiconductor bulk crystal using an epitaxial growth method, and a number of means for solving it have been reported. For example, when a group III nitride semiconductor crystal layer is epitaxially grown using a base substrate such as sapphire or silicon carbide (heteroepitaxial growth), distortion occurs near the interface between the base substrate and the formed group III nitride semiconductor crystal layer. There have been reports of problems such as cracks occurring and crystal warping when the underlying substrate is removed. For example, a method of forming a cavity between the base substrate and the crystal layer (see Patent Document 1), a method of heat-treating the crystal at a temperature of 1150 ° C. or higher after the crystal growth (so-called annealing treatment), etc. are proposed. (See Patent Document 2).

JP 2000-106455 A JP 2003-277195 A

In order to commercialize a compound semiconductor single crystal layer formed by an epitaxial growth method as a substrate for an element, for example, a molding process for slicing the crystal or polishing the surface is necessary. In many cases, crystal cracks (cracks) sometimes occur, and this is a cause of yield reduction in the production of substrates and the like.
An object of the present invention is to prevent crystal cracks (cracks) that occur during molding processing and to improve the yield in the production of semiconductor bulk crystals.

  As a result of intensive studies to solve the above problems, the inventors of the present invention, in a semiconductor bulk crystal manufacturing method for manufacturing a semiconductor bulk crystal by epitaxially growing a compound semiconductor single crystal layer on a base substrate, A crystal composite (a crystal in which the base substrate and the compound semiconductor single crystal layer are integrated) is prepared so that a cavity is formed in the vicinity of the boundary of the compound semiconductor single crystal layer, and the crystal composite is heated to 1000 ° C. It has been found that by heating at the above temperature, the base substrate and the compound semiconductor single crystal layer can be separated without causing crystal cracks (cracks), and the present invention has been completed.

That is, the present invention is as follows.
(1) A crystal composite including a base substrate and a compound semiconductor single crystal layer formed on a main surface of the base substrate and further having a cavity near a boundary between the base substrate and the compound semiconductor single crystal layer is prepared. A semiconductor bulk crystal comprising: a preparatory step; and a separation step of heating the crystal complex at a temperature of 1000 ° C. or higher to separate the base substrate and the compound semiconductor single crystal layer to obtain a semiconductor bulk crystal Manufacturing method.
(2) The method for producing a semiconductor bulk crystal according to (1), wherein the base substrate and the compound semiconductor single crystal layer satisfy a condition of a lattice mismatch degree represented by the following formula.
2 | a ₁ −a ₂ | / [a ₁ + a ₂ ] ≦ 1 × 10 ⁻³
(Wherein a ₁ is the lattice constant of the underlying substrate and the lattice constant of the crystal axis perpendicular to the direction of epitaxial growth, and a ₂ is the lattice constant of the compound semiconductor single crystal layer and orthogonal to the direction of epitaxial growth. Represents the lattice constant of the axis.)
(3) The method for producing a semiconductor bulk crystal according to (1) or (2), wherein the separation step is a step of heating in the presence of an oxygen source.
(4) The method for producing a semiconductor bulk crystal according to (3), wherein the separation step is a step of heating in the presence of water (H ₂ O).
(5) The method for producing a semiconductor bulk crystal according to any one of (1) to (4), wherein the thickness of the base substrate is 100 μm or more and 1 mm or less.
(6) The contact area between the base substrate and the compound semiconductor single crystal layer in the crystal composite is 10% or more and 90% or less of the total area of the main surface of the base substrate. The manufacturing method of the semiconductor bulk crystal in any one.
(7) The method for producing a semiconductor bulk crystal according to any one of (1) to (6), wherein the compound semiconductor single crystal layer is formed by a halide vapor phase epitaxy (HVPE method).
(8) The method for producing a semiconductor bulk crystal according to any one of (1) to (7), wherein the base substrate and the compound semiconductor single crystal layer are group III nitride semiconductor crystals.
(9) The method for producing a semiconductor bulk crystal according to (8), wherein a main surface of the base substrate is a C plane.

  ADVANTAGE OF THE INVENTION According to this invention, the crack (crack) at the time of the shaping | molding process of the compound semiconductor single crystal layer formed by the epitaxial growth method can be prevented, and the yield in manufacture of a semiconductor bulk crystal can be improved.

It is a conceptual diagram showing the crystal composite_body | complex which concerns on this invention. It is a conceptual diagram of the apparatus for forming a compound semiconductor single crystal layer. It is a conceptual diagram showing the process sequence for forming an unevenness | corrugation on the main surface of a base substrate. It is a conceptual diagram showing the apparatus for implementing the isolation | separation process which concerns on this invention.

In describing the details of the method for producing a semiconductor bulk crystal of the present invention, embodiments and specific examples of the group III nitride semiconductor crystal will be described. However, the present invention is limited to the following contents without departing from the spirit of the present invention. It can be implemented with appropriate modifications.
Furthermore, the numerical range expressed using “to” in the present specification means a range including numerical values described before and after “to” as a lower limit value and an upper limit value.

[Method for Producing Semiconductor Bulk Crystal of the Present Invention]
The method for producing a semiconductor bulk crystal of the present invention (hereinafter sometimes abbreviated as “manufacturing method of the present invention”) includes “a base substrate and a compound semiconductor single crystal layer formed on the main surface of the base substrate”. Furthermore, a preparatory step for preparing a crystal composite having a cavity near the boundary between the base substrate and the compound semiconductor single crystal layer (hereinafter sometimes referred to as “preparation step”) ”, and“ the crystal composite at 1000 ° C. or higher ” And a separation step of separating the base substrate and the compound semiconductor single crystal layer to obtain a semiconductor bulk crystal (hereinafter sometimes abbreviated as “separation step”) ”. .
In the process of manufacturing a semiconductor bulk crystal in which a compound semiconductor single crystal layer (growth layer) is epitaxially grown (crystal growth) on a base substrate, the present inventors combine the following methods (a) and (b): It has been found that the base substrate and the compound semiconductor single crystal layer can be separated naturally without generating crystal cracks (cracks) or can be easily separated by applying a slight force.
(A) The shape of the base substrate, crystal growth conditions, etc. are devised to form a void near the boundary between the base substrate and the growth layer.
(B) The crystal composite in which the base substrate and the compound semiconductor single crystal layer are integrated is subjected to a heat treatment (so-called annealing treatment) at a temperature of 1000 ° C. or higher.
Both the methods (a) and (b) are effective in reducing the distortion generated near the interface between the base substrate and the growth layer. For example, the method (a) has a void acting as a buffer region. Therefore, it is considered that the method (b) has an action of releasing the generated distortion. Therefore, in the crystal composite (the crystal in which the base substrate and the compound semiconductor single crystal layer are integrated) subjected to either of the methods (a) or (b), the strain is originally relaxed. That is, it is usually difficult to think that the base substrate and the growth layer are naturally separated. In particular, in homoepitaxial growth in which the compound semiconductor single crystal layer to be formed is the same type as that of the base substrate, the strain generated is relatively small in the first place. It is thought that it has been sufficiently relaxed. However, the present inventors have found the fact that by combining the methods (a) and (b), the base substrate and the growth layer are naturally separated from each other with a void as a boundary. Even if the method of either (a) or (b) is performed, it can be said that the strain still remains between the base substrate and the growth layer.

<Preparation step of preparing a crystal composite including a base substrate and a compound semiconductor single crystal layer formed on the main surface of the base substrate and further having a cavity near the boundary between the base substrate and the compound semiconductor single crystal layer>
The manufacturing method of the present invention is “a crystal composite including a base substrate and a compound semiconductor single crystal layer formed on the main surface of the base substrate, and further having a cavity near the boundary between the base substrate and the compound semiconductor single crystal layer ( Hereinafter, it is characterized by including a preparatory step for preparing “a crystal complex according to the present invention” (hereinafter, abbreviated as “a preparatory step according to the present invention”) ”.
“Crystal complex” means a crystal in which a compound semiconductor single crystal layer is formed on a main surface of a base substrate and the base substrate and the compound semiconductor single crystal layer are integrated, and the present invention. Is characterized in that it has a cavity in the vicinity of the boundary between the base substrate and the compound semiconductor single crystal layer. Specifically, “having a cavity near the boundary between the base substrate and the compound semiconductor single crystal layer” specifically means that the cavity is located at a position where the shortest distance between the boundary surface between the base substrate and the compound semiconductor single crystal layer and the cavity is within 100 μm. It means to exist.
“Preparing a crystal composite” includes preparing a crystal composite by forming a compound semiconductor single crystal layer on a main surface of a base substrate, and obtaining such a crystal composite. To do. In the present invention, the “main surface” means the widest surface among the surfaces on the base substrate or the compound semiconductor single crystal layer.

The crystal composite according to the present invention includes a base substrate and a compound semiconductor single crystal layer formed on the main surface of the base substrate, and further has a cavity near the boundary between the base substrate and the compound semiconductor single crystal layer. For example, the other embodiments are not particularly limited, but preferred embodiments of the crystal composite according to the present invention will be described below.
If the cavity in the crystal composite exists in the vicinity of the boundary between the base substrate and the compound semiconductor single crystal layer, that is, at the position where the shortest distance between the boundary surface of the base substrate and the compound semiconductor single crystal layer and the cavity is within 100 μm, Although the specific position is not particularly limited, as shown in 1a, 1b, or 1c of FIG. 1 (in FIG. 1, 1 represents a base substrate, 2 represents a compound semiconductor single crystal layer, and 3 represents a cavity). It is preferably present at a position in contact with both the base substrate and the compound semiconductor single crystal layer. The presence of the cavity at a position in contact with both the base substrate and the compound semiconductor single crystal layer tends to facilitate separation near the boundary between the base substrate and the compound semiconductor single crystal layer.
The shape, number, distribution, etc. of the cavities are not particularly limited, but from the viewpoint of easy separation of the base substrate and the compound semiconductor single crystal layer, the cavities are widely distributed near the boundary between the base substrate and the compound semiconductor single crystal layer. Preferably it is. Specifically, as shown in FIG. 1, a configuration in which a plurality of rectangular parallelepiped cavities are arranged in parallel with the boundary surface between the base substrate and the compound semiconductor single crystal layer and also with the cavities parallel to each other can be mentioned. . Note that the orientation of the long side of the rectangular parallelepiped (7 in FIG. 1) is the M plane or the A plane ((11-20) plane and a plane that is crystal geometrically equivalent to this plane in the case of a group III nitride semiconductor crystal. The width of the cavity (4 in FIG. 1) is usually 0.1 μm or more, preferably 0.5 μm or more, more preferably 1 μm or more, usually 1 mm or less, preferably 500 μm or less, more The height of the cavity (5 in FIG. 1) is usually 0.1 μm or more, preferably 1 μm or more, more preferably 2 μm or more, and usually 1 mm or less, preferably 500 μm or less, more preferably The width of the non-cavity part (6 in FIG. 1) is usually 0.1 μm or more, preferably 1 μm or more, more preferably 2 μm or more, and usually 13 mm or less, preferably 2 mm or less. Preferably it is 1mm or less. If it is the crystalline complex as described above, thereby separating the base substrate and the compound semiconductor single crystal layer spontaneously or can be easily separated.
The thickness (maximum thickness) of the base substrate in the crystal composite is usually 100 μm or more, preferably 200 μm or more, more preferably 300 μm or more, and usually 1 mm or less, preferably 800 μm or less, more preferably 600 μm or less.
The growth thickness (maximum thickness) of the compound semiconductor single crystal layer in the crystal complex is usually 30 μm or more, preferably 100 μm or more, more preferably 200 μm or more, and usually 50,000 μm or less, preferably 25000 μm or less, more preferably 10,000 μm or less. It is. The effect of this invention can be utilized as it is in the said range.
In addition, as described above, it is preferable that the cavity in the crystal composite exists at a position in contact with both the base substrate and the compound semiconductor single crystal layer. In such a case, the contact area between the base substrate and the compound semiconductor single crystal layer is Is preferably 10% or more, more preferably 20% or more of the total area of the main surface of the base substrate (the area of the projection surface obtained by projecting the main surface of the base substrate in the growth direction of the compound semiconductor single crystal layer). Preferably, it is 30% or more. The contact area between the base substrate and the compound semiconductor single crystal layer is preferably 95% or less of the total area of the main surface of the crystal composite, more preferably 92% or less, and 90% or less. Is more preferable. Within the above range, the base substrate and the formed compound semiconductor single crystal layer can be separated naturally or more easily. It should be noted that the growth direction is a direction mainly growing in the growth of the entire crystal and corresponds to the thickness direction of the crystal.

  The kind of compound semiconductor single crystal layer, that is, the kind of semiconductor bulk crystal produced by the production method of the present invention is not particularly limited, but is particularly suitable for the production of a group III nitride semiconductor crystal. In addition, the specific type of the group III nitride semiconductor crystal is not particularly limited. For example, in addition to a nitride composed of one group III element such as GaN, AlN, and InN, two or more types such as GaInN and GaAlN are used. A mixed crystal composed of a group III element is exemplified.

The type of the base substrate according to the present invention is not particularly limited, but it is preferable to select the base substrate so that the base substrate and the compound semiconductor single crystal layer satisfy the condition of the degree of lattice mismatch represented by the following formula. The degree of lattice mismatch means a theoretical value calculated from the lattice constant of a complete crystal.
2 | a ₁ −a ₂ | / [a ₁ + a ₂ ] ≦ 1 × 10 ⁻³
(Wherein a ₁ is the lattice constant of the underlying substrate and the lattice constant of the crystal axis perpendicular to the growth direction of the compound semiconductor single crystal layer, and a ₂ is the lattice constant of the compound semiconductor single crystal layer and the compound (Represents the lattice constant of the crystal axis perpendicular to the growth direction of the semiconductor single crystal layer.)
The degree of lattice mismatch between the base substrate and the compound semiconductor single crystal layer to be formed is more preferably 5 × 10 ⁻⁴ or less, further preferably 1 × 10 ⁻⁴ or less, and further preferably 1 × 10 ⁻⁵ or less. It is particularly preferred. Within the above range, a high-quality semiconductor bulk crystal having a low dislocation density or the like can be produced.
For example, when the type of the compound semiconductor single crystal layer is a group III nitride semiconductor crystal, the base substrate includes metal oxides such as sapphire, ZnO, and BeO, silicon-containing materials such as SiC and Si, and GaN, InGaN, and AlGaN. Group III nitride semiconductor crystals, etc., but as the base substrate that satisfies the above-mentioned lattice mismatch degree, a group III nitride semiconductor crystal having the same composition as the group III nitride semiconductor crystal to be grown is preferable. I can say that.
The base substrate may be a single crystal substrate, or may be a so-called “epi substrate” in which an epitaxial film is formed on a single crystal substrate or a laminate. However, a single crystal substrate is preferable from the viewpoint of easy separation of the base substrate and the compound semiconductor single crystal layer.

The crystal plane (index plane) of the main surface of the base substrate is not particularly limited. For example, when a group III nitride semiconductor crystal is used as the base substrate, non-polarity such as C plane (polar plane), A plane, M plane, etc. Any of a semipolar surface such as a surface or an S surface may be used. The “C plane” refers to the (0001) plane and the (000-1) plane in the group III nitride semiconductor crystal having a hexagonal crystal structure (Wurtzite crystal structure), and the “A plane” refers to (2-1 -10) A plane and a plane geometrically equivalent to such plane, and "M plane" means a (10-10) plane and a plane geometrically equivalent to such plane. Further, the “semipolar plane such as S plane” means a plane that is inclined with respect to the C plane, that is, the (0001) plane, and the abundance ratio of the group III element and the nitrogen element is not 1: 1. Specifically, (10-11) plane, (10-1-1) plane, (20-21) plane, (20-2-1) plane, (10-12) plane, (10-1-2) A surface etc. can be mentioned. The crystal plane includes a plane within a range having an off angle of 10 ° or less from each crystal axis measured with an accuracy of ± 0.01 ° or less, preferably an off angle of 5 ° or less. More preferably, it is within 3 °.
The crystal plane of the main surface of the base substrate is preferably adopted as appropriate in consideration of the crystal plane of the final product, for example. When manufacturing a group III nitride semiconductor crystal having a C-plane as a main surface, it is efficient to employ a group III nitride semiconductor crystal having a C-plane as a main surface as a base substrate. Further, when a group III nitride semiconductor crystal having an M plane as a main surface is manufactured, it is efficient to employ a group III nitride semiconductor crystal having an M plane as a main surface as a base substrate.

  The preparation step according to the present invention includes forming the compound semiconductor single crystal layer on the main surface of the base substrate as described above to produce the crystal composite according to the present invention. For example, (A) a method of forming irregularities on the main surface of the base substrate and epitaxially growing a compound semiconductor single crystal layer on the main surface; and (B) a main surface of the base substrate. Examples include a method of removing a mask after forming a mask and epitaxially growing a compound semiconductor single crystal layer on the main surface. Hereinafter, the details of the methods (A) and (B) will be described.

(A) A method of forming irregularities on the main surface of the base substrate and epitaxially growing a compound semiconductor single crystal layer on the main surface. “Forming irregularities on the main surface of the base substrate” specifically refers to the base substrate. Is processed into a structure as shown in FIG. 3N. The irregularities are cavities or structures that trigger the cavities when the compound semiconductor single crystal layer is epitaxially grown to produce a crystal composite, and the irregularities should be appropriately set according to the intended shape of the cavities.
Examples of the method for forming irregularities on the main surface of the base substrate include a method of forming a mask pattern on the base substrate by a known photolithography method, and etching an opening without a mask to form a groove. Specifically, (1) mask formation → (2) photoresist application → (3) exposure → (4) development → (5) mask removal and photoresist removal → (6) etching → (7) mask removal procedure However, the present invention is not limited to such an embodiment, and may be changed by appropriately adopting a known method according to the purpose. A specific method for epitaxially growing the compound semiconductor single crystal layer on the main surface of the base substrate will be described later.

  The method for forming the mask is not particularly limited in the production method of the present invention, and a known method can be adopted as appropriate. Can be mentioned. The type of the mask material is not particularly limited, and specific examples include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, tantalum oxide, zirconium oxide, and hafnium oxide. Further, the thickness of the mask to be formed is not particularly limited, but is usually 1 nm or more, preferably 5 nm or more, more preferably 10 nm or more, and usually 10 μm or less, preferably 8 μm or less, more preferably 5 μm or less.

  It is preferable to apply hexamethyldisilazane as a primer on the formed mask. By applying the primer, the hydrophobicity of the mask can be increased and the adhesion of the resist can be increased.

The kind of the photoresist used in the production method of the present invention is not particularly limited, and a known one or a commercially available one can be appropriately adopted and used. In addition, the shape of the photomask to be used should be adopted in consideration of the shape of the target base substrate (the shape of the concave and convex portions), and specifically, stripes, lattices, squares, dots, holes And the like. Further, the exposure, development, photoresist removal method and the like are not particularly limited, and can be appropriately performed according to the type of the photoresist.
For example, when a positive type photoresist is used, a portion of the photoresist exposed through the photomask is dissolved by development, and a mask formed in advance appears. Subsequently, with the use of buffered hydrofluoric acid (NH ₄ HF ₂ ), the mask of the portion where the photoresist pattern has been removed (exposed portion) is removed by wet etching, and the photoresist at the portion not exposed (unexposed portion) is removed. Dissolve with acetone. Thereby, a mask can be formed in an arbitrary part of the main surface.

The edging method in the production method of the present invention is not particularly limited, and a known method can be adopted as appropriate. However, it is particularly preferable to use a reactive ion etching (RIE) apparatus. Although the etching gas is not particularly limited, a gas containing a halogen element such as chlorine or fluorine is preferable. Specifically, chlorine gas (Cl ₂ ), silicon tetrachloride (SiCl ₄ ), boron trichloride (BCl ₃ ), hydrogen bromide (HBr), sulfur hexafluoride (SF ₆ ), trifluoromethane (CHF ₃ ), tetrafluoromethane (CF ₄ ) and the like are more preferably used alone or in combination.

  In the manufacturing method of the present invention, it is preferable to form a mask on the concave portion of the base substrate, that is, the bottom surface or side wall of the groove. By forming the mask on the bottom and side walls of the groove, crystal growth from the bottom and side walls of the groove can be suppressed, and a cavity can be easily formed in the crystal composite. Examples of the method for forming the mask film only on the bottom and side walls of the groove include a lift-off method and a self-alignment method using a photoresist.

(B) A method of removing a mask after forming a mask on the main surface of the base substrate and epitaxially growing a compound semiconductor single crystal layer on the main surface. “Forming a mask on the main surface of the base substrate” For example, this means that a mask pattern is formed on the base substrate by a known photolithography method as described above. In such a method, the mask portion is a portion that becomes a cavity of the crystal composite, and the shape of the photomask, the thickness of the mask, and the like should be appropriately set according to the shape of the target cavity. “Removing the mask” means that a cavity is formed in the portion where the mask is removed. A specific method for removing the mask should be appropriately selected according to the type and state of the mask, and examples thereof include wet etching. A specific method for epitaxially growing the compound semiconductor single crystal layer on the main surface of the base substrate will be described later.

  Further, as a means for forming a cavity, a mask is formed on the base substrate, a second nitride semiconductor is laterally grown on the mask from the exposed portion of the base substrate, and the mask is not completely covered, and dry. For example, a method of forming a space below the second nitride semiconductor grown in the lateral direction by removing the mask by etching or wet etching.

In the production method of the present invention, the specific growth method when forming the compound semiconductor single crystal layer on the main surface of the base substrate is not particularly limited, and halide vapor phase epitaxy (HVPE), organometallic chemical vapor deposition (MOCVD method), organometallic chloride vapor phase growth method (MOC method), sublimation method, melt growth, high-pressure solution method, flux method, heat treatment method, etc. . Among these, it is preferable to employ the HVPE method.
Further, the compound semiconductor single crystal layer formed over the main surface of the base substrate is not limited to one type, and a plurality of single crystal layers may be formed. Further, the growth method for forming the single crystal layer is not limited to one type, and a plurality of types of growth methods may be appropriately combined. Therefore, for example, a plurality of single crystal layers can be formed continuously using one type of growth method, a single type of single crystal layer can be formed intermittently using a plurality of types of growth methods, or a plurality of single crystal layers can be formed. A plurality of single crystal layers may be intermittently formed using various kinds of growth methods. Note that the use of a plurality of types of growth methods includes, for example, a formation method in which a single crystal layer is formed using the MOCVD method and then a new single crystal layer is formed thereon using the HVPE method. In the production method of the present invention, it is preferable to epitaxially grow the target compound semiconductor single crystal directly on the base substrate. That is, it is preferable that the base substrate and the compound semiconductor single crystal are in direct contact with each other across the cavity.
Hereinafter, in describing the details of the growth process according to the present invention, the configuration of the manufacturing apparatus and specific examples of growth conditions in the case of manufacturing a GaN crystal by the HVPE method will be described, but the present invention is limited to the following modes. is not.

  As a manufacturing apparatus used for the HVPE method, an apparatus having a configuration as shown in the conceptual diagram of FIG. Such a manufacturing apparatus includes a reactor (reaction vessel) 100, a susceptor 107 for placing a base substrate, a reservoir 105 for storing a group III element source, an introduction pipes 101 to 104 for introducing gas into the reactor, and for exhausting. The exhaust pipe 108 and the heater 106 for heating the reactor are provided. In addition, you may change suitably the number of introduction pipes according to the kind of gas to be used.

  Quartz, sintered boron nitride, stainless steel and the like are used as the material of the reactor, and quartz is particularly preferable. The material of the susceptor is preferably carbon, and in particular, the one whose surface is coated with SiC is preferable. The shape of the susceptor is not particularly limited as long as the base substrate can be placed, but it is preferable that the structure does not exist in the vicinity of the crystal growth surface during crystal growth. If there is a structure that can grow near the crystal growth surface, there is a possibility that a polycrystal will adhere to the crystal growth surface, and HCl gas will be generated as a product to adversely affect the crystal to be grown. is there. The contact surface between the base substrate and the susceptor is preferably separated from the main surface (crystal growth surface) of the base substrate by 1 mm or more, more preferably 3 mm or more, and further preferably 5 mm or more.

Examples of the gas species used for crystal growth include GaCl as a gallium source (group III element source), NH _{3 as} a nitrogen source, carrier gas, separate gas, dopant, and the like. GaCl serving as a gallium source can be generated and supplied by, for example, putting Ga in the reservoir 105 and supplying a gas that reacts with Ga, such as HCl, from the introduction tube 103. In addition to Ga, Al, In, or the like can be placed in the reservoir 105 depending on the purpose. A carrier gas may be supplied from the introduction pipe 103 together with HCl, and examples of the carrier gas include H ₂ , N ₂ , He, Ne, Ar, or a mixed gas thereof. NH _{3 as} a nitrogen source, carrier gas, separate gas, dopant, and the like can be supplied from the introduction pipes 101, 102, and 104. As the separate gas, H ₂ , N ₂ , He, Ne, Ar, or a mixture thereof Examples of the dopant gas include O ₂ , H ₂ O, SiH ₄ , SiH ₂ Cl ₂ , and H ₂ S.

  The exhaust pipe 108 may exist at any position on the top surface, bottom surface, and side surface of the inner wall of the reactor 100, but is preferably located below the crystal growth end from the viewpoint of dust removal, and as shown in FIG. It is more preferable that it is installed.

The temperature condition (temperature in the reactor) of the growth step according to the present invention is usually 950 ° C. or higher, preferably 970 ° C. or higher, more preferably 980 ° C. or higher, usually 1200 ° C. or lower, preferably 1100 ° C. or lower, more preferably Is 1050 ° C. or lower. Moreover, it is preferable to suppress the temperature drop during crystal growth within 60 ° C., more preferably within 40 ° C., and further preferably within 20 ° C.
The pressure condition (pressure in the reactor) of the growth step according to the present invention is usually 10 kPa or more, preferably 30 kPa or more, more preferably 50 kPa or more, and usually 200 kPa or less, preferably 150 kPa or less, more preferably 120 kPa or less. .

  The growth process according to the present invention is preferably performed while rotating the base substrate. Although the rotational speed of a base substrate is not specifically limited, It is preferable that it is 1-50 rpm, and it is more preferable that it is 5-20 rpm.

  The crystal growth rate in the growth step according to the present invention is not particularly limited, but in the case of a GaN crystal, it is usually 5 μm / h or more, preferably 50 μm / h, more preferably 100 μm / h or more, and usually 500 μm / h or less. The growth rate can be controlled by appropriately setting the type, flow rate, supply port-crystal growth end distance, and the like of the carrier gas.

The carrier concentration of the compound semiconductor single crystal layer formed by the growth process according to the present invention is not particularly limited, but in the case of a GaN crystal, it is usually 1 × 10 ¹³ cm ⁻³ or more, preferably 1 × 10 ¹⁴ cm ⁻³ or more, More preferably, it is 1 × 10 ¹⁷ cm ⁻³ or more, usually 1 × 10 ²¹ cm ⁻³ or less, preferably 1 × 10 ²⁰ cm ⁻³ or less, more preferably 5 × 10 ¹⁹ cm ⁻³ or less.

<Separation step of heating the crystal composite at a temperature of 1000 ° C. or higher to separate the base substrate and the compound semiconductor single crystal layer to obtain a semiconductor bulk crystal>
The production method of the present invention includes a “separation step of heating a crystal complex at a temperature of 1000 ° C. or more to separate a base substrate and a compound semiconductor single crystal layer to obtain a semiconductor bulk crystal”.
“Separation of the base substrate and the compound semiconductor single crystal layer” means that the base substrate and the formed compound semiconductor single crystal layer are naturally separated through such a separation process, and also the natural separation. Even if it is not done, it means that it can be easily separated by applying a slight force without slicing or the like.

In the separation step according to the present invention, the crystal complex is heated at a temperature of 1000 ° C. or higher. The heating temperature is preferably 1100 ° C. or higher, more preferably 1300 ° C. or higher, and usually 2500 ° C. or lower, preferably 2220 ° C. Hereinafter, it is more preferably 1600 ° C. or lower, and further preferably 1400 ° C. or lower. If the temperature is too low, the separation becomes difficult, and if it is too high, the compound single crystal layer tends to decompose, and if it is in the above range, the base substrate and the compound semiconductor single crystal layer can be easily separated. The decomposition of the compound single crystal layer can be suppressed.

  The heating time in the separation step according to the present invention is not particularly limited, and should be appropriately set according to the heating temperature. When the heating temperature is high, the heating time is short, and when the heating temperature is low, the heating time is Is to lengthen. Specifically, it is usually 1 second or longer, preferably 1 minute or longer, more preferably 10 minutes or longer, more preferably 30 minutes or longer, particularly preferably 1 hour or longer, usually 200 hours or shorter, preferably 100 hours or shorter, more Preferably it is 24 hours or less. For example, when the heating temperature is in the range of 1275 to 1375 ° C., the heating time is preferably 1 second to 24 hours, and more preferably 1.0 to 10 hours. Moreover, when heating temperature is in the range of 1150-1250 degreeC, it is preferable that it is 1.0 to 200 hours, and it is more preferable that it is 24 to 100 hours. Within the above range, the base substrate and the formed compound semiconductor single crystal layer can be separated naturally or more easily.

The separation step according to the present invention is not particularly limited as long as the crystal complex is heated at a temperature of 1000 ° C. or higher, but the compound semiconductor single crystal layer is a group III nitride semiconductor crystal layer. In this case, it is preferable that heating is performed in an atmosphere of ammonia (NH ₃ ), nitrogen (N ₂ ), or a mixed gas thereof. The NH ₃ concentration or N ₂ concentration in the atmosphere is not particularly limited, but the NH ₃ concentration is usually 0.5% or more, preferably 1% or more, more preferably 5% or more, and usually 50% or less, preferably 25 % Or less, more preferably 10% or less. Further, the N ₂ concentration is usually 50% or more, preferably 75% or more, more preferably 90% or more, and usually 99.5% or less, preferably 99% or less, more preferably 95% or less. Within the above range, excessive oxidation of the group III nitride semiconductor crystal can be prevented.

The separation step according to the present invention may be performed in a closed system or a distribution system, but is preferably performed in a distribution system. When the compound semiconductor single crystal layer is a group III nitride semiconductor crystal layer, the flow rate (in the case of a mixed gas of NH ₃ and N ₂ ) is usually 50 ml / min or more, preferably 150 ml / min or more, more preferably 180 ml. / Min or more, usually 500 ml / min or less, preferably 300 ml / min or less, more preferably 250 ml / min or less. Also, the pressure condition is not particularly limited, and is usually 1 MPa or more, preferably 10 MPa or more, more preferably 5 GPa or more, and usually 10 GPa or less.

The rate of temperature drop after heating in the separation step according to the present invention is not particularly limited, but it is usually usually 100 ° C./hour or more, preferably 1000 ° C./hour or more, more preferably 3000 ° C./hour or more. For example, it can be rapidly cooled at a rate of 1 × 10 ⁶ ° C./hour or more using ice water or the like. The rate of temperature increase or the rate of temperature decrease may be kept constant or may be changed with time.

The separation step according to the present invention is preferably performed in the presence of an oxygen source in addition to the aforementioned NH ₃ and N ₂ . By being performed in the presence of an oxygen source, a surface modified layer such as an oxide, hydroxide, or oxyhydroxide is formed on the surface of the compound semiconductor single crystal layer, and the crystal becomes fragile. It is considered that the single crystal layer is easily separated. The presence of an oxygen source includes a method in which a compound containing an oxygen atom is contained in the atmosphere, and a method of generating a compound containing an oxygen atom in the atmosphere. As a method for generating a compound containing an oxygen atom in the atmosphere, for example, a reaction vessel made of a metal oxide such as silica (SiO ₂ ), alumina (Al ₂ O ₃ ), zirconia (ZrO ₂ ), titania (TiO ₂ ), etc. And a method of generating water molecules by reacting the inner wall of the reaction vessel with ammonia. Examples of the compound containing an oxygen atom include oxygen (O ₂ ), water (H ₂ O), carbon monoxide (CO), carbon dioxide (CO ₂ ), and the like. Of these, it is more preferable to use alumina as an oxygen source.

The apparatus for carrying out the separation step according to the present invention is not particularly limited as long as it can be heated to a temperature of 1000 ° C. or higher. For example, a tubular electric furnace as shown in the conceptual diagram of FIG. 4 is preferable. Can be mentioned. This electric furnace includes an alumina reaction tube (Al ₂ O ₃ 99.7%) 200, a heater 202 for heating the inside of the reaction tube, a gas introduction tube 203, and a gas exhaust tube 204. A crystal 201 in which a base substrate and a compound semiconductor single crystal layer are integrated can be installed in an alumina reaction tube 200 and heated while introducing an atmospheric gas from a gas introduction tube 203 at a predetermined flow rate.

  As described above, a surface-modified layer such as an oxide, hydroxide, or oxyhydroxide is formed on the surface of the compound semiconductor single crystal layer by performing the separation step according to the present invention in the presence of an oxygen source. It will be. In this case, it is preferable to include a surface-modified layer removal step (hereinafter sometimes abbreviated as “surface-modified layer removal step”) for removing the surface-modified layer. Examples of the surface alteration layer removing step include a method of immersing the compound semiconductor single crystal in an acid solution and a mechanical polishing method, but a method of immersing the compound semiconductor single crystal in the acid solution from the viewpoint of efficiency and simplicity. preferable. Although the kind of acid solution to be used is not specifically limited, hydrochloric acid, sulfuric acid, and nitric acid are mentioned, and nitric acid is particularly preferable. The concentration of the acid solution is not particularly limited, but is usually 10% or more, preferably 30% or more. By using a high-concentration acid solution or mixed acid solution, film removal becomes efficient. Further, the immersion in the acid solution is preferably performed while stirring using a stirrer, an ultrasonic vibration device, or the like, and more preferably performed while heating at a temperature of 60 ° C. or higher, preferably 80 ° C. or higher.

  In addition to the steps described above, the production method of the present invention may include a slicing step for slicing the compound semiconductor single crystal to a desired size, a surface polishing step for polishing the surface, and the like. Specific examples of the slicing step include wire slicing and inner peripheral edge slicing, and the surface polishing step includes, for example, an operation of polishing the surface using abrasive grains such as diamond abrasive grains, CMP (chemical mechanical polishing). An operation of etching a damaged layer by RIE after mechanical polishing can be mentioned.

  Hereinafter, as a method for producing a semiconductor bulk crystal of the present invention, the characteristics of the present invention will be described more specifically with reference to examples in the case of producing a group III nitride semiconductor crystal (GaN crystal). The present invention is not limited to the following contents as long as they do not deviate from the above, and can be implemented with appropriate modifications.

<Preparation process for preparing a crystal composite>
The preparation steps described below will be described with reference to FIG. 3A to 3N are views for explaining a processing procedure for forming irregularities on the surface of a single-crystal GaN free-standing substrate.

[Base substrate]
A single crystal gallium nitride (GaN) substrate (8) was prepared as a base substrate (FIG. 3A). This single crystal GaN substrate is a self-supporting substrate having a disk shape with a thickness of 400 μm and a diameter of 50 mm and having a (0001) plane (C plane) on the surface. A plurality of such single crystal GaN free-standing substrates were prepared in order to evaluate the shape of the irregularities formed under the processing conditions described later.

[Mask formation and cleaning]
About 1.0 μm of a silicon nitride film (9) was deposited on the surface of the above-mentioned GaN free-standing substrate by plasma CVD (FIG. 3B). This GaN free-standing substrate with a silicon nitride film was subjected to ultrasonic cleaning for 10 minutes in a solvent of acetone and methanol, respectively, and rinsed with pure water for 5 minutes.

[OAP application]
Hexamethyldisilazane (HMDS: “OAP” manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied as a primer (10) to the surface of the cleaned GaN free-standing substrate (FIG. 3C). First, it was uniformed with a spinner at 1000 rpm for 7 seconds, then at 4000 rpm for 30 seconds, and then baked at 100 ° C. for 90 seconds. This is a process necessary for improving the adhesion between the silicon nitride film and the resist described later.

[Resist application]
A positive resist (11) is applied on the HMDS (10) (FIG. 3D), and is made uniform by a spinner in the same procedure as the above-mentioned OAP application, and then pre-baked for 30 minutes on a 90 ° C. hot plate. It was. Pre-baking is a process for fixing the resist. The positive resist used is “MCPR-2200X” manufactured by Rohm and Haas Co., Ltd.

[exposure]
The resist was exposed using a Cr mask for exposure. In this Cr mask pattern, a stripe pattern having a line (Mask) / space (Window) of 10 μm / 2 μm is formed, and the stripe direction is <1-100> on the surface of a GaN free-standing substrate as a base substrate. A Cr mask was set so that exposure was performed. The exposure amount of the mask aligner was 70 mJ / cm ^2, and post-baking was performed at 120 ° C. for 90 seconds on a hot plate after exposure.

[developing]
The exposed GaN free-standing substrate was immersed in a positive resist developer (“NMD-3” manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 90 seconds to remove the exposed portion of the resist (13) and HMDS (12) (FIG. 3E). ). Thereafter, rinsing was performed with pure water for about 90 seconds.

[Mask removal and photoresist removal]
Dry etching of silicon nitride was performed with a plasma etching apparatus (FIG. 3F). Thereafter, ultrasonic cleaning was performed in the order of Rohm and Haas remover 1165A and acetone to dissolve and remove the remaining resist (11) and HMDS (10) (FIG. 3G).

[etching]
By the reactive ion etching (RIE) method, the free-standing substrate in the region where the silicon nitride (11) on the free-standing substrate surface was removed was etched to a depth of about 3 μm to form a groove (FIG. 4H). The apparatus conditions during the etching are an RF power of 200 W, a Cl2 gas flow rate of 30 sccm, and an etching time of 10 minutes.

[Mask removal]
Silicon nitride (9) was wet etched with a 1: 5 mixture of 50% hydrofluoric acid and 40% ammonium fluoride (FIG. 3I). The etching time is 10 minutes.

[Concave mask formation]
A silicon nitride mask having a thickness of about 100 nm was formed in the concave portion of the GaN free-standing substrate having irregularities on the surface for the purpose of inhibiting the growth of GaN during HVPE growth described later (FIG. 3N). For patterning the silicon nitride film, the same technique (FIGS. 3J to 3M) as in the process using the above-described photoresist was used.

  When a part of the GaN free-standing substrate (8) having the surface irregularities thus formed was cleaved and the planar SEM image and the cross-sectional SEM image were observed, the groove depth was 2.94 μm at the center of the substrate. It was confirmed that the terrace width was 9.2 μm and the groove width was 2.2 μm.

  A GaN free-standing substrate having a diameter of 50 mm and a thickness of 400 μm subjected to surface processing as described above was prepared. The main surface of the base substrate is the (0001) plane.

[Formation of Compound Semiconductor Single Crystal Layer]
(1) The crystal was set on the substrate holder in the reactor of the HVPE apparatus with + C facing upward. Note that the back surface of the GaN free-standing substrate is in contact with the substrate holder and is not in direct contact with the source gas.
(2) The temperature of the reaction chamber was raised to 1005 ° C., and the raw material was supplied from the + C plane direction to grow Si-doped GaN. Dichlorosilane (SiH ₂ Cl ₂ ) was used as the Si-doped precursor gas, and hydrogen chloride (HCl) was introduced from the same inlet. In this growth step, the growth pressure is set to 1.01 × 10 ⁵ Pa, the partial pressure of NH ₃ gas is 8.13 × 10 ³ Pa, the partial pressure of N ₂ gas is 1.17 × 10 ⁴ Pa, GaCl gas The partial pressure was 7.0 × 10 ² Pa and the partial pressure of H ₂ gas was 8.04 × 10 ⁴ Pa. The flow rate of dichlorosilane was 2.6 sccm at 0.5% dilution, and 3 sccm was introduced at 100% hydrogen chloride. The respective volume molar partial pressures in the total volume of the introduction pipe are 6.822 × 10 ⁻⁶ (dichlorosilane) and 1.574 × 10 ⁻³ (HCl).
(3) After growing for 17 hours, the temperature was lowered to room temperature. The obtained GaN single crystal had a circular shape with no abnormal growth, and the film thickness in the c-axis direction was about 2.3 mm. The area of the main surface (C surface) was 1963.0 mm ² with an effective diameter of 50 mm when a 50 mm free-standing substrate was used.

<Separation process of separating a base substrate and a compound semiconductor single crystal layer to obtain a semiconductor bulk crystal>
The separation process described below will be described with reference to FIG.
The crystal (crystal complex) 201 obtained in the growth step is placed in an alumina reaction tube (Al ₂ O ₃ 99.7%) 200, and an ammonia / nitrogen mixed gas is supplied at a flow rate of 200 ml / min. Heat treatment was performed while introducing from the introduction tube 203. Note that the ammonia / nitrogen mixed gas (NH ₃ 8.5% + N ₂ 91.5%) was mixed with ammonia gas and nitrogen gas in a 47-liter cylinder of 4.9 MPa until 45% until a uniform mixed gas was obtained. What was left for more than a day was used. The temperature increase in the heat treatment was performed using a heater 202 from room temperature to 600 ° C. at 300 ° C./hour, from 600 ° C. to 1300 ° C. at a temperature increase rate of 250 ° C./hour, and maintained at 1300 ° C. for 6 hours. . Cooling was performed from 1300 ° C. to 600 ° C. at a cooling rate of 100 ° C./hour.

  As a result of confirming the crystal after the heat treatment, surprisingly, the base substrate, the compound semiconductor single crystal layer, and the (group III nitride semiconductor crystal) are the same species, but the base is formed with the cavity as a boundary. Separation of the substrate and the crystal layer was confirmed over the entire surface of the base substrate. Further, the crystal surface after heating (after the separation step) was black, and as a result of identification by XRD, it was found that gallium hydroxide, gallium oxide, and gallium metal were mixed. From this, it was confirmed that the hydrolysis reaction of the GaN crystal was caused by the water molecules generated by the reaction between ammonia and the alumina of the core tube member.

The obtained crystal is immersed in concentrated nitric acid (containing 69% of HNO ₃ ) at 120 ° C. to remove the gallium metal adhering to the surface, and a crystal in which cream-like gallium oxyhydroxide and white gallium oxide are present on the surface A sample was obtained. Thus, it was confirmed that a surface altered layer composed of a group III element was formed on the crystal surface after heating (after the separation step), and GaN crystals were present in the inside. It was visually confirmed that the back surface of the growth layer after immersion in nitric acid, that is, the growth layer side surface separated from the cavity, was flat, and the growth layer side could be obtained as a bulk crystal. As a result, a growth layer having high quality crystallinity could be obtained separately from the substrate without requiring slicing or the like.

  A semiconductor bulk crystal obtained by the production method of the present invention, such as a group III nitride semiconductor crystal, is a light emitting element on a relatively short wavelength side such as an ultraviolet to blue light emitting diode or a semiconductor laser, and a green to red relatively long wavelength. It is also useful as a substrate for manufacturing the side light emitting element, and further as a substrate for semiconductor devices such as electronic devices.

DESCRIPTION OF SYMBOLS 1 Base substrate 2 Compound semiconductor single crystal layer 3 Cavity 4 Cavity width 5 Cavity height 6 Non-cavity width 7 Cavity long side 8 Base substrate 9 Silicon nitride film 10 HMDS (hexamethyldisilazane)
11 Positive resist 12 Silicon nitride film 13 Positive resist 100 Reactor (reaction vessel)
101-104 Introduction pipe 105 Reservoir 106 Heater 107 Susceptor 108 Exhaust pipe 109 Substrate holder 200 Alumina pipe 201 Crystal composite body 202 Heater 203 Gas introduction pipe 204 Gas exhaust pipe

Claims (9)

A preparatory step of preparing a crystal composite including a base substrate and a compound semiconductor single crystal layer formed on a main surface of the base substrate, and further having a cavity near a boundary between the base substrate and the compound semiconductor single crystal layer; And a separation step of heating the crystal complex at a temperature of 1000 ° C. or higher to separate the base substrate and the compound semiconductor single crystal layer to obtain a semiconductor bulk crystal. . The method for producing a semiconductor bulk crystal according to claim 1, wherein the base substrate and the compound semiconductor single crystal layer satisfy a condition of a lattice mismatch degree represented by the following formula.
2 | a ₁ −a ₂ | / [a ₁ + a ₂ ] ≦ 1 × 10 ⁻³
(Wherein a ₁ is the lattice constant of the underlying substrate and the lattice constant of the crystal axis perpendicular to the growth direction of the compound semiconductor single crystal layer, and a ₂ is the lattice constant of the compound semiconductor single crystal layer and the compound (Represents the lattice constant of the crystal axis perpendicular to the growth direction of the semiconductor single crystal layer.) The method for producing a semiconductor bulk crystal according to claim 1, wherein the separation step is a step of heating in the presence of an oxygen source. The method for producing a semiconductor bulk crystal according to claim 3, wherein the separation step is a step of heating in the presence of water (H ₂ O). The manufacturing method of the semiconductor bulk crystal of any one of Claims 1-4 whose thickness of the said base substrate is 100 micrometers or more and 1 mm or less. The contact area between the base substrate and the compound semiconductor single crystal layer in the crystal composite is 10% or more and 90% or less of the total area of the main surface of the base substrate. The manufacturing method of the semiconductor bulk crystal of description. The method for producing a semiconductor bulk crystal according to any one of claims 1 to 6, wherein the compound semiconductor single crystal layer is formed by a halide vapor phase epitaxy (HVPE method). The method for producing a semiconductor bulk crystal according to claim 1, wherein the base substrate and the compound semiconductor single crystal layer are group III nitride semiconductor crystals. The method for producing a semiconductor bulk crystal according to claim 8, wherein a main surface of the base substrate is a C plane.

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