JP2013207700A - Transistor circuit, power supply device, display device, electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve high voltage resistance of a transistor circuit without using an exclusive process.SOLUTION: A transistor circuit 31 includes: a node nd1 to which an off voltage VOFF (from negative to positive) is applied; a node nd2 to which a negative voltage VSS is applied; a node nd3 to which a ground voltage GND is applied; a plurality of CMOS FETs 311-313 series-connected to between the node nd1 and the node nd2; and a gate voltage generation section 314 which divides a voltage applied to between the node nd1 and the node nd3 to generate gate voltages Vg1-Vg3 of the CMOS FETs 311-313.

Description

  The present invention relates to a high breakdown voltage of a transistor circuit using a complementary metal oxide semiconductor field effect transistor (CMOSFET).

  A semiconductor integrated circuit device in which a large number of MOSFETs are integrated may be required to have a high breakdown voltage depending on the application (for example, an application that handles both positive and negative voltages).

  As an example of the related art related to the above, Patent Document 1 can be cited.

JP 2011-223222 A

  Since a DMOSFET [double-diffused MOSFET] is easy to realize a high breakdown voltage as compared with a general CMOSFET, a DMOSFET is often used in a portion where a high breakdown voltage is required. However, as shown in FIG. 9, the N-channel DMOSFET 200 has an n-type drain region 202 in contact with the p-type semiconductor substrate 201 due to its device structure. A low voltage could not be applied. Therefore, when the ground voltage GND is applied to the p-type semiconductor substrate 201, the N-channel DMOSFET 200 cannot handle a negative voltage.

  On the other hand, as shown in FIG. 10, in the case of the N-channel CMOSFET 300, a p-type well (back gate region) 303 and an n-type drain region 304 are used using an n-type well 302 to which a positive voltage or a ground voltage GND is applied. Since the n-type source region 305 and the gate electrode 306 can be electrically insulated from the p-type semiconductor substrate 301 (floating state), a negative voltage can be handled. However, in the N-channel CMOSFET 300, the breakdown voltage is easily increased between the p-type semiconductor substrate 301 and the n-type well 302, but the other portion (between the n-type well 302 and the p-type well 303, the n-type drain region 304). And p-type well 303, n-type source region 305, and gate electrode 306, between n-type source region 305 and p-type well 303 and gate electrode 306, and between p-type well 303 and gate electrode 306 It was difficult to increase the breakdown voltage for (between). Note that if a dedicated process specialized in increasing the breakdown voltage is used, it is possible to increase the breakdown voltage of the N-channel CMOSFET 300, but there is a problem in that the number of processes is increased and the cost is increased.

  In view of the above problems found by the inventors of the present application, the present invention provides a transistor circuit capable of realizing a high breakdown voltage without using a dedicated process, and a power supply device and a display device using the transistor circuit And it aims at providing an electronic device.

  In order to achieve the above object, a transistor circuit disclosed in the present specification includes a first node to which a first voltage is applied, and a second node to which a second voltage lower than the first voltage is applied. A third node to which a third voltage equal to or higher than a ground voltage is applied, a plurality of CMOSFETs connected in series between the first node and the second node, and the first node and the third node A configuration (first configuration) is provided that includes a gate voltage generation unit that divides a voltage applied therebetween to generate a gate voltage of each CMOSFET.

  In the transistor circuit having the first configuration, the gate voltage generation unit may include a resistance ladder (second configuration) connected between the first node and the third node.

  In the transistor circuit having the second configuration, the gate voltage generation unit includes a transistor having a gate connected to the resistor ladder and a source connected to the gate of the CMOSFET (third configuration). Good.

  In the transistor circuit having the third configuration, the second voltage is a negative voltage, and the first voltage is a voltage changing from the negative voltage to a positive voltage (fourth configuration). .

  In the transistor circuit having the fourth configuration, the plurality of CMOSFETs may be floating NMOSFETs (fifth configuration).

  In the transistor circuit having the fifth configuration, the floating NMOSFET includes a p-type semiconductor substrate, an n-type well formed on the p-type semiconductor substrate, and a p-type formed in the n-type well. A well, an n-type source region and an n-type drain region formed in the p-type well, and a gate electrode formed on a channel region sandwiched between the n-type source region and the n-type drain region And (6th configuration).

  In the transistor circuit having the sixth structure, the p-type well may be electrically insulated from the p-type semiconductor substrate by the n-type well (seventh structure).

  In the transistor circuit having the seventh configuration, the p-type semiconductor substrate may be connected to a ground terminal (eighth configuration).

  In the transistor circuit having the eighth configuration, the n-type well surrounds the n-type buried insulating layer buried in the p-type semiconductor substrate and the n-type buried insulating layer. It is preferable to adopt a configuration (ninth configuration) including an n-type epitaxial insulating layer stacked up to the surface layer of the p-type semiconductor substrate.

  Further, in the transistor circuit having the ninth configuration, the floating NMOSFET has a p-type low insulating layer formed between the p-type well and the n-type buried insulating layer (tenth configuration). ).

  Further, a power supply device disclosed in the present specification includes a positive voltage generation circuit that generates a positive voltage, a negative voltage generation circuit that generates a negative voltage, a first external terminal to which the positive voltage is applied, A second external terminal to which a negative voltage is applied; a third external terminal to which the negative voltage or the positive voltage is applied; and the negative voltage is applied to the third external terminal during normal operation, and the A discharge control circuit for applying the positive voltage to three external terminals, and the discharge control circuit comprises the tenth configuration connected between the second external terminal and the third external terminal. The transistor circuit includes a transistor circuit (an eleventh structure).

  In the power supply device having the eleventh configuration, the discharge control circuit includes a PMOSFET connected between the first external terminal and the third external terminal, and a gate and a ground terminal of the PMOSFET. And an NMOSFET connected to the first MOSFET and a resistor connected between the first external terminal and the gate of the PMOSFET (a twelfth configuration).

  A display device disclosed in the present specification includes a liquid crystal display panel, a driver for driving the liquid crystal display panel, and a power supply device having the twelfth configuration for supplying a positive voltage and a negative voltage to the driver. , (A thirteenth configuration).

  In addition, the electronic device disclosed in this specification has a display device (fourteenth configuration) including the display device having the thirteenth configuration.

  According to the technology disclosed in this specification, a transistor circuit capable of realizing a high breakdown voltage without using a dedicated process, and a power supply device, a display device, and an electronic device using the transistor circuit are provided. can do.

Block diagram showing one configuration example of a display device Time chart showing output behavior during off-sequence Circuit diagram showing a first configuration example of a transistor circuit Vertical sectional view and top view of floating NMOSFETs 311 to 313 Time chart showing output behavior (first example) during off-sequence Circuit diagram showing a second configuration example of a transistor circuit Time chart showing output behavior (second example) during off-sequence External view of electronic device (tablet PC) Vertical section of N-channel DMOSFET Vertical section of N-channel CMOSFET

<Display device>
FIG. 1 is a block diagram illustrating a configuration example of a display device. The display device 100 of this configuration example includes a liquid crystal display panel 1, a driver 2 that drives the liquid crystal display panel 1, and a power supply device 3 that supplies an on voltage VON and an off voltage VOFF to the driver 2.

  The power supply device 3 is a semiconductor integrated circuit device having a positive voltage generation circuit 10, a negative voltage generation circuit 20, and a discharge control circuit 30. Further, the power supply device 3 has external terminals T1 to T3 as means for establishing electrical connection with the outside of the device.

  The external terminal T1 is a first external terminal to which an on voltage VON (positive voltage) is applied. The external terminal T2 is a second external terminal to which an off voltage VOFF (a negative voltage VSS in a normal operation and an on voltage VON in an off sequence) is applied. The external terminal T3 is a third external terminal to which the negative voltage VSS is applied. The external terminals T1 and T3 are connected to output smoothing capacitors C1 and C2, respectively.

  The positive voltage generation circuit 10 generates an on voltage VON and outputs it to the external terminal T1. The positive voltage generation circuit 10 generates the ON voltage VON when the control signal CTL is at a low level (logic level when output is enabled), and when the control signal CTL is at a high level (logic level when output is disabled). The generation of the ON voltage VON is stopped. Note that a switching regulator or the like can be used as the positive voltage generation circuit 10 and the positive voltage generation circuit 10.

  The negative voltage generation circuit 20 generates a negative voltage VSS and outputs it to the external terminal T3. The negative voltage generation circuit 20 generates the negative voltage VSS when the control signal CTL is at a low level, and stops generating the negative voltage VSS when the control signal CTL is at a high level. As the negative voltage generation circuit 20, a negative output charge pump or the like can be used.

  Discharge control circuit 30 includes NMOSFETs 31 and 32, PMOSFET 33, and resistor 34. The drain of the NMOSFET 31 is connected to the external terminal T2. The source of the NMOSFET 31 is connected to the external terminal T3. The gate of the NMOSFET 31 is connected to the application terminal of the ground voltage GND. The drain of the NMOSFET 32 is connected to the gate of the PMOSFET 33. The source of the NMOSFET 32 is connected to the application terminal of the ground voltage GND. The gate of the NMOSFET 32 is connected to the application end of the control signal CTL. The source of the PMOSFET 33 is connected to the external terminal T1. The drain of the PMOSFET 33 is connected to the external terminal T2. A first end of the resistor 34 is connected to the external terminal T1. The second end of the resistor 34 is connected to the gate of the PMOSFET 33.

  The discharge control circuit 30 configured as described above applies the negative voltage VSS to the external terminal T3 during normal operation of the power supply device 3 (when the control signal CTL is at a low level), while the power supply device 3 is in an off sequence. When the control signal CTL is at a high level, the voltage application path to the external terminal T2 is switched so as to apply the ON voltage VON to the external terminal T3.

  FIG. 2 is a time chart showing the output behavior of the power supply device 3 during the off sequence, in which the on voltage VON, the ground voltage GND, the off voltage VOFF, and the negative voltage VSS are depicted in order from the top.

  During normal operation (before time t1), since the control signal CTL is at a low level, the NMOSFET 32 is turned off and the PMOSFET 33 is turned off. At this time, since a voltage (GND-VSS) exceeding the on-threshold voltage Vth of the NMOSFET 31 is applied between the gate and source of the NMOSFET 31, the NMOSFET 31 is turned on. Therefore, the off voltage VOFF applied to the external terminal T2 is substantially equal to the negative voltage VSS.

  When the control signal CTL rises to a high level at time t1, the output operation of the positive voltage generation circuit 10 is stopped, so that the ON voltage VON (= OFF voltage VOFF) starts to gradually decrease due to natural discharge of the capacitor C1. . Further, when the control signal CTL is raised to a high level at time t1, the NMOSFET 32 is turned on. At this time, since a voltage (VON-GND) exceeding the on-threshold voltage Vth of the PMOSFET 33 is applied between the gate and source of the PMOSFET 33, the PMOSFET 33 is turned on. As a result, the off voltage VOFF applied to the external terminal T2 is rapidly raised to almost the on voltage VON. Further, as long as a voltage exceeding the on-threshold voltage Vth is applied between the gate and the source of the NMOSFET 31 after the time t1, the NMOSFET 31 continues to be turned on, so that the negative voltage VSS rises rapidly following the off-voltage VOFF. Thereafter, when the voltage applied between the gate and source of the NMOSFET 31 falls below the on-threshold voltage Vth of the NMOSFET 31, the NMOSFET 31 is turned off. Thereafter, the negative voltage VSS gradually approaches the ground voltage GND with the natural discharge of the capacitor C2.

  By the way, since the differential voltage (= VON−VSS) between the ON voltage VON and the negative voltage VSS is applied to the NMOSFET 31 and the PMOSFET 33 among the elements forming the discharge control circuit 30 at the maximum, the NMOSFET 31 and the PMOSFET 33 can withstand this differential voltage. Only high breakdown voltage is required. At that time, with respect to the PMOSFET 33, it is possible to realize a high breakdown voltage relatively easily by using a P-channel type DMOSFET. However, for the NMOSFET 31, it is not possible to use an N-channel DMOSFET that can easily increase the breakdown voltage for the reason described above. Therefore, if the NMOSFET 31 is formed with a single element, an N-channel CMOSFET having a floating structure must be formed using a dedicated process specialized for increasing the breakdown voltage, resulting in an increase in the number of processes and an increase in cost. It will be scratched.

  In view of the above problems, a transistor circuit is proposed below that can realize a high breakdown voltage as a whole circuit by connecting a plurality of CMOSFETs in series.

<Transistor circuit>
[First configuration example]
FIG. 3 is a circuit diagram illustrating a first configuration example of the transistor circuit. The transistor circuit 31X of the first configuration example is a circuit block that functions as an alternative to the above-described NMOSFET 31, and includes nodes nd1 to nd3, floating NMOSFETs 311 to 313, and a gate voltage generation unit 314.

  The node nd1 is a first node corresponding to the drain of the NMOSFET 31, and is connected to the external terminal T2 to which the off voltage VOFF is applied. The off voltage VOFF corresponds to a first voltage that changes from a negative voltage to a positive voltage.

  The node nd2 is a second node corresponding to the source of the NMOSFET 31, and is connected to the external terminal T3 to which the negative voltage VSS is applied. Note that the negative voltage VSS corresponds to a second voltage equal to or lower than the first voltage.

  The node nd3 is a third node corresponding to the gate of the NMOSFET 31, and is connected to a ground terminal to which the ground voltage GND is applied. The ground voltage GND corresponds to a third voltage that is equal to or higher than the ground voltage.

  The floating NMOSFETs 311 to 313 are N-channel CMOSFETs having a floating structure connected in series between the node nd1 and the node nd2. Note that FIG. 3 shows a configuration example in which the number of series stages of the floating NMOSFET is three. However, the number of series stages is reduced to two in consideration of the withstand voltage performance required for the transistor circuit 31X. Or, conversely, it may be increased to four or more stages.

  The gate voltage generation unit 314 divides the voltage applied between the nodes nd1 and nd3 to generate the gate voltages Vg1 to Vg3 of the floating NMOSFETs 311 to 313. Gate voltage generation unit 314 includes resistors R1 to R3 (resistance ladder RL) connected in series between nodes nd1 and nd3.

  Next, the connection relationship of the circuit elements will be specifically described. The source and back gate of the floating NMOSFET 311 are both connected to the node nd2. The drain of the floating NMOSFET 311 is connected to the source and back gate of the floating NMOSFET 312. The gate of the floating NMOSFET 311 and the n-type epitaxial insulating layer (see FIG. 4 described later) are connected to the node nd3. The drain of the floating NMOSFET 312 is connected to the source and back gate of the floating NMOSFET 313. The gate of the floating NMOSFET 312 and the n-type epitaxial insulating layer are connected to a connection node (applied end of the divided voltage V1) between the resistor R1 and the resistor R2. The drain of the floating NMOSFET 313 is connected to the node nd1. The gate of the floating NMOSFET 313 and the n-type epitaxial insulating layer are connected to a connection node (an application end of the divided voltage V2) between the resistors R2 and R3.

  In the transistor circuit 31X configured as described above, the ground voltage GND is applied as the gate voltage Vg1 to the gate of the floating NMOSFET 311. When the resistance values of the resistors R1 to R3 are all the same value, a divided voltage V1 (= (1/3) × VOFF) is applied as the gate voltage Vg2 to the gate of the floating NMOSFET 312. A divided voltage V2 (= (2/3) × VOFF) is applied to the gate as the gate voltage Vg3.

  Next, the device structure of the floating NMOSFETs 311 to 313 will be specifically described. FIG. 4 is a longitudinal sectional view and a top view of the floating NMOSFETs 311 to 313. Since the floating NMOSFETs 311 to 313 all have the same device structure, only the floating NMOSFET 311 is depicted in the top view as a representative. In the following, description will be made focusing on only the floating NMOSFET 311. If the reference numeral 311 is replaced with the reference numeral 312 or the reference numeral 313, it can be understood as an explanation of the floating NMOSFET 312 or 313.

  The floating NMOSFET 311 includes a p-type semiconductor substrate A1, an n-type buried insulating layer A2, an n-type epitaxial insulating layer A3, a p-type low insulating layer A4, a p-type well A5, an n-type source region A6, n A type drain region A7, a gate electrode A8, and contact regions A9 and A10 are included.

  The p-type semiconductor substrate A1 is a base material for integrating the floating NMOSFET 311. A ground voltage GND is applied to the p-type semiconductor substrate A1.

  The n-type buried insulating layer A2 is an n-type impurity layer (so-called B / L [buried layer] layer) buried in the p-type semiconductor substrate A1.

  The n-type epitaxial insulating layer A3 is an n-type impurity layer that is stacked up to the surface layer of the p-type semiconductor substrate A1 so as to surround the n-type buried insulating layer A2.

  That is, in the floating NMOSFET 311, an n-type well (A2 + A3) is formed on the p-type semiconductor substrate A1 by the n-type buried insulating layer A2 and the n-type epitaxial insulating layer A3.

  The p-type low insulating layer A4 is a p-type impurity layer (so-called L / I [low isolation] layer) formed between the p-type well A5 and the n-type buried insulating layer A2.

  The p-type well A5 is a p-type impurity layer formed in the n-type well (A2 + A3). That is, the p-type well A5 is electrically insulated from the p-type semiconductor substrate A1 by the n-type well (A2 + A3). The p-type well A5 corresponds to the back gate region (BG) of the floating NMOSFET 311.

  The n-type source region A6 is an n-type impurity region formed in the p-type well A5 as the source (S) of the floating NMOSFET 311.

  The n-type drain region A7 is an n-type impurity region formed in the p-type well A5 as the drain (D) of the floating NMOSFET 311.

  The gate electrode A8 is a metal electrode formed on the channel region sandwiched between the n-type source region A6 and the n-type drain region A7 as the gate (G) of the floating NMOSFET 311.

  The contact region A9 is a p-type impurity region formed in the p-type well A5 in order to establish electrical connection with the back gate (BG) of the floating NMOSFET 311.

  The contact region A10 is an n-type impurity region formed in the n-type epitaxial insulating layer A3 in order to establish electrical connection with the n-type well (A2 + A3).

  An element isolation layer A11 is formed between the floating NMOSFETs 311 to 313. Further, a passivation layer A12 is formed on the outermost layer of the floating NMOSFETs 311 to 313.

  FIG. 5 is a time chart showing the output behavior during the off sequence using the transistor circuit 31X. As shown in FIG. 5, in the transistor circuit 31X, during the off sequence of the power supply device 3 (after time t1), the off voltage VOFF (= on voltage VON) and the negative voltage VSS are equally divided. The drain-source voltages Vds1 to Vds3 of the floating NMOSFETs 311 to 313 are generated. That is, the voltage applied to each of the floating NMOSFETs 311 to 313 is suppressed to about ３ of the voltage (= VOFF−VSS) applied to the transistor circuit 31X. Therefore, when forming the floating NMOSFETs 311 to 313, an inexpensive normal CMOS process with a smaller number of steps can be used without using a dedicated process specialized for increasing the breakdown voltage, so that it is used in the negative voltage region. The high breakdown voltage of the transistor circuit 31X can be realized at low cost and on a small scale.

[Second configuration example]
FIG. 6 is a circuit diagram illustrating a second configuration example of the transistor circuit. The transistor circuit 31Y of the second configuration example has basically the same configuration as that of the first configuration example. As additional components of the gate voltage generation unit 314, NMOSFETs N1 and N2, resistors R4 and R5, a current source CS1 and It is characterized in that it includes CS2. Accordingly, the same parts as those in the first configuration example are denoted by the same reference numerals as those in FIG. 3, and redundant description is omitted. Hereinafter, the characteristic parts of the second configuration example will be described mainly.

  The drain of the NMOSFET N1 is connected to the application terminal of the ON voltage VON via the resistor R4. The source of the NMOSFET N1 is connected to the gate of the floating NMOSFET 312 and is also connected to the node nd3 through the current source CS1. The gate of the NMOSFET N1 is connected to a connection node (an application end of the divided voltage V1) between the resistor R1 and the resistor R2.

  The drain of the NMOSFET N2 is connected to the application terminal of the ON voltage VON via the resistor R5. The source of the NMOSFET N2 is connected to the gate of the floating NMOSFET 313, and is also connected to the node nd3 through the current source CS2. The gate of the NMOSFET N2 is connected to a connection node (an application end of the divided voltage V2) between the resistors R2 and R3.

  In the transistor circuit 31Y configured as described above, the ground voltage GND is applied as the gate voltage Vg1 to the gate of the floating NMOSFET 311. Further, the source voltage V3 of the NMOSFET N1 is applied as the gate voltage Vg2 to the gate of the floating NMOSFET 312, and the source voltage V4 of the NMOSFET N2 is applied as the gate voltage Vg3 to the gate of the floating NMOSFET 313.

  FIG. 7 is a time chart showing an output behavior (second example) during an off sequence using the transistor circuit 31Y. As shown in FIG. 7, in the transistor circuit 31Y, the gate voltages Vg1 to Vg3 are all maintained at the ground voltage GND during the period in which the off voltage VOFF is a negative voltage (before time t2). This is because the gate-source voltages of the NMOSFETs N1 and N2 fall below the respective on-threshold voltages Vth during the period when the off-voltage VOFF is a negative voltage, and the NMOSFETs N1 and N2 are turned off. Note that while the gate voltages Vg1 to Vg3 are maintained at the ground voltage GND, the floating NMOSFETs 311 to 313 are all turned on, and the negative voltage VSS is output as the off voltage VOFF.

  As described above, the transistor circuit 31Y of the second configuration example can secure the gate-source voltage necessary for turning on the floating NMOSFET even when the number of series stages of the floating NMOSFET increases. There is no need to worry about the normal operation of the device 3.

  Thereafter, the off-voltage VOFF is raised to a positive voltage during the off-sequence of the power supply device 3 (after time t1). When the gate-source voltages of the NMOSFETs N1 and N2 exceed the respective on-threshold voltages Vth at time t2, the NMOSFET N1 and N2 is turned on. Accordingly, the source voltages V3 and V4 of the NMOSFETs N1 and N2 (= the gate voltages Vg2 and Vg3 of the floating NMOSFETs 312 and 313) rise to voltage values that are lower than the divided voltages V1 and V2 by the respective on-threshold voltages Vth.

  At this time, the source voltage Vs1 (negative voltage VSS) of the floating NMOSFET 311 is clamped to a voltage lower than the gate voltage Vg1 (ground voltage GND) by the on-threshold voltage Vth. The source voltage Vs2 of the floating NMOSFET 312 (the drain voltage Vd1 of the floating NMOSFET 311) is clamped to a voltage that is lower than the gate voltage Vg2 by the on-threshold voltage Vth. The source voltage Vs3 of the floating NMOSFET 313 (the drain voltage Vd2 of the floating NMOSFET 312) is clamped to a voltage that is lower than the gate voltage Vg3 by the on-threshold voltage Vth.

  As a result, after time t2, in the transistor circuit 31Y, the drains of the floating NMOSFETs 311 to 313 are equally divided between the off voltage VOFF (= on voltage VON) and the negative voltage VSS, as in the first configuration example described above. -The source-to-source voltages Vds1 to Vds3 are generated, and appropriate withstand voltage distribution is realized.

<Application to electronic devices>
FIG. 8 is an external view of an electronic device (tablet PC) on which the display device 100 is mounted. The electronic device X of this configuration example includes an imaging unit X1 mounted on the front and back of the main body, an operation unit X2 (such as various buttons) that accepts user operations, and a display that displays characters and videos (including photographed images). Part X3. The display unit X3 has a touch panel function for accepting a user's touch operation.

  In particular, if the display device 100 described above is mounted as the display unit X3, the off-sequence operation shown in FIG. 2 can be realized without increasing the size of the discharge control circuit 30 (and hence the power supply device 3). It is possible to contribute to downsizing and cost reduction of the electronic device X.

<Other variations>
In the above embodiment, the tablet PC is taken as an example of an application target of the present invention. However, the application target of the present invention is not limited to this, and the present invention is a general transistor circuit that requires high breakdown voltage. It can be widely applied to.

  Various technical features disclosed in the present specification can be variously modified within the scope of the technical creation in addition to the above-described embodiment.

  For example, in the above embodiment, the transistor circuit used in the negative voltage region has been described as an example. However, the transistor circuit disclosed in the present specification can also be used in the positive voltage region. Such an application is effective when the DMOS process cannot be used in order to realize a high breakdown voltage of the MOSFET.

  As described above, the above-described embodiment is to be considered as illustrative in all points and not restrictive, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that fall within the meaning and range equivalent to the scope of the claims are included.

  The technology disclosed in this specification is used as a technology for realizing high breakdown voltage of CMOSFETs included in various applications such as tablet PCs, smartphones, LCD-TVs, PDP-TVs, DVD recorders, and BD recorders. Is possible.

DESCRIPTION OF SYMBOLS 1 Liquid crystal display panel 2 Driver 3 Power supply device 10 Positive voltage generation circuit 20 Negative voltage generation circuit 30 Discharge control circuit 31 NMOSFET (CMOS)
31X, 31Y Transistor circuit 311, 312, 313 Floating NMOSFET (CMOS)
314 Gate Voltage Generation Unit 32 NMOSFET (DMOS)
33 PMOSFET (DMOS)
34 Resistance 100 Display device T1 to T3 External terminal C1, C2 Capacitor nd1 to nd3 Node RL Resistance ladder R1 to R5 Resistance N1, N2 NMOSFET (DMOS)
CS1, CS2 Current source A1 p-type semiconductor substrate A2 n-type buried insulating layer A3 n-type epitaxial insulating layer A4 p-type low insulating layer A5 p-type well (back gate region)
A6 n-type source region A7 n-type drain region A8 gate electrode A9 contact region A10 contact region A11 element isolation layer A12 passivation layer X electronic device (tablet PC)
X1 imaging unit X2 operation unit X3 display unit

Claims (14)

A first node to which a first voltage is applied;
A second node to which a second voltage lower than the first voltage is applied;
A third node to which a third voltage equal to or higher than the ground voltage is applied;
A plurality of CMOSFETs connected in series between the first node and the second node;
A gate voltage generator that divides a voltage applied between the first node and the third node to generate a gate voltage of each CMOSFET;
A transistor circuit comprising:   The transistor circuit according to claim 1, wherein the gate voltage generation unit includes a resistance ladder connected between the first node and the third node.   The transistor circuit according to claim 2, wherein the gate voltage generation unit includes a transistor having a gate connected to the resistor ladder and a source connected to a gate of the CMOSFET.   4. The transistor circuit according to claim 3, wherein the second voltage is a negative voltage, and the first voltage is a voltage that changes from the negative voltage to a positive voltage.   The transistor circuit according to claim 4, wherein each of the plurality of CMOSFETs is a floating NMOSFET. The floating NMOSFET is
a p-type semiconductor substrate;
An n-type well formed on the p-type semiconductor substrate;
A p-type well formed in the n-type well;
An n-type source region and an n-type drain region formed in the p-type well;
A gate electrode formed on a channel region sandwiched between the n-type source region and the n-type drain region;
6. The transistor circuit according to claim 5, further comprising:   The transistor circuit according to claim 6, wherein the p-type well is electrically insulated from the p-type semiconductor substrate by the n-type well.   The transistor circuit according to claim 7, wherein the p-type semiconductor substrate is connected to a ground terminal. The n-type well is
An n-type buried insulating layer buried in the p-type semiconductor substrate;
An n-type epitaxial insulating layer laminated up to a surface layer of the p-type semiconductor substrate so as to surround the n-type buried insulating layer;
The transistor circuit according to claim 8, comprising:   The transistor circuit according to claim 9, wherein the floating NMOSFET has a p-type low insulating layer formed between the p-type well and the n-type buried insulating layer. A positive voltage generation circuit for generating a positive voltage;
A negative voltage generation circuit for generating a negative voltage;
A first external terminal to which the positive voltage is applied;
A second external terminal to which the negative voltage is applied;
A third external terminal to which the negative voltage or the positive voltage is applied;
A discharge control circuit that applies the negative voltage to the third external terminal during normal operation and applies the positive voltage to the third external terminal during an off-sequence;
Have
The power supply apparatus according to claim 10, wherein the discharge control circuit includes the transistor circuit according to claim 10 connected between the second external terminal and the third external terminal. The discharge control circuit includes:
A PMOSFET connected between the first external terminal and the third external terminal;
An NMOSFET connected between the gate and the ground end of the PMOSFET;
A resistor connected between the first external terminal and the gate of the PMOSFET;
The power supply device according to claim 11, further comprising: A liquid crystal display panel;
A driver for driving the liquid crystal display panel;
The power supply device according to claim 12, which supplies a positive voltage and a negative voltage to the driver.
A display device comprising:   An electronic apparatus comprising the display device according to claim 13.

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