JP5516260B2 - Negative power supply control circuit - Google Patents

Description

  The present invention relates to a negative power supply control circuit that controls a negative power supply of an electronic device.

  The electronic device includes a power supply device that generates a stable power supply voltage at each unit in the device. The power supply voltage is not limited to one, and two power supply voltages, positive and negative, are required for driving power for LCD (Liquid Crystal Display) and CCD (Charge Coupled Device). Since a portable terminal device such as a mobile phone is a single power source such as a battery, a negative power source circuit is used to generate a negative power source voltage. For example, a negative voltage is generated by a voltage inversion type DC / DC converter to drive a device that requires a negative power source.

  As a technique for generating such a negative voltage, a voltage inversion type charge pump circuit that repeats charge transfer between a charging capacitor and an output capacitor is widely used.

  Normally, a negative power supply circuit is not configured as a single power supply device, but may be built in a multi-output power supply device together with a power supply circuit such as a step-down converter or boost converter that outputs other positive power supply voltage. Is almost. This is because it is not necessary to configure the input power supply with a reverse polarity for a load circuit operating with a single power supply voltage. In many cases, the negative power supply voltage is activated after power is supplied to a logic circuit unit such as a CPU and the initial state is determined.

  Patent Document 1 describes a power supply device having a negative power supply circuit that is excellent in safety and does not output a positive voltage before starting. A power supply device having a negative power supply circuit described in Patent Document 1 includes a voltage converter that outputs a negative output voltage from a positive input voltage, a positive reference voltage source, a first switch, and a plurality of resistors. And a detection circuit configured to detect the output voltage, and an error amplifier that inputs a connection point potential and a ground potential of the plurality of resistors and outputs a signal for controlling the voltage conversion unit.

  FIG. 1 is a block diagram of a negative power supply control circuit that controls a negative power supply.

As shown in FIG. 1, the negative power supply control circuit 10 that controls the negative power supply includes a negative voltage input terminal Vin ⁻ , a control terminal Vcont, a GND connection terminal, and a negative voltage output terminal Vo ⁻ .

  The negative power source is a general negative power source circuit that rectifies and smoothes a back electromotive voltage generated in an inductor by a switching operation of a switch by a diode and an output capacitor. The negative power source is an inverting charge pump that switches the flying capacitor in the same phase / in reverse phase.

In the above configuration, the negative power supply control circuit 10, the negative voltage input terminal Vin ^- a negative voltage is input, a negative voltage output terminal Vo ^- outputs a negative voltage. Also, a negative control voltage is input to the control terminal Vcont.

JP 2008-86135 A

  However, since such a conventional negative power supply control circuit is controlled by a negative control voltage, there is a problem that it cannot be directly controlled by a microcomputer having a positive control voltage.

If there is no control terminal itself, the power supply Vin ^- inevitably the operation by only. Since there is no control terminal, it is difficult to control the startup sequence.

  An object of the present invention is to provide a negative power supply control circuit configured by a CMOS process.

  The negative power supply control circuit of the present invention is a negative power supply control circuit that controls a negative power supply with a positive voltage control signal, the source is connected to the positive voltage control voltage input terminal, the gate is connected to the GND connection terminal, A PMOS transistor having a back gate connected to the source potential; an NMOS transistor having a drain connected to the drain of the PMOS transistor; a gate and a source connected to a negative voltage input terminal; and a drain of the PMOS transistor and the NMOS transistor. A clamp circuit connected between a drain connection point, the GND connection terminal, and the negative voltage input terminal and clamping the potential at the connection point to the GND potential is adopted.

  According to the present invention, it is possible to realize a negative power supply control circuit of positive voltage control configured by a CMOS process.

Block diagram of a negative power supply control circuit for controlling a conventional negative power supply The circuit diagram which shows the structure of the negative power supply control circuit which concerns on embodiment of this invention The figure which shows the control characteristic of the negative power supply control circuit of the said embodiment

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment)
FIG. 2 is a circuit diagram showing a configuration of a negative power supply control circuit according to one embodiment of the present invention. This embodiment is an example applied to a negative power supply control circuit configured by a CMOS process.

As shown in FIG. 2, the negative power supply control circuit 100 includes a positive voltage control voltage input terminal Vcont, a GND connection terminal, a negative voltage input terminal Vin ⁻ , and a negative voltage output terminal Vo ⁻ .

The negative power supply control circuit 100 has a resistor R connected between the input terminal Vcont and the GND connection terminal, a back gate as a source potential, a source connected to the input terminal Vcont via the resistor R1, and a gate connected to GND. A P-channel MOS transistor M1 (referred to as PMOS transistor M1) connected to the terminal, a drain connected to the drain of a depletion N-channel MOS transistor M2 (referred to as NMOS transistor M2), a drain connected to the drain of the PMOS transistor M1, a gate and An NMOS transistor M2 having a source connected to the negative voltage input terminal Vin ⁻ , a connection point a between the drain of the PMOS transistor M1 and the drain of the NMOS transistor M2, the GND connection terminal and the negative voltage input terminal Vin ⁻ ; Connection point a And a regulator amplifier 140 to be output to ^- a clamp circuit 130 for clamping the potential to substantially GND potential, to stabilize the potential of the connection point a negative voltage output terminal Vo.

Resistor R, when turning off the control voltage Vcont, the negative voltage input terminal Vin ^- prevents the Vcont is drawn into the negative voltage. The resistor R causes the PMOS transistor M1 to operate stably.

  The resistor R1 and the PMOS transistor M1 constitute a VI conversion circuit 110 that converts the control voltage Vcont into a current I1 at a voltage equal to or higher than the GND potential. The resistor R1 and the PMOS transistor M1 pass a control current I1 that is substantially proportional to the control voltage Vcont.

  The PMOS transistor M1 has a source connected to the input terminal Vcont that is a positive voltage, a gate connected to the GND connection terminal, and a drain connected to the drain of the NMOS transistor M2. Further, the PMOS transistor M1 has no parasitic even when operated at a voltage higher than the GND potential by setting the back gate as the source potential. In other words, the PMOS transistor M1 can be operated at a voltage equal to or higher than the GND potential without forming a parasitic diode by setting the back gate to the source potential.

The NMOS transistor M2 is connected in series with the PMOS transistor M1, and constitutes an IV conversion circuit 120 in which a gate and a source are connected, a drain current I2 is supplied, and a potential appears at the connection point a of the drain. The potential at the connection point a is input to the clamp circuit 130 as the control signal _VA and is supplied to the regulator amplifier 140.

The clamp circuit 130 includes an inverter 131 including a PMOS transistor M3 and an NMOS transistor M4 whose control signal _VA is input to a common gate, and a depletion N-channel MOS transistor that connects a gate and a source and supplies a constant current that drives the inverter 131 comprises PMOS transistors M6 and M7 clamps the drain voltage to the GND potential (second PMOS transistor) - M5 (referred NMOS transistors M5), based on the output signal _{V B} of the inverter 131, the source of the PMOS transistor M1.

  The source of the PMOS transistor M3 constituting the inverter 131 is connected to the GND connection terminal, the gate is connected to the gate and the common gate of the NMOS transistor M4, and the drain is the drain connection point b of the NMOS transistor M4. The source of the NMOS transistor M4 is connected to the drain of the NMOS transistor M5, the gate is connected to the gate and the common gate of the PMOS transistor M3, and the drain is the drain connection point b of the PMOS transistor M3.

The inverter 131 is an operating voltage between GND and the drain of the NMOS transistor M5, and inverts and outputs the control signal _VA connected to the common gate to the drain connection point b. The output signal V _{B at the} drain connection point b is connected to the drain of the PMOS transistor M6 and the common gate of the PMOS transistor M7.

NMOS transistor M5 has a drain connected to the inverter 131, a gate and a source negative voltage input terminal Vin ^- connects to and operates the inverter 131.

The source of the PMOS transistor M6 is connected to the GND connection terminal, a gate connected to the output signal _{V B} together with the gate of the PMOS transistor M7, the drain is connected to the output signal _{V B.} The gate-source voltage of the PMOS transistor M6 is set to V _GS6 .

The source of the PMOS transistor M7 is connected to the drain of the PMOS transistor M1, a gate connected to the output signal _{V B} together with the gate of the PMOS transistor M6, the drain is negative voltage input terminal Vin ^- is connected to. The gate-source voltage of the PMOS transistor M7 is set to V _GS7 .

  Hereinafter, the operation of the negative power supply control circuit 100 configured as described above will be described.

The source-drain current I1 of the PMOS transistor M1 and the source-drain current I2 of the NMOS transistor M2 are assumed. The control signal V _{A at} the connection point a between the drain of the PMOS transistor M1 and the drain of the NMOS transistor M2 is connected to the input of the inverter 131 of the clamp circuit 130 and the gate of the PMOS transistor M7 of the clamp circuit 130 and to the regulator amplifier 140. Supplied.

[When Vcont = Low]
I1 <I2 and V _A = Low.

The inverter 131 (PMOS transistor M3 and NMOS transistor M4) has an output signal V _B = GND when the PMOS transistor M3 is turned on and the threshold voltage of the PMOS transistor M3 is ignored.

With V _B = GND, the PMOS transistors M6 and M7 of the clamp circuit 130 are turned off, and the current consumption during standby can be reduced to zero.

[When Vcont = High]
I1 ≧ I2 and V _A = High.

The inverter 131 (PMOS transistor M3 and NMOS transistor M4) becomes V _B = GND−V _GS6 when the PMOS transistor M4 is turned on. V _GS6 is determined by the constant current of the NMOS transistor M5.

The control signal V _A becomes High. Then, the control signal V _A is clamped by V _A = V _B + V _GS7 .

_Here, setting the _{V GS6} ≒ _{V GS7,} the _{V A = V B + V GS7} = GND-V GS6 + V GS7 ≒ GND.

Since _VA is clamped to almost the GND potential, it operates without exceeding the standard breakdown voltage of each element.

  FIG. 3 is a diagram illustrating the input / output characteristics of the negative power supply control circuit 100. As shown in FIG. 3, the control output voltage for controlling the negative power supply can be linearly obtained from the positive control voltage.

As described above in detail, according to the present embodiment, the negative power supply control circuit 100 includes the resistor R connected between the positive control voltage input terminal Vcont and the GND connection terminal and the source connected to the positive voltage. The PMOS transistor M1 is connected to the control voltage input terminal Vcont, the gate is connected to the GND connection terminal, and the back gate is connected to the source potential. The negative power supply control circuit 100 has a drain connected to the drain of the PMOS transistor M1, the gate and source negative voltage input terminal Vin ^- comprises NMOS transistor M2 to be connected to. The negative power supply control circuit 100 is connected between the connection point a between the drain of the PMOS transistor M1 and the drain of the NMOS transistor M2, the GND connection terminal, and the negative voltage input terminal Vin ^−, and the potential at the connection point a is substantially reduced. and a regulator amplifier 140 to be output to ^- a clamp circuit 130 for clamping the GND potential, to stabilize the potential of the connection point a negative voltage output terminal Vo.

  Thereby, the following effects can be acquired.

  (1) A negative power source using a CMOS process can be provided with an on / off control function.

  (2) On / off control for a negative power supply can be controlled by a positive voltage of a microcomputer or the like. Because it is positive voltage control, it can be controlled by a normal microcomputer port.

  (3) The threshold of the control voltage is a TTL (Transistor-Transistor Logic) level. It can be applied to general microcomputer ports.

  (4) Since it can be configured by a standard CMOS process, the cost can be reduced.

  (5) Since it is manufactured by a CMOS process, low current consumption is possible.

  (6) A high breakdown voltage element is not required, and a standard breakdown voltage CMOS process can be used. In particular, by using the withstand voltage of the PMOS transistor M6 of the clamp circuit 130, it is not necessary to design the withstand voltage of the PMOS transistor M1 to be particularly high, and it can be configured with the same withstand voltage as other MOS transistors. Thereby, cost reduction can be achieved.

  (7) Current consumption during standby (when Vc = 0 V in FIG. 2) can be made zero.

(8) for comparing the M2 and M1 of the current, Vin ^- it is possible to set the threshold without being affected by the power variation.

  The above description is an illustration of a preferred embodiment of the present invention, and the scope of the present invention is not limited to this.

  For example, the negative power supply may be any negative power supply circuit, and the same effect can be obtained.

  In the above embodiment, an example using a MOS transistor has been described, but any transistor may be used. For example, a MIS (Metal Insulated Semiconductor) transistor may be used. The MIS transistor may be a MIS transistor formed on a silicon substrate having an SOI (Silicon On Insulator) structure. Furthermore, Bi-CMOS or a combination thereof may be used. However, it goes without saying that MOS transistors are advantageous in terms of power consumption.

  In the above-described embodiment, the name “negative power supply control circuit” is used. However, this is for convenience of explanation, and it goes without saying that a negative power supply control circuit, a negative power supply circuit, or the like may be used.

  Furthermore, the circuit units constituting the negative power supply control circuit, for example, the number of transistors of the clamp circuit, the type of elements, etc. are not limited to the above-described embodiments. Needless to say, various compensation transistors may be added to the negative power supply control circuit.

  The negative power supply control circuit according to the present invention can be applied to all power supply devices that control the negative power supply of electronic devices that require two types of positive and negative power supply voltages, such as LCDs and CCDs.

DESCRIPTION OF SYMBOLS 100 Negative power supply control circuit 110 VI conversion circuit 120 IV conversion circuit 130 Clamp circuit M1, M3, M6, M7 P channel MOS transistor M2, M5 Depletion N channel MOS transistor M4 N channel MOS transistor Vcont Control voltage of positive voltage Input terminal GND GND connection terminal Vin ^- Negative voltage input terminal Vo ^- Negative voltage output terminal

Claims (5)

A negative power supply control circuit for controlling a negative power supply with a positive voltage control signal,
A PMOS transistor having a source connected to a positive control voltage input terminal, a gate connected to a GND connection terminal, and a back gate connected to a source potential;
An NMOS transistor having a drain connected to the drain of the PMOS transistor and a gate and a source connected to a negative voltage input terminal;
A clamp circuit connected between a connection point of the drain of the PMOS transistor and the drain of the NMOS transistor, the GND connection terminal, and the negative voltage input terminal, and clamps the potential of the connection point to the GND potential;
A negative power supply control circuit.   The negative power supply control circuit according to claim 1, further comprising a resistor connected between the control voltage input terminal and the GND connection terminal.   The negative power supply control circuit according to claim 1, further comprising a regulator amplifier that stabilizes the potential at the connection point and outputs the stabilized potential to a negative voltage output terminal. The clamp circuit is an operating voltage between the GND connection terminal and the negative voltage input terminal, and an inverter that inverts and outputs a control signal connected to a common gate;
The negative power supply control circuit according to claim 1, further comprising: a second PMOS transistor that clamps a source-drain voltage of the PMOS transistor to a GND potential based on an output signal of the inverter. The negative power supply control circuit according to claim 1, wherein the NMOS transistor is a depletion N-channel MOS transistor.

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