JP2013207413A - Inverting buffer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inverting buffer circuit that suppresses a signal distortion due to a change in resistance value under the influence of a potential of a semiconductor substrate or the like around a resistive element layer.SOLUTION: The inverting buffer circuit includes a first resistive element R1 as an input resistance, and a second resistive element R2 as a feedback resistance. The first resistive element R1 includes a first resistive element layer formed on the semiconductor substrate via an insulating layer. The second resistive element R2 includes a second resistive element layer formed on the semiconductor substrate via an insulating layer with one end being connected to one end of the first resistive element layer, and a first conductive layer arranged under or over the second resistive element layer and biased by a predetermined bias potential based on a potential of the other end of the second resistive element layer. Where a resistance ratio of a resistance value of the first resistive element R1 to a resistance value of the second resistive element R2 is 1:x (1≤x), a voltage value of the predetermined bias potential is (x+1)/(2x) times the potential of the other end of the second resistive element layer.

Description

  The present invention relates to an inverting buffer circuit including a resistance element, and more particularly to an inverting buffer circuit configured to suppress signal distortion caused by a change in resistance value of the resistance element.

In a semiconductor integrated circuit, a desired electronic circuit is configured by combining elements such as a resistance element, a capacitor, and a transistor. For this reason, it is desirable that the characteristics of each element remain as small as possible. Taking a resistance element as an example, the change in resistance value of the resistance element is not very preferable in constructing an electronic circuit.
However, the resistance element formed on the semiconductor substrate is made of polysilicon or a diffusion layer, and the depletion layer spreads by the potential difference between the potential of the semiconductor substrate in the periphery (upper surface and lower surface) and the potential of the resistance element. The state changes and the width of the conductive region changes. For this reason, the resistance value of the resistance element changes.

In the resistance element formed on the semiconductor substrate, the change in resistance value from the upper surface and the lower surface of the resistance element is essentially the same, so only the change from the lower surface will be discussed below.
Now, as shown in FIG. 9, the relationship between the resistance value R of the resistance element formed on the semiconductor substrate and the substrate potential V0 on the lower surface of the resistance element is expressed by the following equation.

Here, VA and VB are voltages applied to both ends of the resistance element, R0 is an ideal resistance value when there is no change in the resistance value of the resistance element, and k is a primary coefficient depending on the substrate voltage.
A semiconductor device (resistive element) 10 of Patent Document 1 as shown in FIG. 10 is known in order to suppress a change in resistance value due to such a potential with a peripheral semiconductor substrate or the like.

In this semiconductor device 10, a P-type diffusion region 13 is formed on the main surface of an N-type island region 12 formed on a P-type semiconductor substrate 11. On this surface, a first electrode 14 for applying a high potential voltage and a second electrode 15 for applying a low potential voltage are provided, and a high voltage is provided on the surface of the island region 12 outside the surface of the P-type diffusion region 13. A third electrode 16 for applying a potential voltage and a fourth electrode 17 for applying a low potential voltage are provided.
As a result, the semiconductor device 10 is configured such that the potential distribution of the island region 12 follows the potential distribution of the P-type diffusion region 13.

Japanese Patent Laid-Open No. 5-190773

By the way, when forming a resistance element in a semiconductor substrate, in order to suppress that a resistance value changes with the electric potential of the lower surface of a resistance element, the resistance element 20 as shown in FIG. 11 can be considered.
In the resistance element 20, a resistance element layer 23 having a first electrode 21 and a second electrode 22 is formed on a semiconductor substrate 24. The lower portion of the resistance element layer 23 is uniformly covered with the first conductive layer 25 biased by the potential of the first electrode 21 and the second conductive layer 26 biased by the potential of the second electrode 22. ing. As described above, the first conductive layer 25 and the second conductive layer 26 that cover at least one of the lower or upper portion of the resistive element layer 23 biased at both ends are connected to the semiconductor substrate 24 and the like around the resistive element layer 23. The change in the resistance value is suppressed by canceling out the change in the resistance value due to the voltage difference.

For example, when the semiconductor substrate 24 is a P-type substrate and the first conductive layer 25 and the second conductive layer 26 are N-type diffusion layers having a low impurity concentration called N-well, the resistance element 20 includes a semiconductor substrate. It is possible to apply a voltage greater than 24 potentials.
Further, as shown in FIG. 12, the semiconductor substrate 24 is a P-type substrate, and the first conductive layer 25 and the second conductive layer 26 are separated from the semiconductor substrate 24 by an N-well 24a to which the power supply voltage VDD is applied. In this case, a voltage equal to or lower than the power supply voltage can be applied to the resistance element.

FIG. 13 is a circuit diagram of a configuration of a general inverting buffer circuit 40 using the resistance element 20 shown in FIGS. 11 and 12.
The inverting buffer circuit 40 is configured using an operational amplifier (operational amplifier) 41 and resistance elements R10 and R20 including the resistance element 20. Further, the resistance values of the resistance elements R10 and R20 do not change depending on the potential with the surrounding semiconductor substrate or the like. For this reason, the inverting buffer circuit 40 has the same gain when the input signal is at a high voltage and when the input signal is at a low voltage, and no distortion occurs in the output.

  However, the inverting buffer circuit 40 uses the resistance element 20 shown in FIGS. Therefore, when the semiconductor substrate 24 is a P-type substrate, the junction capacitance between the first conductive layer 25 and the second conductive layer 26 and the semiconductor substrate 24 or between the N-well 24a to which the power supply voltage VDD is applied is obtained. Thus, noise superimposed on the substrate voltage or the power supply voltage may be superimposed on the signal voltage at the negative input terminal (−) of the operational amplifier 41 serving as a high impedance node.

Further, since the first conductive layer 25 and the second conductive layer 26 are electrically separated, the entire area of the resistive element 20 is increased as compared to the area of the resistive element layer 23 alone, and the layout of the inverting buffer circuit 40 is increased. The area increases.
In view of the above problems, the present invention provides an inversion buffer that can suppress signal distortion caused by a change in resistance value under the influence of a potential of a semiconductor substrate or the like around a resistance element layer. An object is to provide a circuit.

In order to achieve the above object, the present invention has the following configuration.
One aspect of the present invention is an inverting buffer circuit including an input resistance element and a feedback resistance element. The first resistance element includes a first resistance element layer formed on a semiconductor substrate with an insulating layer interposed therebetween, and one end of the first resistance element is the first resistance element. A second resistive element layer connected to one end of the first resistive element layer and formed on the semiconductor substrate via an insulating layer; and a second resistive element layer disposed below or above the second resistive element layer. A first conductive layer biased at a predetermined bias potential based on an end potential, and the first resistive element and the second resistive element are the input resistive element. And when the resistance ratio of the resistance value of the first resistance element and the resistance value of the second resistance element is 1: x (1 ≦ x), The voltage value is other than the second resistance element layer. Characterized in that (x + 1) / (2x) a fold with respect to the potential.

According to the present invention, without adding a path for a substrate voltage or a noise signal superimposed on a power supply voltage, a semiconductor substrate around the resistive element layer, a power supply line passing through the upper part of the resistive element layer, a signal line, etc. Thus, it is possible to provide an inverting buffer circuit or the like that can suppress signal distortion caused by a change in resistance value under the influence of the potential of the.
Further, since the number of portions where the potential of the lower or upper portion of the resistive element layer is controlled by the conductive layer is reduced, an increase in layout area due to the separation of the conductive layer is suppressed.

1 is a circuit diagram showing a configuration of a first embodiment of an inverting buffer circuit of the present invention. FIG. FIG. 2 is a circuit diagram showing a configuration of a voltage control circuit shown in FIG. 1. It is a top view (top view) which shows the structure of the resistive element group shown in FIG. It is sectional drawing of the AA line of FIG. It is a circuit diagram which shows the structure of 2nd Embodiment of the inversion buffer circuit of this invention. It is a circuit diagram which shows the structure of 3rd Embodiment of the inversion buffer circuit of this invention. It is a top view which shows the structure of the resistive element group shown in FIG. It is sectional drawing of the AA line of FIG. It is a figure explaining the relationship between the resistance value of the resistive element formed on a semiconductor substrate, and the electric potential of the lower surface of the resistive element. It is sectional drawing of the conventional resistive element. It is sectional drawing of the resistive element considered in order to suppress that a resistance value changes with the electric potential of the lower surface of a resistive element, when forming a resistive element in a semiconductor substrate. When forming a resistance element in a semiconductor substrate, it is sectional drawing of the other resistance element considered in order to suppress that a resistance value changes with the electric potential of the lower surface of a resistance element. FIG. 13 is a circuit diagram of a conventional inverting buffer circuit using the resistance element shown in FIGS. 11 and 12.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First Embodiment)
FIG. 1 is a circuit diagram showing a configuration of a first embodiment of an inverting buffer circuit according to the present invention.
As shown in FIG. 1, the inverting buffer circuit 100 according to the first embodiment includes a signal input terminal 101, a signal output terminal 102, an operational amplifier 300, and a resistance element group 200 including two resistance elements R1 and R2. The voltage control circuit 400 is provided.

An input voltage VIN that is an input signal is supplied to the signal input terminal 101. An output voltage VOUT that is an output signal is output from the signal output terminal 102.
The operational amplifier 300 has a negative input terminal (−), a positive input terminal (+), and an output terminal. A reference voltage (common voltage) VCOM is applied to the positive input terminal (+) of the operational amplifier 300, and the output terminal of the operational amplifier 300 is connected to the signal output terminal 102.

As shown in FIG. 1, the resistive element group 200 includes two resistive elements R1 and R2, which are connected in series. The resistance values of the resistance elements R1 and R2 are in a ratio of 1: x using a real number x (1 ≦ x) (see FIG. 1). In the resistance element group 200 of FIG. 1, each of N1 to N4 represents a node.
The resistance element R <b> 1 functions as an input resistance element and is connected between the signal input terminal 101 and the negative side input terminal (−) of the operational amplifier 300.

The resistance element R2 functions as a feedback resistance element, and the node N2 side which is one end thereof is connected to the negative side input terminal (−) of the operational amplifier 300, and the node N3 side which is the other end is the output terminal and the signal output terminal 102 of the operational amplifier 300. It is connected to the.
In the inverting buffer circuit 100 configured as described above, since the resistance ratio of the resistance element R1 corresponding to the input resistance and the resistance element R2 corresponding to the feedback resistance is 1: x, the input voltage VIN having the common voltage VCOM is amplified by the amplification factor x (1 ≦ x) is an electronic circuit to be amplified.

Further, the resistance element R2 is provided with a conductive layer 205 as shown in FIG. The node N4 related to the conductive layer 205 is biased with a predetermined bias potential output from the voltage control circuit 400.
The voltage control circuit 400 receives the voltage of the node N3 at the input terminal IN, generates an output voltage based on the input voltage, and outputs the generated voltage from the output terminal OUT to the conductive layer 205 below the resistance element R2. . That is, when the amplification factor of the inverting buffer circuit 100 is x, the voltage control circuit 400 uses the input voltage of the input terminal IN (the output voltage VOUT of the signal output terminal 102) as the reference and the (x + 1) based on the common voltage VCOM. ) / (2x) times the voltage, and this generated voltage is output from the output terminal OUT to the conductive layer 205 below the resistor element R2.

Therefore, the voltage control circuit 400 includes an input terminal IN, an output terminal OUT, and two resistance elements R401 and R402 as shown in FIG. 2, for example.
The input terminal IN is connected to the node N3 side of the resistance element R2. The output terminal OUT is connected to the conductive layer 205. The resistance element R401 is connected between the input terminal IN and the output terminal OUT. One end of the resistance element R401 is connected to the output terminal OUT, and a common voltage VCOM is applied to the other end. The ratio of the resistance values of the resistance elements R401 and R402 is (x-1) / 2: (x + 1) / 2.

Next, a specific configuration of the resistance element group 200 shown in FIG. 1 will be described with reference to FIGS. 3 and 4. 3 is a plan view of the resistance element group 200 as viewed from above, and FIG. 4 is a cross-sectional view taken along line AA of FIG.
As shown in FIGS. 3 and 4, the resistance element group 200 includes two resistance elements R1 and R2, which are formed on a P-type substrate 208, which is a semiconductor substrate.

The resistance element R1 includes a resistance element layer 201 made of polysilicon or the like. The resistance element layer 201 is formed on the P-type substrate 208 via an interlayer insulating film 203 such as silicon oxide (SiO 2) which is an insulating layer. The node N 1 side of the resistance element 201 is connected to the signal input terminal 101.
The resistance element R2 includes a resistance element layer 202 made of polysilicon, and a conductive layer 205 that is disposed below the resistance element layer 202 and to which a bias potential is applied. The node N2 side of the resistive element layer 202 is connected to the node N2 side of the resistive element layer 201. The node N3 side of the resistance element layer 202 is connected to the input terminal IN and the signal output terminal 102 of the voltage control circuit 400, respectively.

  The resistance element layer 202 is formed on the P-type substrate 208 via an interlayer insulating film 204 such as silicon oxide. The conductive layer 205 is disposed below the resistance element layer 202 and is formed of a P-well. The conductive layer 205 is separated from the P-type substrate 208 by an N-type diffusion layer (N-well) 207 having a low impurity concentration. Further, a P-type diffusion layer 206 having a high impurity concentration called P + is formed in the conductive layer 205. The conductive layer 205 is connected to the output terminal OUT of the voltage control circuit 400 by the diffusion layer 206.

  In the resistance element group 200 having such a configuration, the resistance element R1 includes a P-type substrate 208 that is grounded to VSS via the interlayer insulating film 203 below the resistance element layer 201. The resistance element R2 includes a conductive layer 205 below the resistance element layer 202 with an interlayer insulating film 204 interposed therebetween. An output voltage from the output terminal OUT of the voltage control circuit 400 is applied to the conductive layer 205 as a bias voltage.

  3 and 4, the conductive layer 205 is disposed below the resistive element layer 202. Instead, the conductive layer is disposed above the resistive element layer 202. Anyway. In this case, the conductive layer is disposed on the resistance element layer 202 via an interlayer insulator. The replacement of this point is the same for the resistance element group of the embodiment described later.

Next, when the input voltage VIN is applied to the signal input terminal 101 of the inverting buffer circuit 100, the substrate voltage dependence of the resistance element is canceled out in the output voltage VOUT from the signal output terminal 102, and no distortion is generated in the signal. This will be described below.
Now, assuming that the applied voltage (V1) of the node N1 is V (N1) = VIN + VCOM, ignoring a minute change due to the substrate voltage dependency of the resistance value, the voltages of the nodes N2 to N4 are V (N2), V (N3) and V (N4) are as follows.

V (N2) = VCOM
V (N3) = − xVIN + VCOM
V (N4) =-{(x + 1) / 2} VIN + VCOM
At this time, when the ideal resistance value R of the resistance element R1 is set, the ideal resistance value of the resistance element R2 is xR.

It should be noted that ignoring a minute voltage change at each node due to a minute change due to the substrate voltage dependency of the resistance value is equivalent to ignoring a high-order term with respect to a minute quantity k in the above equation (2). , Usually not a problem.
Subsequently, using this resistance value, the transfer function of the inverting buffer circuit 100 is obtained in a linear range with respect to the minute amount k as follows.

That is, the inverting buffer circuit 100 according to the first embodiment means that the transfer function at the output voltage VOUT does not change with the input voltage VIN, and the signal is not distorted.
Further, since no extra parasitic capacitance is added to the node N2 corresponding to the high impedance node, noise superimposed on the substrate voltage or the power supply voltage is not superimposed on the signal voltage due to the present invention.
Further, since the number of portions where the potential of the lower or upper portion of the resistive element layer is controlled by the conductive layer is reduced, an increase in layout area due to the separation of the conductive layer is suppressed.

(Second Embodiment)
FIG. 5 is a circuit diagram showing the configuration of the second embodiment of the inverting buffer circuit of the present invention.
As shown in FIG. 5, the inverting buffer circuit 500 according to the second embodiment includes a signal input terminal 501, a signal output terminal 502, an operational amplifier 300, and a resistance element group 200 including two resistance elements R1 and R2. The voltage control circuit 400 is provided.

An input voltage VIN that is an input signal is supplied to the signal input terminal 501. An output voltage VOUT that is an output signal is output from the signal output terminal 502.
The operational amplifier 300 has a negative input terminal (−), a positive input terminal (+), and an output terminal. A reference voltage (common voltage) VCOM is applied to the positive input terminal (+) of the operational amplifier 300, and the output terminal of the operational amplifier 300 is connected to the signal output terminal 502.

  Resistance element group 200 is configured in the same manner as resistance element group 200 shown in FIGS. 1, 3, and 4. However, since the resistance element R2 functions as an input resistance element, it is connected between the signal input terminal 501 and the negative side input terminal (−) of the operational amplifier 300. The resistor element R1 functions as a feedback resistor element, and the node N2 side which is one end thereof is connected to the negative side input terminal (−) of the operational amplifier 300, and the node N1 side which is the other end is connected to the output terminal and signal output of the operational amplifier 300. The terminal 502 is connected.

The resistance element R2 is provided with a conductive layer 205 as shown in FIG. The node N4 related to the conductive layer 205 is biased with a predetermined bias potential output from the output terminal OUT of the voltage control circuit 400.
The voltage control circuit 400 receives the voltage of the node N3 (the input voltage VIN of the input signal terminal 501) at the input terminal IN, generates an output voltage based on the input voltage, and generates the generated voltage from the output terminal OUT as a resistance element. Output to the conductive layer 205 below R2. Here, the voltage control circuit 400 is configured as shown in FIG.

In the inverting buffer circuit 500 having such a configuration, since the resistance ratio of the resistance element R1 corresponding to the feedback resistance and the resistance element R2 corresponding to the input resistance is x: 1, the input voltage is attenuated by 1 / x when the common voltage is VCOM. The electronic circuit is attenuated to (1 ≦ x).
Further, the voltage control circuit 400 generates a voltage (x + 1) / (2x) times based on the common voltage VCOM based on the input voltage of the input terminal IN (the input voltage VIN of the signal input terminal 501). The generated voltage is output from the output terminal OUT to the conductive layer 205 below the resistance element R2.

At this time, like the inverting buffer circuit 100 shown in FIG. 1, the inverting buffer circuit 500 does not change the transfer function at the output voltage VOUT by the input voltage VIN, and does not distort the signal.
Further, since no extra parasitic capacitance is added to the node N2 corresponding to the high impedance node, noise superimposed on the substrate voltage or the power supply voltage does not overlap the signal voltage.
Furthermore, since the number of portions where the potential of the lower or upper portion of the resistive element layer is controlled by the conductive layer is reduced, an increase in the layout area accompanying the conductive layer separation is suppressed.

(Third embodiment)
FIG. 6 is a circuit diagram showing a configuration of a third embodiment of the inverting buffer circuit of the present invention.
As shown in FIG. 6, the inverting buffer circuit 600 according to the third embodiment includes a signal input terminal 601, a signal output terminal 602, an operational amplifier 300, a resistor element group 700, semiconductor switches SW1 to SW3, a voltage, The control circuit 400a is provided, and the gain can be varied by using the switches SW1 to SW3.

An input voltage VIN that is an input signal is supplied to the signal input terminal 601. An output voltage VOUT, which is an output signal, is output from the signal output terminal 602.
The operational amplifier 300 has a negative input terminal (−), a positive input terminal (+), and an output terminal. A reference voltage (common voltage) VCOM is applied to the positive input terminal (+) of the operational amplifier 300, and the output terminal of the operational amplifier 300 is connected to the signal output terminal 602.

The resistance element group 700 includes one resistance element R1 and three resistance elements R2 to R4. The resistance element group 700 includes nodes N1 to N7 as shown in FIG. In addition, the resistance ratio of the resistance elements R1 to R6 of the resistance element group 900 has the following relationship.
R1: R2: R3: R4 = 1: 2: 1: 1
The resistor element R1 functions as an input resistor element, and is connected between the signal input terminal 601 and the negative input terminal (−) of the operational amplifier 300.

The resistance elements R2 to R4 function as feedback resistance elements and are connected in series. Then, by using the switches SW1 to SW3, all or a part of the resistance elements R2 to R4 is selected, and the selected resistance element is placed between the negative side input terminal (−) and the output terminal of the operational amplifier 300. It can be connected freely.
For this reason, the node N3 which is one end of the resistance element R2 is connected to the negative side input terminal (−) of the operational amplifier via the switch SW3. A node N4 that is a common connection point of the resistance elements R2 and R3 and a node N5 that is a common connection point of the resistance elements R3 and R4 are respectively connected to the negative input terminal (−) of the operational amplifier via the switches SW2 and SW1. Has been. Further, a node N6 which is one end of the resistance element R4 is connected to the output terminal of the operational amplifier 300 and the signal output terminal 602.

Further, each of the resistance elements R2 to R4 is provided with a common conductive layer 705 as shown in FIG. The node N7 at one end of the conductive layer 705 is biased by a predetermined bias potential output from the voltage control circuit 400a.
The voltage control circuit 400a inputs the voltage of the node N6 to the input terminal IN, generates an output voltage based on the input voltage, and generates the generated voltage from the output terminal OUT to the conductive layers 705 below the resistance elements R2 to R4. Output to. That is, the voltage control circuit 400a generates a desired voltage based on the input voltage of the input terminal IN (the output voltage VOUT of the signal output terminal 602) with reference to the common voltage VCOM, and this generated voltage is output from the output terminal OUT. This circuit outputs to the conductive layer 705 below the resistance elements R2 to R4.

Therefore, the voltage control circuit 400a includes an input terminal IN, an output terminal OUT, three resistance elements R401 to R403, and three semiconductor switches SW4 to SW6, as shown in FIG. 6, for example.
The input terminal IN is connected to a node N6 that is one end of the resistance element R4. The output terminal OUT is connected to a common conductive layer 705 below the resistance elements R2 to R4.

The three resistance elements R401 to R403 are connected in series, one end of the series circuit is connected to the input terminal IN, and the common voltage VCOM is applied to the other end of the series circuit. The resistance ratio of the resistance elements R401, R402, and R403 is 2: 1: 5.
The switch SW4 has one end connected to one end of the resistance element R401 and the other end connected to the output terminal OUT. One end of the switch SW5 is connected to the node N8 which is a common connection portion of the resistance elements R401 and R402, and the other end is connected to the output terminal OUT. One end of the switch SW6 is connected to the node N9 which is a common connection portion of the resistance elements R402 and R403, and the other end is connected to the output terminal OUT.

Next, a specific configuration of the resistance element group 700 illustrated in FIG. 6 will be described with reference to FIGS. 7 and 8. 7 is a plan view of the resistance element group 700, and FIG. 8 is a cross-sectional view taken along line AA of FIG.
As shown in FIGS. 7 and 8, the resistance element group 700 includes four resistance elements R1 to R4, which are formed on a P-type substrate 708 which is a semiconductor substrate.

The resistance element R1 includes a resistance element layer 701 made of polysilicon. The resistance element layer 701 is formed on a P-type substrate 708 via an interlayer insulating film 703 such as silicon oxide (SiO 2) that is an insulating layer. The node N1 side of the resistance element layer 701 is connected to the signal input terminal 601.
Each of the resistance elements R2 to R4 includes a resistance element layer 702 made of polysilicon and a common conductive layer 705 that is disposed below the resistance element layer 702 and to which a bias potential is applied. Each anti-element layer 702 is formed on a P-type substrate 708 via an interlayer insulating film 704 such as silicon oxide. The conductive layer 705 is disposed below the three resistance element layers 702 and is formed of a P-well. The conductive layer 705 is separated from the P-type substrate 708 by an N-type diffusion layer (N-well) 707 having a low impurity concentration. Further, a P-type diffusion layer 706 having a high impurity concentration called P + is formed in the conductive layer 705.

The three resistance element layers 702 related to the resistance elements R2 to R4 are connected in series by nodes N4 and N5. The common conductive layer 705 related to the resistance elements R <b> 2 to R <b> 4 is connected to the node 7. Furthermore, the node N6 side of the resistance element layer 702 related to the resistance element R4 is connected to the input terminal IN and the signal output terminal 602 of the voltage control circuit 400a.
In the resistance element group 700 having such a configuration, the resistance element R1 includes a P-type substrate 708 grounded to VSS via an interlayer insulating film 703 below the resistance element layer 701. In addition, each of the resistance elements R <b> 2 to R <b> 4 includes a conductive layer 705 via an interlayer insulating film 704 below the resistance element layer 702. Then, the output voltage from the output terminal OUT of the voltage control circuit 400a is applied to the conductive layer 705 as a bias voltage.

Next, an operation example of the third embodiment will be described with reference to FIG.
In the third embodiment, the resistor element R4 is selected as a feedback resistor by turning on the switch SW1, and this can be connected between the negative side input terminal (−) and the output terminal of the operational amplifier 300. Similarly, the resistance elements R3 and R4 are selected as feedback resistors by turning on the switch SW2, and the resistance elements R2 to R4 are selected as feedback resistors by turning on the switch SW3. It can be connected between the input terminal (−) and the output terminal.

  Therefore, in the third embodiment, by selectively turning on SW1 to SW3, the ratio of the resistance element R1 corresponding to the input resistance and the resistance elements R2 to R4 corresponding to the feedback resistance is 1: 1, 1: 2. , 1: 4, and functions as an inverting buffer circuit or an electronic volume circuit that can change the amplification factor of the input voltage VIN, which is an input signal, by 1, 2 or 4 times.

At this time, in the third embodiment, by appropriately controlling the semiconductor switches SW4 to SW6, the power supply line passing through the semiconductor substrate around the resistive element layer and the upper part of the resistive element layer at all amplification factors. The signal distortion caused by the change of the resistance value due to the influence of the potential of the signal line or the like does not occur. This will be described below.
First, when the amplification factor is 1, the switches SW1 and SW4 are turned on, and the switches SW2, SW3, SW5, and SW6 are turned off. At this time, since the inverting buffer circuit 600 is equivalent to the case where the amplification factor x of the inverting buffer circuit 100 in FIG. 1 is 1, the transfer function at the output voltage VOUT is not changed by the input voltage VIN, and the signal is not distorted. .

Next, when the amplification factor is double, the switches SW2 and SW5 are turned on, and the switches SW1, SW3, SW4, and SW6 are turned off. At this time, since the inverting buffer circuit 600 is equivalent to the case where the amplification factor x of the inverting buffer circuit 100 in FIG. 1 is 2, the transfer function at the output voltage VOUT is not changed by the input voltage VIN, and the signal is not distorted. .
Further, when the amplification factor is four times, the semiconductor switches SW3 and SW6 are turned on, and SW1, SW2, SW4 and SW5 are turned off. At this time, since the inverting buffer circuit 600 is equivalent to the case where the amplification factor x of the inverting buffer circuit 100 in FIG. 1 is 4, the transfer function at the output voltage VOUT is not changed by the input voltage VIN, and the signal is not distorted. .

  As described above, in the inverting buffer circuit 600 according to the third embodiment, the potential below the feedback resistor is biased with an appropriate voltage by the voltage control circuit 400a for each amplification factor. For this reason, signal distortion caused by the change in the resistance value occurs due to the influence of the potential of the semiconductor substrate around the resistive element layer, the power supply line passing through the upper part of the resistive element layer, the signal line, etc. Can be prevented.

Further, in the inverting buffer circuit 600 of FIG. 6, when the gain setting is increased, the potential of the entire lower part of the feedback resistance element group may be controlled to an appropriate voltage by the voltage control circuit. At this time, it is not necessary to separate the conductive layer under the feedback resistor in accordance with each gain, so that an increase in area can be minimized.
When there are a large number of gain settings, voltage control of the conductive layer below the feedback resistance element group need not necessarily be performed for all gain settings. Even if a voltage corresponding to the output voltage at a relatively close gain setting is applied to the lower portion of the resistor with respect to the set gain, a certain effect can be expected.

In the inverting buffer circuit 600 according to the third embodiment, if the resistance elements R2 to R4 of the resistance element group 700 are input resistances and the resistance element R1 is a feedback resistance, an inverting buffer circuit having an arbitrary attenuation factor is obtained. realizable.
In this case, the lower potential of the input resistance is biased with an appropriate voltage by the voltage control circuit 400a for an arbitrary attenuation rate, so that it passes through the semiconductor substrate around the resistive element layer and the upper part of the resistive element layer. It is possible to prevent the occurrence of signal distortion due to the change of the resistance value under the influence of the potential of the power line, the signal line and the like.

  The inverting buffer circuit of the present invention can be applied to various electronic devices that require a buffer circuit.

R1 to R4, R401 to R403 Resistive elements SW1 to SW6 Semiconductor switches (switches)
100, 500, 600 Inverting buffer circuit 101, 501, 601 Signal input terminal 102, 502, 602 Signal output terminal 200, 700 Resistive element group 201, 202, 701, 702 Resistive element layer 203, 204, 703, 704 Insulating layer 205 , 705 Conductive layer 208, 708 P-type substrate (semiconductor substrate)
300 Operational amplifier 400, 400a Voltage control circuit

Claims (7)

In an inverting buffer circuit including an input resistance element and a feedback resistance element,
A first resistive element comprising a first resistive element layer formed on a semiconductor substrate via an insulating layer;
One end is connected to one end of the first resistance element layer, the second resistance element layer is formed on the semiconductor substrate through an insulating layer, and the second resistance element layer is disposed below or above the second resistance element layer. A second resistive element comprising: a first conductive layer biased at a predetermined bias potential based on a potential at the other end of the element layer;
The first resistance element and the second resistance element are either the input resistance element or the feedback resistance element,
When the resistance ratio between the resistance value of the first resistance element and the resistance value of the second resistance element is 1: x (1 ≦ x), the voltage value of the predetermined bias potential is the other end of the second resistance element layer. An inverting buffer circuit characterized by being (x + 1) / (2x) times the potential of. A signal input terminal to which an input signal is input;
A signal output terminal for outputting an output signal;
An operational amplifier having a negative input terminal, a positive input terminal, and an output terminal, and a reference voltage is applied to the positive input terminal;
An input resistance element connected between the signal input terminal and the negative input terminal of the operational amplifier;
A feedback resistor element having one end connected to the negative input terminal of the operational amplifier and the other end connected to the output terminal and the signal output terminal of the operational amplifier;
The input resistance element comprises a first resistance element including a first resistance element layer formed on a semiconductor substrate via an insulating layer,
The feedback resistance element has one end connected to one end of the first resistance element layer, and a second resistance element layer formed on the semiconductor substrate via an insulating layer, and a lower part or an upper part of the second resistance element layer. A first conductive layer disposed and biased at a predetermined bias potential based on a potential at the other end of the second resistive element layer, and a second resistive element,
When the resistance ratio between the resistance value of the first resistance element and the resistance value of the second resistance element is 1: x (1 ≦ x), the voltage value of the predetermined bias potential is the other end of the second resistance element layer. An inverting buffer circuit characterized by being (x + 1) / (2x) times the potential of. A signal input terminal to which an input signal is input;
A signal output terminal for outputting an output signal;
An operational amplifier having a negative input terminal, a positive input terminal, and an output terminal, and a reference voltage is applied to the positive input terminal;
An input resistance element connected between the signal input terminal and the negative input terminal of the operational amplifier;
A feedback resistor element having one end connected to the negative input terminal of the operational amplifier and the other end connected to the output terminal and the signal output terminal of the operational amplifier;
The feedback resistive element comprises a first resistive element comprising a first resistive element layer formed on a semiconductor substrate via an insulating layer,
The input resistance element has one end connected to one end of the first resistance element layer, a second resistance element layer formed on the semiconductor substrate via an insulating layer, and a lower or upper portion of the second resistance element layer. A first conductive layer disposed and biased at a predetermined bias potential based on a potential at the other end of the second resistive element layer, and a second resistive element,
When the resistance ratio between the resistance value of the first resistance element and the resistance value of the second resistance element is 1: x (1 ≦ x), the voltage value of the predetermined bias potential is the other end of the second resistance element layer. An inverting buffer circuit characterized by being (x + 1) / (2x) times the potential of.   4. The inverting buffer circuit according to claim 1, further comprising a voltage control circuit that outputs the predetermined bias potential. 5. The voltage control circuit includes:
A third resistance element having one end connected to the other end of the second resistance element layer;
A fourth resistance element having one end connected to the other end of the third resistance element and the first conductive layer, and a reference voltage applied to the other end;
With
5. The inverting buffer circuit according to claim 4, wherein a resistance ratio between the resistance value of the third resistance element and the resistance value of the fourth resistance element is (x−1) / 2: (x + 1) / 2. . The second resistance element comprises a plurality of resistance elements,
A plurality of first switches for selecting some or all of the plurality of resistance elements;
6. The inverting buffer circuit according to claim 5, wherein a resistance ratio between the resistance value of the first resistance element and the resistance value of the second resistance element is varied by the plurality of first switches. The third resistance element includes a plurality of resistance elements,
A plurality of second switches for selecting some or all of the plurality of resistance elements;
6. The inverting buffer circuit according to claim 5, wherein a resistance ratio of a resistance value of the third resistance element and a resistance value of the fourth resistance element is varied by the plurality of second switches.

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