JP7434410B2 - Voltage amplification circuit device and voltage application circuit - Google Patents
Voltage amplification circuit device and voltage application circuit Download PDFInfo
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- 230000003321 amplification Effects 0.000 title claims description 68
- 238000003199 nucleic acid amplification method Methods 0.000 title claims description 68
- 239000004020 conductor Substances 0.000 claims description 37
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 29
- 229920005591 polysilicon Polymers 0.000 description 29
- 239000000758 substrate Substances 0.000 description 25
- 230000004044 response Effects 0.000 description 12
- 230000003071 parasitic effect Effects 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000012535 impurity Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- -1 As and P Chemical class 0.000 description 1
- 239000000872 buffer Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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Description
本発明は、電圧増幅回路装置及び電圧印加回路に関する。 The present invention relates to a voltage amplification circuit device and a voltage application circuit.
従来、シリコン系の半導体製造工程では安定した特性を持つ抵抗としてポリシリコン抵抗が良く使われている。図６には、ポリシリコン抵抗Ｒ１、Ｒ２を備えた電圧増幅回路の一部の断面構造が示されている。電圧増幅回路は、グランドに接続され且つ電気的に固定されたｐ型基板ｐ－ｓｕｂに形成されている。ポリシリコン抵抗Ｒ１、Ｒ２は、ｐ型基板ｐ－ｓｕｂの上に、ＳｉＯ２等の絶縁膜を介在させて形成されている。ポリシリコン抵抗Ｒ１、Ｒ２の抵抗値の調整はＡｓ、Ｐ等の不純物イオンを注入することにより行われ、不純物イオンの注入密度が低い場合に抵抗値を高く調整することができる。 Conventionally, polysilicon resistors have often been used as resistors with stable characteristics in silicon-based semiconductor manufacturing processes. FIG. 6 shows a cross-sectional structure of a portion of a voltage amplification circuit including polysilicon resistors R1 and R2. The voltage amplification circuit is formed on a p-type substrate (p-sub) connected to ground and electrically fixed. Polysilicon resistors R1 and R2 are formed on a p-type substrate p-sub with an insulating film such as SiO 2 interposed therebetween. The resistance values of the polysilicon resistors R1 and R2 are adjusted by implanting impurity ions such as As and P, and when the impurity ion implantation density is low, the resistance values can be adjusted to be high.
しかし、ポリシリコン抵抗Ｒ１、Ｒ２とｐ型基板ｐ－ｓｕｂとの電位差により、ポリシリコン抵抗Ｒ１、Ｒ２で励起されるキャリア電荷の数が変動し、ポリシリコン抵抗Ｒ１、Ｒ２の抵抗値が変化する問題がある。 However, due to the potential difference between the polysilicon resistors R1 and R2 and the p-type substrate p-sub, the number of carrier charges excited in the polysilicon resistors R1 and R2 changes, and the resistance values of the polysilicon resistors R1 and R2 change. There's a problem.
また、図７に、抵抗Ｒ３、抵抗Ｒ４、及びオペアンプＡ１による電圧増幅回路が示されている。抵抗Ｒ３、抵抗Ｒ４は、図６と同様に、ｐ型基板ｐ－ｓｕｂの電位をグランドに接続している。Ｖ３、Ｖ４の電圧に対しＶ５はＶ５＝Ｖ４＋抵抗Ｒ４／抵抗Ｒ３×（Ｖ４－Ｖ３）で決まる電圧となる。Ｖ３とＶ５が異なる電圧関係である場合に、抵抗Ｒ３の端子とｐ型基板ｐ－ｓｕｂとの間の電圧と、抵抗Ｒ４の端子とｐ型基板ｐ－ｓｕｂとの間の電圧とが異なるため、抵抗Ｒ３と抵抗Ｒ４の電圧依存による抵抗値変動に差が生じ、出力電圧の大きさが、設定値から変動し、回路利得の誤差となる。 Further, FIG. 7 shows a voltage amplification circuit including a resistor R3, a resistor R4, and an operational amplifier A1. Resistors R3 and R4 connect the potential of the p-type substrate p-sub to the ground, as in FIG. With respect to the voltages of V3 and V4, V5 is a voltage determined by V5=V4+resistance R4/resistance R3×(V4-V3). When V3 and V5 have different voltage relationships, the voltage between the terminal of resistor R3 and the p-type substrate p-sub is different from the voltage between the terminal of resistor R4 and the p-type substrate p-sub. , a difference occurs in the resistance value fluctuations of the resistors R3 and R4 due to voltage dependence, and the magnitude of the output voltage fluctuates from the set value, resulting in an error in the circuit gain.
ところで、従来、図８に示すように、ポリシリコン抵抗Ｒ３、Ｒ４の各々の端子の電位とポリシリコン抵抗Ｒ３、Ｒ４の各々の下地のｐ型基板ｐ－ｓｕｂの電位を同等にする技術がある。この技術では、ポリシリコン抵抗Ｒ３、Ｒ４の各々の下地のｐ型基板ｐ－ｓｕｂをポリシリコン抵抗Ｒ３、Ｒ４の各々の端子に接続している。これにより、ポリシリコン抵抗Ｒ３、Ｒ４の各々の電位とｐ型基板ｐ－ｓｕｂの電位との間の電位差が無くなり、ポリシリコン抵抗Ｒ３、Ｒ４の電位の変動時に回路利得が変化することを防止することができる。 By the way, conventionally, as shown in FIG. 8, there is a technique for making the potential of each terminal of polysilicon resistors R3 and R4 equal to the potential of the p-type substrate p-sub underlying each of polysilicon resistors R3 and R4. . In this technique, the p-type substrate p-sub underlying each of the polysilicon resistors R3 and R4 is connected to the terminal of each of the polysilicon resistors R3 and R4. This eliminates the potential difference between the potential of each of the polysilicon resistors R3 and R4 and the potential of the p-type substrate p-sub, and prevents the circuit gain from changing when the potential of the polysilicon resistors R3 and R4 changes. be able to.
図８の構成では、ポリシリコン抵抗Ｒ３、Ｒ４とｐ型基板ｐ－ｓｕｂとの間に、双方を電極とし且つ双方の間の絶縁膜を誘電体とする寄生容量が生じ、この寄生容量と、ポリシリコン抵抗Ｒ３、Ｒ４の各々とによりフィルタが生成される。このため、回路の応答速度が低下する問題がある。 In the configuration of FIG. 8, a parasitic capacitance occurs between the polysilicon resistors R3 and R4 and the p-type substrate p-sub, in which both electrodes are used and the insulating film between the two is used as a dielectric, and this parasitic capacitance and A filter is created by each of polysilicon resistors R3 and R4. Therefore, there is a problem that the response speed of the circuit decreases.
特許文献１（特に図１）の集積回路では、ポリシリコン抵抗が基板に形成されたウェル領域に接続されている。なお、寄生ダイオードによるリーク電流対策としてウェル電位用抵抗ユニットを設けた実施例（図４）が開示されているが、この構成だと、ウェル領域と基板とのｐｎ接合部に発生する寄生容量によりフィルタが形成されてしまい、動作遅延が発生する。 In the integrated circuit of Patent Document 1 (particularly FIG. 1), a polysilicon resistor is connected to a well region formed in a substrate. An example (FIG. 4) is disclosed in which a well potential resistor unit is provided as a measure against leakage current caused by a parasitic diode, but with this configuration, parasitic capacitance generated at the pn junction between the well region and the substrate A filter is formed, causing an operation delay.
本開示は、上記した点に鑑みてなされたものであり、電圧増幅回路装置における電圧増幅回路の応答速度を従来の技術より向上させることができる、電圧増幅回路装置及び電圧印加回路を提供することを目的とする。 The present disclosure has been made in view of the above points, and provides a voltage amplification circuit device and a voltage application circuit that can improve the response speed of the voltage amplification circuit in the voltage amplification circuit device compared to conventional techniques. With the goal.
本開示の第１の態様の電圧増幅回路装置は、第１導体及び第２導体との間に各々誘電体が介在している第１抵抗及び第２抵抗を備え、入力電圧を増幅して出力する電圧増幅回路と、前記電圧増幅回路とは別経路で前記入力電圧が入力され、前記電圧増幅回路の入力と出力との間にオペアンプと直列に接続された第３抵抗及び第４抵抗を含み、前記第１導体に前記第３抵抗の一端が接続され、前記第２導体に前記第４抵抗の一端が接続され、前記第１導体及び前記第２導体に電圧を印加する電圧印加回路と、を備える。 A voltage amplifying circuit device according to a first aspect of the present disclosure includes a first resistor and a second resistor each having a dielectric interposed between the first conductor and the second conductor, and amplifies and outputs an input voltage. and a third resistor and a fourth resistor to which the input voltage is input through a route different from the voltage amplification circuit, and which are connected in series with an operational amplifier between the input and output of the voltage amplification circuit. , one end of the third resistor is connected to the first conductor, one end of the fourth resistor is connected to the second conductor, and a voltage application circuit applies a voltage to the first conductor and the second conductor; Equipped with.
本開示の第２の態様の電圧増幅回路装置では、第１の態様において、電圧印加回路は、前記第１抵抗及び前記第２抵抗との電位差が減少する電圧を、前記第１導体及び前記第２導体に印加する。 In the voltage amplification circuit device according to the second aspect of the present disclosure, in the first aspect, the voltage application circuit applies a voltage that reduces the potential difference between the first resistor and the second resistor to the first conductor and the second resistor. Apply to 2 conductors.
本開示の第３の態様の電圧増幅回路装置では、第１の態様又は第２の態様において、前記電圧増幅回路は、反転電圧増幅回路又は正転電圧増幅回路である。 In a voltage amplification circuit device according to a third aspect of the present disclosure, in the first aspect or the second aspect, the voltage amplification circuit is an inversion voltage amplification circuit or a non-inversion voltage amplification circuit.
本開示の第４の態様の電圧増幅回路装置は、第１の態様又は第２の態様において、前記電圧増幅回路として２つ並列に接続された反転電圧増幅回路を備え、前記２つ並列に接続された反転電圧増幅回路のそれぞれに対応した２つの前記電圧印加回路を備え、前記２つの電圧印加回路のそれぞれは、対応する前記反転電圧増幅回路の前記第１導体及び前記第２導体に電圧を印加する。本開示の第５の態様の電圧増幅回路装置は、前記第３抵抗と前記第４抵抗との抵抗比は、前記第１抵抗と前記第２抵抗との抵抗比と同じである。 A voltage amplifying circuit device according to a fourth aspect of the present disclosure, in the first aspect or the second aspect, includes two inverting voltage amplifying circuits connected in parallel as the voltage amplifying circuit, and the two inverting voltage amplifying circuits are connected in parallel. two voltage application circuits corresponding to each of the inversion voltage amplification circuits, and each of the two voltage application circuits applies a voltage to the first conductor and the second conductor of the corresponding inversion voltage amplification circuit. Apply. In the voltage amplification circuit device according to a fifth aspect of the present disclosure, a resistance ratio between the third resistor and the fourth resistor is the same as a resistance ratio between the first resistor and the second resistor.
本開示の第６の態様の電圧印加回路は、第１導体及び第２導体との間に各々誘電体が介在している第１抵抗及び第２抵抗を備え、入力電圧を増幅して出力する電圧増幅回路とは別経路で前記入力電圧が入力され、前記電圧増幅回路の入力と出力との間にオペアンプと直列に接続された第３抵抗及び第４抵抗を含み、前記第１導体に前記第３抵抗の一端が接続され、前記第２導体に前記第４抵抗の一端が接続され、前記第１導体及び前記第２導体に電圧を印加する。 A voltage application circuit according to a sixth aspect of the present disclosure includes a first resistor and a second resistor each having a dielectric interposed between the first conductor and the second conductor, and amplifies and outputs an input voltage. The input voltage is inputted through a route different from the voltage amplification circuit, and includes a third resistor and a fourth resistor connected in series with an operational amplifier between the input and output of the voltage amplification circuit, and the first conductor is connected to the One end of the third resistor is connected, one end of the fourth resistor is connected to the second conductor, and a voltage is applied to the first conductor and the second conductor.
本開示によれば、電圧増幅回路装置における電圧増幅回路の応答速度を従来の技術より向上させることができる。 According to the present disclosure, the response speed of a voltage amplification circuit in a voltage amplification circuit device can be improved compared to conventional techniques.
以下、開示の技術の実施形態の一例を図面を参照しつつ説明する。なお、各図面において同一または等価な構成要素及び部分には同一の参照符号を付与し、重複する説明は適宜省略する。 An example of an embodiment of the disclosed technology will be described below with reference to the drawings. In each drawing, the same or equivalent components and parts are given the same reference numerals, and duplicate explanations will be omitted as appropriate.
［第１の実施の形態］
図１には、第１の実施の形態の反転電圧増幅回路装置１０Ａが示されている。反転電圧増幅回路装置１０Ａは、２つの抵抗Ｒ３、Ｒ４を備え、入力電圧Ｖ３を増幅して出力電圧Ｖ５として出力する反転電圧増幅回路を備えている。抵抗Ｒ３、Ｒ４は、ここではポリシリコン抵抗である。抵抗Ｒ３、Ｒ４は、図示しないウェル領域の上に、ＳｉＯ２等の絶縁膜を形成し、当該絶縁膜の上に形成されている。抵抗Ｒ３、Ｒ４では、ポリシリコンに不純物が注入され、抵抗値が調整されている。なお、反転電圧増幅回路を構築する抵抗の個数は２個に限定されない。例えば、１個でも、３個、４個でもよい。他の実施の形態でも同様である。
[First embodiment]
FIG. 1 shows an inversion voltage amplification circuit device 10A according to a first embodiment. The inversion voltage amplification circuit device 10A includes two resistors R3 and R4, and includes an inversion voltage amplification circuit that amplifies the input voltage V3 and outputs it as an output voltage V5. Resistors R3 and R4 are polysilicon resistors here. The resistors R3 and R4 are formed by forming an insulating film such as SiO 2 on a well region (not shown), and forming the insulating film on the insulating film. In resistors R3 and R4, impurities are implanted into polysilicon to adjust the resistance values. Note that the number of resistors constructing the inversion voltage amplification circuit is not limited to two. For example, it may be one, three, or four. The same applies to other embodiments.
また、第１の実施の形態の反転電圧増幅回路装置１０Ａは、この反転電圧増幅回路装置１０Ａとは別経路で入力電圧Ｖ３が入力され、抵抗Ｒ３、Ｒ４の各々の下地となるウェル領域に電圧を印加する電圧印加回路１２Ａを備えている。電圧印加回路１２Ａは、抵抗Ｒ３とその下地のウェル領域との電位差、抵抗Ｒ４とその下地となるウェル領域との電位差がそれぞれなくなる電圧を、下地となるウェル領域にそれぞれ印加する。ここで、抵抗Ｒ３の下地となるウェル領域とは、抵抗Ｒ３に対向する導体としてのｎ型ウェル領域であり、ｐ型基板の主面部に形成され、この基板に対してｐｎ接合分離されている。 Further, in the inversion voltage amplification circuit device 10A of the first embodiment, the input voltage V3 is inputted through a different path from the inversion voltage amplification circuit device 10A, and the voltage is applied to the well regions underlying each of the resistors R3 and R4. It is provided with a voltage application circuit 12A that applies the voltage. The voltage application circuit 12A applies voltages that eliminate the potential difference between the resistor R3 and the underlying well region, and the potential difference between the resistor R4 and the underlying well region, respectively, to the underlying well region. Here, the well region underlying the resistor R3 is an n-type well region as a conductor facing the resistor R3, and is formed on the main surface of a p-type substrate, and is separated by a pn junction with respect to this substrate. .
反転電圧増幅回路装置１０Ａの反転電圧増幅回路は、直列に接続された２つの抵抗Ｒ３、Ｒ４を備えている。抵抗Ｒ３の一方の端子は、入力電圧Ｖ３の電圧端子に接続され、抵抗Ｒ３の他方の端子は、抵抗Ｒ４の一方の端子に接続され、抵抗Ｒ４の他方の端子は、出力電圧Ｖ５の電圧端子に接続されている。また、反転電圧増幅回路は、抵抗Ｒ３の他方の端子と抵抗Ｒ４の一方の端子との間が反転入力端子（－）に接続され且つ電圧Ｖ４の電圧端子が非反転入力端子（＋）に接続されたオペアンプＡ１を備えている。オペアンプＡ１の出力端子は、出力電圧Ｖ５の電圧端子に接続されている。 The inversion voltage amplification circuit of the inversion voltage amplification circuit device 10A includes two resistors R3 and R4 connected in series. One terminal of the resistor R3 is connected to the voltage terminal of the input voltage V3, the other terminal of the resistor R3 is connected to one terminal of the resistor R4, and the other terminal of the resistor R4 is connected to the voltage terminal of the output voltage V5. It is connected to the. Further, in the inverting voltage amplification circuit, the other terminal of the resistor R3 and one terminal of the resistor R4 are connected to the inverting input terminal (-), and the voltage terminal of the voltage V4 is connected to the non-inverting input terminal (+). It is equipped with an operational amplifier A1. The output terminal of the operational amplifier A1 is connected to the voltage terminal of the output voltage V5.
電圧印加回路１２Ａは、入力電圧Ｖ３の電圧端子が非反転入力端子（＋）に接続されたオペアンプＡ２を備えている。オペアンプＡ２の出力端子は、オペアンプＡ２の反転入力端子（－）に接続さている。また、電圧印加回路１２Ａは、直列に接続された２つの抵抗Ｒ３′、Ｒ４′を備えている。抵抗Ｒ３′の一方の端子は、オペアンプＡ２の出力端子に接続され、抵抗Ｒ３′の他方の端子は、抵抗Ｒ４′の一方の端子に接続され、抵抗Ｒ４′の他方の端子は、抵抗Ｒ４の他方の端子と出力電圧Ｖ５の電圧端子との間に接続されている。抵抗Ｒ３′、Ｒ４′は、ポリシリコン抵抗であり、抵抗Ｒ３、Ｒ４と同様に形成される。抵抗Ｒ３′、Ｒ４′の抵抗比と、抵抗Ｒ３、Ｒ４の抵抗比とは同じである。例えば、Ｒ３′＝（Ｒ３）／２、Ｒ４′＝（Ｒ４）／２である。なお、上記抵抗比はこれに限定されず、例えば、Ｒ３′＝（Ｒ３）／３、Ｒ４′＝（Ｒ４）／３Ｒ３′＝（Ｒ３）／４、Ｒ４′＝（Ｒ４）／４等でもよい。 The voltage application circuit 12A includes an operational amplifier A2 whose voltage terminal for input voltage V3 is connected to a non-inverting input terminal (+). The output terminal of the operational amplifier A2 is connected to the inverting input terminal (-) of the operational amplifier A2. Further, the voltage application circuit 12A includes two resistors R3' and R4' connected in series. One terminal of resistor R3' is connected to the output terminal of operational amplifier A2, the other terminal of resistor R3' is connected to one terminal of resistor R4', and the other terminal of resistor R4' is connected to the output terminal of resistor R4. It is connected between the other terminal and the voltage terminal of the output voltage V5. Resistors R3' and R4' are polysilicon resistors and are formed similarly to resistors R3 and R4. The resistance ratio of resistors R3' and R4' is the same as that of resistors R3 and R4. For example, R3'=(R3)/2, R4'=(R4)/2. Note that the above resistance ratio is not limited to this, and may be, for example, R3'=(R3)/3, R4'=(R4)/3R3'=(R3)/4, R4'=(R4)/4, etc. .
反転電圧増幅回路の抵抗Ｒ３、Ｒ４及び電圧印加回路１２Ａの抵抗Ｒ３′、Ｒ４′の各々は、上記のように図示しない誘電体を介して図示しないウェル領域の上に形成されている。抵抗Ｒ３の下地となるウェル領域は、オペアンプＡ２に接続されている。抵抗Ｒ３′の下地となるウェル領域は、オペアンプＡ２に接続されている。同様に、抵抗Ｒ４の下地となるウェル領域は、オペアンプＡ２に接続されている。抵抗Ｒ４′の下地となるウェル領域は、オペアンプＡ２に接続されている。 As described above, the resistors R3 and R4 of the inverting voltage amplification circuit and the resistors R3' and R4' of the voltage application circuit 12A are formed on the well region (not shown) via the dielectric material (not shown). A well region underlying the resistor R3 is connected to the operational amplifier A2. A well region underlying resistor R3' is connected to operational amplifier A2. Similarly, the well region underlying resistor R4 is connected to operational amplifier A2. A well region underlying resistor R4' is connected to operational amplifier A2.
電圧端子に電圧Ｖ３が入力され、入力電圧Ｖ３の変動時、オペアンプＡ２は、電圧Ｖ３をバッファ（増幅）し、抵抗Ｒ３’及び抵抗Ｒ４’により抵抗Ｒ３、抵抗Ｒ４と同じ電圧を作成し、抵抗Ｒ３、抵抗Ｒ４の各々の下地となるウェル領域に電圧を印加する。即ち、オペアンプＡ２は、電圧印加回路１２Ａとは別経路により、抵抗Ｒ３、抵抗Ｒ４の各々の下地となるウェル領域に電圧を印加する。このように、オペアンプＡ２が、抵抗Ｒ３’及び抵抗Ｒ４’により抵抗Ｒ３、抵抗Ｒ４と同じ電圧を作成し、抵抗Ｒ３、抵抗Ｒ４の各々の下地となるウェル領域に電圧を印加すると、抵抗Ｒ３とその下地のウェル領域との電位差、抵抗Ｒ４とその下地のウェル領域との間の電位差が各々０になる。つまり、抵抗Ｒ３と誘電体とウェル領域とにより形成される寄生容量、及び抵抗Ｒ４と誘電体とウェル領域とにより形成される寄生容量の生成が抑制又は防止される。 Voltage V3 is input to the voltage terminal, and when the input voltage V3 fluctuates, operational amplifier A2 buffers (amplifies) voltage V3, creates the same voltage as resistor R3 and resistor R4 with resistor R3' and resistor R4', and A voltage is applied to the well regions underlying each of resistors R3 and R4. That is, the operational amplifier A2 applies a voltage to the well regions underlying each of the resistors R3 and R4 through a route different from the voltage applying circuit 12A. In this way, when operational amplifier A2 creates the same voltage as resistor R3 and resistor R4 using resistor R3' and resistor R4', and applies the voltage to the well region underlying each of resistor R3 and resistor R4, the resistor R3 and The potential difference with the underlying well region and the potential difference between the resistor R4 and the underlying well region are each zero. In other words, the generation of the parasitic capacitance formed by the resistor R3, the dielectric, and the well region, and the parasitic capacitance formed by the resistor R4, the dielectric, and the well region are suppressed or prevented.
このように、抵抗Ｒ３と誘電体と抵抗Ｒ３の下地のウェル領域とにより形成される寄生容量、及び抵抗Ｒ４と誘電体と抵抗Ｒ４の下地のウェル領域とにより形成される寄生容量の生成が抑制又は防止されるので、反転電圧増幅回路において抵抗Ｒ３及び抵抗Ｒ４と寄生容量とによるフィルタが構成されなくなる。このため、反転電圧増幅回路の応答速度は図８の回路と同程度に速くすることができる。 In this way, the generation of the parasitic capacitance formed by the resistor R3, the dielectric, and the well region underlying the resistor R3, and the parasitic capacitance formed by the resistor R4, the dielectric, and the well region underlying the resistor R4 are suppressed. Alternatively, since the inverting voltage amplification circuit is prevented from forming a filter by the resistor R3, the resistor R4, and the parasitic capacitance, the filter is no longer configured. Therefore, the response speed of the inversion voltage amplifier circuit can be made as fast as that of the circuit shown in FIG.
また、上記のように、抵抗Ｒ３、抵抗Ｒ４の各々と、抵抗Ｒ３、抵抗Ｒ４の各々の下地となるウェル領域との間の電位差が０になるので、抵抗Ｒ３、抵抗Ｒ４で励起されるキャリア電荷の数の変動を抑制又は防止して、抵抗Ｒ３、抵抗Ｒ４の抵抗値の変動を抑制又は防止することができる。更に、このように、抵抗Ｒ３、抵抗Ｒ４の抵抗値の変動が抑制又は防止されるので、回路利得の誤差を小さくすることができる。 Furthermore, as described above, the potential difference between each of the resistors R3 and R4 and the well region underlying each of the resistors R3 and R4 becomes 0, so carriers excited by the resistors R3 and R4 By suppressing or preventing variations in the number of charges, it is possible to suppress or prevent variations in the resistance values of the resistors R3 and R4. Furthermore, since fluctuations in the resistance values of the resistors R3 and R4 are suppressed or prevented in this way, errors in circuit gain can be reduced.
以上のように第１の実施の形態は、図６の回路に対し精度と応答速度とを向上することができる。 As described above, the first embodiment can improve accuracy and response speed compared to the circuit shown in FIG.
［第２の実施の形態］
次に、第２の実施の形態を説明する。図２には、第２の実施の形態の反転電圧増幅回路装置１０Ｂが示されている。第２の実施の形態の反転電圧増幅回路装置１０Ｂは、図１に示した第１の実施の形態の反転電圧増幅回路装置１０Ａと略同様の構成であるので、同一部分には同一の符号を付してその説明を省略し、主として異なる部分について説明する。
[Second embodiment]
Next, a second embodiment will be described. FIG. 2 shows an inversion voltage amplification circuit device 10B according to a second embodiment. The inverting voltage amplifying circuit device 10B of the second embodiment has substantially the same configuration as the inverting voltage amplifying circuit device 10A of the first embodiment shown in FIG. The explanation will be omitted and the different parts will be mainly explained.
図２に示すように、反転電圧増幅回路装置１０Ｂは、２つの抵抗Ｒ３、Ｒ４を備えた反転電圧増幅回路と、抵抗Ｒ３、Ｒ４の各々の下地となるウェル領域に電圧を印加する電圧印加回路１２Ｂとを備えている。なお、第１の実施の形態と第２の実施の形態との反転電圧増幅回路は同様の構成であり、第１の実施の形態と第２の実施の形態との電圧印加回路１２Ａ、１２Ｂは同様の構成である。 As shown in FIG. 2, the inversion voltage amplification circuit device 10B includes an inversion voltage amplification circuit including two resistors R3 and R4, and a voltage application circuit that applies a voltage to a well region underlying each of the resistances R3 and R4. 12B. Note that the inverting voltage amplification circuits of the first embodiment and the second embodiment have the same configuration, and the voltage application circuits 12A and 12B of the first embodiment and the second embodiment have the same structure. It has a similar configuration.
図１に示した第１の実施の形態の反転電圧増幅回路装置１０Ａでは、抵抗Ｒ４′の他方の端子は、抵抗Ｒ４の他方の端子と出力電圧Ｖ５の電圧端子との間に接続されている。これに対し、第２の実施の形態では、電圧印加回路１２Ｂの抵抗Ｒ４′の他方の端子と、出力電圧Ｖ５の電圧端子及び抵抗Ｒ４の他方の端子との間に、オペアンプＡ３が更に設けられている点で相違している。より詳細には、電圧印加回路１２Ｂの抵抗Ｒ４′の他方の端子には、オペアンプＡ３の出力端子が接続され、オペアンプＡ３の出力端子は、オペアンプＡ３の反転入力端子（－）に接続されている。オペアンプＡ３の非反転入力端子（＋）は、抵抗Ｒ４の他方の端子と出力電圧Ｖ５の電圧端子との間に接続されている。オペアンプＡ３は、抵抗Ｒ４’の他方の端子の端子電圧を出力電圧Ｖ５の電圧と同電位に保持する。第２の実施の形態では、オペアンプＡ３により、電圧印加回路１２Ｂと、抵抗Ｒ４の他方の端子及び出力電圧Ｖ５の電圧端子との間とを切断し、電流が抵抗Ｒ４から抵抗Ｒ４′に流入することが防止されている。よって、電流が抵抗Ｒ４から抵抗Ｒ４′に流入しないようにして、反転電圧増幅回路の応答速度を、第１の実施の形態より、向上させることができる。 In the inverting voltage amplifier circuit device 10A of the first embodiment shown in FIG. 1, the other terminal of the resistor R4' is connected between the other terminal of the resistor R4 and the voltage terminal of the output voltage V5. . On the other hand, in the second embodiment, an operational amplifier A3 is further provided between the other terminal of the resistor R4' of the voltage application circuit 12B and the voltage terminal of the output voltage V5 and the other terminal of the resistor R4. They are different in that they are More specifically, the output terminal of the operational amplifier A3 is connected to the other terminal of the resistor R4' of the voltage application circuit 12B, and the output terminal of the operational amplifier A3 is connected to the inverting input terminal (-) of the operational amplifier A3. . The non-inverting input terminal (+) of the operational amplifier A3 is connected between the other terminal of the resistor R4 and the voltage terminal of the output voltage V5. The operational amplifier A3 maintains the terminal voltage of the other terminal of the resistor R4' at the same potential as the output voltage V5. In the second embodiment, the operational amplifier A3 disconnects the voltage application circuit 12B from the other terminal of the resistor R4 and the voltage terminal of the output voltage V5, and current flows from the resistor R4 to the resistor R4'. This is prevented. Therefore, the response speed of the inverting voltage amplifying circuit can be improved compared to the first embodiment by preventing current from flowing into the resistor R4' from the resistor R4.
［第３の実施の形態］
次に、第３の実施の形態を説明する。図３には、第３の実施の形態の差動増幅回路装置１０Ｃが示されている。第３の実施の形態の差動増幅回路装置１０Ｃは、図２に示した第２の実施の形態の反転電圧増幅回路装置１０Ａと同様の構成を有するので、同一部分には同一の符号を付してその説明を省略し、主として異なる部分について説明する。
[Third embodiment]
Next, a third embodiment will be described. FIG. 3 shows a differential amplifier circuit device 10C according to a third embodiment. The differential amplifier circuit device 10C according to the third embodiment has the same configuration as the inverting voltage amplifier circuit device 10A according to the second embodiment shown in FIG. The explanation will be omitted and the different parts will be mainly explained.
図３に示すように、差動増幅回路装置１０Ｃは、２つの抵抗Ｒ９、Ｒ１０を備えた反転電圧増幅回路、及び、オペアンプＡ８、抵抗Ｒ９′、及びＲ１０′を備え、抵抗Ｒ９、Ｒ１０の下地となるウェル領域に電圧を印加する電圧印加回路１２Ｃ１を備えている。差動増幅回路装置１０Ｃは、２つの抵抗Ｒ１１、Ｒ１２を備えた反転電圧増幅回路、及び、オペアンプＡ１０、抵抗Ｒ１１′、及びＲ１２′を備え、抵抗Ｒ１１、Ｒ１２のウェル領域に電圧を印加する電圧印加回路１２Ｃ２を備えている。 As shown in FIG. 3, the differential amplifier circuit device 10C includes an inverting voltage amplifier circuit including two resistors R9 and R10, an operational amplifier A8, resistors R9' and R10', and a base layer of the resistors R9 and R10. A voltage application circuit 12C1 is provided to apply a voltage to the well region. The differential amplifier circuit device 10C includes an inverting voltage amplifier circuit including two resistors R11 and R12, an operational amplifier A10, resistors R11', and R12', and a voltage applied to the well regions of the resistors R11 and R12. It includes an application circuit 12C2.
抵抗Ｒ９～Ｒ１２、抵抗Ｒ９′～Ｒ１２′は、ポリシリコン抵抗であり、図示しないウェル領域の上に絶縁膜を介在させて形成されている。抵抗Ｒ９′～Ｒ１２′では、ポリシリコンに不純物が注入され、抵抗値が調整されている。抵抗Ｒ９′、Ｒ１０′の抵抗比と、抵抗Ｒ９、Ｒ１０の抵抗比とは同じである。抵抗Ｒ１１′、Ｒ１２′の抵抗比と、抵抗Ｒ１１、Ｒ１２の抵抗比とは同じである。 Resistors R9 to R12 and resistors R9' to R12' are polysilicon resistors, and are formed on a well region (not shown) with an insulating film interposed therebetween. In the resistors R9' to R12', impurities are implanted into polysilicon to adjust the resistance values. The resistance ratio of resistors R9' and R10' is the same as that of resistors R9 and R10. The resistance ratio of resistors R11' and R12' is the same as that of resistors R11 and R12.
なお、第２の実施の形態と第３の実施の形態との反転電圧増幅回路は略同様の構成である。第３の実施の形態では、入力電圧Ｖ１０、Ｖ１１用に２つの電圧端子があり、一方の端子に一方の反転電圧増幅回路が接続され、他方の端子に他方の反転電圧増幅回路が接続されている。また、第３の実施の形態では、出力電圧Ｖ１３、Ｖ１２用に２つの電圧端子があり、一方の端子に一方の反転電圧増幅回路が接続され、他方の端子に他方の反転電圧増幅回路が接続されている。入力電圧Ｖｉｎは、Ｖ１０－Ｖ１１であり、出力電圧Ｖｏｕｔは、Ｖ１２－Ｖ１３である。 Note that the inversion voltage amplification circuits of the second embodiment and the third embodiment have substantially the same configuration. In the third embodiment, there are two voltage terminals for input voltages V10 and V11, one inverting voltage amplifying circuit is connected to one terminal, and the other inverting voltage amplifying circuit is connected to the other terminal. There is. Further, in the third embodiment, there are two voltage terminals for output voltages V13 and V12, one inverting voltage amplifying circuit is connected to one terminal, and the other inverting voltage amplifying circuit is connected to the other terminal. has been done. The input voltage Vin is V10-V11, and the output voltage Vout is V12-V13.
また第３の実施の形態では、２つの反転電圧増幅回路は、出力電圧Ｖ１３、Ｖ１２用の２つの電圧端子に、出力端子が接続された１つのオペアンプＡ７を、共有している。 Further, in the third embodiment, the two inverting voltage amplifier circuits share one operational amplifier A7 whose output terminal is connected to two voltage terminals for output voltages V13 and V12.
一方の反転電圧増幅回路及び電圧印加回路１２Ｃ１と、他方の反転電圧増幅回路及び電圧印加回路１２Ｃ２との各々は、第２の実施の形態と同様の作用効果を有する。 Each of the inverting voltage amplifying circuit and voltage applying circuit 12C1 on one side and the inverting voltage amplifying circuit and voltage applying circuit 12C2 on the other side has the same effects as in the second embodiment.
［第２の実施の形態及び第３の実施の形態の変形例］
第２の実施の形態（図２参照）ではオペアンプＡ３を備え、第３の実施の形態（図３参照）ではオペアンプＡ９、Ａ１１を備えているが、本開示の技術は、これに限定されない。例えば、オペアンプＡ３、Ａ９、Ａ１１の代わりに、コイルを設けてもよい。第２の実施の形態及び第３の実施の形態と同様の作用効果を有する。
[Modifications of the second embodiment and the third embodiment]
Although the second embodiment (see FIG. 2) includes an operational amplifier A3, and the third embodiment (see FIG. 3) includes operational amplifiers A9 and A11, the technology of the present disclosure is not limited thereto. For example, coils may be provided in place of the operational amplifiers A3, A9, and A11. It has the same effects as the second embodiment and the third embodiment.
但し、コイルは大面積を必要とするため、オペアンプに置き換えた第２の実施の形態及び第３の実施の形態の方が、レイアウト面積を縮小しコストを低減することができる。 However, since the coil requires a large area, the second and third embodiments in which the coil is replaced with an operational amplifier can reduce the layout area and cost.
［第４の実施の形態］
次に、第４の実施の形態を説明する。図４には、第４の実施の形態の正転電圧増幅回路装置１０Ｄが示されている。第４の実施の形態の正転電圧増幅回路装置１０Ｄは、２つの抵抗Ｒ５、Ｒ６を備えた正転電圧増幅回路と、オペアンプＡ４、抵抗Ｒ５′、Ｒ６′を備え、抵抗Ｒ５、Ｒ６の各々の下地となるウェル領域に電圧を印加する電圧印加回路１２Ｄとを備えている。
[Fourth embodiment]
Next, a fourth embodiment will be described. FIG. 4 shows a forward rotation voltage amplification circuit device 10D according to a fourth embodiment. A forward voltage amplifying circuit device 10D according to the fourth embodiment includes a forward voltage amplifying circuit including two resistors R5 and R6, an operational amplifier A4, and resistors R5' and R6'. A voltage application circuit 12D is provided for applying a voltage to a well region that serves as a base.
正転電圧増幅回路装置１０Ｄの正転電圧増幅回路は、直列に接続された２つの抵抗Ｒ５、Ｒ６を備えている。抵抗Ｒ５の一方の端子は、入力電圧Ｖ６の電圧端子に接続され、抵抗Ｒ５の他方の端子は、抵抗Ｒ６の一方の端子に接続され、抵抗Ｒ４の他方の端子は、グランドに接続されている。抵抗Ｒ５の他方の端子と抵抗Ｒ６の一方の端子との間は、出力電圧Ｖ７の電圧端子が接続されている。よって、第４の実施の形態の正転電圧増幅回路装置１０Ｄの正転電圧増幅回路は、分圧回路であり、回路利得（電圧増幅）の割合は１より小さい。 The normal rotation voltage amplification circuit of the normal rotation voltage amplification circuit device 10D includes two resistors R5 and R6 connected in series. One terminal of the resistor R5 is connected to the voltage terminal of the input voltage V6, the other terminal of the resistor R5 is connected to one terminal of the resistor R6, and the other terminal of the resistor R4 is connected to ground. . A voltage terminal of an output voltage V7 is connected between the other terminal of the resistor R5 and one terminal of the resistor R6. Therefore, the normal voltage amplifying circuit of the normal voltage amplifying circuit device 10D of the fourth embodiment is a voltage dividing circuit, and the ratio of the circuit gain (voltage amplification) is smaller than 1.
電圧印加回路１２Ｄは、第１の実施の形態の電圧印加回路１２Ａと略同様の構成であるので、異なる部分のみを説明する。電圧印加回路１２Ｄの抵抗Ｒ６′の他方の端子はグランドに接続されている。 Since the voltage application circuit 12D has substantially the same configuration as the voltage application circuit 12A of the first embodiment, only the different parts will be described. The other terminal of resistor R6' of voltage application circuit 12D is connected to ground.
抵抗Ｒ５、Ｒ６、抵抗Ｒ５′、Ｒ６′は、ポリシリコン抵抗であり、図示しないウェル領域の上に、絶縁膜を介在させて形成されている。これらの抵抗Ｒ５等では、ポリシリコンに不純物が注入され、抵抗値が調整されている。 Resistors R5, R6, and resistors R5', R6' are polysilicon resistors, and are formed on a well region (not shown) with an insulating film interposed therebetween. In these resistors R5 and the like, impurities are implanted into polysilicon to adjust the resistance value.
抵抗Ｒ５の下地となるウェル領域は、抵抗Ｒ５′の一方の端子に接続されている。抵抗Ｒ５′の下地となるウェル領域は、抵抗Ｒ５′の一方の端子に接続されている。抵抗Ｒ６の下地となるウェル領域は、抵抗Ｒ６′の一方の端子に接続されている。そして、抵抗Ｒ６′の下地となるウェル領域は、抵抗Ｒ６′の一方の端子に接続されている。 A well region underlying the resistor R5 is connected to one terminal of the resistor R5'. A well region underlying the resistor R5' is connected to one terminal of the resistor R5'. A well region underlying the resistor R6 is connected to one terminal of the resistor R6'. The well region underlying the resistor R6' is connected to one terminal of the resistor R6'.
抵抗Ｒ５′、Ｒ６′の抵抗比と、抵抗Ｒ５、Ｒ６の抵抗比とは同じである。 The resistance ratio of resistors R5' and R6' is the same as that of resistors R5 and R6.
第４の実施の形態でも、分圧される点を除くと、第１の実施の形態と同様の作用、効果を有する。即ち、第４の実施の形態でも、入力電圧Ｖ６の変動時、応答の遅れによる電圧誤差はＶ６の変動幅に比べ小さいため、抵抗Ｒ５、抵抗Ｒ６抵抗値の電圧依存誤差は早期に縮小する。また抵抗Ｒ５、抵抗Ｒ６の経路の応答速度は下地応答より速く収束する。 The fourth embodiment also has the same functions and effects as the first embodiment, except for the fact that the pressure is divided. That is, in the fourth embodiment as well, when the input voltage V6 fluctuates, the voltage error due to the delay in response is smaller than the fluctuation range of V6, so the voltage-dependent error in the resistance values of the resistors R5 and R6 is quickly reduced. Further, the response speed of the path between the resistors R5 and R6 converges faster than the underlying response.
［第５の実施の形態］
次に、第５の実施の形態を説明する。図５には、第５の実施の形態の正転電圧増幅回路装置１０Ｅが示されている。第５の実施の形態の正転電圧増幅回路装置１０Ｅは、入力電圧Ｖ８の電圧端子に非反転入力端子（＋）が接続されたオペアンプＡ５、２つの抵抗Ｒ７、Ｒ８を備えた正転電圧増幅回路、及び抵抗Ｒ７、Ｒ８の各々の下地となるウェル領域に電圧を印加する電圧印加回路１２Ｅを備えている。
[Fifth embodiment]
Next, a fifth embodiment will be described. FIG. 5 shows a normal rotation voltage amplification circuit device 10E according to a fifth embodiment. A normal voltage amplification circuit device 10E according to the fifth embodiment is a normal voltage amplification circuit including an operational amplifier A5 having a non-inverting input terminal (+) connected to a voltage terminal of an input voltage V8, and two resistors R7 and R8. The circuit includes a voltage application circuit 12E that applies a voltage to the well region underlying each of the resistors R7 and R8.
オペアンプＡ５の出力端子は、出力電圧Ｖ９の電圧端子と、抵抗Ｒ７の一方の端子とに接続されている。抵抗Ｒ７の他方の端子は、抵抗Ｒ８の一方の端子に接続され、抵抗Ｒ８の他方の端子がグラウンドに接続されている。抵抗Ｒ７の他方の端子と抵抗Ｒ８の一方の端子との間は、オペアンプＡ５の反転入力端子（－）に接続されている。オペアンプＡ５の出力端子は、電圧印加回路１２ＥのオペアンプＡ６の非反転入力端子（＋）に接続されている。 The output terminal of the operational amplifier A5 is connected to the voltage terminal of the output voltage V9 and one terminal of the resistor R7. The other terminal of resistor R7 is connected to one terminal of resistor R8, and the other terminal of resistor R8 is connected to ground. The other terminal of the resistor R7 and one terminal of the resistor R8 are connected to the inverting input terminal (-) of the operational amplifier A5. The output terminal of the operational amplifier A5 is connected to the non-inverting input terminal (+) of the operational amplifier A6 of the voltage application circuit 12E.
正転電圧増幅回路装置１０Ｅの正転電圧増幅回路の利得は１より大きい。 The gain of the normal voltage amplification circuit of the normal voltage amplification circuit device 10E is greater than 1.
電圧印加回路１２Ｅは、第４の実施の形態の電圧印加回路１２Ｄと同様である。電圧印加回路１２ＥのオペアンプＡ６、抵抗Ｒ７′、抵抗８′は、第４の実施の形態の電圧印加回路１２ＤのオペアンプＡ４、抵抗Ｒ５′、抵抗６′に対応する。 The voltage application circuit 12E is similar to the voltage application circuit 12D of the fourth embodiment. The operational amplifier A6, the resistor R7', and the resistor 8' of the voltage application circuit 12E correspond to the operational amplifier A4, the resistor R5', and the resistor 6' of the voltage application circuit 12D of the fourth embodiment.
第５の実施の形態でも、抵抗７、抵抗８の各々の下地となるウェル領域への電圧印加については、第４の実施の形態と同様の作用、効果を有する。即ち、第５の実施の形態でも、入力電圧Ｖ８の変動時、応答の遅れによる電圧誤差はＶ８の変動幅に比べ小さいため、抵抗Ｒ７、抵抗Ｒ８抵抗値の電圧依存誤差は早期に縮小する。また抵抗Ｒ７、抵抗Ｒ８の経路の応答速度は下地応答より速く収束する。 The fifth embodiment also has the same functions and effects as the fourth embodiment regarding voltage application to the well regions underlying each of the resistors 7 and 8. That is, in the fifth embodiment as well, when the input voltage V8 fluctuates, the voltage error due to the delay in response is smaller than the fluctuation range of V8, so the voltage-dependent error in the resistance values of the resistors R7 and R8 is quickly reduced. Further, the response speed of the path between resistor R7 and resistor R8 converges faster than the underlying response.
［その他の変形例］
以上説明した各例では、抵抗は、ポリシリコン抵抗として形成され、１つの共通の基板
に形成されたウェル領域の上に誘電体を介在させて形成されている。
本開示の技術は、これに限定されない。例えば、基板にｎ型基板を使用することができる。この場合、ウェル領域はｐ型とされ、基板とウェル領域とは逆バイアスとなる調整がなされる。
また、１つの共通の基板が複数の抵抗毎にアイソレーション構造により相互に電気的に分離され、この分離された領域毎に誘電体を介在させて抵抗が設けられてもよい。アイソレーション構造には、トレンチ及びトレンチ内に絶縁体が埋め込まれたトレンチ分離構造を実用的に使用することができる。
また、抵抗は、ポリシリコン抵抗に限定されるものではなく、他の材料、具体的には、高融点金属とシリコンとの化合物であるシリサイド、高融点金属を抵抗材料として使用してもよい。抵抗は、単層構造に限られるものではなく、例えばシリコン膜上にシリサイド膜を積層した複合層構造であってもよい。
また、誘電体は、シリコン酸化膜に限らず、シリコン窒化膜であっても、更にシリコン酸化膜とシリコン窒化膜とを積層した複合膜であってもよい。
勿論、基板は、シリコン基板に限定されない。例えば、シリコン基板上に絶縁体を介在させてシリコン層が形成されたＳＯＩ基板が使用されてもよい。加えて、ＩＩＩ－Ｖ族化合物半導体基板であってもよい。
さらに、抵抗は、シリコン基板に形成された半導体領域（拡散層）を用いて形成されてもよい。この場合、半導体領域上に誘電体を介在させて導体が設けられ、この導体に電圧印加回路から電圧が印加される構成とされる。導体として、上記のポリシリコン、シリサイド等を実用的に使用することができる。
[Other variations]
In each of the examples described above, the resistor is formed as a polysilicon resistor, and is formed on a well region formed on one common substrate with a dielectric material interposed therebetween.
The technology of the present disclosure is not limited to this. For example, an n-type substrate can be used as the substrate. In this case, the well region is made p-type, and the substrate and the well region are adjusted to have opposite biases.
Further, one common substrate may be electrically isolated from each other by an isolation structure for each of the plurality of resistors, and a resistor may be provided in each separated region with a dielectric interposed therebetween. As the isolation structure, a trench and a trench isolation structure in which an insulator is embedded in the trench can be practically used.
Further, the resistor is not limited to a polysilicon resistor, and other materials, specifically, silicide, which is a compound of a high melting point metal and silicon, or a high melting point metal may be used as the resistance material. The resistor is not limited to a single layer structure, but may have a composite layer structure in which a silicide film is laminated on a silicon film, for example.
Further, the dielectric is not limited to a silicon oxide film, but may be a silicon nitride film or a composite film in which a silicon oxide film and a silicon nitride film are laminated.
Of course, the substrate is not limited to a silicon substrate. For example, an SOI substrate may be used in which a silicon layer is formed on a silicon substrate with an insulator interposed therebetween. Additionally, a III-V compound semiconductor substrate may be used.
Furthermore, the resistor may be formed using a semiconductor region (diffusion layer) formed in a silicon substrate. In this case, a conductor is provided on the semiconductor region with a dielectric interposed therebetween, and a voltage is applied to the conductor from a voltage application circuit. The above-mentioned polysilicon, silicide, etc. can be practically used as the conductor.
１０Ａ、１０Ｂ 反転電圧増幅回路装置
１０Ｃ 差動増幅回路装置
１０Ｄ、１０Ｅ 正転電圧増幅回路装置
１２Ａ、１２Ｂ、１２Ｃ１、１２Ｃ２、１２Ｄ、１２Ｅ 電圧印加回路
10A, 10B Inverting voltage amplifier circuit device 10C Differential amplifier circuit device 10D, 10E Normal voltage amplifier circuit device 12A, 12B, 12C1, 12C2, 12D, 12E Voltage application circuit
Claims (3)
前記入力電圧が入力される非反転入力を有する第１オペアンプと、前記第１オペアンプの反転入力、前記第１オペアンプの出力及び前記第１導体に一端が接続された第３抵抗と、前記第３抵抗の他端及び前記第２導体に一端が接続されると共に前記オペアンプの前記出力及び前記第２抵抗の前記他端に他端が接続された第４抵抗とを含み、前記第１導体及び前記第２導体に電圧を印加する電圧印加回路と、
を備えた電圧増幅回路装置。 An input that receives an input voltage, an operational amplifier, a first resistor and a second resistor each having a dielectric interposed between the first conductor and the second conductor , and an output that amplifies the input voltage and outputs the amplified input voltage. a voltage amplification circuit comprising: the first resistor having one end connected to the input and the other end connected to the inverting input of the operational amplifier; and the second resistor having one end connected to the inverting input of the operational amplifier and a voltage amplification circuit that amplifies and outputs the input voltage, the voltage amplification circuit having one end connected to the other end of the first resistor and the other end connected to the output of the operational amplifier and the output of the voltage amplification circuit;
a first operational amplifier having a non-inverting input to which the input voltage is input; a third resistor having one end connected to the inverting input of the first operational amplifier, the output of the first operational amplifier, and the first conductor; a fourth resistor whose other end is connected to the other end of the resistor and the second conductor, and whose other end is connected to the output of the operational amplifier and the other end of the second resistor; a voltage application circuit that applies voltage to the second conductor;
A voltage amplification circuit device equipped with.
前記入力電圧が入力される非反転入力を有する第１オペアンプと、前記第１オペアンプの反転入力、前記第１オペアンプの出力及び前記第１導体に一端が接続された第３抵抗と、前記第３抵抗の他端及び前記第２導体に接続される一端と他端とを有する第４抵抗とを含み、前記第１導体及び前記第２導体に電圧を印加する電圧印加回路と、
前記第４抵抗の前記他端に接続された出力及び反転入力と、前記オペアンプの前記出力及び前記第２抵抗の前記他端に接続された非反転入力を有する第２オペアンプと
を含む、
電圧増幅回路装置。 An input that receives an input voltage, an operational amplifier, a first resistor and a second resistor each having a dielectric interposed between the first conductor and the second conductor , and an output that amplifies the input voltage and outputs the amplified input voltage. a voltage amplification circuit comprising: the first resistor having one end connected to the input and the other end connected to the inverting input of the operational amplifier; and the second resistor having one end connected to the inverting input of the operational amplifier and a voltage amplification circuit that amplifies and outputs the input voltage, the voltage amplification circuit having one end connected to the other end of the first resistor and the other end connected to the output of the operational amplifier and the output of the voltage amplification circuit;
a first operational amplifier having a non-inverting input to which the input voltage is input; a third resistor having one end connected to the inverting input of the first operational amplifier, the output of the first operational amplifier, and the first conductor; a voltage application circuit that applies a voltage to the first conductor and the second conductor, the fourth resistor having one end and the other end connected to the other end of the resistor and the second conductor;
a second operational amplifier having an output and an inverting input connected to the other end of the fourth resistor, and a non-inverting input connected to the output of the operational amplifier and the other end of the second resistor;
including ,
Voltage amplification circuit device.
前記電圧増幅回路の前記出力に接続される非反転入力、並びに互いに接続された反転入力及び出力を有する第１オペアンプと、前記第１オペアンプの前記出力及び前記第１導体に一端が接続された第３抵抗と、前記第３抵抗の他端及び前記第２導体に接続された一端とグラントに接続された他端とを有する第４抵抗とを含み、前記第１導体及び前記第２導体に電圧を印加する、電圧印加回路と、
を含む、
電圧増幅回路装置。 an operational amplifier having an input receiving an input voltage and a non-inverting input receiving the input voltage; a first resistor and a second resistor each having a dielectric interposed between the first conductor and the second conductor; and the input and an output for amplifying and outputting a voltage, the first resistor being connected to one end connected to the output of the voltage amplification circuit and the output of the operational amplifier, and an inverting input of the operational amplifier. The second resistor has one end connected to the other end of the first resistor and the inverting input of the operational amplifier, and the other end connected to ground. A voltage amplification circuit that amplifies and outputs the voltage,
a first operational amplifier having a non-inverting input connected to the output of the voltage amplification circuit, and an inverting input and an output connected to each other; and a first operational amplifier having one end connected to the output of the first operational amplifier and the first conductor. and a fourth resistor having one end connected to the other end of the third resistor and the second conductor, and the other end connected to the ground, and a voltage is applied to the first conductor and the second conductor. a voltage application circuit that applies
including ,
Voltage amplification circuit device.
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