JPS59108169A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce influence due to parasitic capacity by constituting a resistor by polysilicone forming a diffused resistor just under said resistor through an insulating film, and impressing voltage through a voltage follower circuit to one end of said diffused resistor and earthing the other end. CONSTITUTION:An integrating circuit is constituted of an operational amplifier OP1, a resistor R1 and a capacitor C1. The resistor R1 used for the integrating circuit is constituted by polysilicone and the diffused resistor R2 is formed just under the resistor R1 through the insulating film. Voltage through the voltage follower circuit receiving input voltage Ei from an input terminal IN is impressed to one end of the resistor R2 and the other end is earthed.

Description

[Detailed description of the invention] The present invention relates to a semiconductor integrated circuit device.

BACKGROUND ART Diffusion resistors and polysilicon resistors are conventionally known as resistive elements used in semiconductor integrated circuit devices. In these resistance elements, parasitic (stray) capacitance is inevitably present between them and the semiconductor substrate. The influence of the amount of charge cannot be ignored.

An object of the present invention is to provide a semiconductor integrated circuit device equipped with a resistance element whose parasitic capacitance is substantially reduced.

Another object of the present invention is to provide a semiconductor integrated circuit device equipped with a highly accurate integrating circuit.

Further objects of the invention will become apparent from the following description and drawings.

Hereinafter, this invention will be explained in detail together with examples.

FIG. 1 shows a circuit diagram of an embodiment in which the present invention is applied to an integrating circuit.

The integrating circuit of this embodiment uses an operational amplifier OPI, and a resistor R1 is connected between its inverting input terminal (-) and input terminal IN.
is connected, a capacitor C1 is connected between its inverting input terminal (-) and the output terminal OUT, and its non-inverting input terminal (
+) is grounded. In this embodiment, the resistor R1 is made of polycrystalline silicon, which is excellent in terms of voltage dependence and stray capacitance, although it is not particularly limited.

In order to reduce the actual stray capacitance, the second
A diffused resistor R2 as shown by a broken line in the figure is formed directly under the polysilicon forming the resistor R1 shown by a solid line in the layout diagram of the figure, with an insulating film interposed therebetween.

As shown in FIG. 1, one end of this resistor R2 is applied with a voltage via a voltage follower circuit that receives the input voltage Ei from the input terminal IN, and the other end is grounded. The voltage follower circuit is configured using an operational amplifier PO2 as is well known. Therefore, in this embodiment, the resistor R1 and the resistor R2 are capacitively coupled.

However, the input voltage Ei supplied from the input terminal IN
When is transmitted through the resistor R1, a similar voltage is transmitted through the resistor R2, so that the potential difference between the resistors R1 and R2 can be maintained at the same potential. Therefore, since charging and discharging current can be prevented or significantly reduced from flowing through the stray capacitance C81, highly accurate integration operation can be realized.

Note that since the stray capacitance C32 between the resistor R2 and the semiconductor substrate, which is the ground potential of the circuit, is charged and discharged by the operational amplifier OP2 constituting the Poldage follower circuit, has no effect.

FIG. 3 shows a circuit diagram of another embodiment of the invention.

In this embodiment, a resistor R1 and a capacitor C1 similar to those described above are used.
In the integrating circuit consisting of the and operational amplifier OPI, the resistor R1 is configured as follows.

That is, a well region WELL as shown by the dotted line in the layout diagram of FIG. 4 is formed, and a polysilicon resistor R1 as shown by the solid line in the same figure is formed thereon via an insulating film. As shown in FIG. 3, this well region WELL includes a voltage follower circuit similar to the above that receives the input voltage Ei supplied from the input terminal IN of the integrating circuit, and a voltage dividing resistor that divides the output voltage. R3°R4 are provided to feed a voltage of E i /2, although not particularly limited.

In this embodiment, the well regions W L', L 1 .
Since a pressure of half the input voltage Ei is applied to
By reducing the voltage applied to the stray capacitance C3I associated with the resistor R1, its charging and discharging current can be reduced, so that the stray capacitance can be substantially reduced. For example, if the input voltage Ei changes symmetrically between positive polarity and negative polarity, the charge charged in the stray capacitance C3I by the positive polarity input voltage ', -E + will be the negative polarity input voltage. Since they are discharged at the time of -Ei, they can cancel each other out, and the influence on the fk component can be prevented.

Therefore, this integrating circuit is suitable for, for example, a measuring instrument requiring an integrating circuit or a semiconductor integrated circuit device constituting an analog-to-digital conversion circuit.

Furthermore, as is clear from FIG. 4, the resistor R1 can be formed with a high degree of integration. That is, when forming the resistor R1 on the well region, its pattern can be uniquely determined by the pattern of the resistor R1.

By the way, when forming a resistor R2 with a similar pattern directly below the resistor R2, as in the embodiment shown in Fig. 2, the size of the resistor R2 is determined by the pattern of the resistor R2, which needs to be formed larger. becomes.

The invention is not limited to the above embodiments.

The resistance means constituting the resistor R1 through which the signal passes may be other resistance means. Furthermore, any resistor or conductor means may be used to shield the semiconductor substrate.

The resistance means according to the present invention can be widely used in various semiconductor integrated circuits as it reduces the charging and discharging of the stray capacitance due to the signal voltage.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an integrating circuit showing one embodiment of the present invention, FIG. 2 is a layout diagram showing one embodiment of the resistors R1 and R2, and FIG. 3 is another embodiment of the present invention. FIG. 4 is a circuit diagram of an example integrating circuit. FIG. 4 is a layout diagram showing an embodiment of the resistor R1. OPI, OF2... operational amplifier, C1... capacitor,
R1, R2, R3, R4...Resistance, WELL...Well area Figure 1 C----〇 2nd Figure 10 t17 It/T

Claims (1)

[Claims] 1. A first resistance means constituting a resistance element, a second resistance means or conductor means configured to be electrically isolated between the resistance means and the semiconductor substrate, and the above-mentioned It is characterized by comprising a high input impedance Poldage follower circuit which receives the Shingetsu supplied from one end of the first resistor means and transmits its output or its divided voltage output to the second resistor means or the conductor means. Semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the first resistance means is formed of polysilicon. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the resistor means or the conductor means is constituted by a well region. 4. The semiconductor integrated circuit device according to claim 1, 2 or 3, wherein the first resistance means constitutes an integrating circuit.