GB2220092A - Integrating circuit - Google Patents

Abstract

The circuit includes first and second operational amplifiers (A1, A2), the output of the first amplifier (A1) being connected via a first resistor (R2 ) to an inverting input of the second amplifier (A2), the first amplifier having a feedback connection between its output and its inverting input, the second amplifier being configured as a Miller integrator, the output of the second amplifier being connection via a second resistor (RF) to the non-inverting input of the first amplifier, the signal input(s) to the integrating circuit being between the non-inverting inputs of the amplifiers, in either the shown non-inverting sense, or vice-versa (Fig. 1). Gain and time constant are thus independent. The circuit may be developed as either a. summing (Fig. 3), or differencing (Fig. 4) integrating circuit. <IMAGE>

Description

INTEGRATING CIRCUIT.

This invention relates to an integrating circuit and finds application in high time constant low bandwidth feedback loop arrangements, such as in temperature control and in phase locked loop circuits.

A very well-known form of integrator is the Miller integrator described in many textbooks. The Miller integrator incorporates an active device, e.g. a transistor amplifier, in order to improve the linearity of the output from a source such as a pulse generator. A capacitance connected between the input and the output of the amplifier results in an apparent increase in the capacitance across the input terminals of the amplifier.

With current technology the amplifier is conveniently configured as an operational amplifier.

According to the present invention there is provided an integrating circuit including first and second operational amplifiers, the output of the first amplifier being connected via a first resistor to an inverting input of the second amplifier, the first amplifier having a feedback connection between its output and its inverting input, the second amplifier being configured as a Miller integrator, the output of the second amplifier being connected via a second resistor to the non-inverting input of the first amplifier, the signal input(s) to the integrating circuit being between the non-inverting inputs of the amplifiers.

Embodiments of the invention will now be described with reference to the accompanying drawings, in which: Figure 1 illustrates an inverting integrating circuit; Figure 2 illustrates a non-inverting integrating circuit; Figure 3 illustrates a summing integrating circuit, and Figure 4 illustrates an asymmetrical differencing integrating circuit.

In the basic integrating circuit which is common to all embodiments a first operational amplifier A1 has its non-inverting input connected to a circuit terminal T1. The output of amplifier A1 is connected via resistor R2 to the inverting input of a second operational amplifier A2. The first amplifier A1 has a negative feedback connection between its output and its inverting input. The second amplifier A2 has a capacitance C connected between its output and its inverting input, thus forming a Miller integrator. The output of the second amplifier A2 is connected via resistor RF to the non-inverting input of amplifier A1. The non-inverting input of amplifier A2 is connected to a second terminal T2.

An input signal comprised of a voltage relative to ground (Ov) or to a specified reference voltage (Vr) is connected to one of the terminals, the other terminal being Ov or Vr In contrast to the conventional Miller integrator the circuit of Figure 1 will multiply the integration time of a signal V. at terminal T1 by the gain (1 +v) of the loop. The gain factor of the loop is given by F R1 where R1 is a resistance via which the input voltage is applied to the circuit. The time constant # of the circuit- is given by # = C2R2 (1 + ) The gain factor + can be used to reduce the need for high values of C2 when long time constants # are required.This is important with surface mounted component technology as high value capacitors are presently unobtainable for surface mounting. With conventional components it avoids the need to use high value electrolytic capacitors in low voltage HF circuits.

The time constant r can be set independently of the gain because the gain is determined by RF/R1.

This is useful in a control loop when long time constants are frequently required at specific gain values. The two operational amplifiers can be a multi-unit set. The circuit is also configurable as a very low bandwith filter.

As a specific example, if the following component values are used: R1 = 2 kohm R2 = 1 Mohm PF = 20 kohm C2 = 100 nF.

then't= 1.1 seconds and = voltage ratio of 10 - 20dB.

The basic circuit will have similar properties when configured as a non-inverting integration circuit as shown in Figure 2. In this case it is terminal T1 which is connected to ground or Vr via resistor R1 and terminal T2 is connected to Vi. Then the time constant # is given by = C2 R2 and the gain factor is given by = R1+RF R1 Figure 3 shows a summing integrator circuit where a number of signal inputs V1 - Vn are connected in parallel to terminals T1(1), T1(2) T The terminals Tl(l) ... are connected via respective resistors 1(1) ... Rl(n) to the non-inverting input of amplifier A1. In all other respects the circuit is the same as that shown in Figure 1.

Assuming that Vr = Ov, then 1) For the case of 'n' inputs all with equal resistance (i.e. R1(1) =R1(2) =R1(3) =Rl(n)) for unit step inputs Vo(t) = - (I - e-t/#) (V1 + v2 + V3 + .... Vn) where = R F R1 C2R2 (1 + n+) t = time in seconds.

2) For the case if 'n' inputs, where the input resistances are not equal (i.e. R1(1)# R1(2) F R1(3)#R1(N)) for unit step inputs Vo(t) = -RF (1 - e-t/#) (V1/R1(1) + V2/R1(2) + V3/R1(3) + .... Vn/R1(n) where % = C R ( 1 + RF) 2 2 RT where RT is the total parallel input resistance i.e. 1 = 1 + 1 + 1 + .... 1 RT R1(1) R1(2) R1(3) R 1(n) As shown in Figure 4 the circuit is configured as a differencing integrator. The two inputs V1 and V2 are applied to terminals T1 and T3 respectively. T1 + T2 are connected via respective resistances R1 and R3 to the non-inverting inputs of A1 and A2 respectively. The non-inverting input of A2 is connected via a further resistance R4 to terminal T2 which is again assumed to be at Ov.Then 1) For the case R4 = RF and R3 = R1 for unit step inputs

where = RF R1 #1 = C2R2 #2 = C2R2(1 + ) By making #2 > > #1,thus #1 - 1 # 1 #2 i.e. C2R2 - 1 # 1 C2R2(1 + ) 1 - 1 # 1 (1 + ) 1 - 1 # 1 (1 + RF) R1 R1 -1 # 1 i.e. make RF > > R1 (' ' large) R1 + RF then Vo(t)# (1 - e -t/#2) (V - V) 2 2) For the case R # R # R # R then 4 F 3 1 for unit step inputs

where 2 = C R 1 2 2 #2 = C2R2 (1 + RF ) R1 By making #2 > > #1, thus #1 - 1 # - 1 #2 i.e. C2 R2 - 1 # -1 C2 R2 (1 + RF) R1 R1 - 1 42 - 1 when RF > > R1 then R1 + RF

Claims (5)

CLAIMS.

1. An integrating circuit including first and second operational amplifiers, the output of the first amplifier being connected via a first resistor to an inverting input of the second amplifier, the first amplifier having a feedback connection between its output and its inverting input, the second amplifier being configured as a Miller integrator, the output of the second amplifier being connected via a second resistor to the non-inverting input of the first amplifier, the signal input(s) to the integrating circuit being between the non-inverting inputs of the amplifiers.

2. An integrating circuit according to claim 1 wherein the non-inverting input of one amplifier is connected to ground.

3. An integrating circuit according to claim 1 or 2 having a plurality of signal input terminals connected to the non-inverting input of one amplifier via respective input resistances.

4. An integrating circuit according to claim 1 or 2 having a first signal input terminal connected via a first input resistance to the non-inverting terminal of the first amplifier and a second input terminal connected via a second input resistance to the non-inverting input of the second amplifier.

5. An integrating circuit substantially as described with reference to the accompanying drawings.