CN108551343A - Calibration circuit and its calibration method applied to signal chains analog gain - Google Patents
Calibration circuit and its calibration method applied to signal chains analog gain Download PDFInfo
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- CN108551343A CN108551343A CN201810300265.1A CN201810300265A CN108551343A CN 108551343 A CN108551343 A CN 108551343A CN 201810300265 A CN201810300265 A CN 201810300265A CN 108551343 A CN108551343 A CN 108551343A
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- resistance
- calibration
- poly
- voltage
- signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
- H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
Abstract
Present invention is disclosed a kind of calibration methods of the calibration circuit applied to signal chains analog gain.It is set in signal transmission device on the auxiliary channel of amplifier, is made of the calibration voltage generator under the first Poly resistance, the 2nd Poly resistance and reference voltage V ref；Wherein calibration voltage generator is bunchiness conventional, electric-resistance and the digital analog converter that switch arrays are constituted, and the output end of calibration voltage generator accesses the substrate pressure regulation of two Poly resistance.Using the calibration circuit and its calibration method of the present invention, using the voltage coefficient characteristic of Poly resistance, which can realize the calibration of superhigh precision analog gain, and calibration process avoids not in signal primary path on the influence of the performance of PGA primary paths；The area requirements for greatly reducing calibration circuit, avoid the expense and cost of calibration cell resistance and calibration switch chip occupying area；In addition the calibration circuit is also avoided that the influence in terms of introducing PGA dynamic properties and improves the voltage linear degree of PGA.
Description
Technical field
The present invention relates to a kind of analog gain of signal transmission device calibration field more particularly to a kind of simulations of superhigh precision
Gain calibration circuit and its calibration method.
Background technology
With the rapid development of mechanics of communication, the hardware chip design as hardware foundation related fields is also constantly occurring
Revolutionary fusion type development.In order to improve the analog gain of signal chains transmission in signal transmission device, need to realize resistance
Matching.Traditional calibration circuit is realized using calibrating resistance, specifically, as shown in Figure 1, calibrating resistance needs to use cell resistance
Parallel connection generates, and thus the area of resistance and parasitic capacitance are larger.In scheme as shown, the gain of PGA for 1 and gain accuracy needs
Control is 0.01%.Assuming that resistance R1 itself realizes that resistance R2 disregards by 10 cell resistance series connection, in order to ensure electricity in design
The voltage coefficient and Flick noises of resistance, the area of usual cell resistance is larger, that is, uses the resistance of wider width；In order to realize
0.01% gain accuracy, calibrating resistance R3（Summary is Rtrim）Minimum unit need to accomplish 1000 cell resistance parallel connections.Figure
Show circuit explanation：If containing N number of cell resistance, wherein cell resistance R3N=Rtrim/2N, R3N-1=Rtrim/2N-1, and so on
R32=Rtrim/22、R31=Rtrim/21.Therefore the area of the calibrating resistance and the parasitic capacitance of introducing are all very big, not only increase
Chip cost, while also limiting the bandwidth and stability of amplifier.
In addition, in order to realizing resistance calibration in calibration circuit shown in FIG. 1, need unwanted resistive short, because
This is also very high to the switching requirements of branch, and resistance value is generally required much smaller than minimum calibrating resistance unit.As shown in Figure 1
Example, it is assumed that R1 resistance is 10Kohm, in order to meet under 0.01% required precision, then the minimum unit of calibrating resistance is about
In 1ohm, in order to ensure switch resistance does not influence calibrating resistance value, then switch resistance is less than 0.1~0.2ohm.If being
System has N calibrations, then the area and additional increased parasitic capacitance shared by switch resistance are all considerable, equally influences chip
The bandwidth and stability of cost and amplifier.
Invention content
In view of the above-mentioned existing deficiency in terms of signal chains analog gain calibration, the purpose of the present invention is directed to one kind
Calibration circuit and its calibration method applied to signal chains analog gain.
The present invention realizes that the technical solution of said one purpose is, is applied to the calibration electricity of signal chains analog gain
Road is set in signal transmission device on the auxiliary channel of amplifier, it is characterised in that：The calibration circuit is by the first Poly electricity
Calibration voltage generator composition under resistance, the 2nd Poly resistance and reference voltage V ref；A wherein termination of the first Poly resistance
Ground connects bypass input signal, and the negative of amplifier is accessed in the other end of the first Poly resistance and one end of the 2nd Poly resistance together
Pole input terminal, the output end of the other end access amplifier of the 2nd Poly resistance, and calibration voltage generator is that bunchiness is commonly electric
The digital analog converter that resistance and switch arrays are constituted, the output end of calibration voltage generator access the substrate tune of two Poly resistance
Pressure.
Further, the conventional, electric-resistance of the calibration voltage generator is in series and accesses the both ends reference voltage V ref, and
One end of a switch of switch arrays is equipped between two neighboring conventional, electric-resistance, the state correspondence arbitrarily switched is controlled by institute
The digital calibration signal of input, the output end of calibration voltage generator are total output end of switch arrays.
Further, the reference voltage V ref is equivalent to the output voltage of amplifier.
Further, the area occupied of the conventional, electric-resistance is less than the area occupied of cell resistance.
The present invention realizes that the technical solution of another above-mentioned purpose is, is applied to the calibration side of signal chains analog gain
Method, it is characterised in that including step：
Introduce calibration circuit：It is connect on the auxiliary channel of amplifier in signal transmission device and sets the first Poly resistance, the 2nd Poly
Calibration voltage generator under resistance and reference voltage V ref；It is defeated that one end of the first Poly resistance is wherein grounded or is connect bypass
Enter signal, the negative input of amplifier is accessed in the other end of the first Poly resistance and one end of the 2nd Poly resistance together, will
The output end of the other end access amplifier of 2nd Poly resistance, and the output end for calibrating voltage generator is accessed into two Poly
The substrate of resistance；
Calibrating resistance：Digital calibration signal is inputted towards calibration voltage generator, modulation calibration voltage generator is based on the base
The output of quasi- voltage Vref adjusts two Poly resistance of the underlayer voltage of the first Poly resistance and the 2nd Poly resistance and calibration
Resistance value.
Further, it is introduced into calibration circuits step, using bunchiness conventional, electric-resistance and switch arrays structure, actually digital-to-analogue turns
Conventional, electric-resistance is in series and accesses the both ends reference voltage V ref, and two neighboring common electricity by the calibration voltage generator of parallel operation
One end of a switch of switch arrays is equipped between resistance, total output end of switch arrays is set as the defeated of calibration voltage generator
Outlet.
Further, in calibrating resistance step, the digital calibration signal of input corresponds to whole switches of control switch arrays
State, and to reference voltage V ref partial pressure outputs.
Using the calibration circuit and its calibration method of the present invention, have substantive distinguishing features outstanding and significant progress：
Using the voltage coefficient characteristic of Poly resistance, which can realize the calibration of superhigh precision analog gain, and calibration process
Not in signal primary path, avoid on the influence of the performance of PGA primary paths；The area requirements for greatly reducing calibration circuit, keep away
The expense and cost of calibration cell resistance and calibration switch chip occupying area are exempted from；In addition the calibration circuit, which is also avoided that, draws
Enter the influence in terms of PGA dynamic properties and improves the voltage linear degree of PGA.
Description of the drawings
Fig. 1 is the calibration circuit diagram of existing signal chains analog gain.
Fig. 2 is the calibration circuit diagram of signal chains analog gain of the present invention.
Specific implementation mode
Just attached drawing in conjunction with the embodiments below, the embodiment of the present invention is described in further detail, so that of the invention
Technical solution is more readily understood, grasps, to make relatively sharp define to protection scope of the present invention.
Designer of the present invention is directed to the deficiency in terms of existing signal chains analog gain calibration, it is comprehensive be engaged in for many years the industry it
Experience is dedicated to proposing the calibrating resistance link of the analog gain breakthrough of technological improvement.
The practicability and advantage of innovation scheme of the present invention for ease of understanding, first technical solution of the present invention relies under simple introduction
With the Poly resistance of realization.Poly resistance is distinctive resistance type in CMOS or BICMOS, gently mixes up Poly resistance squares
Resistance number is hundreds of between thousands of, and the resistance number of heavily doped resistance is between 25-50.Usually use NSD or PSD into
Row mixes up.And without other N or P-type layer time.The size of Poly resistance is not only related with doping concentration, also has with lattice direction
It closes.In plane of crystal, lattice direction relatively it is mixed and disorderly a bit, so also more neat than lattice inside is big for resistance, if
When Poly resistance ratios are thinner, unit resistance is larger, particularly with the Poly resistance gently mixed up.A variety of different Poly resistance
Temperature coefficient is different, and the poly resistance gently mixed up will appear negative temperature coefficient, and heavily doped poly resistance is certainly then positive temperature
Spend coefficient.Such as some square resistance numbers, in 2000 or so Poly resistance, temperature coefficient can be negative.So will appear a temperature
The almost nil doping concentration of coefficient is spent, but such concentration is difficult control.Probably on the ground that square resistance number is 200 or so
Side.The deviation of general technology can cause to be difficult to control.But temperature coefficient to be controlled at 250ppm/ degrees Celsius as possible.Poly
Resistance is typically all that process is heavily doped in the place of resistance head, could reduce contact resistance in this way.So general Poly resistance
All it is made of resistance head and resistance body part.The width difference of Poly resistance is 10% under general technology, so Poly resistance
Calculating when, it should be noted that the corrected parameter of resistance.Poly resistance is preferably drawn on oxygen, can reduce in this way substrate and it between
Capacitance, while resistance deviation caused by other factors can be reduced.Generally upper layer Poly can be selected to do poly resistance,
In bicmos, deep-N+ can be below Poly resistance.The oxide layer below Poly resistance can be increased in this way.But want
Notice that deep-N+ has to several microns of the edge beyond poly resistance.Poly resistance does not adapt to transient current variation, because
It is thick oxide layer below Poly resistance, heat-conducting effect is very poor, and Poly resistance is at a certain temperature, and lattice will produce variation,
Very greatly so as to cause resistance coefficient variation.So by the use of Poly resistance in suitable place.Not all bicmos techniques
Suitable resistance can be provided, because Poly can cause Poly resistance coefficients very low when doing grid by heavily doped, if
There is no special level to be differentiated, then Poly layers will be not suitable for doing resistance because resistance coefficient is too low.Especially exist
Under silicided techniques, Poly resistance square resistance numbers can drop to 2 ohms, you must use such as N-Well resistance
Other resistance.Or heavily doped and silicided place will be needed to be distinguished with unwanted place by some levels.
Poly resistance is extraordinary resistance selection, because Poly resistance deviations are small, temperature coefficient can control, while need not be independent
Island.It is usually the case that everybody can select poly resistance.Further, since the molding structure characteristic of Poly resistance, applies
It can be influenced in the voltage on its substrate and exhausts layer thickness and injection ion ionization distribution of charges, thus impart its resistance value with lining
The voltage coefficient of bottom voltage microvariations.
（The voltage coefficient described above for not referring to resistance, the conclusion obtained are somewhat forced）In view of the above-mentioned of Poly resistance
Advantage, and it is with certain voltage coefficient, i.e. the underlayer voltage of resistance can influence its resistance value.Exactly this is utilized in the present invention
The calibration circuit of signal chains analog gain is applied and introduced to feature, realizes that superhigh precision analog gain is calibrated with this.Such as figure
Shown in 2, the present invention is applied to the calibration circuit of signal chains analog gain, is set to the auxiliary channel of amplifier in signal transmission device
On.From the point of view of circuit structure feature：The calibration circuit is by the first Poly resistance R4, the 2nd Poly resistance R5 and reference voltage V ref
Under calibration voltage generator Z composition；One end of wherein the first Poly resistance R4 is grounded, the other end of the first Poly resistance R4 with
The negative input of amplifier, the other end access amplification of the 2nd Poly resistance R5 are accessed in one end of 2nd Poly resistance R5 together
The output end of device, and calibration voltage generator Z is bunchiness conventional, electric-resistance and the digital analog converter that switch arrays are constituted, calibration voltage
The output end of generator Z accesses the substrate pressure regulation of two Poly resistance.In addition to diagram embodiment, the above-mentioned first Poly electricity of the present invention
One end of resistance R4 can also connect bypass input signal.The calibration of analogue transmission chain also applicable gain as dual signal input.
More specifically, the conventional, electric-resistance of calibration voltage generator Z is in series and accesses the both ends reference voltage V ref, and
One end of a switch of switch arrays is equipped between two neighboring conventional, electric-resistance, the state correspondence arbitrarily switched is controlled by institute
The output end of the digital calibration signal A of input, calibration voltage generator Z are total output end of switch arrays.And said reference is electric
Pressure Vref is equivalent to the output voltage of amplifier.Calibration voltage generator Z is substantially a digital analog converter, but the converter
In required resistance less resistive unit may be used（It can differ with the resistance unit and conventional calibration resistance of main signal
It causes）, in addition its switch can also use very small switch arrays, avoid original scheme alignment unit and calibration switch to account for significantly
With very big area overhead, cost is substantially reduced.
On calibration circuit base shown in Fig. 2, above application includes step in the calibration method of signal chains analog gain：
Introduce calibration circuit：It is connect on the auxiliary channel of amplifier in signal transmission device and sets the first Poly resistance, the 2nd Poly resistance
With the calibration voltage generator under reference voltage V ref；Wherein one end of the first Poly resistance is grounded, the first Poly resistance
The negative input of amplifier is accessed in one end of the other end and the 2nd Poly resistance together, by another termination of the 2nd Poly resistance
Enter the output end of amplifier, and the output end for calibrating voltage generator is accessed to the substrate of two Poly resistance；Calibrating resistance：Face
Digital calibration signal is inputted to calibration voltage generator, modulation calibration voltage generator is based on the defeated of the reference voltage V ref
Go out, adjust the underlayer voltage of the first Poly resistance and the 2nd Poly resistance and calibrates the resistance value of two Poly resistance.
More specifically, above-mentioned be introduced into calibration circuits step, actually counted using bunchiness conventional, electric-resistance and switch arrays structure
Conventional, electric-resistance is in series and accesses the both ends reference voltage V ref by the calibration voltage generator of mode converter, and two neighboring general
It is powered and is equipped with one end switched of switch arrays between hindering, total output end of switch arrays is set as calibration voltage generator
Output end.
In above-mentioned calibrating resistance step, the digital calibration signal of input corresponds to whole on off states of control switch arrays,
And to reference voltage V ref partial pressure outputs.
Using the calibration circuit and its calibration method of the present invention, have substantive distinguishing features outstanding and significant progress：
Using the voltage coefficient characteristic of Poly resistance, which can realize the calibration of superhigh precision analog gain, and calibration process
Not in signal primary path, avoid on the influence of the performance of PGA primary paths；The area requirements for greatly reducing calibration circuit, keep away
The expense and cost of calibration cell resistance and calibration switch chip occupying area are exempted from；In addition the calibration circuit is logical using auxiliary
Road generates calibration voltage to realize the matching calibration of resistance, avoids in existing scheme since calibrating resistance and calibration switch introduce
Parasitic capacitance, to avoid introduce PGA dynamic properties in terms of influence, while also solve resistance due to different voltages introduce
Nonlinear problem, improve the voltage linear degree of PGA.
The preferred embodiment of the present invention has been described above in detail, and still, the invention is not limited in above-mentioned particular implementations
Mode, those skilled in the art can modify within the scope of the claims or equivalents, should be included in this hair
Within bright protection domain.
Claims (7)
1. applied to the calibration circuit of signal chains analog gain, it is set in signal transmission device on the auxiliary channel of amplifier,
It is characterized in that：The calibration circuit is given birth to by the calibration voltage under the first Poly resistance, the 2nd Poly resistance and reference voltage V ref
It grows up to be a useful person composition；One end of wherein the first Poly resistance is grounded or connects bypass input signal, the other end of the first Poly resistance with
The negative input of amplifier is accessed in one end of 2nd Poly resistance together, the other end access amplifier of the 2nd Poly resistance
Output end, and calibration voltage generator is bunchiness conventional, electric-resistance and the digital analog converter that switch arrays are constituted, calibration voltage generates
The output end of device accesses the substrate pressure regulation of two Poly resistance.
2. being applied to the calibration circuit of signal chains analog gain according to claim 1, it is characterised in that：The calibration voltage
The conventional, electric-resistance of generator is in series and accesses the both ends reference voltage V ref, and switch is equipped between two neighboring conventional, electric-resistance
One end of one switch of array, the state correspondence arbitrarily switched are controlled by inputted digital calibration signal, calibration voltage life
The output end grown up to be a useful person is total output end of switch arrays.
3. being applied to the calibration circuit of signal chains analog gain according to claim 1, it is characterised in that：The reference voltage
Vref is equivalent to the output voltage of amplifier.
4. being applied to the calibration circuit of signal chains analog gain according to claim 1, it is characterised in that：The conventional, electric-resistance
Area occupied be less than cell resistance area occupied.
5. the calibration method applied to signal chains analog gain, it is characterised in that including step：
Introduce calibration circuit：It is connect on the auxiliary channel of amplifier in signal transmission device and sets the first Poly resistance, the 2nd Poly
Calibration voltage generator under resistance and reference voltage V ref；It is defeated that one end of the first Poly resistance is wherein grounded or is connect bypass
Enter signal, the negative input of amplifier is accessed in the other end of the first Poly resistance and one end of the 2nd Poly resistance together, will
The output end of the other end access amplifier of 2nd Poly resistance, and the output end for calibrating voltage generator is accessed into two Poly
The substrate of resistance；
Calibrating resistance：Digital calibration signal is inputted towards calibration voltage generator, modulation calibration voltage generator is based on the base
The output of quasi- voltage Vref adjusts two Poly resistance of the underlayer voltage of the first Poly resistance and the 2nd Poly resistance and calibration
Resistance value.
6. being applied to the calibration method of signal chains analog gain according to claim 5, it is characterised in that：Introduce calibration circuit
In step, the calibration voltage generator of actually digital analog converter is built using bunchiness conventional, electric-resistance and switch arrays, it will common electricity
Resistance is in series and accesses the both ends reference voltage V ref, and a switch of switch arrays is equipped between two neighboring conventional, electric-resistance
One end, total output end of switch arrays is set as the output end of calibration voltage generator.
7. being applied to the calibration method of signal chains analog gain according to claim 5, it is characterised in that：Calibrating resistance step
In, the digital calibration signal of input corresponds to whole on off states of control switch arrays, and to reference voltage V ref partial pressure outputs.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110531296A (en) * | 2019-08-09 | 2019-12-03 | 格威半导体(厦门)有限公司 | The gain calibration methods thereof of battery management system |
| CN110837016A (en) * | 2019-11-19 | 2020-02-25 | 思瑞浦微电子科技（苏州）股份有限公司 | Precision matching resistor array and calibration method thereof |
| WO2020258396A1 (en) * | 2019-06-28 | 2020-12-30 | 上海类比半导体技术有限公司 | Trimming circuit of differential amplifier |
| CN112953535A (en) * | 2019-12-11 | 2021-06-11 | 上海交通大学 | Gain error calibration device and method for analog-digital converter with segmented structure |
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| US5600276A (en) * | 1994-06-06 | 1997-02-04 | Yokogawa Electric Corporation | Integrated circuit comprising a resistor of stable resistive value |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020258396A1 (en) * | 2019-06-28 | 2020-12-30 | 上海类比半导体技术有限公司 | Trimming circuit of differential amplifier |
| CN110531296A (en) * | 2019-08-09 | 2019-12-03 | 格威半导体(厦门)有限公司 | The gain calibration methods thereof of battery management system |
| CN110531296B (en) * | 2019-08-09 | 2022-05-10 | 格威半导体(厦门)有限公司 | Gain calibration method of battery management system |
| CN110837016A (en) * | 2019-11-19 | 2020-02-25 | 思瑞浦微电子科技（苏州）股份有限公司 | Precision matching resistor array and calibration method thereof |
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| CN112953535A (en) * | 2019-12-11 | 2021-06-11 | 上海交通大学 | Gain error calibration device and method for analog-digital converter with segmented structure |
| CN112953535B (en) * | 2019-12-11 | 2022-08-16 | 上海交通大学 | Gain error calibration device and method for analog-digital converter with segmented structure |
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Application publication date: 20180918 |