JP2013205393A - Wiring defect detection device, wiring defect detection method, wiring defect detection program, and wiring defect detection program recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring defect detection device capable of efficient wiring defect inspection by improving a detection rate of true defects, a wiring defect detection method, a wiring defect detection program, and a wiring defect detection program recording medium.SOLUTION: A wiring defect detection device and a wiring defect detection method according to an embodiment of the present invention include the steps of: photographing a liquid crystal panel applied with voltage with an infrared camera for macro measurement; identifying if there is a heating spot in a pixel part and a peripheral circuit part respectively from the obtained image; determining whether or not respective heating spots are on the same current path; and decreasing, if the respective heating spots are on the same current path, micro photographic priority of the heating spot identified in the peripheral circuit part lower than micro photographic priority of the heating spot identified in the pixel part.

Description

  The present invention relates to a wiring defect detection device, a wiring defect detection method, a wiring defect detection program, and a wiring defect detection program recording medium suitable for detecting defects in wiring formed on a panel such as a liquid crystal panel and a solar battery panel.

  The liquid crystal panel manufacturing process includes, for example, an array (TFT) process, a cell (liquid crystal) process, and a module process. Among these, in the array process, after a gate electrode, a semiconductor film, a source / drain electrode, a protective film, and a transparent electrode are formed on a transparent substrate, an array defect inspection is performed, and a short circuit such as an electrode or a wiring The presence of defects such as disconnection is inspected.

  In general, for array defect inspection, a method is used in which a probe is brought into contact with an end portion of a wiring, and an electric resistance at both ends of the wiring and an electric resistance and / or capacitance between adjacent wirings are measured. However, even if the presence or absence of a defect in the wiring portion can be detected in the array defect inspection by this method, it is not easy to specify the position of the defect. As an example of an inspection method for identifying the position of a defect, there is a visual inspection in which an operator observes and identifies a substrate with a microscope, but this inspection method is burdensome to the operator, and it is difficult to determine the defect visually. Sometimes the position of the defect was wrong. In order to solve this problem and to perform a quicker inspection, in recent years, an infrared inspection is used in which a substrate is photographed with an infrared camera, image processing is performed, and a defect position is specified.

  Patent Document 1 relates to an infrared inspection. As shown in FIG. 18, in a thin film transistor liquid crystal substrate, a short circuit defect 803 is generated by applying a voltage V between scanning lines 811 to 815 and signal lines 821 to 825. Cause heat. On the other hand, the scanning lines 811 to 815 and the signal lines 821 to 825 are detected with an infrared microscope along the broken line 806 before and after voltage application, and the difference between the detected image signals is taken and projected in the X and Y directions. A technique for specifying the pixel address of the short-circuit defect 803 by calculating the above is disclosed.

  In recent years, many apparatuses equipped with relatively large panels (for example, 60-type liquid crystal panels) have been distributed, and the manufacture of large panels has become active. The inspection method disclosed in Patent Document 2 performs defect inspection by moving an infrared camera in order to inspect a defect in a wiring portion, and dividing one large panel into a plurality of blocks and imaging each divided region. be able to.

Japanese Patent Laid-Open No. 6-51011 (published February 25, 1994) Japanese Patent Laid-Open No. 2-64594 (published on March 5, 1990)

By the way, a thin film transistor liquid crystal substrate of a liquid crystal panel has an active area which is an effective display area and a peripheral circuit area around the active area. This peripheral circuit area is a non-effective display area in which a circuit for outputting a signal to the wiring arranged in the active area is disposed. However, when the above-described defect inspection by the infrared camera is performed, When a heat generation location is detected, this heat generation is caused by a short circuit occurring in the active area in addition to a short circuit defect occurring in a circuit in the peripheral circuit area. In other words, the heat generated in the peripheral circuit area is not a true short-circuit defect (hereinafter referred to as a true defect), that is, a pseudo defect.

  However, since the above-described conventional configuration method cannot sufficiently generate heat in the entire wiring path, whether the heat generation point obtained by imaging the peripheral circuit area indicates this pseudo defect or indicates a true defect. It is not possible to distinguish between them. For this reason, in wiring defect inspection for liquid crystal panels, a method of taking an image with an infrared camera in two steps, specifically, taking a wide area (macro image) as the first step, In the case of the method of identifying the position of the heat generation point by taking a microscopic image of a narrower area including the heat generation point as a second step with a higher spatial resolution (micro image pickup) as a second step, Micro imaging is performed while moving a micro imaging camera in a predetermined moving direction, regardless of whether it is a pseudo defect or a true defect.

  Here, the wiring defect detection device places a limit on the tact time per liquid crystal panel. Alternatively, there is a limit on the number of micro photographings per liquid crystal panel. Alternatively, both restrictions are provided. If such a restriction is not provided, the processing capability (average inspection processing speed of the liquid crystal panel) of the wiring defect detection device greatly varies depending on the defect occurrence state. For example, if an abnormality occurs in the manufacturing process and more defects than usual are generated, the wiring defect detection device cannot inspect all the liquid crystal panels being manufactured. For this reason, all the liquid crystal panels can be inspected by providing the above-mentioned restriction, but instead, all the defects generated in the liquid crystal panel cannot be micro-photographed. That is, it can be said that the true defect detection rate is poor in the above-described method.

  Therefore, the present invention has been made in view of the above problems, and its purpose is to improve the detection rate of true defects in the wiring defect inspection in which infrared camera photographing is performed in two stages as described above, and to improve efficiency. An object of the present invention is to provide a wiring defect detection apparatus, a wiring defect detection method, a wiring defect detection program, and a wiring defect detection program recording medium capable of performing a wiring defect inspection.

  The inventors of the present invention discriminate whether the heat generation location obtained by imaging the peripheral circuit area is a pseudo defect or a true defect, and if it is a pseudo defect, do not perform micro imaging of the area or perform micro imaging It has been found that the above-mentioned purpose is realized by lowering the priority.

That is, the wiring defect detection device according to the present invention is to solve the above problems,
A wiring defect detection device for detecting a wiring defect of a wiring panel having wiring arranged over an active area in which active elements are arranged in a matrix and a peripheral area around the active area. There,
Voltage applying means for applying a voltage to the terminal of the wiring;
Macro photographing means for macro photographing at least a part of the peripheral area and at least a part of the active area including the wiring to which the voltage is applied by the voltage applying means, using a macro photographing infrared camera; ,
From the infrared image obtained by the infrared camera, a heat generation point specifying means for specifying whether or not there is a heat generation point in each of at least a part of the peripheral area and at least a part of the active area,
When it is specified by the heat generation point specifying means that a heat generation point exists in each of at least a part of the peripheral area and at least a part of the active area, it is present in at least a part of the peripheral area. Determining means for determining whether or not the heat generation location and the heat generation location in at least a part of the active area are in the same current path at the time of voltage application;
When it is determined by the determination means that the current path is the same current path, micro-photographing of a region including a heat generation location in at least a part of the active area in the same current path is performed on the same current path. Adjusting means for adjusting the photographing priority so as to preferentially perform micro-photographing of an area including a heat generation point in at least a part of the peripheral area;
And a micro photographing unit that performs micro photographing using an infrared camera for micro photographing based on the photographing priority adjusted by the adjusting unit.

  According to the above configuration, even if the heat generation point specifying means specifies that there is a heat generation point in at least a part of the peripheral area, it is distinguished whether the heat generation point is a true defect or a pseudo defect. If it is a pseudo defect, the priority of micro photography is lowered. Therefore, the detection rate of true defects can be improved.

  Specifically, according to the configuration of the present invention, if the heat generation location specified in at least a part of the peripheral area is in the same current path as the heat generation location in the active area, Heat generation is caused by a wiring defect in the active area. That is, the heat generation location in the peripheral area is assumed to represent a pseudo defect, and the priority of micro photography of the heat generation location in the peripheral area is lowered, Priority is given to micro-photographing of heat generation points. That is, it is possible to postpone micro-photographing of a heat generation portion that is a pseudo defect. On the other hand, if the heat generation point specified in at least a part of the peripheral area is not in the same current path as the heat generation point in the active area, the heat generation point in the peripheral area represents a true defect (that is, in the peripheral area). Therefore, the imaging priority of the micro imaging is not lowered. As a result, the heat generation portion representing the true defect is preferentially micro-photographed, so that the tact time per liquid crystal panel is limited. Alternatively, there is a limit on the number of micro photographings per liquid crystal panel. Or even if both of the restrictions are provided, the true defect generated in the liquid crystal panel can be micro-photographed efficiently. Thereby, the detection rate of a true defect can be improved. In addition, improving the defect detection rate of the wiring defect detection device is directly linked to the improvement of the defect correction rate by the laser irradiation device, so by adopting the above configuration of the present invention, the defect of the laser irradiation device is improved. It can also contribute to improving the correction rate.

In addition to the above configuration, as one form of the wiring defect detection device according to the present invention,
When the wiring of the wiring panel is arranged in a straight line across the active area and the peripheral area, the determination means includes the position coordinates of the heat generation location in at least a part of the peripheral area. The position coordinates of the heat generation points in at least a part of the active area are compared, and if they are within a predetermined allowable error range, it is determined that the heat generation points are in the same current path. preferable.

  According to the above configuration, the position coordinates of the heat generation location in at least a partial area of the peripheral area are compared with the position coordinates of the heat generation location in at least a partial area of the active area. If it is within the allowable error range, it is determined that the heat generation location is in the same current path, and the priority of micro imaging of the heat generation location in at least a part of the peripheral area is lowered, that is, The micro-photographing of the heat generation point can be postponed.

In the case of a wiring panel having a relatively small number of wirings, the wiring of the wiring panel is arranged in a straight line over the active area and the peripheral area. For example, in the case of a liquid crystal panel with a relatively small number of wires, a plurality of data signal lines and a plurality of scanning signal lines intersect perpendicularly to each other, and each line is arranged in a straight line over the active area and the peripheral area. Yes. In such a case, for example, for a certain scanning signal line, there is a heat generation point in the active area, and the extension position of the certain scanning signal line in the peripheral area or the extension position If a heat generation location is specified within a predetermined allowable error range, the heat generation location in the peripheral area is caused by a wiring defect in the active area (appearing as the heat generation location in the active area). Yes, that is, the heat generation point in the peripheral area is determined to be due to a pseudo defect and not a true defect, and the priority of micro-photographing of the heat generation point in the peripheral area is lowered, that is, the heat generation in the peripheral area You can postpone micro-photographing of the location.

In addition to the above configuration, as one form of the wiring defect detection device according to the present invention,
If the wiring is inclined in the portion arranged in the peripheral area with respect to the portion arranged in the active area, the determination means specifies a predetermined range including the wiring. If the heat generation location in at least a part of the peripheral area and the heat generation location in at least a part of the active area are within the predetermined range, the heat generation locations are the same current. It is preferable to determine that the route is present.

  According to said structure, if it exists in the predetermined range, it will determine with the heat_generation | fever location being in the said same electric current path | route, and the micro imaging | photography of the heat_generation | fever location in the at least one part area | region of the said surrounding area The priority can be lowered, that is, the micro-photographing of the heat generation point can be postponed.

  In the case of a wiring panel having a relatively large number of wirings or a wiring panel having a narrow peripheral area (so-called narrow frame), the wiring of the wiring panel is arranged in a straight line in the active area, but in the peripheral area. Then, there is a case where it is formed to be inclined with respect to the straight line portion. That is, there is a wiring panel in which the wiring is bent in the vicinity of the active area in the peripheral area. In some cases, the length of the portion formed in the peripheral area is relatively long, and the end portion of the wiring may be far away from the forming portion in the active area of the wiring. In such a case, according to the above configuration of the present invention, a predetermined range including the entire wiring is specified, and within the predetermined range, a heat generation point in the peripheral area and a heat generation point in the active area ( If the heat generation location in the peripheral area is generated by the defect, that is, it is determined that the heat generation location in the peripheral area is due to a pseudo defect and is not a true defect. It is possible to lower the priority of micro-photographing of the location, that is, to postpone micro-photographing of the heat generation location in the surrounding area.

That is, the wiring defect detection method according to the present invention, in order to solve the above problems,
A wiring defect detection method for detecting a wiring defect of a wiring panel having wiring arranged over an active area in which active elements are arranged in a matrix and a peripheral area around the active area. There,
A voltage application step of applying a voltage to the terminal of the wiring;
A macro imaging step of performing macro imaging with an infrared camera of at least a part of the peripheral area and at least a part of the active area including the wiring to which the voltage is applied in the voltage application step;
A heat generation point specifying step for specifying whether or not there is a heat generation point in each of at least a part of the peripheral area and at least a part of the active area from the infrared image obtained by the macro imaging step; ,
If it is determined in the heat generation location identifying step that there are heat generation locations in each of at least a part of the peripheral area and at least a part of the active area, they are present in at least a part of the peripheral area. A determination step of determining whether the heat generation location and the heat generation location in at least a part of the active area are in the same current path at the time of voltage application;
If it is determined in the determination step that the current path is the same current path, micro-photographing of a region including a heat generation location in at least a part of the active area in the same current path is performed on the same current path. An adjustment step of adjusting the imaging priority so as to be performed in preference to the micro-imaging of the area including the heat generation point in at least a part of the peripheral area;
And a micro photographing step of performing micro photographing based on the photographing priority adjusted by the adjusting step.

  According to the above configuration, whether the heat generation location specified in the peripheral area is heat generation due to a true defect or heat generation due to a pseudo defect is distinguished, and if the heat generation location is a pseudo defect, the priority of micro imaging of the heat generation location is lowered. . Therefore, the detection rate of true defects can be improved.

  Specifically, according to the configuration of the present invention, if the heat generation location specified in at least a part of the peripheral area is in the same current path as the heat generation location in the active area, Heat generation is caused by a wiring defect in the active area. That is, the heat generation location in the peripheral area is assumed to represent a pseudo defect, and the priority of micro photography of the heat generation location in the peripheral area is lowered, Priority is given to micro-photographing of heat generation points. That is, it is possible to postpone micro-photographing of a heat generation portion that is a pseudo defect. On the other hand, if the heat generation point specified in at least a part of the peripheral area is not in the same current path as the heat generation point in the active area, the heat generation point in the peripheral area represents a true defect (that is, in the peripheral area). Therefore, the imaging priority of the micro imaging is not lowered. As a result, the heat generation portion representing the true defect is preferentially micro-photographed, so that the tact time per liquid crystal panel is limited. Alternatively, there is a limit on the number of micro photographings per liquid crystal panel. Or even if both of the restrictions are provided, the true defect generated in the liquid crystal panel can be micro-photographed efficiently. Thereby, the detection rate of a true defect can be improved. In addition, improving the defect detection rate of the wiring defect detection device is directly linked to the improvement of the defect correction rate by the laser irradiation device, so by adopting the above configuration of the present invention, the defect of the laser irradiation device is improved. It can also contribute to improving the correction rate.

  Note that each of the above means of the wiring defect detection device may be realized by a computer. In this case, a program for realizing the above-described means of the wiring defect detection apparatus in the computer by operating the computer as the above-described means, and a computer-readable recording medium recording the program are also included in the scope of the present invention. enter.

  The present invention relates to a wiring defect detection method, a wiring defect detection device, and a wiring defect detection capable of performing an efficient wiring defect inspection by improving a true defect detection rate in wiring defect inspection in which infrared camera photographing is performed in two stages. A program and a wiring defect detection program recording medium can be provided.

(A) is a block diagram which shows the main structures of the wiring defect detection apparatus which implement | achieves the wiring defect detection method which concerns on one Embodiment of this invention, (b) is a perspective view of the motherboard which is a detection target. is there. 1 is a perspective view of a wiring defect detection device according to an embodiment of the present invention. It is a figure which shows the structure of the infrared camera for macro measurement used for macro imaging | photography. It is a figure which shows arrangement | positioning of the infrared camera shown in FIG. It is a top view of a liquid crystal panel and a probe. It is a figure which shows the flowchart of the wiring defect detection method which concerns on one Embodiment of this invention. It is a schematic diagram which shows the defect of a pixel part. It is a schematic diagram which shows the short circuit path | route used in this invention. It is a figure which shows the detailed flowchart about a part of flowchart of FIG. It is a schematic diagram of the infrared image which carried out macro photography. It is a figure which shows the block search rule used for the wiring defect detection method. It is a figure which shows typically the G block and S block used for a wiring defect detection method. It is a figure which shows the detailed flowchart about a part of flowchart of FIG. It is a figure which shows the detailed flowchart about a part of flowchart of FIG. It is a figure which shows the detailed flowchart about a part of flowchart of FIG. It is a figure which shows the detailed flowchart about a part of flowchart of FIG. It is a figure which shows typically the case where S block used for a wiring defect detection method is trapezoid. It is a figure which shows a prior art.

  An embodiment of a wiring defect detection device and a wiring defect detection method according to the present invention will be described with reference to FIGS.

(Configuration of wiring defect detection device)
FIG. 1A is a block diagram showing a configuration of the wiring defect detection apparatus 100 in the present embodiment, and FIG. 1B is a target in which a wiring defect is detected using the wiring defect detection apparatus 100. 1 is a perspective view of a mother substrate 1. FIG.

  The wiring defect detection apparatus 100 detects defects such as wiring in a plurality of liquid crystal panels 2 (wiring panels) formed on the mother substrate 1 (wiring panel) shown in FIG. can do. As the liquid crystal panel 2, a relatively large liquid crystal panel of about 60 type can be applied.

  As shown in FIG. 1A, the wiring defect detection apparatus 100 includes a probe 3 for conducting electrical connection with wiring disposed on the liquid crystal panel 2, and probe moving means for moving the probe 3 onto each liquid crystal panel 2. 4 is provided. The wiring defect detection device 100 also includes an infrared camera 5 for acquiring an infrared image, and camera moving means 6 for moving the infrared camera 5 on the liquid crystal panel 2. Further, the wiring defect detection apparatus 100 includes a control unit 7 (a heat generation point specifying unit, a determining unit, an adjusting unit, a macro imaging unit, a micro imaging unit) that controls the probe moving unit 4 and the camera moving unit 6. Further, the probe 3 includes a resistance measuring unit 8 for measuring the resistance between the wirings arranged on the liquid crystal panel 2, and a voltage applying unit 9 (voltage application) for applying a voltage between the wirings of the liquid crystal panel 2. Means) are connected. The resistance measuring unit 8 and the voltage applying unit 9 are controlled by the control unit 7.

FIG. 2 is a perspective view showing the configuration of the wiring defect detection apparatus 100 in the present embodiment. The configuration of the wiring defect detection apparatus 100 will be further described. In the wiring defect detection apparatus 100, as shown in FIG. 2, an alignment stage 11 on which the mother substrate 1 is placed is installed on a base. The alignment stage 11 is adjusted in parallel with the XY coordinate axes of the probe moving unit 4 and the camera moving unit 6. At this time, a position confirmation optical camera 12 for confirming the position of the mother substrate 1 provided above the alignment stage 11 is used to adjust the position of the alignment stage 11.

  The probe moving means 4 is slidably installed on a guide rail 13 a disposed outside the alignment stage 11. Guide rails 13b and 13c are also installed on the main body side of the probe moving means 4, and the mount portion 14a is installed so as to be able to move in the XYZ coordinate directions along these guide rails 13. A probe 3 corresponding to the liquid crystal panel 2 is mounted on the mount portion 14a.

  The camera moving means 6 is slidably installed on a guide rail 13d disposed outside the probe moving means 4. Further, guide rails 13e and 13f are also installed on the main body of the camera moving means 6, and the three mount portions 14b, 14c, and 14d are separately moved along the guide rails 13 in the XYZ coordinate directions. can do.

  The mount part 14c of the wiring defect detection apparatus 100 is equipped with an infrared camera 5a (macro photography infrared camera) for macro measurement (macro photography), and the mount part 14b is used for micro measurement (micro photography). An infrared camera 5b (micro imaging infrared camera) is mounted, and a positioning optical camera 16 is mounted on the mount portion 14d.

  Here, there are two types of infrared cameras 5. One is an infrared camera 5a for macro measurement, and the other is an infrared camera 5b for micro measurement.

  The infrared camera 5a for macro measurement is an infrared camera capable of macro measurement with a field of view extended to about 520 × 405 mm. The infrared camera 5a for macro measurement is configured by combining, for example, four infrared cameras in order to widen the field of view.

  Here, FIG. 3 is a perspective view showing the configuration of the infrared camera 5a for macro measurement. The XYZ coordinate system shown in FIG. 3 is the same coordinate system as FIG. The infrared camera 5a for macro measurement includes four infrared cameras 5a-1 to 5a-4. In the infrared cameras 5a-1 to 5a-4, the central axis of the lens is inclined from the direction perpendicular to the liquid crystal panel 2. This prevents the infrared cameras 5a-1 to 5a-4 themselves reflected on the liquid crystal panel 2 from being photographed as a heat source. FIG. 4 shows an example in which the infrared camera 5a-1 and the infrared camera 5a-2 are installed so as not to be reflected in each other. 4A is a diagram showing the field of view of the infrared camera 5a-1 and the field of view reflected on the liquid crystal panel 2. FIG. 4B is the field of view of the infrared camera 5a-2 and reflected on the liquid crystal panel 2. It is a figure showing a visual field. The infrared camera 5a-2 can prevent the infrared camera 5a-1 from being reflected by tilting the central axis relative to the infrared camera 5a-1. Similarly, the infrared camera 5a-3 and the infrared camera 5a-4 can be installed so as not to be reflected from each other, and the infrared camera 5a-1, the infrared camera 5a-4, the infrared camera 5a-2, and the infrared camera 5a-3. Similarly, it can be installed so that it does not reflect each other.

  In addition, arrangement | positioning of the infrared cameras 5a-1 to 5a-4 for macro measurement is not restricted to the above-mentioned arrangement | positioning, Each can be attached to a perpendicular direction. Infrared rays emitted from the camera itself are captured (the camera is reflected in the image, but there is no problem because the difference between the captured images before and after heat generation (an image representing the rising temperature) is performed as described later. Rather, there is an advantage that the entire captured image is focused (focused) as compared with the aspect in which the central axis is inclined as described above.

  Further, the infrared camera 5b for micro measurement is an infrared camera capable of photographing with high spatial resolution although the field of view is as small as about 16 × 12 mm.

  The camera moving means 6 can also be equipped with a laser irradiation device for correcting a defective portion by adding a mount portion. By mounting the laser irradiation device, the defect can be continuously corrected by irradiating the defect with a laser after specifying the position of the defect.

  The probe moving means 4 and the camera moving means 6 are installed on separate guide rails 13a and 13d, respectively. Therefore, it is possible to move above the alignment stage 11 in the X coordinate direction without interfering with each other. Accordingly, the infrared cameras 5a and 5b and the alignment optical camera 16 can be moved onto the liquid crystal panel 2 while the probe 3 is in contact with the liquid crystal panel 2.

  FIG. 5A is a plan view of one liquid crystal panel 2 among the plurality of liquid crystal panels 2 formed on the mother substrate 1. As shown in FIG. 5A, each liquid crystal panel 2 includes a pixel portion 17 (active area) in which a TFT is formed at each intersection where a scanning line and a signal line intersect, and a scanning line and a signal line, respectively. A connected peripheral circuit section 18 (peripheral area) is formed. Pads 19 a to 19 d are provided at the edge of each liquid crystal panel 2, and the pads 19 a to 19 d are connected to the wiring of the pixel unit 17 or the peripheral circuit unit 18. Note that the pad 19 is not limited to the one installed in the four directions (19a to 19d) as shown in FIG. 5A. For example, the pad 19 has three directions (for example, 19a and 19b). , And 19d). Further, the pads arranged in one direction need not be arranged at equal intervals, and may be grouped into one or a plurality of groups.

  FIG. 5B is a plan view of the probe 3 (voltage applying means) for conducting with the pads 19a to 19d disposed on the liquid crystal panel 2. FIG. The probe 3 has a frame shape that is substantially the same size as the liquid crystal panel 2 shown in FIG. 5A, and probe pins 21a to 21d are located at positions corresponding to the pads 19a to 19d of the liquid crystal panel 2. It has.

  The probe pins 21a to 21d individually connect each of the probe pins 21 to the resistance measuring unit 8 and the voltage applying unit 9 shown in FIG. 1A via relay ON / OFF switching (not shown). be able to. For this reason, the probe 3 can selectively connect a plurality of wirings connected to the pads 19a to 19d, or can connect the plurality of wirings together.

  As described above, since the probe 3 has a frame shape that is approximately the same size as the liquid crystal panel 2, when aligning the positions of the pads 19 a to 19 d and the probe pins 21 a to 21 d, The position can be confirmed from the inside using the positioning optical camera 16.

  A voltage applying unit 9 is connected to the probe 3, and the voltage applying unit 9 applies a voltage to the probe 3 to cause the probe 3 to conduct to the liquid crystal panel 2. A resistance measuring unit 8 is also connected to the probe 3. The probe 3 is electrically connected to the liquid crystal panel 2, and the resistance measuring unit 8 measures a resistance value between adjacent wirings to be described later. When performing defect inspection, the temperature of the liquid crystal panel 2 is measured using the infrared camera 5 before and after applying a voltage between the wirings of the liquid crystal panel 2 via the probe 3 or between the wirings.

The wiring defect detection device 100 of this embodiment having such a configuration is a case where the size of the liquid crystal panel 2 is larger than the size of the imaging field of view of the infrared camera 5, for example, the 60 type described above. However, it is an aspect which can implement | achieve the defect detection by imaging. Although details will be described later, this can be realized by dividing the liquid crystal panel 2 into a plurality of inspection areas according to the imaging field of view of the infrared camera 5 and moving the infrared camera 5 while moving the infrared camera 5. This is because the defect detection of the entire area 2 is performed.

  In addition, the wiring defect detection device 100 of the present embodiment includes a probe pin 21 that applies a voltage and a probe pin that does not apply a voltage so as not to generate heat as much as possible in a region other than the region included in the imaging range (field of view) of the infrared camera 5. 21 is switched according to the position of the infrared camera 5. As a result, when a certain inspection region (that is, a certain imaging region) is heated by voltage application, the uninspected region is prevented from generating heat as much as possible. As a result, when the infrared camera 5 moves and a new inspection area becomes an inspection object, heat generation data can be acquired from the inspection area with high accuracy, and thus accurate defect detection can be performed.

  In addition, the wiring defect detection apparatus 100 according to the present embodiment is characterized by the fact that when a heat generation location is found in the peripheral circuit section 18 provided around the pixel section 17 of each liquid crystal panel 2, this heat generation is caused by a true defect. Whether or not it is the above-described pseudo defect, and if it is a pseudo defect, control is performed to set the photographing priority of micro photographing low. This control is performed by the control unit 7. Below, the defect detection using the wiring defect detection apparatus 100 of this embodiment is explained in full detail.

(Wiring defect detection method)
FIG. 6 is a flowchart of a wiring defect detection method using the wiring defect detection apparatus 100 according to the present embodiment.

The wiring defect detection method of this embodiment is
(I) a voltage application step for applying a voltage to the wiring terminals;
(Ii) A macro imaging step of macro-photographing at least a partial region of the peripheral circuit unit 18 and at least a partial region of the pixel unit 17 including the wiring to which the voltage is applied in the voltage application step with an infrared camera. When,
(Iii) From the infrared image obtained by the macro imaging step, it is specified whether or not there is a heat generation point in each of at least a part of the peripheral circuit unit 18 and at least a part of the pixel unit 17. A process of identifying a fever, and
(Iv) When it is specified in the heat generation location specifying step that there are heat generation locations in each of at least a part of the peripheral circuit unit 18 and at least a part of the pixel unit 17, at least the peripheral circuit unit 18 Determination step (v) for determining whether the heat generation location in a part of the region and the heat generation location in at least a part of the pixel portion 17 are in the same current path when a voltage is applied (v) If it is determined that they are in the same current path, micro-photographing of an area including a heat generation location in at least a part of the area of the pixel unit 17 in the same current path is performed by the peripheral circuit section in the same current path. An adjustment step (vi) for adjusting the priority of photographing so as to be performed in preference to the micro-photographing of the region including the heat generation point in at least a part of the region 18. The photographing priority adjusted by the adjustment step And micro photography step of micro-photography based on the position,
Is included.

  In the wiring defect detection method according to the present embodiment, wiring defects are sequentially detected in steps S1 to S16 for each of the plurality of liquid crystal panels 2 formed on the mother substrate 1 shown in FIG. Is done.

  Hereinafter, each step of step S1-step S16 is demonstrated.

  In step S1, the mother substrate 1 is placed on the alignment stage 11 of the wiring defect detection apparatus 100 shown in FIG. 2, and the position of the mother substrate 1 is adjusted so as to be parallel to the XY coordinate axes.

  In step S2, the probe 3 is moved by the probe moving means 4 shown in FIG. 2 to the upper part of the certain liquid crystal panel 2 of the mother substrate 1 whose position has been adjusted in step S1, and the upper, lower, left and right probe pins 21a to 21d are moved. The liquid crystal panel 2 is in contact with the upper, lower, left and right pads 19a to 19d.

  In step S3, subsequent to step S2, corresponding to various defect detection modes, the wiring for resistance inspection is selected, and the probe pin 21 to be conducted is switched.

  Here, various defect detection modes will be described with reference to FIGS. 7A to 7C schematically show the positions of the defective portions 23 (wiring short-circuit portions) generated in the pixel portion 17 as an example.

  FIG. 7A shows a defective portion 23 in which the wiring X and the wiring Y are short-circuited at the intersection in a liquid crystal panel where the wiring X and the wiring Y intersect vertically, such as scanning lines and signal lines. Show. The probe pin 21 to be conducted is switched to the pair of the upper probe pin 21a and the left probe pin 21d shown in FIG. 5B or the pair of the right probe pin 21b and the lower probe pin 21c. The presence / absence of the defect portion 23 can be specified by measuring the resistance value between the wirings X1 to X10 and the wirings Y1 to Y10 in FIG. In the future, a defect detection mode for detecting a defect by applying a voltage to the wiring X-wiring Y will be referred to as 'defect detection mode A', and the detected defect type will be referred to as 'defect type A'.

  FIG. 7B shows a defective portion 23 that is short-circuited between adjacent wiring lines X such as a scanning line and an auxiliary capacitance line (Cs line). Such a defective portion 23 switches the probe pins 21 to be electrically connected as shown in FIG. 5B to a pair of odd-numbered probe pins 21b and even-numbered probe pins 21d on the right side, so that the wires X1 to X10 By measuring the resistance value between adjacent wirings, it is possible to identify the wiring having the defect portion 23. In the future, a defect detection mode for detecting a defect by applying a voltage to the wiring XX will be referred to as 'defect detection mode B', and the detected defect type will be referred to as 'defect type B'.

  FIG. 7C shows a defective portion 23 short-circuited between adjacent wirings Y such as a signal line and an auxiliary capacitance line (Cs line). Such a defective portion 23 is obtained by replacing the probe pin 21 to be electrically conductive shown in FIG. 5B with a pair of adjacent probe pins (the odd-numbered probe pin 21a and the even-numbered adjacent probe pin 21a. Or a pair of adjacent probe pins (a pair of an odd-numbered probe pin 21c and an adjacent even-numbered probe pin 21c) in the lower probe pin 21c. By switching and measuring the resistance value between the adjacent wirings Y1 to Y10, the wiring having the defective portion 23 can be specified. In the future, a defect detection mode in which a defect is detected by applying a voltage to the wiring YY will be referred to as 'defect detection mode C', and the detected defect type will be referred to as 'defect type C'.

  In step S4, the probe pin 21 switched in step S3 is conducted, and the resistance value between the selected wirings is measured and acquired. The acquired resistance value is stored in the data storage unit 10 together with information between the selected wirings.

  In step S5, it is determined whether or not the resistance value measurement has been completed in all of the defect detection modes A, B, and C. For example, it is assumed that the resistance value is measured in the order of the defect detection modes A, B, and C. When only the measurement of the resistance value in the defect detection mode A has been completed, the process returns to step S3, the probe pin 21 is switched to the defect detection mode B, and the resistance value is measured in the subsequent step S4. When the measurement of the resistance value in the defect detection modes A and B is completed, the process returns to step S3, the probe pin is switched to the defect detection mode C, and the resistance value is measured in the subsequent step S4. When the measurement of the resistance value is completed in all the defect detection modes A, B, and C, the process proceeds to the subsequent step S6.

  In step S6, it is determined whether or not the liquid crystal panel 2 being inspected has a defect that requires infrared inspection.

  First, the resistance value acquired in step S4 is compared with the resistance test threshold value stored in advance in the data storage unit 10. Here, when the resistance value acquired in step S4 is larger than the resistance inspection threshold value stored in advance in the data storage unit 10, it can be specified that the liquid crystal panel 2 under inspection has no defect, which will be described later. The process proceeds to step S16. On the other hand, when the resistance value acquired in step S4 is equal to or lower than the resistance inspection threshold value stored in advance in the data storage unit 10, it can be specified that there is a defect between the wirings in the liquid crystal panel 2 being inspected. Then, the process proceeds to step S7.

  For example, as shown in FIG. 7A, when a defect 23 occurs at a location where the wiring X and the wiring Y intersect, an abnormality is detected in the wiring X4 and the wiring Y4 by the resistance inspection between the wirings. The position up to the defect portion 23 can be specified. Therefore, in the case of the defect portion 23 shown in FIG. 7A, it is not always necessary to specify the position by infrared detection (step S6). That is, if a resistance inspection is performed for every combination of the wiring X and the wiring Y, the position can be specified, so that infrared detection is not necessary. However, since the number of combinations is enormous, it takes a long time. For example, in the case of a full high-definition liquid crystal panel, since there are 1080 lines X and lines Y 1920, the total number of combinations is about 2.70 million. If a resistance test is performed for each such combination, the tact time becomes long and the detection processing capability is greatly reduced, which is not realistic. Therefore, the number of resistance inspections can be reduced by combining all the combinations of the wiring X and the wiring Y into several and performing a resistance inspection. For example, if a resistance test is performed between the wiring X grouped together and the wiring Y grouped together, the number of times of resistance testing is only one. However, a short circuit between wirings can be detected by resistance inspection, but the position cannot be specified. Therefore, it is necessary to specify the position of the defect portion 23 by infrared detection.

  On the other hand, as shown in FIG. 7B or FIG. 7C, when a defective portion 23 occurs between adjacent wirings, there is a defective portion between a pair of wirings, for example, the wiring X3 and the wiring X4. Can be identified. However, since the position of the defect portion 23 cannot be specified in the length direction of the wiring, it is necessary to specify the position of the defect portion 23 by infrared detection.

  Since the resistance inspection between adjacent wirings is enormous, it takes a long time. For example, in the case of a full high-definition liquid crystal panel, the number of resistance inspections between adjacent wires X is 1079, and the number of resistance inspections between adjacent wires Y is 1919. In the case of resistance inspection between adjacent wirings X as in the case of FIG. 7B, if resistance inspection is performed between all X odd numbers and all X even numbers, the number of resistance inspections is only one. Times. In the case of resistance inspection between adjacent wirings Y as in the case of FIG. 7C, if resistance inspection is performed between all Y odd numbers and all Y even numbers, the number of resistance inspections is only one. Times. However, a short circuit between wirings can be detected by resistance inspection, but the position cannot be specified. Therefore, it is necessary to specify the position of the defective part 23 by infrared detection after the subsequent step S7.

  That is, in step S6, the presence / absence of a short-circuit defect and the type of wiring that is a short-circuit defect are detected.

  In step S7, one defect detection mode that requires infrared inspection is selected from the defect detection modes A, B, and C. Specifically, in step S4, one defect detection mode corresponding to the wiring in which the defect stored in the data storage unit 10 exists is selected.

  In step S8, the probe pin used for power feeding is determined based on the defect detection mode information determined in step S7.

  Specifically, in the defect detection mode A, the defect part 23 as shown in FIG. 7A can be detected. When the defect detection mode A is selected, it corresponds to the first inspection region R1 of the left pad 19d and the upper pad 19a among the upper, lower, left and right pads 19a to 19d shown in FIG. Among the probe pins 21a to 21d shown in FIG. 5B, the probe pin 21d and a part of the probe pin 21a corresponding to the first inspection region R1 are fed so that only a part to be fed is fed. Is selected and determined as a probe pin for power supply. Thereby, the defect portion 23 corresponding to the defect detection mode A generates heat, and the infrared camera 5 can capture an infrared image.

  In the defect detection mode B, the defect part 23 as shown in FIG. 5B can be detected. When the defect detection mode B is selected, the probe pin 21a illustrated in FIG. 3B is supplied with power so that only the pad 19d is supplied among the pads 19a to 19d illustrated in FIG. Of 21d, the probe pin 21 is switched to the probe pin 21d. Thereby, the defect portion 23 corresponding to the defect detection mode B generates heat, and the infrared camera 5 can capture an infrared image.

  In the defect detection mode C, the defect portion 23 as shown in FIG. 5C can be detected. When the defect detection mode C is selected, the probe pin 21a shown in FIG. 3 (b) is supplied so that power is supplied only to the pad 19a among the pads 19a to 19d shown in FIG. 3 (a). To 21d, the probe pin 21 is switched to the probe pin 21a. Thereby, the defect part 23 corresponding to the defect detection mode C generates heat, and the infrared camera 5 can take an infrared image.

  In step S9, the voltage value applied between the wirings of the liquid crystal panel 2 is set based on the resistance value stored in the data storage unit 10 in step S4.

  Specifically, in step S9, a voltage value of the applied voltage V (volt) that is proportional to the resistance value acquired in step S4 is set.

  That is, the applied voltage V (volt) is expressed by the following formula (1);

And set.

  For example, the maximum current value m is specified as 20 milliamperes, and a voltage value proportional to the resistance is calculated.

  Further, if the maximum value is also set for the calculated voltage value (for example, 50 volts) and this set maximum voltage value is larger than the voltage value calculated by the above equation (1), this step In S11, the voltage value to be set is not the voltage value calculated from the above equation (1) but the maximum voltage value. Thereby, the current value of the current flowing between the wirings of the liquid crystal panel 2 becomes smaller than the maximum current value.

  Here, the current I (ampere) is expressed by the following equation (2);

It becomes. That is, the current can be made constant by appropriately determining the applied voltage.

  Here, the resistance value R of the wiring formed on the substrate is expressed by the following equation (3):

The electrical resistivity ρ and the cross-sectional area A are constants determined by the type and location of the wiring. Therefore, the resistance value R / L = ρ / A of the wiring per unit length is also a constant. That is, if the number assigned to each wiring type and location is i, the resistance value r (i) per unit length of the wiring i is given by the following equation (4):

It is expressed.

  Here, the calorific value J (joule) per unit time is expressed by the following formula (5):

In view of the above, the calorific value of the wiring i per unit length of the wiring i is expressed by the following formula (6) from the above formulas (2), (4) and (5):

It becomes.

  Here, FIG. 8 is a diagram for explaining the short-circuit path, and is an example of an electrical wiring diagram of the thin film transistor substrate. In the thin film transistor substrate of FIG. 8, scanning lines (wirings) 31 to 35 and signal lines (wirings) 41 to 45 are arranged in a grid pattern on a glass substrate, and thin film transistors and transparent pixel electrodes (not shown) are connected to each intersection. This is a substrate on which 5 × 5 pixels are formed as a whole. A thin film transistor substrate and a common electrode substrate (not shown) are arranged in parallel and a liquid crystal is sealed between them, which is a liquid crystal panel. Further, as shown in FIG. 8, the leading end portions of the scanning lines 31p to 35p of the scanning line are commonly connected to the thin film transistor substrate by the common line 30 to prevent electrostatic breakdown. The same applies to the signal lines. In the thin film transistor substrate shown in FIG. 8, a short-circuit portion 50 is formed between the scanning line 33 and the signal line 43. In such a thin film transistor substrate, considering the case where the short-circuit path is divided as lead line 33p → scan line 33 → short-circuit point 50 → signal line 43 → lead line 43p, the scan line 33 and signal per unit length are considered. The heat generation amount of the line 43 can be made constant.

  Accordingly, the scanning line 33 and the signal line 43 can be stably recognized from the infrared image by appropriately determining the constant m in advance regardless of the magnitude of the electrical resistance of the short-circuited portion.

  Then, by further analyzing the recognized wiring portion and specifying a portion where the scanning line 33 and the signal line 43 are short-circuited, the short-circuited portion can be specified. If the resistance value at the short-circuited portion is high, the amount of heat generated at the short-circuited portion increases, and therefore the short-circuited portion can be easily identified from the infrared image.

  Further, in order to determine the voltage based on the resistance value of the wiring, the control unit 7 may execute the process of calculating the above expression (1) each time. Alternatively, the relationship between the resistance value and the voltage may be stored in advance as a table, and the control unit 7 may refer to this table each time and determine the voltage from the resistance value.

  That is, the amount of heat generated per unit time can be made constant by applying an applied voltage V (volt) proportional to the resistance value to the liquid crystal panel 2 based on the equation (1).

  Depending on the type of substrate or the cause of a short circuit such as the location of a defect on the substrate, for example, the resistance value of the short circuit path including the defect 23 as shown in FIG. However, if this step S9 is performed, the calorific value per unit time of the short circuit path including the defect can be made constant. When the amount of heat generated is constant, when the electrical resistance value of the defect is large, the defect itself generates heat, and when the electrical resistance value of the defect is small, the wiring portion of the short circuit path generates heat well. For this reason, a defect can be easily detected in any case of infrared inspection.

In step S10, first, the voltage represented by the equation (1) set in step S9 is applied to the probe pin 21 determined in step S8 (voltage application step). Here, the macro camera infrared camera 5 a is controlled by the control unit 7 so as to be interlocked with the application of the voltage to the probe pin 21. As a result, the voltage is applied to the probe pin 21 and the current path begins to generate heat. At the same time, the infrared camera 5a for macro measurement starts imaging (macro imaging) under the control of the control unit 7 (macro imaging). Process). The infrared camera 5a for macro measurement has a field of view capable of photographing the pixel portion 17 and the peripheral circuit portion 18 of the liquid crystal panel 2 at a time. Then, using the infrared image before the current path generates heat and the macro imaged infrared image after the current path generates heat, an infrared inspection is performed based on the difference image between the infrared images (that is, the temperature difference of the liquid crystal panel before and after voltage application) Is performed, and a heat generation point exceeding a predetermined temperature difference is specified (heat generation point specifying step). Further, in the above processing, it is possible to specify the defect type by assuming that the heat generation portion is a defect.

  In step S10, the entire surface of the liquid crystal panel 2 can be photographed at once by the macro measurement infrared camera 5a. However, the present invention is not limited to this, and when the imaging target region is wider than the field of view of the infrared camera 5a for macro measurement, the macro image is taken a plurality of times in step S10 to obtain the entire infrared image. You may get.

  In step S11, it is determined whether or not infrared inspection has been performed in all defect detection modes that require infrared inspection (macro imaging).

  Through the above steps, specification of the heat generation location (specification of the presence or absence of a defect) and specification of the defect type using the infrared camera 5a for macro measurement are completed. In the macro measurement, since the spatial resolution of the captured image is low, the approximate position of the defect can be specified. However, the precise position of the defect cannot be specified. Therefore, in order to specify the precise position of the defect, a micro-measurement infrared camera 5b that has a narrower field of view (imaging area) than the macro-measurement infrared camera 5a and can perform high spatial resolution imaging is used. To make micro measurements. In the present embodiment, as described above, the priority order for micro measurement is adjusted. Specifically, it is determined whether the heat generation location of the peripheral circuit portion indicates a true defect or a pseudo defect, and the priority order is adjusted. This will be described in detail below.

  In the following description, a heat generation point specified in an infrared image obtained by macro photography may be referred to as a defect (whether it is a true defect or a pseudo defect).

  In step S12, the priority order for micro measurement is adjusted (determination step, adjustment step). Step S12 includes steps S1201 to S1208. This point will be described with reference to the flowchart shown in FIG.

  In step S1201, in the infrared image taken by the macro measurement infrared camera 5a shown in FIG. 10, it is specified whether there is an unprocessed heat generation location in the peripheral circuit unit 18, and if there is an unprocessed heat generation location, step S1202 is performed. Migrate to

  In step S1202, information on one unprocessed heat generation location in the peripheral circuit unit 18 is extracted. The extracted information includes the attribute of the defect (for example, the block number in which the defect is included, the distance from the outline of the pixel unit 17, etc.).

In step S1203, a block to be searched is extracted from the block search rule based on the extracted heat generation point information. The block search rule is created for each model of the liquid crystal panel 2, and a block to be searched for each defect type can be specified for each model of the liquid crystal panel. An example is shown in FIG. In FIG. 11, a defect type in a certain liquid crystal panel size is associated with a block to be searched, ◎ indicates that a block is searched, and × indicates that a block is not searched. For example, in FIG. The defect in the GG peripheral circuit section (GG defect in the peripheral circuit section) searches the G block, but does not search the S block, the vertical Cs block, and the horizontal Cs block. Note that GG indicates that the defect type of the defect (assumed heat generation location) is a short-circuit defect occurring between the scan lines. Here, the names of the defect types shown in FIG. 11 will be described. G represents a scanning line, S represents a signal line, Cs represents an auxiliary capacitance line, and SS represents a defect. This indicates that the defect type of (assuming the heat generation point) is a short-circuit defect occurring between the signal lines. SCs indicates that the defect type of the defect (assuming a heat generation point) is a short-circuit defect generated between the signal line and the auxiliary capacitance line. In addition, GCs indicates that the defect type of the defect (assuming the heat generation point) is a short-circuit defect generated between the scanning line and the auxiliary capacitance line. SG indicates that the defect type of the defect (assuming the heat generation point) is a short-circuit defect occurring between the signal line and the scanning line. CsCs indicates that the defect type of the defect (assuming the heat generation point) is a short-circuit defect occurring between the storage capacitor line and the storage capacitor line.

  Further, the block names shown in FIG. 11 will be described. The G block is a predetermined area having a longitudinal direction along the horizontal direction (scanning line extending direction) as shown in FIG. The prescribed range includes a plurality of scanning lines, and includes each scanning line from one end to the other end. Here, as shown in FIG. 12A, the G block is configured by dividing one liquid crystal panel 2 into a plurality of pieces, and the number of divisions can be appropriately set according to the size of the panel (FIG. 12). 12 (a) has 5 G blocks).

  The S block is a predetermined area having a longitudinal direction along the vertical direction (signal line extending direction) as shown in FIG. 10, and the range defined by the S block includes a plurality of signal lines. Each signal line is included from one end to the other end. Here, as shown in FIG. 12B, the S block is configured by dividing one liquid crystal panel 2 into a plurality of pieces, and the number of divisions can be appropriately set according to the size of the panel (FIG. 12). 12 (b) has 16 S blocks).

  The block shape of the G block and the S block is not limited to a rectangle, but may be a trapezoid or a polygon that is a pentagon or more. A block can be represented by a polygon, and can be a setting parameter in which the coordinates of each vertex are arranged counterclockwise. For example, the setting parameter of one block can be expressed as the number of vertices n, x1, y1, x2, y2,..., Xn, yn.

  FIG. 17 is a specific example in which the S block is a polygon. The lower diagram of FIG. 17 represents a liquid crystal panel, and an enlarged view enclosed by a broken line is an upper diagram of FIG. The plurality of signal lines are arranged in parallel in the pixel portion and extend to the peripheral circuit portion. The signal line extended from the pixel portion to the peripheral circuit portion is connected to the pad shown in FIG. Specifically, odd-numbered signal lines are collectively connected to odd-numbered signal line pads. The even-numbered signal lines are collectively connected to the even-numbered signal line pads. The odd-numbered signal line pads and the even-numbered signal line pads are provided for each S block. When a star is detected as a heat generation point in the macro measurement in the current path indicated by the bold line, this star must be recognized as the same S block. Therefore, in the case of a liquid crystal panel in which such S wiring is arranged, the S block is preferably not a rectangle but a polygon such as a one-dot chain line.

Further, in the vertical Cs block search, for each heat generation point in the peripheral circuit unit 18, the difference between the X coordinate of the heat generation point in the pixel unit 17 and the X coordinate of the heat generation point in the peripheral circuit unit 18 is a predetermined allowable error CsDiffX. Search for in-range. Similarly, in the horizontal Cs block search, for each heat generation location in the peripheral circuit, the difference between the Y coordinate of the heat generation location in the pixel unit 17 and the Y coordinate of the heat generation location in the peripheral circuit portion 18 is within a predetermined allowable error CsDiffY range. It is searched whether it is. Here, the Cs line is arranged horizontally or vertically in the peripheral circuit. That is, the vertical Cs line in the pixel portion 17 is bent at a right angle immediately after exiting from the pixel portion 17 to the peripheral circuit portion 18. The horizontal Cs line of the pixel unit 17 is bent at a right angle immediately after exiting from the pixel unit 17 to the peripheral circuit unit 18. Since the place that bends at a right angle is a place where the layers are connected to each other, the resistance value is larger than that of the wiring and the heat generation is increased. Therefore, it is easy to misrecognize as a defect. As described above, since the Cs line has only a horizontal line or a vertical line, the search is not performed in a rectangular area like the S block or the G block.

  These four types of blocks depend on the wiring layout design. The search block is set according to the arrangement of the wiring of the liquid crystal panel (according to the model).

  In step S1204, it is determined whether there is an unprocessed block among the blocks extracted in step S1203. If there is no unprocessed block, the process proceeds to step S1210, the defect table attribute OnTheWay is set to 0, and the process from step S1201 is repeated again. On the other hand, if there is an unprocessed block, the process proceeds to step S1205.

  In step S1205, it is determined which block is an unprocessed block. In step S1206, an unprocessed block is searched.

  In step S1206, a horizontal Cs block search, a vertical Cs block search, an S block search, or a G block search is performed. Here, the block search order is the horizontal Cs block search, vertical Cs block search, S block search, and G block search.

  FIG. 13 is a flowchart of the horizontal Cs block search. The horizontal Cs block search includes steps SA1 to SA4. In step SA1, the Y coordinate of the defect in the peripheral circuit part of interest is specified, and in step SA2, all defects in the pixel part 17 of the same defect type as this defect are extracted. The defect table may be used for extraction. Then, in step SA3, a search is made as to whether or not there is even one defect in the pixel portion 17 of the same defect type whose Y coordinate difference is within CsDiffY shown in FIG. Here, CsDiffY indicates an allowable error of the Y coordinate of the horizontal Cs line. This allowable error is a Y coordinate measurement error of a defect in macro imaging. In step SA4, if it is determined that it exists, the return value = 1 is set. If it is determined that it does not exist, the return value = 0 is set, and the horizontal Cs block search is completed.

  Similarly, a flowchart of the vertical Cs block search is shown in FIG. The vertical Cs block search includes steps SB1 to SB4. In step SB1, the X coordinate of the defect in the peripheral circuit part of interest is specified, and in the subsequent step SB2, all defects in the pixel part 17 of the same defect type as this defect are extracted. The defect table may be used for extraction. In step SB3, it is searched whether there is any defect in the pixel unit 17 of the same defect type whose X coordinate difference is within CsDiffX shown in FIG. Here, CsDiffX indicates an allowable error of the X coordinate of the vertical Cs line. This allowable error is an X coordinate measurement error of a defect in macro imaging. In step SB4, if it is determined that there is a return value = 2, if it is determined that there is no return value = 0, the vertical Cs block search is completed.

FIG. 15 is a flowchart of the S block search. The S block search includes steps SC1 to SC8. In step SC1, the S block number of the defect in the peripheral circuit unit 18 of interest is specified, and in step SC2, the attribute BlockS of the defect table of this defect is updated to BkNo. Subsequently, in step SC3, all defects in the pixel portion 17 of the same defect type as this defect are extracted. In step SC4, it is determined whether or not a defect in the pixel portion 17 having the same defect type as that of the defect is extracted for the first time.
Move to 5. In step SC5, the attribute BlockS (S block number) of each extracted defect is calculated. In step SC6, the attribute BlockS (S block number) of the defect table of each defect is updated. Subsequently, in step SC7, it is searched whether there is any defect in the pixel part 17 of the same defect type having the attribute BlockS (S block number) BkNo. If it is determined in step SC8 that it exists. Return value = 3, and if it is determined that it does not exist, return value = 0 and the S block search is completed. Note that the BlockS of the defect in the pixel unit 17 may be calculated only for the first time (only once).

  FIG. 16 is a flowchart of the G block search. The G block search includes steps SD1 to SD8. In step SD1, the G block number of the defect in the peripheral circuit unit of interest is specified, and in step SD2, the attribute BlockG of the defect table of this defect is updated to BkNo. Subsequently, in step SD3, all defects in the pixel portion of the same defect type as this defect are extracted. Then, in step SD4, it is determined whether or not a defect in the pixel portion of the same defect type as this defect is extracted for the first time, and if it is extracted for the first time, the process proceeds to step SD5. In step SD5, the attribute BlockG (G block number) of each extracted defect is calculated, and in step SD6, the attribute BlockG (G block number) of the defect table of each defect is updated. Subsequently, in step SD7, it is searched whether there is even one defect in the pixel portion of the same defect type whose attribute BlockG (G block number) is BkNo, and if it is determined in step SD8 that it exists, the return value = 4, and if it is determined that it does not exist, the return value = 0 and the G block search is completed. It should be noted that BlockG of the defect in the pixel portion may be calculated only for the first time (only once).

  Returning to the description of FIG. 9, in step S1207 (adjustment process), it is determined whether the return value obtained in step S1206 is greater than 0. In step S1208, the defect table attribute OnTheWay of the defect in the peripheral circuit unit 18 is set. The process is updated to the return value, and the process returns to step S1201. If there is no defect in the unprocessed peripheral circuit unit 18, the process ends. When the attribute OnTheWay of the defect table of the defect in the peripheral circuit portion is 1 to 4, it means that the defect in the peripheral circuit portion of interest is in the same current path as the defect in the pixel portion 17. It is possible to specify that the defect in the peripheral circuit portion is a pseudo defect, that is, a location where heat is generated by the defect in the pixel portion 17. As shown in FIG. 10, since a certain defect # 1 in the peripheral circuit section is equal to or less than the defect # 2 inside the outline of the pixel section (within the pixel section) and the allowable error CsDiffY, the same current path as the defect # 2 Since defect # 1 can be determined to be a heat generation location due to defect # 2, it can be determined that defect # 1 is a pseudo defect, and the measurement priority of micro measurement is lowered than defect # 2 ( Not preferred). Similarly, a certain defect # 3 in the peripheral circuit section is within the same current path as the defect # 4 because it is below the tolerance #CsDiffX and the defect # 4 inside the pixel section (inside the pixel section). Since # 3 can be determined to be a heat generation location due to defect # 4, defect # 3 can be determined to be a pseudo defect, and the measurement priority of micro measurement is lowered (not prioritized) over defect # 4. Similarly, a certain defect # 5 in the peripheral circuit portion is in the same current path as the defect # 6 because it is in one G block with the defect # 6 inside (in the pixel portion) the outline of the pixel portion, Since it can be determined that the defect # 5 is a heat generation location due to the defect # 6, it can be determined that the defect # 5 is a pseudo-defect, and the measurement priority of micro measurement is lower than the defect # 6 (not prioritized). . Similarly, a certain defect # 7 in the peripheral circuit portion is in the same current path as the defect # 8 because it is in one S block with the defect # 8 inside (in the pixel portion) the outline of the pixel portion, Since it can be determined that the defect # 7 is a heat generation location due to the defect # 8, it can be determined that the defect # 7 is a pseudo-defect, and the measurement priority of micro measurement is lower than the defect # 8 (not prioritized). .

  Through the above processing, the priority order of micro measurement is specified.

In the present invention, it is assumed that all the heat generation points in the pixel portion (AA) are true defects. Further, it can be seen by macro imaging that the heat generation location in the pixel portion (AA) is a true defect.

Returning to the description of FIG. 6, in step S13, the micro-measurement infrared camera 5b is moved based on the micro-measurement priority order specified above. Three groups 1-3;
Group 1: Multiple heat generation points in the pixel section (assuming that they are true defects)
Group 2 is in the peripheral circuit section, and a plurality of heat generation points (pseudo defects) derived from “Group 1” Group 3 is a true defect (heat generation area other than group 2) in the peripheral circuit section
It is divided roughly into. Therefore, since the group 2 is a pseudo defect, the priority is the lowest, and the groups 1 and 3 are both true defects, and thus need to be ranked from another viewpoint. Another point of view is
1. If it does not occur logically, exclude it in advance. For example, the defect type SG generated between the scanning line and the signal line occurs only in a region where the scanning line and the signal line intersect. Therefore, SGs detected in places other than this region do not occur logically and can therefore be excluded (no micro measurement).
2. The order in which defects are easily corrected by laser irradiation equipment (or the order in which they are easy to correct)
3. The order of defect occurrence frequency is higher (the higher the occurrence frequency, the higher the probability of being a true defect). Based on these, the final order of micro photography is determined.

  Subsequently, in step S14, a voltage is applied, and the infrared camera 5b for micro measurement performs infrared inspection (micro measurement) under the control of the control unit 7 (micro imaging process), and the position coordinates of the defect are specified. The data is recorded in the data storage unit 10.

  In step S15, it is determined whether or not the micro measurement of all the micro measurement scheduled areas has been completed. If not completed, the process returns to step S13, and if completed, the process proceeds to step S16.

  In step S16, it is determined whether or not the wiring defect detection for all the panels has been completed. If not completed, the probe is moved to the liquid crystal panel 2 to be the next wiring defect detection target, and the wiring defect detection is repeated. On the contrary, when the wiring defect detection has been completed in all of the liquid crystal panels 2, all the processes for wiring defect detection are completed.

(Program and recording medium)
Finally, each block included in the wiring defect detection apparatus 100 may be configured by hardware logic. Alternatively, it may be realized by software using a CPU (Central Processing Unit) as follows.

  That is, the wiring defect detection apparatus 100 includes a CPU that executes instructions of a program that realizes each function, a ROM (Read Only Memory) that stores the program, a RAM (Random Access Memory) that expands the program into an executable format, Also, a storage device (recording medium) such as a memory for storing the program and various data is provided. With this configuration, the object of the present invention can be achieved by a predetermined recording medium.

The recording medium only needs to record the program code (execution format program, intermediate code program, source program) of the program of the wiring defect detection apparatus 100, which is software that realizes the above-described functions, in a computer-readable manner. By supplying this recording medium, the wiring defect detection device 100 (or CPU or MPU) as a computer may read and execute the program code recorded on the supplied recording medium.

  The recording medium that supplies the program code to the wiring defect detection apparatus 100 is not limited to a specific structure or type. That is, the recording medium includes, for example, a tape system such as a magnetic tape and a cassette tape, a magnetic disk such as a floppy (registered trademark) disk / hard disk, and an optical disk such as a CD-ROM / MO / MD / DVD / CD-R. System, a card system such as an IC card (including a memory card) / optical card, or a semiconductor memory system such as a mask ROM / EPROM / EEPROM / flash ROM.

  Further, even if the wiring defect detection device 100 is configured to be connectable to a communication network, the object of the present invention can be achieved. In this case, the program code is supplied to the wiring defect detection apparatus 100 via the communication network. This communication network is not limited to a specific type or form as long as it can supply a program code to the wiring defect detection apparatus 100. For example, it may be the Internet, intranet, extranet, LAN, ISDN, VAN, CATV communication network, virtual private network, telephone line network, mobile communication network, satellite communication network, and the like.

  The transmission medium constituting the communication network may be any medium that can transmit the program code, and is not limited to a specific configuration or type. For example, wired communication such as IEEE 1394, USB (Universal Serial Bus), power line carrier, cable TV line, telephone line, ADSL (Asymmetric Digital Subscriber Line) line, infrared rays such as IrDA and remote control, Bluetooth (registered trademark), 802.11 It can also be used by radio such as radio, HDR, mobile phone network, satellite line, terrestrial digital network. The present invention can also be realized in the form of a computer data signal embedded in a carrier wave in which the program code is embodied by electronic transmission.

(Operational effect of this embodiment)
According to the present embodiment, it is distinguished whether the heat generation location specified in the peripheral circuit portion is heat generation due to a true defect or heat generation due to a pseudo defect. Lower. Therefore, the detection rate of true defects can be improved.

  Specifically, according to the above configuration, if a certain heat generation location specified in the peripheral circuit portion is in the same current path as a certain heat generation location specified in the pixel portion, it is specified in the peripheral circuit portion. The heat generation at the heat generation point is due to a wiring defect in the pixel part, that is, the heat generation part specified in the peripheral circuit part is “representing a pseudo defect” and is specified in the peripheral circuit part. The priority of the micro-photographing of the heat generation point is lowered to give priority to the micro-photographing of the heat generation point specified in the pixel portion. That is, it is possible to postpone micro-photographing of a heat generation portion that is a pseudo defect. On the other hand, if the heat generation location specified in the peripheral circuit portion is not in the same current path as the heat generation location specified in the pixel portion, the heat generation location specified in the peripheral circuit portion represents a true defect ( In other words, assuming that there is a wiring defect in the peripheral area), micro shooting is performed at a predetermined timing without lowering the shooting priority of the micro shooting. Thereby, the detection rate of a true defect can be improved.

In general, in the case of a wiring panel having a relatively large number of wirings or a wiring panel having a small peripheral area (so-called narrow frame), the wiring of the wiring panel is arranged in a straight line in the pixel portion. In the portion, the pixel portion may be formed to be inclined with respect to a straight line portion in the pixel portion. That is, there is a wiring panel in which the wiring is bent in the vicinity of the pixel portion of the peripheral circuit portion. In some cases, the length of the portion formed in the peripheral circuit portion is relatively long, and the end portion of the wiring may be far away from the formation portion in the pixel portion of the wiring. In such a case, if the G block and the S block are set as described above, and each block includes a heat generation location of the peripheral circuit portion and a heat generation location (defect) of the pixel portion, the peripheral circuit It is determined that the heat generation point of the part is due to the defect, that is, the heat generation point of the peripheral circuit part is due to a pseudo defect and is not a true defect, and the priority of micro imaging of the heat generation point of the peripheral circuit part is lowered That is, it is possible to postpone micro-photographing of the heat generation part of the peripheral circuit part.

  As mentioned above, although embodiment concerning this invention was described, this invention is not limited to said embodiment. Various modifications can be made within the scope of the claims, and embodiments obtained by appropriately combining technical means disclosed in the embodiments are also included in the technical scope of the present invention.

  The present invention can be used for detecting the wiring state of a semiconductor substrate having wiring such as a liquid crystal panel.

1 Mother board (wiring panel)
2 Liquid crystal panel (wiring panel)
3 Probe (voltage application means)
4 Probe moving means 5 Infrared camera (for macro measurement) (macro photography infrared camera)
5a Infrared camera 5a-1 to 5a-4 Infrared camera 5b Infrared camera (for micro measurement) (micro imaging infrared camera)
6 Camera moving means 7 Control section (heating point specifying means, determining means, adjusting means, macro photographing means, micro photographing means)
8 Resistance measurement unit 9 Voltage application unit (voltage application means)
DESCRIPTION OF SYMBOLS 10 Data memory | storage part 11 Alignment stage 12 Optical camera 13 for position confirmation, 13a-13f Guide rail 14a-14d Mount part 16 Optical camera 17 for alignment Pixel part (active area)
18 Peripheral circuit (peripheral area)
19 Pad (terminal)
19a-19d pad 21 probe pin 21a-21d probe pin 23 defective part 30 common line 31-35 scanning line (wiring)
41-45 signal lines (wiring)
50 Short-circuit location 100 Wiring defect detection device CsDiffX tolerance CsDiffY tolerance

Claims (6)

A wiring defect detection device for detecting a wiring defect of a wiring panel having wiring arranged over an active area in which active elements are arranged in a matrix and a peripheral area around the active area. There,
Voltage applying means for applying a voltage to the terminal of the wiring;
Macro imaging means for macro-imaging with an infrared camera at least a part of the peripheral area and at least a part of the active area including the wiring to which the voltage is applied by the voltage application means;
From the infrared image obtained by the infrared camera, a heat generation point specifying means for specifying whether or not there is a heat generation point in each of at least a part of the peripheral area and at least a part of the active area,
When it is specified by the heat generation point specifying means that a heat generation point exists in each of at least a part of the peripheral area and at least a part of the active area, it is present in at least a part of the peripheral area. Determining means for determining whether or not the heat generation location and the heat generation location in at least a part of the active area are in the same current path at the time of voltage application;
When it is determined by the determination means that the current path is the same current path, micro-photographing of a region including a heat generation location in at least a part of the active area in the same current path is performed on the same current path. Adjusting means for adjusting the photographing priority so as to preferentially perform micro-photographing of an area including a heat generation point in at least a part of the peripheral area;
A wiring defect detection apparatus comprising: a micro photographing unit that performs micro photographing based on the photographing priority adjusted by the adjusting unit.   When the wiring of the wiring panel is arranged in a straight line across the active area and the peripheral area, the determination means includes the position coordinates of the heat generation location in at least a part of the peripheral area. Comparing the position coordinates of the heat generation points in at least a part of the active area and determining that the heat generation points are in the same current path if they are within a predetermined allowable error range. The wiring defect detection device according to claim 1, wherein   If the wiring is inclined in the portion arranged in the peripheral area with respect to the portion arranged in the active area, the determination means specifies a predetermined range including the wiring. If the heat generation location in at least a part of the peripheral area and the heat generation location in at least a part of the active area are within the predetermined range, the heat generation locations are the same current. The wiring defect detection device according to claim 1, wherein the wiring defect detection device determines that the route is present. A wiring defect detection method for detecting a wiring defect of a wiring panel having wiring arranged over an active area in which active elements are arranged in a matrix and a peripheral area around the active area. There,
A voltage application step of applying a voltage to the terminal of the wiring;
A macro imaging step of performing macro imaging with an infrared camera of at least a part of the peripheral area and at least a part of the active area including the wiring to which the voltage is applied in the voltage application step;
A heat generation point specifying step for specifying whether or not there is a heat generation point in each of at least a part of the peripheral area and at least a part of the active area from the infrared image obtained by the macro imaging step; ,
If it is determined in the heat generation location identifying step that there are heat generation locations in each of at least a part of the peripheral area and at least a part of the active area, they are present in at least a part of the peripheral area. A determination step of determining whether the heat generation location and the heat generation location in at least a part of the active area are in the same current path at the time of voltage application;
If it is determined in the determination step that the current path is the same current path, micro-photographing of a region including a heat generation location in at least a part of the active area in the same current path is performed on the same current path. An adjustment step of adjusting the imaging priority so as to be performed in preference to the micro-imaging of the area including the heat generation point in at least a part of the peripheral area;
And a micro imaging process for micro imaging based on the imaging priority adjusted by the adjustment process.   The program for operating the wiring defect detection apparatus of any one of Claim 1 to 3, Comprising: The program for functioning a computer as said each means.   A computer-readable recording medium in which the program according to claim 5 is recorded.

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