JP2013200574A5 - Display device - Google Patents
Display device Download PDFInfo
- Publication number
- JP2013200574A5 JP2013200574A5 JP2013118657A JP2013118657A JP2013200574A5 JP 2013200574 A5 JP2013200574 A5 JP 2013200574A5 JP 2013118657 A JP2013118657 A JP 2013118657A JP 2013118657 A JP2013118657 A JP 2013118657A JP 2013200574 A5 JP2013200574 A5 JP 2013200574A5
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- layer
- insulating layer
- insulating
- provided above
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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- 230000015572 biosynthetic process Effects 0.000 claims 4
- 239000004065 semiconductor Substances 0.000 claims 4
- 239000000758 substrate Substances 0.000 claims 4
- 230000000903 blocking effect Effects 0.000 claims 3
- 239000011347 resin Substances 0.000 claims 2
- 229920005989 resin Polymers 0.000 claims 2
Claims (2)
前記第１の絶縁層は、前記第１の導電層の上方に設けられ、
前記第２の導電層は、前記第１の絶縁層の上方に設けられ、
前記第２の絶縁層は、前記第２の導電層の上方に設けられ、
前記第３の導電層は、前記第２の絶縁層の上方に設けられ、
前記第１の導電層は、トランジスタのチャネル形成領域と重なる領域を有し、
前記第１の導電層は、光を遮ることができる機能を有し、
前記第３の導電層は、前記トランジスタと電気的に接続され、
前記第２の絶縁層は、樹脂を有し、
前記第２の導電層は、前記第１の絶縁層を介して、前記第１の導電層と重なる領域を有し、
前記第３の導電層は、前記第２の絶縁層に設けられた開口において前記第２の導電層と接する領域を有し、
前記基板表面の複数の垂線のうちの少なくとも一つの垂線を含む複数の平面のうちの少なくとも一つの平面において、前記第１の導電層は、前記第１の絶縁層の端部よりも突出した領域を有し、
当該平面において、前記第１の絶縁層は、前記第２の導電層の端部よりも突出した領域を有することを特徴とする表示装置。 A first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer above the substrate surface;
The first insulating layer is provided above the first conductive layer,
The second conductive layer is provided above the first insulating layer,
The second insulating layer is provided above the second conductive layer,
The third conductive layer is provided above the second insulating layer,
The first conductive layer has a region overlapping with a channel formation region of a transistor,
The first conductive layer has a function of blocking light.
The third conductive layer is electrically connected to the transistor,
The second insulating layer has a resin,
The second conductive layer has a region overlapping with the first conductive layer via the first insulating layer,
The third conductive layer has a region in contact with the second conductive layer at an opening provided in the second insulating layer,
In at least one plane of the plurality of planes including at least one perpendicular line of the plurality of perpendicular lines of the substrate surface, the first conductive layer protrudes from the end of the first insulating layer Have
A display device characterized in that, in the plane, the first insulating layer has a region which protrudes more than an end portion of the second conductive layer.
前記第１の絶縁層は、前記第１の導電層の上方に設けられ、
前記第２の導電層は、前記第１の絶縁層の上方に設けられ、
前記第２の絶縁層は、前記第２の導電層の上方に設けられ、
前記第３の導電層は、前記第２の絶縁層の上方に設けられ、
前記半導体層は、トランジスタのチャネル形成領域を有し、
前記第１の導電層は、前記半導体層の上方に設けられ、前記チャネル形成領域と重なる領域を有し、
前記第１の導電層は、光を遮ることができる機能を有し、
前記第４の導電層は、前記半導体層の下方に設けられ、前記チャネル形成領域と重なる領域を有し、
前記第４の導電層は、前記トランジスタのゲート電極と電気的に接続され、
前記第４の導電層は、光を遮ることができる機能を有し、
前記第３の導電層は、光を透過することができる機能を有し、
前記第２の絶縁層は、樹脂を有し、
前記第２の導電層は、前記第１の絶縁層を介して、前記第１の導電層と重なる領域を有し、
前記第３の導電層は、前記第２の絶縁層に設けられた開口において前記第２の導電層と接する領域を有し、
前記基板表面の複数の垂線のうちの少なくとも一つの垂線を含む複数の平面のうちの少なくとも一つの平面において、前記第１の導電層は、前記第１の絶縁層の端部よりも突出した領域を有し、
当該平面において、前記第１の絶縁層は、前記第２の導電層の端部よりも突出した領域を有することを特徴とする表示装置。 The first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the first insulating layer, the second insulating layer, and the semiconductor layer above the substrate surface And
The first insulating layer is provided above the first conductive layer,
The second conductive layer is provided above the first insulating layer,
The second insulating layer is provided above the second conductive layer,
The third conductive layer is provided above the second insulating layer,
The semiconductor layer has a channel formation region of a transistor,
The first conductive layer is provided above the semiconductor layer and has a region overlapping the channel formation region,
The first conductive layer has a function of blocking light.
The fourth conductive layer is provided below the semiconductor layer, and has a region overlapping the channel formation region,
The fourth conductive layer is electrically connected to the gate electrode of the transistor,
The fourth conductive layer has a function of blocking light.
The third conductive layer has a function of transmitting light,
The second insulating layer has a resin,
The second conductive layer has a region overlapping with the first conductive layer via the first insulating layer,
The third conductive layer has a region in contact with the second conductive layer at an opening provided in the second insulating layer,
In at least one plane of the plurality of planes including at least one perpendicular line of the plurality of perpendicular lines of the substrate surface, the first conductive layer protrudes from the end of the first insulating layer Have
A display device characterized in that, in the plane, the first insulating layer has a region which protrudes more than an end portion of the second conductive layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013118657A JP2013200574A (en) | 2013-06-05 | 2013-06-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013118657A JP2013200574A (en) | 2013-06-05 | 2013-06-05 | Semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2012244153A Division JP5386626B2 (en) | 2012-11-06 | 2012-11-06 | Display device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013210800A Division JP5685633B2 (en) | 2013-10-08 | 2013-10-08 | Display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2013200574A JP2013200574A (en) | 2013-10-03 |
| JP2013200574A5 true JP2013200574A5 (en) | 2013-11-21 |
Family
ID=49520813
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013118657A Withdrawn JP2013200574A (en) | 2013-06-05 | 2013-06-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2013200574A (en) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10339885A (en) * | 1997-06-09 | 1998-12-22 | Hitachi Ltd | Active matrix type liquid crystal display device |
| JP3980156B2 (en) * | 1998-02-26 | 2007-09-26 | 株式会社半導体エネルギー研究所 | Active matrix display device |
| JP3941901B2 (en) * | 1998-04-28 | 2007-07-11 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| JP3788707B2 (en) * | 1998-08-06 | 2006-06-21 | 株式会社半導体エネルギー研究所 | Semiconductor device and manufacturing method thereof |
| TW478014B (en) * | 1999-08-31 | 2002-03-01 | Semiconductor Energy Lab | Semiconductor device and method of manufacturing thereof |
| JP5449415B2 (en) * | 2012-01-19 | 2014-03-19 | 株式会社東芝 | Semiconductor light emitting device |
-
2013
- 2013-06-05 JP JP2013118657A patent/JP2013200574A/en not_active Withdrawn
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