JP2013165112A - Aggregate substrate for chip resistor and manufacturing method of chip resistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an aggregate substrate suitable for multi-piece chip resistors in which imperfect contact of a probe is less likely to occur, and to provide a manufacturing method of a chip resistor using the aggregate substrate.SOLUTION: On the front and back principal surfaces of an aggregate substrate 10, as rectangular regions sectioned by split grooves 11, 12 of lattice shape, a plurality of adjoining first chip regions A1 and second chip regions A2 of the same size are arranged, so that the chip regions A1 of one principal surface and the chip regions A2 of the other principal surface have a positional relation corresponding on the front and back. A pair of front surface electrodes 3a being bridged to a resistor 5 are provided at both ends of each first chip region A1 in the longitudinal direction, and a pair of back surface electrodes 3b are provided at both ends of each second chip region A2 in the longitudinal direction. The front surface electrodes 3a and the back surface electrodes 3b in the chip regions A1, A2 adjoining via the split groove 11 are continuous. When forming a trimming groove 8, resistance is measured by touching a probe 20 to an electrode pattern 3 including both electrodes 3a, 3b.

Description

  The present invention relates to a chip resistor collective substrate in which a large number of chip resistors are obtained by dividing along a grid-like dividing line, and a chip resistor manufacturing method performed using the collective substrate.

  The chip resistor is a rectangular parallelepiped insulating base, electrode portions provided at both ends of the insulating base in the longitudinal direction, a resistor that bridges the paired electrode portions, and a resistor covering It is mainly composed of an insulating protective coat. The insulating base is made of ceramic or the like, and the electrode part is formed by plating the base electrode layer. The base electrode layer includes a front electrode, a back electrode, and an end face electrode that bridges both electrodes, and a pair of surface electrodes are bridged by a resistor on one side of the insulating base.

  When manufacturing such a chip resistor, after forming a large number of electrodes, resistors, protective coatings, etc. on a large aggregate substrate at once, the aggregate substrate is divided into a grid-like dividing line ( For example, a large number of chip resistors are taken along a dividing groove. In the manufacturing process of such a chip resistor, a large number of resistors are printed and formed in a predetermined arrangement on one main surface of the collective substrate. However, such as misalignment and bleeding during printing, or uneven temperature in the firing furnace, etc. Due to the influence, it is difficult to avoid slight variations in the size and film thickness of each resistor. Therefore, when manufacturing a chip resistor, a resistance value adjustment operation is performed in which trimming grooves are formed in each resistor in the state of the collective substrate and set to a desired resistance value (electric resistance).

  FIG. 17 is a plan view showing a state before resistance value adjustment in a conventional general chip resistor aggregate board, and FIG. 18 is a cross-sectional view of the aggregate board. In these figures, both front and back main surfaces of the aggregate board 30 are shown. Is divided into a large number of rectangular chip regions A by lattice-shaped dividing lines 31 and 32. On one main surface S1 of the collective substrate 30, a pair of surface electrodes 33 are printed and formed on both end portions in the longitudinal direction (the left-right direction in the drawing) in each chip region A. A bridging resistor 34 is printed. Although the surface electrodes 33 of the chip regions A adjacent in the longitudinal direction are continuous across the dividing line 31 extending in the vertical direction in the figure, the collective substrate 30 is along the dividing line 31 in the primary dividing step. Divided. In addition, on the other main surface S2 of the collective substrate 30, a pair of back surface electrodes 35 are printed on both ends of each chip region A in the longitudinal direction, and the back surface electrodes 35 of the chip regions A adjacent in the longitudinal direction are formed. Is also continuous across the dividing line 31. Then, after covering each resistor 34 exposed on the main surface S1 of the collective substrate 30 with an unillustrated undercoat (first-layer protective coat), the resistance value of each resistor 34 is adjusted one by one. .

  When the resistance value of the resistor 34 is adjusted, a laser beam is applied to the resistor 34 in a state where a probe for measurement (not shown) is in contact with the pair of surface electrodes 33 bridged by the resistor 34. Irradiation forms trimming grooves. Since the resistance value increases as the trimming groove is lengthened, the laser beam irradiation is turned off when the resistance value of the resistor 34 to be trimmed reaches a desired value.

  After the resistance value adjustment, the resistor 34, the trimming groove, the undercoat, and the like are covered with an overcoat that is a second-layer protective coat. Further, the aggregate substrate 30 is divided into strip-shaped substrates in the primary dividing step, and after forming the end face electrodes on the dividing surface, the secondary dividing step of dividing the strip-shaped substrate into individual pieces along the dividing lines 32. Is done. Then, a plated layer of nickel, solder, or the like is deposited on the individual base electrode layer (front electrode, back electrode, and end electrode) of the singulated chip to form the electrode portion, thereby completing the chip resistor.

  By the way, when the miniaturization of the chip resistor is promoted, the chip region A in the collective substrate 30 is narrowed and the surface electrode 33 is reduced in area. It becomes increasingly difficult to make contact. If a probe contact failure occurs, an accurate resistance value cannot be measured, and the manufacturing yield is greatly reduced. Therefore, even when the chip area of the collective substrate becomes narrower as the chip resistor is made smaller, it extends from the surface electrode in the vicinity of the chip area so that the resistance value can be stably measured by the probe. Conventionally, a technique of providing the measured electrodes that have been provided has been proposed (see, for example, Patent Document 1). Such a measurement electrode is provided in an excision blank portion of the collective substrate that is not used as a chip resistor, and the measurement electrode and the surface electrode are collectively printed.

JP 2005-303199 A

  If the measurement electrode extending from the surface electrode is provided in the vicinity of the chip region as in the collective substrate described in Patent Document 1, the probe is brought into contact with a relatively large electrode pattern including both electrodes. Since the resistance value of the resistor can be measured by this, even when the surface electrode is reduced in area, poor probe contact is less likely to occur when the trimming groove is formed. However, in such a conventional collective substrate, it is necessary to secure an excision blank portion in the vicinity of the chip region in order to form the measurement electrode, so that the number of chip resistors obtained from one collective substrate is reduced. There was a problem of poor productivity.

  The present invention has been made in view of such a state of the art, and a first object of the present invention is to provide a collective substrate that is suitable for picking up a large number of chip resistors and is unlikely to cause poor probe contact. It is in. A second object of the present invention is to provide a manufacturing method suitable for manufacturing a chip resistor using such an aggregate substrate.

  In order to achieve the first object described above, the present invention divides along a grid-like dividing line, thereby having a resistor and a surface electrode on one side and a back electrode on the opposite side. In a collective substrate from which resistors are obtained collectively, a first chip region and a second chip region having the same size are adjacent to each other on both the front and back main surfaces as rectangular regions defined by the dividing lines. A plurality of the surface electrodes that are bridged by the resistor are provided at both ends in the longitudinal direction of the first chip region, and the longitudinal direction of the second chip region. A pair of the back surface electrodes is provided at both ends of the surface, and the front surface electrode and the back surface electrode in the first and second chip regions adjacent to each other via the dividing line are continuous. did.

  As described above, the first chip region where the front surface electrode of the chip resistor is provided and the second chip region where the back surface electrode of another chip resistor is provided are adjacent to each other on both the front and back main surfaces of the collective substrate. As a result, a relatively large electrode pattern in which the front electrode and the back electrode in the adjacent first and second chip regions are continuous can be formed. When the chip resistor is downsized, the surface electrode is reduced in area to ensure the effective length of the resistor, but the back electrode soldered to the land does not need to be as small as the surface electrode. Therefore, even if the surface electrode is reduced in area, it is not necessary to make the entire electrode pattern including the back electrode extremely small, and when adjusting the resistance value for forming the trimming groove in the resistor, the probe is brought into contact with this electrode pattern. This makes it possible to easily measure the resistance value. In addition, the electrode pattern including the front electrode and the back electrode may be provided in the adjacent first and second chip regions, and it is necessary to secure an excision blank region for extending the electrode pattern in the vicinity of the chip region. Therefore, the number of chip resistors obtained from one collective substrate can be increased by arranging the first and second chip regions at high density.

  Since the back electrode does not need to be as small as the front electrode as described above, the distance between the back electrodes forming the second chip region pair is larger than the distance between the surface electrodes forming the first chip region pair. Is preferably set narrowly. By doing so, it becomes easy to secure a required area for the electrode pattern in contact with the probe.

  Further, in such a chip resistor aggregate substrate, the first chip regions and the second chip regions are alternately arranged along the longitudinal direction of the both, and in the short direction of the first chip region, When only the first chip regions are arranged and only the second chip regions are arranged in the short direction of the second chip region, the trimming grooves are formed and then arranged in a row in the short direction. It is preferable because a plurality of aligned chip regions can be collectively covered with a band-shaped protective coat.

  In order to achieve the second object, the present invention divides the collective substrate along a grid-like dividing line, thereby having a resistor and a surface electrode on one side and a back electrode on the opposite side. In the chip resistor manufacturing method in which the chip resistors having the above are obtained in a lump, the first chip having the same size as a rectangular region partitioned by the dividing lines on both the front and back main surfaces of the collective substrate After arranging a plurality of regions and second chip regions so as to be adjacent to each other, the longitudinal direction of the second chip region crosses the dividing line from the longitudinal end of the first chip region. A step of forming an electrode pattern so as to extend to an end of the first electrode, and the resistor that bridges the electrode patterns that form a pair at both ends in the longitudinal direction in the first chip region. The process of forming and A step of adjusting a resistance value by forming a trimming groove in the resistor while measuring a resistance value by bringing a probe into contact with the electrode pattern to be formed; and covering the resistor having the trimming groove with a protective coat Thereafter, the method includes a step of dividing the collective substrate along the dividing line to obtain the front surface electrode and the back surface electrode of different chip resistors from the electrode pattern.

  Thus, the electrode pattern extending from the longitudinal end portion of the first chip region to the longitudinal end portion of the second chip region across the dividing line is a chip resistor in the first chip region. In the second chip region, it can be a back electrode of another chip resistor. When the chip resistor is downsized, the surface electrode is reduced in area to ensure the effective length of the resistor, but the back electrode soldered to the land does not need to be as small as the surface electrode. Therefore, even if the surface electrode is reduced in area, it is not necessary to make the entire electrode pattern including the back electrode extremely small, and when adjusting the resistance value for forming the trimming groove in the resistor, the probe is brought into contact with this electrode pattern. Therefore, the resistance value can be easily measured. In addition, since the electrode pattern including the front electrode and the back electrode may be provided in the adjacent first and second chip regions, a blank space for extending the electrode pattern in the vicinity of the chip region is provided on the collective substrate. There is no need to reserve the area. Therefore, it is possible to increase the number of chip resistors obtained from one collective substrate by arranging the first and second chip regions at high density.

  According to the chip resistor aggregate substrate of the present invention, a relatively large electrode pattern in which the front surface electrode and the back surface electrode in the adjacent first and second chip regions are continuous can be formed. Even if the surface electrode is reduced in size with the increase in size, it is not necessary to make the entire electrode pattern including the back electrode extremely small. Therefore, when adjusting the resistance value for forming the trimming groove in the resistor, the resistance value can be easily measured by bringing the probe into contact with the electrode pattern. In addition, since this chip resistor assembly substrate does not need to secure an excision blank area for extending the electrode pattern in the vicinity of the chip area, the first and second chip areas are arranged with high density, and 1 It is possible to increase the number of chip resistors obtained from a single aggregate substrate. Therefore, the collective substrate of the present invention has an excellent effect that it is suitable for picking up a large number of chip resistors and hardly causes poor probe contact.

  In the method for manufacturing a chip resistor according to the present invention, the electrode pattern extending from the end in the longitudinal direction of the first chip region to the end in the longitudinal direction of the adjacent second chip region is in the first chip region. Can be used as the front electrode of the chip resistor, and can be used as the back electrode of the chip resistor in the second chip region. Therefore, according to the manufacturing method of the present invention, even if the surface electrode is reduced in size as the chip resistor is downsized, it is not necessary to make the entire electrode pattern including the back electrode extremely small, and the resistor is trimmed. At the time of adjusting the resistance value for forming the groove, the resistance value can be easily measured by bringing the probe into contact with the electrode pattern. Further, this electrode pattern may be provided in the first and second chip regions, and it is not necessary to secure a cut blank region for extending the electrode pattern in the vicinity of the chip region on the collective substrate. The number of chip resistors obtained from one collective substrate can be increased by arranging the first and second chip regions at high density. Therefore, by adopting the method of the present invention, a small chip resistor can be manufactured efficiently and inexpensively.

It is process drawing of planar view which shows the state which formed the electrode pattern in the collective board in the manufacture process of the chip resistor which concerns on the example of embodiment of this invention. It is process drawing of the cross sectional view which shows the same state as FIG. It is process drawing of planar view which shows the state which formed the resistor in the aggregate substrate of FIG. FIG. 4 is a cross-sectional process diagram illustrating the same state as FIG. 3. FIG. 4 is a process view in plan view showing a state in which trimming grooves are formed in the resistor of FIG. 3. FIG. 6 is a cross-sectional process diagram illustrating the same state as FIG. 5. It is process drawing of planar view which shows the state which formed the protective coat in the aggregate substrate of FIG. FIG. 8 is a cross-sectional process diagram illustrating the same state as FIG. 7. It is process drawing of planar view which shows the state which divided | segmented the assembly board | substrate of FIG. 7 into the strip-shaped board | substrate primarily. FIG. 10 is a cross-sectional process diagram illustrating the same state as FIG. 9; It is process drawing of planar view which shows the state which formed the end surface electrode in the strip-shaped board | substrate of FIG. FIG. 12 is a sectional view showing the same state as FIG. 11. It is process drawing of planar view which shows the state which divided | segmented the strip-shaped board | substrate of FIG. 11 into the chip | tip single-piece | unit. FIG. 14 is a cross-sectional process diagram illustrating the same state as that of FIG. 13. It is a top view which shows the chip resistor completed by performing the plating process to the chip single-piece | unit of FIG. It is sectional drawing of the chip resistor shown in FIG. It is a top view which shows the state before resistance value adjustment in the aggregate substrate for chip resistors which concerns on a prior art example. It is sectional drawing of the aggregate substrate shown in FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIGS. 1 to 14 are manufacturing process diagrams of a chip resistor according to an embodiment of the present invention, and FIGS. 15 and 16 are completed chip resistors. Shows the vessel. 1 and 2 show the same steps, and similarly, FIGS. 3 and 4, FIGS. 5 and 6, FIGS. 7 and 8, FIGS. 9 and 10, FIGS. 11 and 12, FIGS. FIG. 14 shows the same process.

  First, the configuration of the chip resistor 1 shown in FIGS. 15 and 16 will be described. The chip resistor 1 includes a rectangular parallelepiped insulating base 2, a pair of surface electrodes 3 a provided at both ends in the longitudinal direction on the upper surface of the insulating base 2, and a longitudinal length on the lower surface of the insulating base 2. A pair of back surface electrodes 3b provided at both ends of the direction, a pair of end surface electrodes 4 provided on the side surface of the insulating base 2 and bridging the electrodes 3a, 3b, and the insulating base 2 A resistor 5 provided on the upper surface and bridging the surface electrodes 3a on both sides in the longitudinal direction, an insulating protective coat 6 covering the resistor 5, and a plating layer covering the electrodes 3a, 3b, 4 7 is mainly composed.

  The insulating base 2 is made of ceramic or the like, and the insulating base 2 is separated into pieces by dividing the collective substrate 10 shown in FIGS. 1 to 8 along the grid-like dividing grooves 11 and 12. It is.

  The surface electrode 3a, the end face electrode 4 and the back face electrode 3b are formed at both ends in the longitudinal direction of the insulating base 2 as a base electrode layer continuous in a U-shape, and the plating layer 7 is attached to the base electrode layer. Thus, the electrode part of the chip resistor 1 is formed. The front surface electrode 3a and the back surface electrode 3b are collectively formed on the main surface of the collective substrate 10, while the end surface electrode 4 is a divided surface of a strip-shaped substrate 13 (see FIG. 9) obtained by dividing the collective substrate 10 into primary parts. It is formed. The plating layer 7 includes an innermost nickel (Ni) plating layer in close contact with the base electrode layer, and an outermost solder (Sn / Pb) plating layer or tin (Sn) plating layer exposed on the outer surface. It has a laminated structure of two or more layers.

  The resistor 5 is made of ruthenium oxide or the like, and a trimming groove 8 (see FIG. 5) is formed in the resistor 5 in order to adjust the resistance value. As will be described later, the trimming groove 8 is formed by irradiating a laser beam in the state of the collective substrate 10. During this laser trimming, a probe is applied to the electrode pattern 3 existing on both sides in the longitudinal direction of the resistor 5. The resistance 5 is set to a desired resistance value by measuring the resistance value by bringing 20 (see FIG. 5) into contact therewith.

  The protective coat 6 has a two-layer structure of an undercoat that covers the resistor 5 before the trimming groove 8 is formed and an overcoat provided on the undercoat, of which the undercoat is not shown. That is, the overcoat shown as the protective coat 6 is formed after the trimming groove 8 is formed in the resistor 5, and the undercoat, the resistor 5, the trimming groove 8, and the like are covered by this overcoat. ing.

  Next, a manufacturing method of the chip resistor 1 configured as described above will be described with reference to FIGS.

  First, a collective substrate 10 is prepared in which primary division grooves 11 and secondary division grooves 12 extending in a lattice shape in the vertical and horizontal directions are formed in advance. By these lattice-shaped dividing grooves 11 and 12, both the front and back main surfaces of the collective substrate 10 are partitioned into a number of rectangular chip regions. Each chip region corresponds to the upper surface (the surface where the front surface electrode 3a and the resistor 5 are present) or the lower surface (the surface where the rear surface electrode 3b is present) of one chip resistor 1. As shown in FIGS. 1 to 8, the front and back main surfaces of the collective substrate 10 are provided with a first chip region A1 corresponding to the upper surface of the chip resistor 1 and a second chip corresponding to the lower surface of the chip resistor 1. The chip regions A2 are arranged so as to be adjacent to each other in the horizontal direction of the figure (the longitudinal direction of the chip resistor 1). That is, the first chip area A1 and the second chip area A2, which are rectangular areas of the same size, are alternately arranged along the longitudinal direction of both the front and back main surfaces of the collective substrate 10, The first chip area A1 on one main surface and the second chip area A2 on the other main surface are set to have a corresponding positional relationship on the front and back. That is, the second chip region A2 on the lower surface side is located directly below the arbitrary first chip region A1 existing on the upper surface of the collective substrate 10, and is directly below the arbitrary second chip region A2 existing on the upper surface of the collective substrate 10. The first chip region A1 on the lower surface side is located at the bottom. However, as is clear from FIG. 1, only the first chip region A1 is arranged in the short direction of the first chip region A1, and the second chip region is arranged in the short direction of the second chip region A2. The arrangement is such that only A2 are arranged.

  Then, a silver paste or the like is screen-printed and fired on the front and back main surfaces of the collective substrate 10 so as to cross the primary dividing groove 11, thereby forming electrodes of a predetermined size as shown in FIGS. 1 and 2. Pattern 3 is formed. In the electrode pattern 3, a portion existing in the first chip region A1 corresponds to the front surface electrode 3a, and a portion existing in the second chip region A2 corresponds to the back surface electrode 3b. That is, by forming the electrode pattern 3, the surface electrode 3a is provided at both ends in the longitudinal direction of the first chip region A1, and the back electrode 3b is provided at both ends in the longitudinal direction of the second chip region A2. Thus, the front electrode 3a and the back electrode 3b in the first and second chip regions A1 and A2 adjacent in the longitudinal direction continuously form one electrode pattern 3.

  In the next step, as shown in FIGS. 3 and 4, a resistor paste such as ruthenium oxide is screen-printed on all the first chip regions A1 arranged on the front and back main surfaces of the collective substrate 10. By firing, the resistors 5 in which both end portions in the longitudinal direction are superimposed on the electrode pattern 3 in each chip region A1 are collectively formed. In this step, the pair of surface electrodes 3a that form a pair in each first chip region A1 are bridged by the resistor 5.

  Thereafter, the undercoat (not shown) is formed by screen-printing and baking a glass paste in a region covering each resistor 5 individually. This undercoat is for preventing the vicinity of the trimming groove 8 of the resistor 5 from being damaged by the heat of the laser beam irradiated in the next step.

  That is, in the next step, in order to adjust the resistance value of each resistor 5, the trimming groove 8 is formed by sequentially irradiating a number of resistors 5 covered with the undercoat with a laser beam. (See FIGS. 5 and 6). At that time, the probe 20 is brought into contact with the electrode patterns 3 existing on both sides in the longitudinal direction of the resistor 5 to be trimmed, and laser trimming is performed while measuring the resistance value through the probes 20. When the laser beam irradiation is started and the trimming groove 8 becomes longer, the resistance value increases accordingly. Therefore, when the resistance value of the resistor 5 to be trimmed reaches a desired value, the laser beam irradiation is performed. Turn off. Since the electrode pattern 3 that is a continuous body of the front surface electrode 3a and the back surface electrode 3b is relatively large, the probe 20 is connected to the electrode pattern 3 even if the chip regions A1 and A2 are narrowed as the chip resistor 1 is downsized. It is easy to contact.

  When the laser trimming is completed for all the resistors 5 existing on both the front and back main surfaces of the collective substrate 10, as the next step, a resin paste (or glass paste) covering the undercoat, the resistor 5, the trimming groove 8, etc. ) Is screen-printed and cured by heating to form a protective coat 6 that is a belt-like overcoat (see FIGS. 7 and 8). This protective coat (overcoat) 6 is for protecting the resistor 5 from the external environment.

  The process up to this point is a batch process for the collective substrate 10. In the next process, a primary break process is performed in which the collective substrate 10 is divided into strips along the primary division grooves 11, and FIG. 9 and FIG. A strip-shaped substrate 13 as shown in FIG. In this step, each electrode pattern 3 is divided by the primary dividing groove 11, and therefore, the front electrode 3 a and the back electrode 3 b of the chip resistor 1 different from each other can be obtained from each electrode pattern 3.

  In the next step, the end face electrode 4 is formed by sputtering Ni / Cr or the like on the dividing surface of the strip-shaped substrate 13. Since the end surface electrode 4 bridges the front surface electrode 3a and the back surface electrode 3b, the base electrode layer continuous in a U-shape is obtained as shown in FIGS.

  Thereafter, a secondary break process is performed in which the strip-shaped substrate 13 is divided along the secondary dividing grooves 12. As a result, as shown in FIGS. 13 and 14, a piece (chip alone) having a size equivalent to that of the chip resistor 1 is obtained. The chip thus separated has a base electrode layer (surface electrode 3a, back electrode 3b, and end electrode 4) at both ends in the longitudinal direction of the insulating base 2, and the paired surface electrodes 3a are bridged. The tangled resistor 5 is covered with a protective coat 6.

  Finally, a nickel-plated or solder-plated nickel plating or solder plating is applied to the base electrode layer (surface electrode 3a, back electrode 3b, and end face electrode 4) of each chip alone to form a plated layer 7 having a laminated structure that covers the base electrode layer. Thus, the chip resistor 1 as shown in FIGS. 15 and 16 is completed.

  In the present embodiment, the first and second chip regions A1 and A2 are partitioned by engraving the grid-like dividing grooves 11 and 12 on the collective substrate 10, but the grid shape set as a virtual line is used. It is also possible to divide the chip region by dividing lines and to cut the collective substrate 10 with a laser beam or the like along the dividing lines.

  As described above, in this embodiment, the first chip area A1 where the front electrode 3a is provided and the second chip area A2 where the back electrode 3b is provided are provided on the front and back main surfaces of the collective substrate 10. Since they are set so as to be adjacent to each other in the longitudinal direction, a relatively large electrode pattern 3 in which the front surface electrode 3a and the back surface electrode 3b in the adjacent first and second chip regions A1 and A2 are continuous can be formed. . That is, the electrode pattern 3 extending from the end portion in the longitudinal direction of the first chip region A1 to the end portion in the longitudinal direction of the second chip region A2 across the primary dividing groove (partition line) 11 is In one chip region A1, it can be the surface electrode 3a of the chip resistor 1, and in the second chip region A2, it can be the back electrode 3b of another chip resistor 1. When the chip resistor 1 is downsized, the surface electrode 3a is reduced in area to ensure the effective length of the resistor 5, but the back electrode 3b soldered to the land needs to be as small as the surface electrode 3a. Absent. Therefore, even if the surface electrode 3a is reduced in area, it is not necessary to make the entire electrode pattern 3 including the back electrode 3b extremely small, and the laser trimming that forms the trimming groove 8 in the resistor 5 in order to adjust the resistance value. Sometimes, the resistance value can be easily measured by bringing the probe 20 into contact with the electrode pattern 3. In addition, the electrode pattern 3 including the front electrode 3a and the back electrode 3b may be provided in the adjacent first and second chip regions A1 and A2. Therefore, the electrode pattern 3 is provided near the chip region on the collective substrate 10. Therefore, it is not necessary to secure a resection margin area for extending the length. Therefore, in order to increase productivity, the first and second chip regions A1 and A2 can be arranged at high density to increase the number of chip resistors 1 obtained from one collective substrate 10, and as a result. As a result, a small chip resistor can be manufactured at low cost.

  In this embodiment, the back electrode 3b is formed to be about twice as large as the front electrode 3a. However, the area ratio between the electrodes 3b and 3a is the size of the land to which the back electrode 3b is soldered. The size can be appropriately selected in consideration of the overall size of the chip resistor 1 and the like. However, the back electrode 3b is preferably formed to be larger than at least the front electrode 3a, and this makes it easy to secure a required area for the electrode pattern 3 with which the probe 20 is brought into contact.

  In the present embodiment, the first chip area A1 and the second chip area A2 are alternately arranged along the longitudinal direction of the first chip area A1, and the first chip area A1 is short in the short direction of the first chip area A1. Since only the chip area A1 is arranged and only the second chip area A2 is arranged in the short direction of the second chip area A2, a plurality of chip areas arranged in a row by the protective coat 6 are collected. Can be coated. However, the present invention is not limited to this. For example, the first chip region A1 and the second chip region A2 are alternately arranged along the short direction of both, and the first chip region A1. Even if the first chip region A1 is arranged in the longitudinal direction of the second chip region and only the second chip region A2 is arranged in the longitudinal direction of the second chip region A2, the chips are adjacent in the short direction. It is possible to form a relatively large electrode pattern 3 in which the front surface electrode 3a and the back surface electrode 3b in the regions A1 and A2 are continuous. In this case, however, each chip area must be individually covered with the protective coat 6.

DESCRIPTION OF SYMBOLS 1 Chip resistor 2 Insulation base 3 Electrode pattern 3a Front surface electrode 3b Back surface electrode 4 End surface electrode 5 Resistor 6 Protective coating 7 Plating layer 8 Trimming groove 10 Collective substrate 11, 12 Divided groove (divided line)
13 Strip board 20 Probe A1 First chip area A2 Second chip area

Claims (4)

By dividing along a grid-like dividing line, a collective substrate is obtained in which chip resistors having a resistor and a surface electrode on one side and a back electrode on the opposite side are collectively obtained,
As a rectangular area defined by the dividing lines, a plurality of first chip areas and second chip areas having the same size are arranged side by side on both the front and back main surfaces, respectively,
A pair of the surface electrodes bridged by the resistor is provided at both longitudinal ends of the first chip region, and a pair of the back electrodes are disposed at both longitudinal ends of the second chip region. A collective substrate for chip resistors, characterized in that the front electrode and the back electrode in the first and second chip regions which are provided and are adjacent to each other via the dividing line are continuous.   The interval between the back electrodes forming the pair of the second chip regions is set to be narrower than the interval between the surface electrodes forming the pair of the first chip regions. An aggregate substrate for chip resistors.   3. The first chip area and the second chip area are alternately arranged along the longitudinal direction of both of the first chip area and the second chip area in a short direction of the first chip area. A chip resistor assembly substrate, wherein only the first chip regions are arranged, and only the second chip regions are arranged in a short direction of the second chip region. Manufacture of a chip resistor in which a chip resistor having a resistor and a surface electrode on one side and a back electrode on the opposite side is obtained by dividing the aggregate substrate along a grid-like division line A method,
A plurality of first chip areas and second chip areas having the same size are arranged side by side as a rectangular area partitioned by the dividing lines on the front and back main surfaces of the collective substrate. And forming an electrode pattern so as to extend from the longitudinal end of the first chip region across the dividing line to the longitudinal end of the second chip region;
Forming, in the first chip region, the resistor that bridges the electrode patterns that are paired at both ends in the longitudinal direction;
A step of adjusting a resistance value by forming a trimming groove in the resistor while measuring a resistance value by bringing a probe into contact with the paired electrode patterns;
After covering the resistor in which the trimming groove is formed with a protective coat, the aggregate substrate is divided along the dividing line, and the surface electrode and the back electrode of the chip resistor different from the electrode pattern are formed. And a step of obtaining the chip resistor.