JP2013157377A - Soldering method of semiconductor device and soldering jig - Google Patents
Soldering method of semiconductor device and soldering jig Download PDFInfo
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- JP2013157377A JP2013157377A JP2012015140A JP2012015140A JP2013157377A JP 2013157377 A JP2013157377 A JP 2013157377A JP 2012015140 A JP2012015140 A JP 2012015140A JP 2012015140 A JP2012015140 A JP 2012015140A JP 2013157377 A JP2013157377 A JP 2013157377A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
Abstract
Description
この発明は、半導体モジュールなどの半導体装置の半田付け方法および半田付け治具に関する。 The present invention relates to a soldering method and a soldering jig for a semiconductor device such as a semiconductor module.
半導体モジュールなどの半導体装置では、銅ベースと導電パターン付絶縁基板および導電パターン付絶縁基板と半導体チップを半田などの接合材を用いて接合することが多い。つぎに、従来の半導体装置の半田付け方法についてその一例を説明する。 In a semiconductor device such as a semiconductor module, a copper base and an insulating substrate with a conductive pattern, and an insulating substrate with a conductive pattern and a semiconductor chip are often bonded using a bonding material such as solder. Next, an example of a conventional soldering method for a semiconductor device will be described.
図１１は、従来の半導体装置の半田付け方法を示し、同図（ａ）〜同図（ｅ）は工程順に示した要部工程断面図である。
まず、図１１（ａ）において、銅ベース５１上にレジストを塗布してレジストパターン５２を形成する。このレジストパターン５２の代わりに、半田を弾く鉛筆やレーザーマーキングなどで罫書きすることもある。このレジストパターン５２や罫書きは半田流れを防止するためのものである。
FIG. 11 shows a conventional soldering method for a semiconductor device, and FIG. 11A to FIG. 11E are cross-sectional views of essential parts shown in the order of steps.
First, in FIG. 11A, a resist is applied on the copper base 51 to form a resist pattern 52. In place of the resist pattern 52, ruled lines may be written with a pencil that repels solder, laser marking, or the like. The resist pattern 52 and ruled lines are for preventing solder flow.
つぎに、図１１（ｂ）において、銅ベース５１上にペースト半田５３を塗布し、導電パターン付絶縁基板５４上にフラックス入りのペースト半田５５を塗布する。
つぎに、図１１（ｃ）において、銅ベース５１上に塗布されたペースト半田５３上に導電パターン付絶縁基板５４を載置し、導電パターン付絶縁基板５４上に塗布されたペースト半田５５上に半導体チップ５６を載置する。
Next, in FIG. 11B, paste solder 53 is applied on the copper base 51, and flux-containing paste solder 55 is applied on the insulating substrate 54 with conductive pattern.
Next, in FIG. 11C, an insulating substrate 54 with a conductive pattern is placed on the paste solder 53 applied on the copper base 51, and on the paste solder 55 applied on the insulating substrate 54 with the conductive pattern. A semiconductor chip 56 is placed.
つぎに、図１１（ｄ）において、減圧・窒素ガス炉５７に入れ、前記のペースト半田５３，５５を溶融させ、その後、冷却して銅ベース５１と導電パターン付絶縁基板５４、導電パターン付絶縁基板５４と半導体チップ５６を半田付けする。 Next, in FIG. 11 (d), the paste solder 53, 55 is melted in a reduced pressure / nitrogen gas furnace 57 and then cooled to cool the copper base 51, the insulating substrate 54 with conductive pattern, and the insulating with conductive pattern. The substrate 54 and the semiconductor chip 56 are soldered.
つぎに、図１１（ｅ）において、半田付け品５８を減圧・窒素ガス炉５７から取り出す。
この方法では、銅ベース５１のレジストパターン５２や罫書きで溶融した半田が半田流れを起こさずに半田の位置が定まるので、溶融した半田上の導電パターン付絶縁基板５４の位置ずれが防止される。また、半導体チップ５６の位置決めは、ペースト半田５５を塗布した導電パターン付絶縁基板５４のおもて面（導電パターン）と半田との良好な濡れ性や半田の表面張力などを利用して、半導体チップ５６が必要以上に動かないようにすることで行なっている。
Next, in FIG. 11 (e), the soldered product 58 is taken out from the reduced pressure / nitrogen gas furnace 57.
In this method, since the position of the solder is determined without causing the solder flow in the resist pattern 52 of the copper base 51 and the solder melted by scoring, the displacement of the insulating substrate 54 with the conductive pattern on the melted solder is prevented. . The semiconductor chip 56 is positioned by utilizing good wettability between the front surface (conductive pattern) of the insulating substrate 54 with conductive pattern coated with the paste solder 55 and the solder, the surface tension of the solder, and the like. This is done by preventing the chip 56 from moving more than necessary.
前記の半田付けでは、導電パターン付絶縁基板５４は、平ら、正反りもしくは負反りがある。ここでは、ボイドが残留しやすい負反りの例であり、銅ベース５１は正反りである。この正反りとは銅ベース側に向かって凸状に湾曲した反りのことをいい負反りはその反対である。尚、半田付け工程では導電パターン付絶縁基板５４には加圧力が加えられていない。 In the above soldering, the insulating substrate 54 with the conductive pattern is flat, positive warped or negative warped. Here, it is an example of the negative warp in which voids tend to remain, and the copper base 51 is a positive warp. This positive warp is a warp curved in a convex shape toward the copper base, and the negative warp is the opposite. In the soldering process, no pressure is applied to the insulating substrate 54 with the conductive pattern.
また、特許文献１では、絶縁回路基板の表面側には、位置決め用のカーボン治具（内コマ）と、その開口部に半田板（板半田）および半導体チップが配置され、その後、加熱炉に挿入される。加熱炉内では、全体が３００℃程度まで加熱され、板半田板が溶融されることによって、絶縁回路基板上へ半導体チップが実装される。このとき、絶縁回路基板が加熱されると、一時的に裏面側に凸形状となるように湾曲する「正反り」状態になるが、カーボン治具の本体裏面形状として、その開口部から離れる方向で薄くなるように、段差部が形成されているので、カーボン治具と絶縁回路基板との密着度を高めることができることが記載されている。 In Patent Document 1, a carbon jig for positioning (inner frame), a solder plate (plate solder) and a semiconductor chip are arranged in the opening on the surface side of the insulated circuit board, and then placed in a heating furnace. Inserted. In the heating furnace, the whole is heated to about 300 ° C., and the plate solder plate is melted to mount the semiconductor chip on the insulating circuit board. At this time, when the insulated circuit board is heated, it is in a “normal warp” state that temporarily curves so as to have a convex shape on the back side, but as the back side shape of the main body of the carbon jig, it is separated from the opening. It is described that since the step portion is formed so as to be thinner in the direction, the adhesion between the carbon jig and the insulated circuit board can be increased.
図１２は、半田付け時の導電パターン付絶縁基板５４の曲がりを示しており、同図（ａ）はペースト半田５３を載置した状態の図、同図（ｂ）はペースト半田５３が溶融したときの図、同図（ｃ）は溶融半田５３ａが固化した半田５３ｂになった状態の図および同図（ｄ）は同図（ｃ）のＢ部にできたミミズボイド６２ｂの平面図である。 12A and 12B show the bending of the insulating substrate 54 with the conductive pattern during soldering. FIG. 12A shows a state where the paste solder 53 is placed, and FIG. 12B shows the paste solder 53 melted. FIG. 4C is a state in which the molten solder 53a has become solidified solder 53b, and FIG. 4D is a plan view of the earthworm void 62b formed in the portion B of FIG.
導電パターン付絶縁基板５４のおもて面の導電パターン５４ａの体積は、パターンが形成されていない裏面導電膜５４ｂの体積より小さい。そのため、加熱される前では絶縁パターン付絶縁基板５４は負反り状態になっている。これに熱を加えると裏面導電膜５４ｂが導電パターン５４ａより伸び率が大きいため、正反り状態になる。これを冷却すると負反り状態に戻る。 The volume of the conductive pattern 54a on the front surface of the insulating substrate 54 with conductive pattern is smaller than the volume of the back conductive film 54b on which no pattern is formed. Therefore, before heating, the insulating substrate 54 with an insulating pattern is in a negative warp state. When heat is applied to this, the back surface conductive film 54b has a higher elongation than the conductive pattern 54a, and thus enters a warp state. When this is cooled, it returns to the negative warpage state.
同図（ａ）に示すように、ペースト半田５３を載置した状態では、銅ベース５１は正反り、導電パターン付絶縁基板５４は負反りの状態である。この状態では、導電パターン付絶縁基板５４とペースト半田５３の間に気体層６０がある。これは板半田の場合も同じである。 As shown in FIG. 5A, in the state where the paste solder 53 is placed, the copper base 51 is warped positively and the insulating substrate 54 with the conductive pattern is negatively warped. In this state, there is a gas layer 60 between the insulating substrate 54 with conductive pattern and the paste solder 53. The same applies to the case of sheet solder.
同図（ｂ）に示すように、ペースト半田５３が溶融して溶融半田５３ａになっている状態では、導電パターン付絶縁基板５４は正反り、銅ベース５１は弱い正反りの状態である。 As shown in FIG. 4B, in the state where the paste solder 53 is melted to form the molten solder 53a, the insulating substrate 54 with conductive pattern is warped and the copper base 51 is weakly warped. .
同図（ｃ）に示すように、溶融半田５３ａが固化した半田５３ｂの状態になる場合は、導電パターン付絶縁基板５４は再び負反り、銅ベース５１はさらに弱い正反りの状態になる。 As shown in FIG. 6C, when the molten solder 53a becomes a solidified solder 53b, the insulating substrate 54 with the conductive pattern warps again, and the copper base 51 becomes a weaker warp.
同図（ｂ）の状態で、溶融半田５３ａ内に多数の気泡６１が発生する。この気泡６１の元になるものはペースト半田５３に含有されているフラックスや溶融時に巻き込んだ雰囲気ガスなどである。この気泡６１を抜くため、減圧雰囲気で半田を溶融させる。しかし、溶融半田５３ａの粘度が高く、溶融半田５３ａ内で発生した気泡６１は外部に抜け切れず溶融半田５３ａ内に残留する。 In the state shown in FIG. 5B, a large number of bubbles 61 are generated in the molten solder 53a. The source of the bubble 61 is a flux contained in the paste solder 53 or an atmospheric gas entrained during melting. In order to remove the bubbles 61, the solder is melted in a reduced pressure atmosphere. However, the viscosity of the molten solder 53a is high, and the bubbles 61 generated in the molten solder 53a cannot remain outside and remain in the molten solder 53a.
また、同図（ｃ）に移行して溶融半田５３ａが固化するときに、残留した気泡６１はそのままの状態で固化した半田５３ｂに残留してボイド６２になる。また溶融半田５３ａが固化するときに、導電パターン付絶縁基板５４が負反り状態に加え、半田自身の収縮（体積）により、図示しない半田ヒゲや同図（ｄ）に示すようなミミズボイド６２ａになり、良好な形状のフィレットができなくなる。 When the molten solder 53a is solidified by moving to FIG. 5C, the remaining air bubbles 61 remain in the solidified solder 53b as they are and become voids 62. Further, when the molten solder 53a is solidified, the insulating substrate 54 with the conductive pattern becomes a negative warp state, and the solder itself shrinks (volume), resulting in a solder whisker (not shown) or a worm void 62a as shown in FIG. A fillet with a good shape cannot be formed.
このように、固化した半田５３ｂにボイド６２やこのボイド６２の一種であるミミズボイド６２ａが形成され、良好な形状のフィレットができなくなる。そうすると、半田接合部での熱抵抗が増大し、また半田接合部に外周部から進展するクラックが、ボイド６２部分で一気に加速し急激に半田接合部の接合強度が低下する。そうすると、耐ヒートサイクル性や温度サイクル性が低下し信頼性寿命が低下する。そのためボイド６２などの発生を防止するために、半田量を増やすと製造コストが増大する。 As described above, the void 62 and the earthworm void 62a which is a kind of the void 62 are formed on the solidified solder 53b, and a fillet having a good shape cannot be formed. If it does so, the thermal resistance in a solder joint part will increase, and the crack which spreads from an outer peripheral part to a solder joint part will accelerate at a stretch in the void 62 part, and the joint strength of a solder joint part will fall rapidly. If it does so, heat cycle resistance and temperature cycle property will fall, and a reliability lifetime will fall. Therefore, if the amount of solder is increased in order to prevent generation of voids 62 and the like, the manufacturing cost increases.
また、特許文献１では、内コマを湾曲した押圧部材や突起のある押圧部材で加圧し、導電パターン付絶縁基板を加圧した状態で銅ベースに半田付けすることについては記載されてない。 Further, Patent Document 1 does not describe that the inner frame is pressed with a curved pressing member or a pressing member having a protrusion, and soldered to a copper base in a state where the insulating substrate with a conductive pattern is pressed.
この発明の目的は、前記の課題を解決して、半田付けでボイドの量を低減できる低コストの半導体装置の半田付け方法および半田付け治具を提供することにある。 An object of the present invention is to provide a low-cost soldering method for a semiconductor device and a soldering jig capable of reducing the amount of voids by soldering by solving the above-described problems.
前記の目的を達成するために、特許請求の範囲の請求項１に記載の発明によれば、半田付け治具を用いて、放熱ベースと導電パターン付絶縁基板および半導体チップを半田付けする半導体装置の半田付け方法において、前記半田付け治具が少なくとも支持台、位置決め用部材および押圧部材を備え、半導体チップの位置決めをする前記位置決め用部材の中央部を前記押圧部材の前記位置決め用部材に向かって突出した部分により加圧し、この状態で該位置決め用部材を介して該位置決め用部材に接する前記導電パターン付絶縁基板を加圧し、半田付けする構成とする。 In order to achieve the above object, according to the first aspect of the present invention, a semiconductor device for soldering a heat dissipation base, an insulating substrate with a conductive pattern, and a semiconductor chip using a soldering jig. In this soldering method, the soldering jig includes at least a support base, a positioning member, and a pressing member, and a central portion of the positioning member for positioning the semiconductor chip is directed toward the positioning member of the pressing member. A pressure is applied by the protruding portion, and in this state, the insulating substrate with a conductive pattern in contact with the positioning member is pressed and soldered through the positioning member.
また、特許請求の範囲の請求項２記載の発明によれば、請求項１に記載の発明において、前記押圧部材が、湾曲した板状部材もしくは平坦な板状部材の中央部に突起を形成したものであり、該突起を前記位置決め用部材の中央部に接触させるとよい。 According to the invention described in claim 2 of the claims, in the invention described in claim 1, the pressing member has a protrusion formed at the center of the curved plate member or the flat plate member. It is preferable that the protrusion is brought into contact with the central portion of the positioning member.
また、特許請求の範囲の請求項３記載の発明によれば、請求項２に記載の発明において、前記押圧部材が、湾曲した板状部材または湾曲した面を備える錘であるとよい。
また、特許請求の範囲の請求項４に記載の発明によれば、請求項１または２に記載の発明において、前記位置決め用部材の材質が、カーボンであるとよい。
According to the invention described in claim 3 of the claims, in the invention described in claim 2, the pressing member may be a curved plate member or a weight having a curved surface.
According to the invention described in claim 4 of the claims, in the invention described in claim 1 or 2, the material of the positioning member may be carbon.
また、特許請求の範囲の請求項５に記載の発明によれば、請求項１または２に記載の発明において、前記位置決め用部材が、前記放熱ベース上に載置される外枠によって位置決めされる内コマと称する部材であるとよい。 According to the invention described in claim 5, the positioning member is positioned by the outer frame placed on the heat dissipation base in the invention described in claim 1 or 2. It may be a member called an inner frame.
また、特許請求の範囲の請求項６に記載の発明によれば、放熱ベースと導電パターン付絶縁基板および半導体チップの半田付けで用いる半田付け治具において、放熱ベースを載置する支持台と、導電パターン付絶縁基板を位置決めする第１の位置決め用部材と、該第１の位置決め用部材で位置決めされ、半導体チップを位置決めする第２の位置決め用部材と、該第２の位置決め用部材に接して導電パターン付絶縁基板に加圧力を与える押圧部材と、該押圧部材に加圧力を与える加圧機構部と、前記支持台に固定され前記加圧機構部を固定する支柱と、を備え、前記押圧部材が前記支持台側に中央部が凸となるように湾曲した部材、もしくは前記中央部に突起が付いた平坦な部材である構成とする。 According to the invention of claim 6, in the soldering jig used for soldering the heat dissipation base, the insulating substrate with the conductive pattern, and the semiconductor chip, a support base on which the heat dissipation base is placed; A first positioning member for positioning the insulating substrate with a conductive pattern; a second positioning member positioned by the first positioning member for positioning the semiconductor chip; and the second positioning member in contact with the first positioning member. A pressure member that applies pressure to the insulating substrate with conductive pattern; a pressure mechanism that applies pressure to the pressure member; and a column that is fixed to the support and fixes the pressure mechanism. The member is configured to be a member that is curved so that the central portion is convex toward the support base, or a flat member that has a protrusion at the central portion.
また、特許請求の範囲の請求項７に記載の発明によれば、請求項６に記載の発明において、前記の湾曲した押圧部材の中央部に突起部を設けるとよい。
また、特許請求の範囲の請求項８に記載の発明によれば、放熱ベースと導電パターン付絶縁基板および半導体チップの半田付けで用いる半導体装置の半田付け治具において、
放熱ベースを載置する支持台と、導電パターン付絶縁基板を位置決めする第１の位置決め用部材と、該第１の位置決め部材で位置決めされ、半導体チップを位置決めする第２の位置決め用部材と、該第２の位置決め用部材の中央部に接して導電パターン付絶縁基板に加圧力を与える底部が湾曲している錘と、を備える構成とする。
According to the invention described in claim 7 of the claims, in the invention described in claim 6, it is preferable to provide a protrusion at the center of the curved pressing member.
According to the invention described in claim 8, in the soldering jig of the semiconductor device used for soldering the heat dissipation base, the insulating substrate with the conductive pattern, and the semiconductor chip,
A support base on which the heat dissipation base is placed; a first positioning member that positions the insulating substrate with conductive pattern; a second positioning member that is positioned by the first positioning member and positions the semiconductor chip; A weight having a curved bottom portion that is in contact with the central portion of the second positioning member and applies pressure to the insulating substrate with the conductive pattern.
また、特許請求の範囲の請求項９に記載の発明によれば、請求項８に記載の発明において、前記錘の底部に突起を設けるとよい。
また、特許請求の範囲の請求項１０に記載の発明によれば、請求項６または８に記載の発明において、前記第１の位置決め用部材および第２の位置決め用部材の材質がカーボンであるとよい。
According to the ninth aspect of the present invention, in the invention according to the eighth aspect, a projection may be provided on the bottom of the weight.
According to the invention described in claim 10 of the claims, in the invention described in claim 6 or 8, the material of the first positioning member and the second positioning member is carbon. Good.
また、特許請求の範囲の請求項１１に記載の発明によれば、請求項６または８に記載の発明において、前記第１の位置決め用部材が外枠と称し、前記第２の位置決め用部材が内コマと称するとよい。 According to the invention described in claim 11 of the claims, in the invention described in claim 6 or 8, the first positioning member is called an outer frame, and the second positioning member is It may be referred to as an inner frame.
この発明によれば、湾曲した面を有する押圧部材もしくは突起を有する押圧部材を介して導電パターン付絶縁基板に加圧力を与えて、放熱ベースに導電パターン付絶縁基板を半田付けすることで、低コストでボイドの量を低減できる半導体装置の半田付け方法および半導体装置の半田付け治具を提供することができる。 According to the present invention, a pressure is applied to the insulating substrate with a conductive pattern via a pressing member having a curved surface or a pressing member having a protrusion, and the insulating substrate with a conductive pattern is soldered to the heat dissipation base. A soldering method for a semiconductor device and a soldering jig for the semiconductor device that can reduce the amount of voids at a cost can be provided.
実施の形態を以下の実施例で説明する。
＜実施例１＞
図１〜図３は、この発明の第１実施例の半導体装置の半田付け方法であり、工程順に示した要部製造工程断面図である。
Embodiments will be described in the following examples.
<Example 1>
FIGS. 1 to 3 are cross-sectional views of the main part manufacturing process shown in the order of the steps in the semiconductor device soldering method according to the first embodiment of the present invention.
まず、図１（ａ）において、支持台１上に銅ベース２１を載置する。支持台１には図示しないピンが形成され、銅ベース２１には図示しない穴が形成され、この穴にピンを嵌合することで銅ベース２１が支持台１に位置決めされる。支持台１には支柱２を固定するための雌ネジ１ａが形成されている。この雌ネジの代わりに支柱２の下部を嵌合する凹部が形成されてる場合もある。 First, in FIG. 1A, the copper base 21 is placed on the support base 1. A pin (not shown) is formed on the support base 1, and a hole (not shown) is formed on the copper base 21. The copper base 21 is positioned on the support base 1 by fitting the pin into this hole. A female screw 1 a for fixing the support column 2 is formed on the support base 1. In some cases, a concave portion for fitting the lower portion of the column 2 is formed instead of the female screw.
つぎに、図１（ｂ）において、銅ベース２１に外枠５を載置する。この外枠５の底部には図示しないガイドが付いており、このガイドで銅ベース２１に位置決めされる。この銅ベース２１は、図示しない冷却フィンに取り付けられ、半導体チップ２５で発生した熱を冷却フィンに逃がす役割と、導電パターン付絶縁基板２３の支持台の役割をする放熱体（放熱ベース）である。 Next, in FIG. 1B, the outer frame 5 is placed on the copper base 21. A guide (not shown) is attached to the bottom of the outer frame 5 and is positioned on the copper base 21 by this guide. The copper base 21 is attached to a cooling fin (not shown) and is a heat radiating body (heat radiating base) that serves to release heat generated in the semiconductor chip 25 to the cooling fin and to serve as a support for the insulating substrate 23 with the conductive pattern. .
つぎに、図１（ｃ）において、銅ベース２１上の外枠５内に板半田２２を載置し、その上に導電パターン付絶縁基板２３を載置する。導電パターン付絶縁基板２３のおもて面には導電パターン２３ａは裏面には裏面導電膜２３ｂが形成されている。 Next, in FIG.1 (c), the plate solder 22 is mounted in the outer frame 5 on the copper base 21, and the insulated substrate 23 with a conductive pattern is mounted on it. A conductive pattern 23a is formed on the front surface of the insulating substrate with conductive pattern 23, and a back conductive film 23b is formed on the back surface.
つぎに、図２（ｄ）において、導電パターン付絶縁基板２３上に外枠５の開口部５ａをガイドとして内コマ６を載置する。この外枠５は第１の位置決め用部材であり、前記の内コマ６は第２の位置決め用部材である。 Next, in FIG. 2D, the inner piece 6 is placed on the insulating substrate with conductive pattern 23 using the opening 5a of the outer frame 5 as a guide. The outer frame 5 is a first positioning member, and the inner frame 6 is a second positioning member.
つぎに、図２（ｅ）において、内コマ６の開口部６ａをガイドに板半田２４を導電パターン付絶縁基板２３上に載置し、その上に開口部６ａをガイドに半導体チップ２５を板半田２４上に載置する。 Next, in FIG. 2E, the plate solder 24 is placed on the insulating substrate 23 with the conductive pattern using the opening 6a of the inner top 6 as a guide, and the semiconductor chip 25 is mounted thereon using the opening 6a as a guide. Place on solder 24.
つぎに、図２（ｆ）において、正反りのある湾曲した板状部材からなる押圧部材４（押え板）の中心部４ａ（湾曲の頂点）を内コマ６の中心部６ｂに接するように載置する。押圧部材４には支柱２とネジ部３が取り付いており、支持台１の雌ネジ１ａに雄ネジ２ａが形成されている支柱２を回転させて差し込んで支持台１に支柱２を固定する。支持台１に凹部が形成されている場合には支柱の下部を凹部に嵌合して支持台１に支柱２を固定する。尚、正反りとは前記したように銅ベース側に向かって凸状に湾曲した反りをいう。 Next, in FIG. 2 (f), the central portion 4 a (curve apex) of the pressing member 4 (presser plate) made of a curved plate member with a warp is in contact with the central portion 6 b of the inner piece 6. Place. The pressing member 4 has a support column 2 and a screw portion 3 attached thereto. The support column 1 is fixed to the support table 1 by rotating and inserting the support column 2 on which the male screw 2 a is formed into the female screw 1 a of the support table 1. When the concave portion is formed on the support base 1, the lower portion of the support column is fitted into the concave portion to fix the support column 2 to the support base 1. In addition, as described above, the normal warp is a warp curved in a convex shape toward the copper base side.
つぎに、図３（ｇ）において、支持台１に固定された支柱２に設けられたネジ部３で押圧部材４の両端を締めて、湾曲した押圧部材４の曲率半径が大きくなるように（平坦になるように）変形させる。そうすると、押圧部材４と内コマ６が接している箇所（４ａと６ｂの箇所）から押圧部材４のバネ作用で内コマ６に加圧力Ｐを与える。この加圧力Ｐは内コマ６を通して導電パターン付絶縁基板２３に与えられる。内コマ６の中心部６ｂに与えれれた加圧力Ｐは、導電パターン付絶縁基板２３と接する内コマ６の底面では均等な加圧力Ｐ１（単位面積あたりの加圧力）となり導電パターン付絶縁基板２３に伝達される。加圧力Ｐ１は、例えば、半田溶融時で加圧力Ｐ１は４ｇ〜８ｇ／ｃｍ２（４×９８Ｐａ〜８×９８Ｐａ）になるようにするとよい。加圧力Ｐ１が４ｇ／ｃｍ２未満では加圧力が小さく溶融半田２２ａから気泡が抜け行かず、固化した半田２２ｂ内に大きなボイドも含めて多数のボイドが残留することになる。一方、加圧力Ｐ１が８ｇ／ｃｍ２を超えると加圧力Ｐ１が大きすぎて、溶融半田２３ａが必要以上に外部へ流失して、固化した半田２３ｂの厚さが薄くなり過ぎて接合強度を低下させてしまう。尚、Ｐ＝Ｐ１×内コマと導電パターン付絶縁基板の接触面積となる。 Next, in FIG. 3G, both ends of the pressing member 4 are tightened with the screw portions 3 provided on the support column 2 fixed to the support base 1 so that the curvature radius of the curved pressing member 4 is increased ( Deform (to be flat). Then, the pressure P is applied to the inner piece 6 by the spring action of the pressing member 4 from the place where the pressing member 4 and the inner piece 6 are in contact (the place of 4a and 6b). The pressure P is applied to the insulating substrate with conductive pattern 23 through the inner piece 6. The applied pressure P applied to the central portion 6b of the inner piece 6 becomes a uniform applied pressure P1 (pressed force per unit area) on the bottom surface of the inner piece 6 in contact with the insulating substrate 23 with the conductive pattern. Is transmitted to. The applied pressure P1 may be, for example, 4 g to 8 g / cm 2 (4 × 98 Pa to 8 × 98 Pa) when the solder is melted. When the applied pressure P1 is less than 4 g / cm 2 , the applied pressure is small and bubbles do not escape from the molten solder 22a, and many voids including large voids remain in the solidified solder 22b. On the other hand, when the applied pressure P1 exceeds 8 g / cm 2 , the applied pressure P1 is too large, and the molten solder 23a flows out to the outside more than necessary, and the thickness of the solidified solder 23b becomes too thin and the joint strength is lowered. I will let you. Note that P = P1 × the contact area between the inner frame and the insulating substrate with the conductive pattern.
つぎに、図３（ｈ）において、減圧・水素ガス炉２６に入れ、前記の導電パターン付絶縁基板２３を加圧しながら板半田２２，２４を溶融させ、その後、冷却して銅ベース２１と導電パターン付絶縁基２３、導電パターン付絶縁基板２３と半導体チップ２５を半田付けする。このとき、加圧力Ｐ（Ｐ１）が印加されるのは板半田２２であり、板半田２４は印加されない。 Next, in FIG. 3 (h), the sheet solders 22 and 24 are melted while being pressed into the decompression / hydrogen gas furnace 26 and pressurizing the insulating substrate 23 with the conductive pattern, and then cooled to be electrically connected to the copper base 21. The insulating base 23 with pattern, the insulating substrate 23 with conductive pattern, and the semiconductor chip 25 are soldered. At this time, the applied pressure P (P1) is applied to the plate solder 22, and the plate solder 24 is not applied.
つぎに、図３（ｉ）において、半田付け品２７を減圧・水素ガス炉２６から取り出し半田付けは終了する。
図４は、半田付け時の導電パターン付絶縁基板の曲がりと半田の状態を示しており、同図（ａ）は板半田が溶融する前の図、同図（ｂ）は溶融中の図、同図（ｃ）は固化中の図である。銅ベース１は予め正反り状態に加工されている。銅ベース１を正反り状態にするのは図示しない冷却フィンに銅ベース１を取り付けるときの冷却フィンの上面と銅ベース１の底面の密着性を上げるためである。また、前記したように、導電パターン付絶縁基板２３のおもて面の導電パターン２３ａの体積は裏面導電膜２３ｂの体積より小さい。そのため、絶縁パターン付絶縁基板２３は負反り状態になっている。これに熱を加えると裏面導電膜２３ａが導電パターン２３ａより伸び率が大きいため、正反り状態になる。これを冷却すると負反り状態に戻る。
Next, in FIG. 3I, the soldered product 27 is taken out from the decompression / hydrogen gas furnace 26, and the soldering is completed.
FIG. 4 shows the state of bending and soldering of the insulating substrate with the conductive pattern during soldering. FIG. 4A is a view before the sheet solder is melted, FIG. 4B is a view during melting, FIG. 2C is a diagram during solidification. The copper base 1 is processed into a warped state in advance. The reason why the copper base 1 is warped is to improve the adhesion between the upper surface of the cooling fin and the bottom surface of the copper base 1 when the copper base 1 is attached to a cooling fin (not shown). Further, as described above, the volume of the conductive pattern 23a on the front surface of the insulating substrate with conductive pattern 23 is smaller than the volume of the back conductive film 23b. Therefore, the insulating substrate with an insulating pattern 23 is in a negative warpage state. When heat is applied to this, the back conductive film 23a has a larger elongation rate than the conductive pattern 23a, so that it is in a warped state. When this is cooled, it returns to the negative warpage state.
同図（ａ）に示すように、板半田２２を載置した状態では銅ベース１は正反り、導電パターン付絶縁基板２３は負反りの状態にある。この状態では、導電パターン付絶縁基板２３と板半田２２の間に雰囲気ガスの気体層２８が存在する。導電パターン付絶縁基板４が加圧力Ｐ１で加圧されているが、この加圧力Ｐ１は小さいので、正反りの曲がりには変化がなく、気体層２８は加圧されない従来の気体層６０と同じである。 As shown in FIG. 6A, in the state where the plate solder 22 is placed, the copper base 1 is warped positively and the insulating substrate with conductive pattern 23 is in a negative warp state. In this state, the gas layer 28 of the atmospheric gas exists between the insulating substrate 23 with the conductive pattern and the sheet solder 22. Although the insulating substrate 4 with the conductive pattern is pressurized with the applied pressure P1, since the applied pressure P1 is small, there is no change in the bending of the forward warp, and the gas layer 28 is not pressurized. The same.
同図（ｂ）に示すように、板半田２２が溶融して溶融半田２２ａになっている状態では、導電パターン付絶縁基板２３は熱変形応力により正反りとなる。そのため、半田２２ａが加圧状態となり、導電パターン付絶縁基板２３と銅ベース１に挟まれた溶融半田２２ａの厚みは小さくなろうとする力が働く。そうすると、板半田２２に含まれる気泡２９ａは移動しやすくなり、外部へ放出され、溶融半田２２ａ中に残留する気泡２９ａはボイド２９として残留する。しかし、外部に気泡２９ａが放出されるのでボイド２９の量は少なくなり、また、大きい気泡２９ａは外部に放出されるので残留する気泡２９の大きさは小さい。 As shown in FIG. 2B, in the state where the sheet solder 22 is melted to become the molten solder 22a, the insulating substrate 23 with the conductive pattern is warped due to thermal deformation stress. Therefore, the solder 22a is in a pressurized state, and a force is applied to reduce the thickness of the molten solder 22a sandwiched between the insulating substrate 23 with the conductive pattern and the copper base 1. If it does so, the bubble 29a contained in the sheet solder 22 will become easy to move, it will be discharge | released outside and the bubble 29a which remains in the molten solder 22a will remain as the void 29. However, since the bubbles 29a are released to the outside, the amount of the voids 29 is reduced, and since the large bubbles 29a are released to the outside, the size of the remaining bubbles 29 is small.
また、高真空引きを繰り返すことで、気泡２９ａは外へ出ようとして移動し、この移動で周囲のボイド２９ａと合体して大きくなり外部へ出やくなる。そのため、移動しない気泡２９ａは小さいまま内部に残留する。 Further, by repeating the high vacuuming, the bubbles 29a move so as to go outside, and by this movement, the bubbles 29a are united with the surrounding voids 29a and become large and easily come out. For this reason, the bubbles 29a that do not move remain small inside.
同図（ｃ）に示すように、半田溶融時にボイド半田凝縮時には、半田自身の体積が収縮し、それに伴って部材である導電パターン付絶縁基板２３や銅ベース２１が変形する。導電パターン付絶縁基板２３に加圧力Ｐ１が加わっているので、溶融半田２２ａが固化するときに、雰囲気ガスを取り込むことが防止され、図１２に示すミミズボイド６２ａや図示しない半田ヒゲの発生が防止される。その結果、固化された半田２２ｂには良好な形状のフィレット２２ｃが形成される。 As shown in FIG. 6C, when the void solder is condensed at the time of melting the solder, the volume of the solder itself contracts, and accordingly, the insulating substrate with conductive pattern 23 and the copper base 21 which are members are deformed. Since the applied pressure P1 is applied to the insulating substrate 23 with the conductive pattern, it is possible to prevent the atmosphere gas from being taken in when the molten solder 22a is solidified, and to prevent the generation of the earthworm void 62a shown in FIG. The As a result, a well-shaped fillet 22c is formed on the solidified solder 22b.
このように、導電パターン付絶縁基板２３に加圧力Ｐ１を加えることで、導電パターン付絶縁基板２３と銅ベース２１の半田付けにおいて、半田量を減少してもボイド２９を低減でき、また残留するボイド２９の大きさを小さくできる。そのため製造コストを低減することができる。 As described above, by applying the pressure P1 to the insulating substrate 23 with the conductive pattern, the void 29 can be reduced and remain even when the solder amount is reduced in the soldering of the insulating substrate 23 with the conductive pattern and the copper base 21. The size of the void 29 can be reduced. Therefore, the manufacturing cost can be reduced.
また、押圧部材４を正反りに湾曲させ、その凸部の頂点（中央部４ａ）で内コマ６の中央部６ｂを押すと、その加圧力Ｐは内コマ６内で広がり導電パターン付絶縁基板２３との接触面では均一化された加圧力Ｐ１となる。そのため、均一化された加圧力Ｐ１で導電パターン付絶縁基板２３は加圧されることになる。また、湾曲した押圧部材４の中央部４ａは内コマ６の中央部６ｂで支えられ、両端部４ｂはネジ部３で支えられる。そのため押圧部材４にはバネ作用が発生し、内コマ６に加圧力Ｐが効果的に伝達される。さらに、平坦な押圧部材で内コマ６を面で押す場合に発生しやすい片押し（内コマ６の片方の端部が平坦な押圧部材で押されること）が、湾曲した押圧部材４の中央部４ａで内コマ６を押すことで防止することができる。 Further, when the pressing member 4 is curved in a straight warp and the central portion 6b of the inner piece 6 is pushed at the apex (center portion 4a) of the convex portion, the pressure P spreads in the inner piece 6 and is insulated with a conductive pattern. At the contact surface with the substrate 23, the applied pressure P1 is uniformized. Therefore, the insulating substrate 23 with the conductive pattern is pressurized with the uniform applied pressure P1. Further, the central portion 4 a of the curved pressing member 4 is supported by the central portion 6 b of the inner piece 6, and both end portions 4 b are supported by the screw portion 3. Therefore, a spring action is generated in the pressing member 4, and the pressure P is effectively transmitted to the inner piece 6. Furthermore, the one-side pressing that is likely to occur when the inner piece 6 is pushed by the surface with the flat pressing member (one end of the inner piece 6 is pushed by the flat pressing member) is the center of the curved pressing member 4. This can be prevented by pressing the inner frame 6 in 4a.
尚、半田付け中の雰囲気ガスとして水素ガスの例を示したが、蟻酸ガスを用いる場合もある。
＜実施例２＞
図５は、この発明の第２実施例の半導体装置の半田付け治具１００の構成図であり、同図（ａ）は要部断面図、同図（ｂ）は外枠５と内コマ６の要部平面図である。同図（ａ）の外枠５と内コマ６の断面図は同図（ｂ）のＸ−Ｘ線で切断した断面図である。この半田付け治具１００は図１の半田付け方法で用いた治具である。また、図５には点線で、銅ベース２１、導電パターン付絶縁基板２３、板半田２２，２４や半導体チップ２５も示した。
In addition, although the example of hydrogen gas was shown as atmospheric gas during soldering, formic acid gas may be used.
<Example 2>
FIGS. 5A and 5B are configuration diagrams of a soldering jig 100 of a semiconductor device according to a second embodiment of the present invention. FIG. 5A is a sectional view of the main part, and FIG. 5B is an outer frame 5 and an inner frame 6. FIG. The sectional view of the outer frame 5 and the inner frame 6 in FIG. 6A is a sectional view taken along the line XX in FIG. This soldering jig 100 is a jig used in the soldering method of FIG. 5 also shows a copper base 21, an insulating substrate with a conductive pattern 23, plate solders 22 and 24, and a semiconductor chip 25 by dotted lines.
この半田付け治具１００は、銅ベース１を載置する支持台１と、支持台１に着脱する支柱２と、支柱２の上部に設けられるネジ部３と、内コマ６を押える正反りに湾曲した押圧部材４とを備える。また、導電パターン付絶縁基板２３および内コマ６を位置決めする外枠５と、半導体チップ５を位置決めする内コマ６とを備える。外枠５および内コマ６の材質は、例えば、カーボンである。正反りに湾曲した押圧部材４はバネ作用があり、その中央部４ａは内コマ６に接する。支持台１には雌ネジ１ａが形成されており、支柱２に形成された雄ネジ２ａを回転させて差し込んで支持台１に支柱２が固定される。支柱２を逆回転させることで支持台１から外すことができる。外枠５の開口部５ａに内コマ６が挿入されて位置決めされる。内コマ６の開口部６ａに板半田２４と半導体チップ２５が挿入されて位置決めされる。また前記のネジ部３は支柱に形成された雄ネジとナットの組み合わせである。 The soldering jig 100 includes a support base 1 on which the copper base 1 is placed, a support 2 that is attached to and detached from the support base 1, a screw portion 3 provided on the top of the support 2, and a forward warp that holds the inner frame 6. And a pressing member 4 that is curved. In addition, an outer frame 5 for positioning the insulating substrate with conductive pattern 23 and the inner frame 6 and an inner frame 6 for positioning the semiconductor chip 5 are provided. The material of the outer frame 5 and the inner frame 6 is, for example, carbon. The pressing member 4 that is curved in a regular warp has a spring action, and its central portion 4 a is in contact with the inner piece 6. An internal thread 1 a is formed on the support base 1, and the external thread 2 a formed on the support 2 is rotated and inserted to fix the support 2 to the support 1. The support 2 can be removed from the support 1 by rotating it in the reverse direction. The inner frame 6 is inserted into the opening 5a of the outer frame 5 and positioned. The plate solder 24 and the semiconductor chip 25 are inserted into the opening 6a of the inner top 6 and positioned. The screw portion 3 is a combination of a male screw and a nut formed on the support column.
この支柱２には押圧部材４が取り付けられ、ネジ部３を締め付けることで押圧部材４の端部が下方へ変形して、バネ作用で内コマ６に加圧力Ｐが伝達される。この加圧力Ｐは加圧力Ｐ１となって導電パターン付絶縁基板２３へ伝達される。 A pressing member 4 is attached to the support column 2, and the end of the pressing member 4 is deformed downward by tightening the screw portion 3, and the pressing force P is transmitted to the inner top 6 by a spring action. The applied pressure P becomes the applied pressure P1 and is transmitted to the insulating substrate 23 with the conductive pattern.
この押圧部材４に加圧力Ｐを伝達する方法としては、図５に示すネジ部３で行なう他につぎのような方法がある。図６（ａ）〜図６（ｃ）の押圧部材４に加圧力Ｐを与える構成は図５の左側Ａを示した。図示しない右側も同様の構成となっている。 As a method for transmitting the pressing force P to the pressing member 4, there are the following methods in addition to the method using the screw portion 3 shown in FIG. The configuration for applying the pressing force P to the pressing member 4 in FIGS. 6A to 6C is the left side A in FIG. The right side (not shown) has the same configuration.
図６は、押圧部材４に加圧力Ｐを与える方法を説明する図であり、同図（ａ）は支柱２にスプリング７を設置した場合の図、同図（ｂ）は、板バネ８を設置した場合の図、同図（ｃ）は、支柱１１にトグルクランプ９を設置した場合の図、同図（ｄ）は、錘１０を設置し直接内コマ６に加圧力Ｐを伝達する図である。 6A and 6B are diagrams for explaining a method of applying the pressing force P to the pressing member 4. FIG. 6A is a diagram in the case where the spring 7 is installed on the support column 2, and FIG. The figure in the case of installation, the figure (c) is a figure in the case of installing the toggle clamp 9 on the support 11, and the figure (d) is the figure in which the weight 10 is installed and the pressure P is directly transmitted to the inner top 6. It is.
同図（ａ）において、スプリング７を縮めることで押圧部材４に加圧力Ｐが伝達される。
同図（ｂ）において、板バネ８の一端は支柱１１にネジ１２で固定され、ネジ１２を締め付けることで、板バネ８の他端が押圧部材４を押し付けて、押圧部材４に加圧力Ｐが伝達される。
In FIG. 5A, the pressure P is transmitted to the pressing member 4 by contracting the spring 7.
In FIG. 2B, one end of the leaf spring 8 is fixed to the support 11 with a screw 12, and the other end of the leaf spring 8 presses the pressing member 4 by tightening the screw 12, and the pressing force P is applied to the pressing member 4. Is transmitted.
同図（ｃ）において、支柱１１に固定されたトグルクランプ９の先端部９ａから加圧力Ｐが押圧部材４に伝達される。
同図（ｄ）において、錘１０の底部１０ａを凸状に湾曲させ、外枠１３を長く形成してガイドにする。このガイドに沿って錘１０は上下に可動する。この錘１０の中央部１０ｂから内コマ６の中央部６ａに加圧力Ｐが伝達される。
In FIG. 2C, the applied pressure P is transmitted to the pressing member 4 from the tip end portion 9 a of the toggle clamp 9 fixed to the column 11.
In FIG. 4D, the bottom 10a of the weight 10 is curved in a convex shape, and the outer frame 13 is formed long to serve as a guide. The weight 10 moves up and down along this guide. A pressing force P is transmitted from the central portion 10 b of the weight 10 to the central portion 6 a of the inner piece 6.
前記したスプリング７、板バネ８、トグルクランプ９および錘１０は押圧部材４に加圧力を与える加圧機構を構成する。
前記したように押圧部材４に伝達された加圧力Ｐは内コマ６を通して導電パターン付絶縁基板２３に均一な加圧力Ｐ１となって伝達される。
The aforementioned spring 7, leaf spring 8, toggle clamp 9 and weight 10 constitute a pressurizing mechanism that applies pressure to the pressing member 4.
As described above, the applied pressure P transmitted to the pressing member 4 is transmitted to the insulating substrate 23 with the conductive pattern through the inner piece 6 as a uniform applied pressure P1.
尚、半田にペースト半田を用いる場合には雰囲気ガスとしては窒素ガス、腐食性ガスおよび窒素ガスと水素ガスの混合ガスを用いる。またペースト半田にはフラックスが含有されているので、内コマ６にはカーボンの代わりにステンレスなどの金属やカーボンにＳｉＣなどガラス系のコーティング処理を施したものを用いるとよい。
＜実施例３＞
図７は、この発明の第３実施例の半導体装置の半田付け治具２００の要部断面図である。
In addition, when using paste solder for solder, nitrogen gas, corrosive gas, and the mixed gas of nitrogen gas and hydrogen gas are used as atmosphere gas. Further, since the paste solder contains flux, the inner piece 6 may be made of a metal such as stainless steel or a glass-based coating treatment such as SiC instead of carbon.
<Example 3>
FIG. 7 is a cross-sectional view of an essential part of a soldering jig 200 of a semiconductor device according to a third embodiment of the present invention.
実施例２の半田付け治具１００との違いは、押圧部材４の中央部４ａに突起３１を設けている点である。
この場合は、正反りの湾曲した板状部材からなる押圧部材４の中央部４ａに突起３１（高さが例えば１ｍｍ〜２ｍｍ程度、断面の大きさは例えば０．６ｍｍ程度〜１ｍｍ程度）を設けることで、突起３１が内コマ６の中央部６ａに確実に突起３１が接して、加圧力Ｐの伝達位置がより正確に定まる。
＜実施例４＞
図８は、この発明の第４実施例の半導体装置の半田付け治具３００の要部断面図である。
The difference from the soldering jig 100 of the second embodiment is that a protrusion 31 is provided at the central portion 4 a of the pressing member 4.
In this case, a protrusion 31 (height is about 1 mm to 2 mm, for example, and the cross-sectional size is about 0.6 mm to 1 mm, for example) is formed on the central portion 4a of the pressing member 4 made of a plate-like member with a curved warp. By providing the projection 31, the projection 31 reliably contacts the central portion 6 a of the inner piece 6, and the transmission position of the pressure P is more accurately determined.
<Example 4>
FIG. 8 is a cross-sectional view of a main part of a soldering jig 300 of the semiconductor device according to the fourth embodiment of the present invention.
実施例２の半田付け治具１００との違いは、押圧部材３２が平坦な板状部材であり、その押圧部材３２の中央部に突起３３を設けている点である。
この場合も、押圧部材３２の中央部に突起３３を設けることで、突起３３が内コマ６の中央部６ａに確実に接して、加圧力Ｐの伝達位置がより正確に決めることができる。
The difference from the soldering jig 100 of the second embodiment is that the pressing member 32 is a flat plate-like member, and a protrusion 33 is provided at the center of the pressing member 32.
Also in this case, by providing the projection 33 at the central portion of the pressing member 32, the projection 33 can reliably contact the central portion 6a of the inner piece 6 and the transmission position of the pressure P can be determined more accurately.
また、この実施例の変形例として、平坦な板状部材の所定の位置に突起を設けた押圧部材を備える半田付け治具がある。この治具によれば、一つの銅ベース上に複数の導電パターン付絶縁基板を半田付けする場合に、導電パターン付絶縁基板それぞれに載置する内コマを押圧部材に形成された突起により均等に加圧することができる。
＜実施例５＞
図９および図１０は、この発明の第５実施例の半導体装置の半田付け方法であり、工程順に示した要部製造工程断面図である。
As a modification of this embodiment, there is a soldering jig including a pressing member provided with a protrusion at a predetermined position of a flat plate-like member. According to this jig, when soldering a plurality of insulating substrates with conductive patterns on one copper base, the inner pieces placed on each of the insulating substrates with conductive patterns are evenly distributed by the protrusions formed on the pressing member. Can be pressurized.
<Example 5>
FIG. 9 and FIG. 10 are cross-sectional views of the main part manufacturing process shown in the order of the steps in the method of soldering the semiconductor device according to the fifth embodiment of the present invention.
まず、図９（ａ）において、支持台１上に銅ベース２１を載置し、銅ベース２１上にレジスト塗布してレジストパターン３５を形成する。レジストパターン３５代わりに、ペースト半田を弾く鉛筆やレーザーマーキングなどで罫書きしてもよい。このレジストパターンや罫書きは溶融半田の流れを防止するためのものである。 First, in FIG. 9A, the copper base 21 is placed on the support base 1, and a resist pattern 35 is formed by applying a resist on the copper base 21. Instead of the resist pattern 35, a ruled line may be drawn with a pencil that repels paste solder, laser marking, or the like. This resist pattern and ruled lines are for preventing the flow of molten solder.
つぎに、図９（ｂ）において、銅ベース２１上にペースト半田３６を塗布し、導電パターン付絶縁基板２３上にペースト半田３７を塗布する。
つぎに、図９（ｃ）において、銅ベース１上に塗布されたペースト半田３６上に導電パターン付絶縁基板２３を載置し、導電パターン付絶縁基板２３上に塗布されたペースト半田３７上に半導体チップ２５を搭載する。
Next, in FIG. 9B, paste solder 36 is applied on the copper base 21 and paste solder 37 is applied on the insulating substrate 23 with conductive pattern.
Next, in FIG. 9C, the insulating substrate 23 with the conductive pattern is placed on the paste solder 36 applied on the copper base 1, and on the paste solder 37 applied on the insulating substrate 23 with the conductive pattern. A semiconductor chip 25 is mounted.
つぎに、図９（ｄ）において、中心部に突起３９が付いている平坦な押圧部材３８を半導体チップ２５上に配置し、突起３９を導電パターン付絶縁基板２３に接するようにする。押圧部材３７には支柱２とネジ部３が取り付けられており、その状態で押圧部材３８を半導体チップ２５上へ載置し、支持台１の雌ネジ１ａに支柱２に形成された雄ネジ２ａを回転して差し込んで支柱２を支持台１に固定する。 Next, in FIG. 9D, a flat pressing member 38 having a protrusion 39 at the center is disposed on the semiconductor chip 25 so that the protrusion 39 is in contact with the insulating substrate 23 with a conductive pattern. The support member 2 and the screw portion 3 are attached to the pressing member 37. In this state, the pressing member 38 is placed on the semiconductor chip 25, and the male screw 2 a formed on the support column 1 on the female screw 1 a of the support 1. The support 2 is fixed to the support base 1 by rotating and inserting.
つぎに、図１０（ｅ）において、支柱２に配置されたネジ部３で押圧部材３８の両側を締めて、押圧部材３８に加圧力Ｐを与える。この加圧力Ｐは突起３９を通して導電パターン付絶縁基板２３の中央部２３ａに与えられる。この加圧力Ｐは導電パターン付絶縁基板２３内で広がりペースト半田３６に加圧力Ｐ２となって伝達される。この加圧力Ｐ２は４ｇ〜８ｇ／ｃｍ２（４×９８Ｐａ〜８×９８Ｐａ）がよい。但し、加圧力Ｐ１に比べると加圧力Ｐ２は面内での均一性はよくない。しかし、従来のように加圧しないで半田付けする方法よりは半田付けは良好である。 Next, in FIG. 10 (e), both sides of the pressing member 38 are tightened with the screw portions 3 arranged on the support column 2, and the pressing force P is applied to the pressing member 38. The pressure P is applied to the central portion 23a of the insulating substrate 23 with the conductive pattern through the protrusion 39. The applied pressure P spreads in the insulating substrate with conductive pattern 23 and is transmitted to the paste solder 36 as applied pressure P2. The pressure P2 is preferably 4 g to 8 g / cm 2 (4 × 98 Pa to 8 × 98 Pa). However, the pressure P2 is not uniform in the surface compared to the pressure P1. However, soldering is better than the conventional method of soldering without applying pressure.
つぎに、図１０（ｆ）において、減圧・窒素ガス炉４０に入れ、前記の導電パターン付絶縁基板２３を加圧しながらペースト半田３６、３７を溶融させ、その後、冷却して銅ベース２１と導電パターン付絶縁基板２３、導電パターン付絶縁基板２３と半導体チップ２５を半田付けする。 Next, in FIG. 10 (f), the paste solders 36 and 37 are melted while pressurizing the insulating substrate 23 with the conductive pattern while being put in a reduced pressure / nitrogen gas furnace 40, and then cooled to be electrically connected to the copper base 21. The insulating substrate with pattern 23, the insulating substrate with conductive pattern 23 and the semiconductor chip 25 are soldered.
つぎに、図１０（ｇ）において、半田付け品４１を減圧・窒素ガス炉４０から取り出す。
押圧部材３８としては、図７の突起３１が形成された湾曲した押圧部材４も用いてもよい。実施例５の場合も実施例１とほぼ同様の効果が得られる。
Next, in FIG. 10G, the soldered product 41 is taken out from the reduced pressure / nitrogen gas furnace 40.
As the pressing member 38, a curved pressing member 4 in which the protrusion 31 of FIG. 7 is formed may be used. In the case of Example 5, substantially the same effect as Example 1 is obtained.
１ 支持台
１ａ 雌ネジ
２，１１支柱
２ａ 雄ネジ
３ ネジ部
４ 押圧部材
４ａ，６ｂ，１０ｂ 中央部
５，１３ 外枠
５ａ，６ａ 開口部
６ 内コマ
７ スプリング
８ 板バネ
９ トグルクランプ
１０ 錘
１０ａ 底部
１２ ネジ
２１ 銅ベース
２２ 板半田
２４ 板半田
２２ａ 溶融半田
２２ｂ 固化した半田
２２ｃ フィレット
２３ 導電パターン付絶縁基板
２３ａ 導電パターン
２３ｂ 裏面導電膜
２５ 半導体チップ
２６ 減圧・水素ガス炉
２７，４１ 半田付け品
２９ ボイド
２９ａ 気泡
３１、３３，３９ 突起
３２ 平坦な押圧部材
３５ レジストパターン
３６，３７ ペースト半田
３８ 平坦な押圧部材
４０ 減圧・窒素ガス炉
１００，２００，３００ 半田付け治具
Ｐ 加圧力
Ｐ１、Ｐ２ 単位面積当たりの加圧力
DESCRIPTION OF SYMBOLS 1 Support stand 1a Female screw 2,11 support | pillar 2a Male screw 3 Screw part 4 Pressing member 4a, 6b, 10b Center part 5,13 Outer frame 5a, 6a Opening part 6 Inner top 7 Spring 8 Leaf spring 9 Toggle clamp 10 Weight 10a Bottom 12 Screw 21 Copper base 22 Plate solder 24 Plate solder 22a Molten solder 22b Solidified solder 22c Fillet 23 Insulating substrate with conductive pattern 23a Conductive pattern 23b Back surface conductive film 25 Semiconductor chip 26 Depressurization / hydrogen gas furnace 27, 41 Soldered product 29 Void 29a Air bubbles 31, 33, 39 Protrusions 32 Flat pressing member 35 Resist pattern 36, 37 Paste solder 38 Flat pressing member 40 Depressurization / nitrogen gas furnace 100, 200, 300 Soldering jig P Pressurizing pressure P1, P2 Unit area Contact pressure
Claims (11)
前記半田付け治具が少なくとも支持台、位置決め用部材および押圧部材を備え、半導体チップの位置決めをする前記位置決め用部材の中央部を前記押圧部材の前記位置決め用部材に向かって突出した部分により加圧し、この状態で該位置決め用部材を介して該位置決め用部材に接する前記導電パターン付絶縁基板を加圧し、半田付けすることを特徴とする半導体装置の半田付け方法。 In a soldering method of a semiconductor device in which a heat dissipation base, an insulating substrate with a conductive pattern, and a semiconductor chip are soldered using a soldering jig,
The soldering jig includes at least a support base, a positioning member, and a pressing member, and a central portion of the positioning member for positioning the semiconductor chip is pressed by a portion protruding toward the positioning member of the pressing member. A soldering method for a semiconductor device, comprising pressing and soldering the insulating substrate with a conductive pattern in contact with the positioning member through the positioning member in this state.
放熱ベースを載置する支持台と、導電パターン付絶縁基板を位置決めする第１の位置決め用部材と、該第１の位置決め用部材で位置決めされ、半導体チップを位置決めする第２の位置決め用部材と、該第２の位置決め用部材に接して導電パターン付絶縁基板に加圧力を与える押圧部材と、該押圧部材に加圧力を与える加圧機構部と、前記支持台に固定され前記加圧機構部を固定する支柱を備え、
前記押圧部材が前記支持台側に中央部が凸となるように湾曲した部材、もしくは前記中央部に突起が付いた平坦な部材であることを特徴とする半導体装置の半田付け治具。 In soldering jigs used for soldering heat dissipation base, conductive substrate with insulating pattern and semiconductor chip,
A support base for placing the heat dissipation base, a first positioning member for positioning the insulating substrate with conductive pattern, a second positioning member for positioning the semiconductor chip, which is positioned by the first positioning member, A pressing member that contacts the second positioning member and applies pressure to the insulating substrate with conductive pattern; a pressure mechanism that applies pressure to the pressing member; and the pressure mechanism that is fixed to the support base. It has a column to fix,
A soldering jig for a semiconductor device, wherein the pressing member is a member that is curved so that a central portion is convex toward the support base, or a flat member that has a protrusion at the central portion.
放熱ベースを載置する支持台と、導電パターン付絶縁基板を位置決めする第１の位置決め用部材と、該第１の位置決め部材で位置決めされ、半導体チップを位置決めする第２の位置決め用部材と、該第２の位置決め用部材の中央部に接して導電パターン付絶縁基板に加圧力を与える底部が湾曲している錘と、を備えることを特徴とする半導体装置の半田付け治具。 In a soldering jig of a semiconductor device used for soldering a heat dissipation base, an insulating substrate with a conductive pattern, and a semiconductor chip,
A support base on which the heat dissipation base is placed; a first positioning member that positions the insulating substrate with conductive pattern; a second positioning member that is positioned by the first positioning member and positions the semiconductor chip; And a weight having a curved bottom that applies pressure to the insulating substrate with a conductive pattern in contact with the center of the second positioning member.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015049849A1 (en) * | 2013-10-04 | 2015-04-09 | Ｎｅｃプラットフォームズ株式会社 | Electronic circuit board and method of assembly for same |
| JP2015170826A (en) * | 2014-03-10 | 2015-09-28 | 三菱マテリアル株式会社 | Manufacturing method of power module substrate with radiation plate |
| JP2020136449A (en) * | 2019-02-19 | 2020-08-31 | 富士電機株式会社 | Method of manufacturing semiconductor device |
| JP2021007979A (en) * | 2019-07-03 | 2021-01-28 | 株式会社関電工 | Soldering jig and method |
| US11552021B2 (en) | 2019-11-19 | 2023-01-10 | Fuji Electric Co., Ltd. | Semiconductor device, semiconductor manufacturing apparatus and method of manufacturing semiconductor device having printed circuit board and insulating board with complementary warps |
| US11637052B2 (en) | 2019-12-06 | 2023-04-25 | Fuji Electric Co., Ltd. | Semiconductor device and semiconductor device manufacturing method |
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2012
- 2012-01-27 JP JP2012015140A patent/JP2013157377A/en not_active Withdrawn
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015049849A1 (en) * | 2013-10-04 | 2015-04-09 | Ｎｅｃプラットフォームズ株式会社 | Electronic circuit board and method of assembly for same |
| JP2015170826A (en) * | 2014-03-10 | 2015-09-28 | 三菱マテリアル株式会社 | Manufacturing method of power module substrate with radiation plate |
| JP2020136449A (en) * | 2019-02-19 | 2020-08-31 | 富士電機株式会社 | Method of manufacturing semiconductor device |
| JP7215206B2 (en) | 2019-02-19 | 2023-01-31 | 富士電機株式会社 | Semiconductor device manufacturing method |
| JP2021007979A (en) * | 2019-07-03 | 2021-01-28 | 株式会社関電工 | Soldering jig and method |
| JP7305465B2 (en) | 2019-07-03 | 2023-07-10 | 株式会社関電工 | Soldering jig and method |
| US11552021B2 (en) | 2019-11-19 | 2023-01-10 | Fuji Electric Co., Ltd. | Semiconductor device, semiconductor manufacturing apparatus and method of manufacturing semiconductor device having printed circuit board and insulating board with complementary warps |
| US11637052B2 (en) | 2019-12-06 | 2023-04-25 | Fuji Electric Co., Ltd. | Semiconductor device and semiconductor device manufacturing method |
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