JP2013153579A - Charging device and program for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a charging device and a program therefor which suppress a turbulence of output waveform and a reduction in power factor.SOLUTION: In a charging device 10, if a timing Ta of a timer interrupt by which an input voltage detection section detects a full-wave-rectified waveform of input voltage is an immediate timing Ta (1) after a zero crossing timing Tb, a delay time Tdly from the zero crossing timing Tb to the immediate timing Ta (1) is calculated, and a storage location of memory for storing an inverse pattern value at the immediate timing Ta (1) is shifted in a time lapse direction by a shift amount corresponding to the delay time Tdly. If the timing Ta of the timer interrupt by which the input voltage detection section detects a full-wave-rectified waveform of input voltage is another timing Ta (2) later than the immediate timing Ta (1), a storage location of memory for storing an inverse pattern value at the different timing Ta (2) is shifted in the time lapse direction by the shift amount corresponding to the delay time Tdly calculated as to the immediate timing Ta (1).

Description

  The present invention relates to a charging device and a program thereof.

  After the AC power is full-wave rectified, the DC power converted by the DC-DC converter can be supplied to the storage battery, and the pulse width modulation signal obtained based on the reverse phase waveform with respect to the full-wave rectified waveform of the AC power As a charging device that controls the switching operation of the DC-DC converter, for example, there is one disclosed in Patent Document 1 below. This charging device stores ideal waveform data set in advance in a waveform memory as a reverse phase waveform with respect to the full-wave rectification waveform of AC power, and generates a pulse width modulation signal based on this waveform data. Yes.

JP 2004-147484 A

  In this type of charging device, control related to charging is often performed by a control device configured by a microcomputer (hereinafter referred to as “microcomputer”). For example, a timer interrupt that occurs at a predetermined time period causes a constant interruption. The charge control process is performed. The charging device disclosed in Patent Document 1 may be configured to periodically perform control processing of a microcomputer that generates a pulse width modulation signal and outputs it to a DC-DC converter by timer interruption.

  Since a commercial power supply is generally used to supply AC power to such a charging device, it is more convenient to perform information processing at a timing based on the frequency of the commercial power supply in the charging control process. For example, the waveform data stored in the waveform memory described above is read out at the timing of timer interrupt and used to generate a pulse width modulation signal, but the initialization of the read position is zero crossing where the polarity of the commercial power supply is switched. It is done based on timing.

  However, since such a pulse width modulation signal controls the switching operation of the DC-DC converter, the frequency of the timer interrupt is set to, for example, several hundred times the frequency of the commercial power supply. Yes. Therefore, it is difficult to synchronize both timings when the integer multiple of the timer interrupt cycle does not match the time cycle of the commercial power supply frequency. Even if the timer interrupt frequency is set so that an integer multiple of the timer interrupt period matches the time period of the commercial power supply frequency, errors that are difficult to avoid physically, such as the accuracy of the frequency and the hardware delay time, may occur. Both timings are difficult to synchronize.

  For this reason, in the charging device disclosed in Patent Document 1, both timings are asynchronous between the zero cross timing and the initialization processing timing even if the waveform data read position is initialized based on the zero cross timing. A time difference with variation due to the occurrence of this occurs. Therefore, the waveform data at the timing deviated from the original timing is read from the waveform memory, and depending on the read waveform data, the power waveform output from the charging device to the storage battery may be disturbed or the power factor There was a problem that it could lead to a decline.

  Further, in the full-wave rectified waveform of AC power, the ratio of ripple components that can be included in the full-wave rectified waveform (the peak value of the unevenness) generally varies depending on the load state of the charging device. That is, the ripple component that can be removed by the smoothing capacitor tends to decrease as the output current decreases. Therefore, the ripple component is small when the load is relatively light, and the ripple component is large when the load is heavy. Therefore, in a configuration in which preset waveform data is read from the waveform memory and a pulse width modulation signal is generated, a pulse width modulation signal that dynamically corresponds to such a load variation cannot be generated. Therefore, there is a problem that the output waveform may be disturbed depending on the lightness of the load state.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a charging device and a program for the same that can suppress disturbance of an output waveform and a decrease in power factor.

  In order to achieve the above object, the charging device described in claim 1 of the claims is configured to be able to supply direct current power converted by a DC-DC converter to a storage battery after full-wave rectification of alternating current power. A charging device for controlling a switching operation of the DC-DC converter by a pulse width modulation signal obtained based on a reverse phase waveform with respect to a full-wave rectified waveform of the AC power, the zero crossing of the input voltage waveform of the AC power A zero-cross detection unit that detects timing, a voltage detection unit that detects a voltage of the full-wave rectified waveform at a time period of a predetermined timing different from the zero-cross timing of the input voltage waveform, and a voltage detected by the voltage detection unit A negative phase corresponding value calculating unit that calculates a negative phase corresponding value corresponding to the negative phase waveform at the predetermined timing, and the negative phase waveform A waveform storage unit that stores a plurality of the anti-phase correspondence values calculated by the anti-phase correspondence value calculation unit for each time period as waveform information in a storage position positioned in time series, and the predetermined timing is When the timing is immediately after the zero cross timing, after calculating the elapsed time from the zero cross timing to the immediately following timing, the storage position of the waveform storage unit that stores the negative phase corresponding value at the immediately following timing is set to the time When the predetermined timing is a timing later than the immediately following timing, the waveform storage unit stores the inverse phase corresponding value at the predetermined timing when the predetermined timing is shifted by the amount corresponding to the elapsed time. The position is shifted in the elapsed time direction by the amount corresponding to the elapsed time calculated at the immediately following timing. And technical features to be.

  Further, the charging device according to claim 2 of the claim is the charging device according to claim 1, wherein the pulse width modulation signal has an arbitrary phase angle with respect to the storage position of the waveform storage unit. It is technically characterized in that it is generated based on the waveform information of the anti-phase waveform read out from the position where the phase is advanced or delayed.

  Furthermore, the charging device according to claim 3 of the claim is the charging device according to claim 1 or 2, wherein the waveform storage unit stores the reverse-phase corresponding value in the waveform storage unit. When the negative phase correspondence value is already stored in the storage position, an average value obtained by adding a new negative phase correspondence value to a predetermined weighting of the negative phase correspondence value already stored is obtained. It is a technical feature that the data is stored in the storage location.

  In order to achieve the above object, the program of the charging device described in claim 4 of the claims is configured such that after the AC power is full-wave rectified, the DC power converted by the DC-DC converter can be supplied to the storage battery. The DC-DC converter is switched by a pulse width modulation signal obtained based on the waveform information stored in the waveform storage unit in a reverse phase waveform with respect to the full-wave rectified waveform of the AC power in a program for controlling the charging device A program for causing a computer to execute control, wherein the voltage detection step detects the voltage of the full-wave rectified waveform at a predetermined time period different from the zero-cross timing of the input voltage waveform of the AC power; and the voltage detection Based on the voltage detected in the step, a negative phase corresponding value of the negative phase waveform at the predetermined timing is calculated. In a negative phase corresponding value calculating step, and when the predetermined timing is a timing immediately after the zero cross timing, a step of calculating an elapsed time from the zero cross timing to the immediate timing and the negative phase corresponding value at the immediately following timing are calculated. Immediately after the zero crossing, including a step of determining the storage position in the storage position of the waveform storage unit positioned in time-series order as the waveform information of the reverse phase waveform by shifting the storage position to the elapsed time corresponding to the elapsed time When the processing step and the predetermined timing are later than the immediately following timing, the waveform storage unit that stores the negative phase corresponding value calculated by the negative phase corresponding value calculating step at the predetermined timing The storage position is determined by the step immediately after the zero crossing. The post-zero cross processing step for determining the position shifted in the time lapse direction by an amount corresponding to the elapsed time, and the storage position of the waveform storage unit determined by the processing step immediately after the zero cross or the post-zero cross processing step. And generating a pulse width modulation signal by reading out the waveform information stored in the waveform storage unit and storing the negative phase corresponding value calculated in the negative phase corresponding value calculating step. And a waveform information output step for outputting to the pulse width modulation section.

  Moreover, the program of the charging device according to claim 5 of the claim is the program according to claim 4, wherein the waveform information output step has an arbitrary phase with respect to the storage position of the waveform storage unit. A technical feature is that the waveform information is read from a position where the phase is advanced or delayed by an angle and is output to the pulse width modulation signal.

  In the first aspect of the invention, when the predetermined timing for detecting the voltage of the full-wave rectified waveform by the voltage detection unit is a timing immediately after the zero cross timing, that is, the negative phase corresponding value of the negative phase waveform stored in the waveform storage unit is the first. In the case of the (first or first) anti-phase correspondence value, after calculating the elapsed time from the zero cross timing to the immediately following timing, the storage position of the waveform storage unit that stores the anti-phase correspondence value at the immediately following timing is set to the time A shift corresponding to the elapsed time is made in the elapsed direction. Further, when the predetermined timing for detecting the voltage of the full-wave rectified waveform by the voltage detection unit is a timing after the immediately following timing, that is, the negative phase corresponding value of the negative phase waveform stored in the waveform storage unit is from the beginning (first). In the case of the later (second or later) anti-phase corresponding value, the storage position of the waveform storage unit that stores the anti-phase corresponding value at the predetermined timing is equivalent to the elapsed time calculated at the immediately subsequent timing, Shift in the direction of time passage.

  Accordingly, the head (first or first) stored in the waveform storage unit corresponds to the elapsed time from the zero cross timing to the immediately subsequent timing, that is, the time delayed from the zero cross timing to the time when the voltage is detected by the voltage detection unit. The storage position of the opposite-phase corresponding value is corrected by shifting it in the direction of time passage (delayed direction), and also when it is the second-phase corresponding value (after the second), it is shifted by an amount corresponding to this delayed time. Compared to the case where the storage position of the first (first) antiphase corresponding value stored in the waveform storage unit is stored in the predetermined position without correcting such a time shift. Therefore, it is possible to store an appropriate anti-phase correspondence value in the waveform storage unit. Therefore, in the charging device, since a pulse width modulation signal based on such an appropriate reverse phase waveform is obtained, it is possible to suppress disturbance in the power waveform due to temporal deviation.

  In the invention of claim 2 or claim 5, the pulse width modulation signal is a waveform of an antiphase waveform read from a position where the phase is advanced or delayed by an arbitrary phase angle with respect to the storage position of the waveform storage unit. Generated based on information. As a result, a pulse width modulation signal based on an antiphase waveform whose phase has been advanced or delayed by an arbitrary phase angle can be obtained, and in addition to suppressing disturbance in the power waveform due to temporal deviation, the power factor is also reduced. Can be suppressed.

  In the invention of claim 3, when storing the anti-phase correspondence value in the waveform storage unit, if the anti-phase correspondence value is already stored in the storage position of the waveform storage unit, the anti-phase correspondence already stored is stored. An average value obtained by adding a new anti-corresponding value to a value obtained by predetermined weighting is stored in a storage position. As a result, since a new anti-phase correspondence value is stored with a weight on the pre-stored anti-phase correspondence value, for example, the current anti-phase correspondence value and the anti-phase correspondence value stored so far in the waveform storage unit are stored. Even if there is a large difference between the corresponding values, it is possible to suppress fluctuations in the negative phase corresponding values compared to the case where the current negative phase corresponding values are stored as they are.

  In the invention of claim 4, when the predetermined timing for detecting the voltage of the full-wave rectified waveform in the voltage detection step is a timing immediately after the zero cross timing, that is, the negative phase corresponding value of the negative phase waveform stored in the waveform storage unit is the head. In the case of the (first or first) negative phase correspondence value, the elapsed time from the zero cross timing to the immediate timing is calculated by the processing step immediately after zero crossing, and the negative phase correspondence value at the immediate timing is used as waveform information of the negative phase waveform. As for the storage position of the waveform storage unit positioned in chronological order, the storage position is determined as a position shifted in the time lapse direction by an amount corresponding to the elapsed time. In addition, when the predetermined timing for detecting the voltage of the full-wave rectified waveform in the voltage detection step is the timing after the immediately following timing (second), the negative phase corresponding value is calculated at this predetermined timing by the processing step after zero crossing. The storage position of the waveform storage unit that stores the anti-phase corresponding value calculated in the step is determined as a position shifted in the time lapse direction by an amount corresponding to the elapsed time calculated in the step immediately after the zero crossing.

  As a result, the head (first or first) stored in the waveform storage unit corresponds to the elapsed time from the zero cross timing to the immediately subsequent timing, that is, the delay time from the zero cross timing until the voltage is detected by the voltage detection step. The storage position of the opposite-phase corresponding value is corrected by shifting it in the direction of time passage (delayed direction), and also when it is the second-phase corresponding value (after the second), it is shifted by an amount corresponding to this delayed time. Compared to the case where the storage position of the first (first) antiphase corresponding value stored in the waveform storage unit is stored in the predetermined position without correcting such a time shift. Therefore, it is possible to store an appropriate anti-phase correspondence value in the waveform storage unit. Therefore, in the program of the charging device, since a pulse width modulation signal based on such an appropriate reverse phase waveform is obtained, it is possible to suppress disturbance in the power waveform due to temporal deviation.

It is a block diagram which shows the structural example of the charging device which concerns on one Embodiment of this invention. FIG. 2 (A) is a reverse phase waveform, FIG. 2 (B) is a full-wave rectified waveform (DC voltage waveform) obtained by full-wave rectification of a three-phase AC voltage, and FIG. 2 (C). Is a partial waveform including a ripple component of the full-wave rectified waveform shown in FIG. 2B and its reverse phase waveform, and FIG. 2D is a PWM signal waveform based on the reverse phase waveform shown in FIG. Each is shown. 3A is a three-phase AC voltage waveform, FIG. 3B is a zero-cross detection signal waveform, FIG. 3C is a timer interrupt signal waveform, and FIG. 3 (A) to 3 (C) are overlaid on each other to enlarge the two-dot chain line α section, and FIG. 3 (E) shows the two-dot chain line β frame shown in FIG. 3 (D). Each of the enlarged waveforms is shown. 4A is a conceptual example of a reverse phase waveform based on reverse pattern values stored in the memory, and FIG. 4B is the reverse of the first one cycle of the processes stored in the memory shown in FIG. 4A. FIG. 4 (C) to FIG. 4 (F) are examples in which the process stored in the memory shown in FIG. 4 (A) is replaced with the concept of the antiphase waveform, and FIG. 4 (G) to FIG. 4 (J) are explanatory views respectively showing comparative examples corresponding to FIG. 4 (C) to FIG. 4 (F). It is a flowchart which shows the flow of the charge control process by the control unit of the charging device which concerns on this embodiment.

  Embodiments of a charging device and a program thereof according to the present invention will be described below with reference to the drawings. First, the hardware configuration of the charging apparatus 10 will be described with reference to FIGS. FIG. 1 is a block diagram illustrating a configuration example of the charging device 10. 2 and 3 illustrate a reverse phase waveform, a full-wave rectified waveform, a PWM signal waveform, a three-phase AC voltage waveform, a zero-cross detection signal waveform, a timer interrupt signal waveform, and the like.

  As shown in FIG. 1, the charging device 10 has a function capable of charging the battery Batt by converting AC power supplied from the three-phase AC power supply AC into DC power. , A step-down IGBT module 13, a step-up IGBT module 15, a detection transformer 18, a current sensor 19, a control unit 20, and the like. The charging device 10 according to the present embodiment is an example of a constant current control type that controls the charging current Io of the charging power supplied to the battery Batt to be a predetermined constant current value Icnt.

  The full-wave rectifier diode 12 is capable of full-wave rectification for all phases (UV phase, VW phase, WU phase) of a three-phase 200 V AC voltage (see FIG. 3A) supplied from a three-phase AC power source AC. It is a semiconductor module composed of a plurality of diodes (semiconductor rectifying elements). The waveform Wrct of the direct-current voltage (input voltage Vi) rectified by the full-wave rectifier diode 12 includes a ripple component of the full-wave rectified waveform as shown in FIG. To the control unit 20. The “ripple component of the full-wave rectified waveform” is a repetitive waveform of peaks and valleys represented by a thick solid line in FIG.

  The step-down IGBT module 13 is a semiconductor module including a switching element for stepping down a DC voltage (input voltage Vi) output from the full-wave rectifier diode 12, and an IGBT (insulated gate bipolar transistor), for example, is used as the switching element. There are things. In this embodiment, for example, it is made of a PNP type IGBT, and an input is connected to the input side (collector) and a choke coil 14 is connected to the output side (emitter), and on / off control is enabled between the input and output. The gate output unit 27 of the control unit 20 is connected to a control terminal (gate) so that the PWM signal Dpwm can be input.

  In the present embodiment, when the charging voltage Vo of the battery Batt needs to be equal to or lower than the voltage supplied from the three-phase AC power supply AC, the charging current Io detected by the current sensor 19 approaches the predetermined constant current value Icnt. The PWM signal Dpwm controlled as described above is input to the switching element via the gate output unit 27. As a result, the on / off period of the switching element is controlled by the PWM signal Dpwm output from the CPU 21. Therefore, the increase / decrease in the output current of the step-down IGBT module 13 toward the predetermined constant current value Icnt as the target value of the charging current Io. Control becomes possible.

  On the other hand, the step-up IGBT module 15 is a semiconductor module including a switching element for stepping up a DC voltage output from the step-down IGBT module 13, and voltage control opposite to that of the step-down IGBT module 13 is performed. That is, the boosting IGBT module 15 allows the charging current Io to approach the predetermined constant current value Icnt when the charging voltage Vo of the battery Batt needs to be higher than the voltage supplied from the three-phase AC power supply AC. The output current of the boosting IGBT module 15 can be increased or decreased.

  In the present embodiment, for example, a diode connected between the input and output so as to allow current from the input side to the output side and prevent a flow in the opposite direction, and a choke coil 14 connected to the input side, And an NPN type IGBT which is connected to a reference potential such as ground so as to be capable of on / off control. The gate output section 27 of the control unit 20 is also connected to the control terminal (gate) of the IGBT so that a PWM signal Upwm that enables on / off control between the input and output can be input. As a result, the on / off period of the switching element is controlled by the PWM signal Upwm output from the CPU 21 so that the output current can be increased or decreased so that the charging current Io approaches the predetermined constant current value Icnt.

  Thus, in the present embodiment, the step-down IGBT module 13 and the step-up IGBT module 15 are in directions opposite to each other such that the step-down IGBT module 13 decreases the voltage and the step-up IGBT module 15 increases the voltage. Voltage control is performed. For this reason, when the charging current Io of the charging device 10 is controlled by the step-down IGBT module 13, current control by the step-up IGBT module 15 is not performed, and during this time, the switching element of the step-up IGBT module 15 is It is controlled by the CPU 21 so as to maintain the off state. Further, when the charging current Io of the charging device 10 is controlled by the boosting IGBT module 15, the current control by the step-down IGBT module 13 is not performed, and during this time, the switching element of the step-down IGBT module 13 is on. It is controlled by the CPU 21 so as to maintain the state.

  In the present embodiment, a smoothing capacitor 16 is connected to the output side of the boosting IGBT module 15 between a reference potential such as ground, and one end side of the smoothing capacitor 16 is connected to the output of the charging device 10. The other end side of the choco 17 is connected. As a result, switching noise and ripple components that can be included in the output voltage of the boosting IGBT module 15 can be removed.

  The detection transformer 18 is a voltage measuring transformer that outputs, with high accuracy, a voltage proportional to a voltage between two predetermined phases out of the three-phase AC voltage input from the three-phase AC power supply AC. In the present embodiment, for example, the input of the detection transformer 18 is connected between the UV phases of the three-phase AC power supply AC, and the output thereof is connected to the input voltage detection unit 23 and the zero cross detection unit 25 of the control unit 20. Thus, a voltage proportional to the UV phase interphase voltage Vuv can be output to the input voltage detection unit 23 and the zero cross detection unit 25. Note that a voltage proportional to the interphase voltages Vvw and Vwu may be output to the input voltage detection unit 23 and the zero cross detection unit 25 by connecting between the VW phase and the WU phase of the three-phase AC power supply AC. Further, each voltage proportional to all the interphase voltages Vuv, Vvw, Vwu may be configured to be output to the input voltage detection unit 23 and the zero cross detection unit 25.

  The current sensor 19 is for current measurement that outputs a voltage proportional to the output current output from the boosting IGBT module 15 and the current value of the output current output from the step-down IGBT module 13 via the boosting IGBT module 15. A current flowing between the smoothing capacitor 16 and the choco coil 17, that is, a charging current Io output from the charging device 10 to the battery Batt is connected between the transformers so as to be detectable. In the present embodiment, the output of the current sensor 19 is connected to the control unit 20 so that a voltage proportional to the charging current Io can be output to the output current detector 28 of the control unit 20.

  The control unit 20 includes a CPU 21, a memory 22, an input voltage detection unit 23, a zero cross detection unit 25, an input voltage detection unit 26, a gate output unit 27, an output current detection unit 28, an output voltage detection unit 29, and the like. And can correspond to the “computer” recited in the claims.

  The CPU 21 is a microcomputer (arithmetic processing unit), and is connected to the memory 22, the input voltage detection unit 23, and the like via an unillustrated system bus, data bus, input / output port, or the like. In the present embodiment, the CPU 21 and the memory 22 are configured as individual semiconductor modules, but may be a one-chip microcomputer in which both are integrated into one module or package.

  The memory 22 is a semiconductor storage device including SRAM, DRAM, EEPROM, and the like, and constitutes a main storage space and an auxiliary storage space used by the CPU 21. The main storage space is allocated to a work area and a data area, and in the auxiliary storage space, a program (charge control program or basic program) coded such that a charge control process and other basic processes described later can be executed by the CPU 21 Stores reverse pattern values (reverse phase corresponding values of reverse phase waveforms). The memory 22 may correspond to a “waveform storage unit” recited in the claims.

  The input voltage detector 23 has an A / D conversion function capable of converting a detection voltage (analog value) proportional to the interphase voltage Vuv output from the detection transformer 18 into digital data (digital value) having a predetermined number of bits. , The input is connected to the output of the detection transformer 18. The output of the input voltage detection unit 23 is configured to be connectable to an input port of the CPU 21. Thus, the CPU 21 can acquire voltage information of the UV phase waveform Wuv of the three-phase AC waveform. When the interphase voltage output from the detection transformer 18 is the voltage Vvw between the VW phases or the voltage Vwu between the WU phases, the CPU 21 determines each of the VW phase waveform Wvw and the WU phase waveform Wwu among the three-phase AC waveforms. Voltage information can be acquired (see FIG. 3A).

  As shown in FIG. 3 (A), the zero-cross detector 25 changes from a negative value to a positive value among points where the AC voltage periodically becomes 0V (a broken line position shown in FIG. 3A), that is, by a rising edge. It has a function capable of detecting the timing of a point Pz (hereinafter referred to as “zero cross point Pz”), and this output is configured to be connectable to an input port of the CPU 21. Thereby, for example, the CPU 21 uses the detection of the rising edge of the zero-cross detection signal Szc input from the zero-cross detection unit 25 to the CPU 21 as a trigger, and the timing of the zero-cross point Pz (hereinafter referred to as “zero-cross timing”) Tb by the input capture function. Can be obtained. The zero cross timing Tb is given by, for example, the count value of the time counter Ct. Note that the timing of the falling edge (change from a positive value to a negative value) may be the zero cross point Pz.

  The input voltage detection unit 26 also has an A / D conversion function similar to the input voltage detection unit 23 and the like, and is connected to the output side of the full-wave rectifier diode 12 to output from the full-wave rectifier diode 12. The three-phase rectified voltage (analog value) after full-wave rectification is converted into digital data (digital value) having a predetermined number of bits. In the present embodiment, as described above, the input voltage Vi (full wave rectified waveform Wrct shown in FIG. 2B) is input from the full wave rectifier diode 12 as a DC voltage including a ripple component. For this reason, the input voltage detector 26 outputs information on the input voltage Vi including such a ripple component. The output of the input voltage detection unit 26 is configured to be connectable to an input port of the CPU 21. Thus, the CPU 21 can acquire voltage information of a full-wave rectified wave (input voltage information including a ripple component). The input voltage detection unit 26 may correspond to a “voltage detection unit” recited in the claims.

  The gate output unit 27 is an output driver for controlling output of PWM signals Dpwm and Upwm generated by the CPU 21 to the step-down IGBT module 13 and the step-up IGBT module 15 as will be described later. For this reason, the input of the gate output unit 27 is connected to the output port of the CPU 21 to which the PWM signals Dpwm and Upwm corresponding to the step-down IGBT module 13 and the step-up IGBT module 15 are output. The outputs are separately connected to the step-down IGBT module 13 and the step-up IGBT module 15, respectively.

  The output current detection unit 28 also has an A / D conversion function like the input voltage detection unit 23 and the like, and the step-down output from the current sensor 19 when the input is connected to the output side of the current sensor 19. The output current value of the IGBT module 13 for boosting and the IGBT module 15 for boosting, that is, the voltage proportional to the charging current Io of the charging device 10 (analog value) can be converted into digital data (digital value) of a predetermined number of bits. ing. The output of the output current detection unit 28 is configured to be connectable to an input port of the CPU 21, whereby the CPU 21 can acquire information on the charging current (output current) of the charging device 10.

  The output voltage detection unit 29 also has an A / D conversion function like the input voltage detection unit 23 and the like, and the input is connected to the output side of the choco coil 17, that is, the output of the charging device 10. The charging voltage Vo of the charging apparatus 10 can be converted into digital data (digital value) having a predetermined number of bits (analog value). The output of the output voltage detection unit 29 is configured to be connectable to an input port of the CPU 21, whereby the CPU 21 can acquire information on the charging voltage (output voltage) of the charging device 10.

  Here, the reverse pattern value stored in the memory 22 by the charge control process described later will be described with reference to FIG. 2, FIG. 4 (A), and FIG. 4 (B). The waveforms shown in FIG. 2 (A) and FIG. 2 (B) correspond to one cycle (period) per phase of the three-phase AC voltage waveform, and in FIG. A voltage when focusing only on the phase is indicated by a solid line, a voltage when focusing only on the VW phase is indicated by a broken line, and a voltage when focusing only on the phase between the WU phases is indicated by an alternate long and short dash line.

  4A shows a conceptual example of a reverse phase waveform Wmem that can be represented by a reverse pattern value stored in the memory 22, and FIG. 4B shows a reverse pattern value in the memory 22. An example is shown in which the reverse pattern value d1 for the first cycle in the process of storing is replaced with the concept of the reverse phase waveform Wmem. The reverse phase waveform Wmem shown in FIG. 4 is based on the premise that time elapses from the left side to the right side of FIG. 2 and FIG. Further, the addresses of the memory 22 can correspond so that the address values sequentially increase from the left side to the right side of the page.

  In this embodiment, the ripple component of the full-wave rectified waveform Wrct as shown in FIG. 2B is reversed in phase (inverted voltage component of the ripple component in the voltage waveform). The reverse pattern value (reverse phase corresponding value) corresponding to the reverse phase waveform Winv as shown in FIG. For example, a reverse pattern data area capable of storing 1024 reverse pattern values in the memory 22 is secured, and one cycle per phase of a three-phase AC voltage waveform is divided by 1024 to elapse from a predetermined reference time. The reverse pattern values can be stored in time series in association with time. The predetermined reference time is set as a predetermined reference position in the reverse pattern data area of the memory 22.

  As will be described later, the reverse pattern value can be obtained by a predetermined calculation based on information of the input voltage Vi after full-wave rectification detected by the input voltage detection unit 26. In the present embodiment, the reverse pattern value is generated at every predetermined timing. It is generated by the charging control process by the timer interruption. Thus, the reverse pattern value corresponding to the reverse phase waveform Winv is accumulated in the memory 22 by generating the reverse pattern value every time the timer interrupts and sequentially storing it in the reverse pattern data area.

  For example, the ripple waveform Ru in 1/6 cycle of one phase (UV phase) of a three-phase AC voltage waveform as shown in FIG. 2C will be described as an example, and stored in the reverse pattern data area of the memory 22. The inverse pattern value that corresponds to the reverse phase waveform Winv indicated by the broken line in FIG. 2 (C) is the minimum value at the peak (maximum value) portion of the ripple component of the full-wave rectified waveform Wrct, and the bottom of the ripple component ( The minimum value is the maximum value. As shown in FIG. 2D, the pulse width of the PWM signal waveform Wpwm also has a minimum value Wmin at the peak portion of the ripple component and a maximum value Wmax at the bottom portion of the ripple component. The pulse widths of these PWM signals are set so that the areas (the areas of the shaded portions shown in FIG. 2C) are almost the same.

  The CPU 21 reads out a reverse pattern value corresponding to the reverse phase waveform Winv as an output pattern from the reverse pattern data area of the memory 22 at a predetermined timing by a timer interrupt, and also reads the read output pattern, the charging current Io, and a predetermined constant. An appropriate PWM signal to be output to the step-down IGBT module 13 or the step-up IGBT module 15 can be generated based on the current value Icnt. Thereby, the charging device 10 can output the charging current Io so as to coincide with the predetermined constant current value Icnt.

  By the way, since the reverse pattern value accumulated in the reverse pattern data area of the memory 22 is generated by the charge control process executed by the timer interrupt, for example, when the timer interrupt occurs every 50 microseconds. If the frequency of the three-phase AC power is 60 Hz, 333.3 times (= 16.7 mS / 50 μS) in one cycle (16.7 milliseconds), and if it is 50 Hz, one cycle (20 milliseconds) ) And is generated by the charge control process at a rate of 400 times (= 20 mS / 50 μS) and stored in the memory 22. However, in this embodiment, the number of reverse pattern values (333 or 400) generated during one cycle does not match the number of data that can be stored in the memory 22 (1024). Therefore, the data is stored in the data area of the memory 22 in a “thinning-out state” in which a time-series gap is created at every interruption time interval (50 microseconds) due to timer interruption.

  For example, when the concept of the reverse phase waveform represented by the reverse pattern value stored in the memory 22 is the waveform Wmem shown in FIG. 4A, the memory is stored during the first cycle (333 in the case of 60 Hz). As shown in FIG. 4B, the inverse pattern value d1 stored in 22 is located at predetermined intervals along the waveform Wmem represented by a broken line. That is, in the first cycle, every predetermined interrupt time interval (for example, 50 microseconds) starts from a predetermined reference time out of 1024 divisions (in the case of FIG. 4B, the oldest time at the left end of the page). A reverse pattern value d1 is stored in the memory 22 so as to form a time-series gap. In FIG. 4B, a short vertical line displayed on the broken line waveform Wmem is a mark for clearly indicating the time-series positional relationship in which the reverse pattern value d1 is stored. Also, it should be noted that the reverse pattern values d1 and the like are reduced to 1/10 or less for convenience of drawing in these drawings.

  In this manner, since the reverse pattern values are stored in the reverse pattern data area of the memory 22 in a thinned state in which time series gaps are formed, until the reverse pattern values for one cycle (1024) are sufficiently aligned. For example, a time of about several tens of cycles (around 1 second) is required. Usually, however, there is a time margin of at least about 1 second after the power is turned on because of the usage characteristics of the charging device 10. Inverse pattern values can be stored and stored in the memory 22.

  For example, when the number of data that can be stored in the memory 22 is 1,024 and the frequency of the three-phase AC power is 60 Hz, the time series gap (thinning interval) is three data (= 1024 pieces / 333 times). Note that such a storage position on the memory 22 is set based on the count value of the counter Ci for counting up during the charging control process, as will be described later, and the zero cross detection unit 25 detects the zero cross. The counter Ci is reset in the charge control process that is performed immediately after the signal Szc is detected, and the count value returns to the initial value (for example, “1”).

  That is, in the charge control process executed by the timer interrupt generated at the timing (hereinafter referred to as “immediate timing”) Ta (1) immediately after the zero cross timing Tb (0) shown in FIGS. 3 (A) and 3 (B). The counter Ci is reset. The initial value of the counter Ci is set, for example, to a value corresponding to the left end (oldest time point) of the reverse phase waveform Wmem shown in FIG. 4B, and returns to that value upon reset. However, as shown in FIGS. 3D and 3E, the zero-cross timing Tb (n) (n is -1, 0, 1) and the timer interrupt timing Ta (n) (n is -1 , 0, 1, 2) do not necessarily match. In some cases, a time lag of up to 50 microseconds (Tdly shown in FIG. 3D) occurs between the two, and the input voltage Vi detected with a delay of 50 microseconds from the zero cross timing Tb (0) is a reverse phase waveform. It can be stored in the memory 22 corresponding to the left end (the oldest time) of Wmem.

  In this case, the reverse pattern value d1 stored in the memory 22 during the first cycle is stored in the memory 22 corresponding to the position shifted from the original reverse phase waveform Wmem, as shown in FIG. Further, the inverse pattern values d2 and d3 stored in the memory 22 in each subsequent cycle correspond to positions shifted from the inverse phase waveform Wmem as shown in FIGS. 4 (H) and 4 (I). And stored in the memory 22. For this reason, as shown in FIG. 4 (J), the negative phase waveform Wmem ′ by the reverse pattern value dn finally stored in the reverse pattern data area has zero cross timing Tb ( 0) and the timing Ta (1) immediately after the timer interruption, the phase advances by the phase angle Fdly corresponding to the delay time Tdly. Note that the reverse pattern values d1 to d3 and dn shown in FIGS. 4G to 4J are emphasized in terms of the drawings in order to clarify the positional shift with respect to the reverse phase waveform Wmem. Please keep in mind.

  Therefore, since the reverse pattern value of the reverse phase waveform Wmem having such a phase shift can be stored in the reverse pattern data area of the memory 22, the reverse pattern value to be read is originally read in the reverse pattern value reading. A reverse pattern value of a waveform Wmem ′ different from the waveform Wmem may be read, and a PWM signal waveform may be generated based on the read pattern value. For this reason, the charging voltage Vo and the charging current Io output from the step-down IGBT module 13 and the step-up IGBT module 15 may be disturbed.

  Therefore, in the present embodiment, as shown in FIG. 3D, in the charge control process by the timer interruption that occurs at the timing Ta (1) immediately after the zero cross timing Tb (0), the storage position of the reverse pattern data area is set. The associated counter Ci is reset, and the time difference (delay time Tdly) between the zero cross timing Tb (0) and the immediately subsequent timing Ta (1) is calculated, and the storage position of the reverse pattern value stored in the reverse pattern data area of the memory 22 Is shifted by this time difference. Thereby, it is possible to suppress the disturbance of the output waveform due to such a shift of the storage position. The timing Ta (0) immediately after the timer interrupt signal Sit and the timing after the timing Ta (0) (hereinafter referred to as “other timing Ta”) Ta (−1), Ta (1), Ta (2) Is given by the count value of the time counter Ct.

  As an example of such a charge control process, a flowchart is shown in FIG. 5 and will be described with reference to FIGS. This charge control process is realized by the charge control program loaded in the main storage area of the memory 22 being activated and executed by the CPU 21 every time a timer interrupt occurs every 50 microseconds, for example. .

  As shown in FIG. 5, in the charge control process, first, a zero-cross information acquisition process is performed in step S101. This process obtains information on whether or not the charge control process is started immediately after the zero cross timing Tb (0) and the time information of the zero cross timing Tb (0). Flag information indicating the presence or absence of the counter, and the count value (time information) of the counter Ct at the zero cross timing Tb (0) by the input capture function are acquired. Note that the count value of the counter Ct held by the input capture is the current value, but the previous (previous) Tb (−1) value is held in the memory 22 and remains.

  In the next step S102, an input voltage acquisition process is performed. In this process, information about the three-phase rectified voltage after full-wave rectification output from the full-wave rectifier diode 12, that is, information on the input voltage Vi is acquired from the input voltage detection unit 26. This information on the input voltage Vi is used in a reverse pattern value calculation process (S119) described later.

  In subsequent step S103, based on the zero-cross information acquired in step S101, a determination process is performed as to whether or not the charge control process is started by a timer interrupt immediately after the zero-cross timing Tb (0). For example, the presence / absence of input capture is determined from the flag value based on the flag information in step S101. If it is determined by this determination processing that the input capture is “present” and the timer is interrupted by the timing Ta (1) immediately after the zero cross timing Tb (0) (S103; Yes), the following step S105 is performed. The process is transferred to. On the other hand, when it is not determined that the input capture is “no” and the timer is triggered by the timer interruption at the timing Ta (1) immediately after the zero cross timing Tb (0) (S103; No), step S105, The process proceeds to step S115 without performing steps S107 and S109.

  That is, when the timer interrupt immediately after the zero cross timing Tb (0) is triggered by a timer interrupt at another later timing Ta (2) (or Ta (0), Ta (-1)) (S103; No), it is not necessary to reset the counter Ci (S107) or calculate the time difference Tdly between the zero-cross timing Tb (0) and the immediately following timing Ta (1) (S109), so these processes are skipped. Further, when the charging control process is started by a timer interruption at the timing Ta (1) immediately after, the following processes of steps S105, S107, and S109 are performed.

  In step S105, an interrupt information acquisition process is performed. This process acquires time information when the timer interrupt occurs. For example, the timer interrupt signal Sit is used as a trigger to acquire the count value (time information) of the counter Ct at the timer interrupt timing Ta.

  In the subsequent step S107, counter initialization processing is performed. That is, in this process, a process for returning the counter Ci to an initial value (for example, zero) is performed. As a result, when the charge control process is started by a timer interruption immediately after the zero cross timing Tb (0), the reverse pattern value can be stored starting from the reference position set in the reverse pattern data area. In step S107, a process for clearing the flag value of the input capture, that is, flag information indicating the presence / absence of the input capture (input capture “none”) is performed. Thus, unless an input capture is generated by a new zero cross point Pz, this flag does not become “captured”.

  In step S109, a delay time calculation process is performed. In this process, a time required from the zero cross timing Tb (0) until the charge control process is started by a timer interruption, that is, a delay time with respect to the zero cross timing Tb (0) is calculated. In the present embodiment, the count value (time information) of the counter Ct at the zero cross timing Tb (0) acquired at step S101, and the count value (time information) of the counter Ct at the timing Ta (1) acquired at step S105. , Delay time Tdly (= Ta (1) −Tb (0)) is calculated.

Each process after step S115 is performed regardless of whether or not the charge control process is started by a timer interrupt immediately after the zero cross timing Tb (0).
In step S115, a storage location calculation process is performed. In this process, the storage destination of the reverse pattern value calculated in the subsequent step S119, that is, the storage position in the reverse pattern data area of the memory 22 is calculated.

  For example, as shown in FIG. 4 (C), every time the charging control process is executed once, a gap corresponding to an interrupt time interval (50 microseconds in the case of 60 Hz) is formed by a timer interrupt. When one cycle time Tcyc of elapses, the storage position of the reverse pattern value d1 is calculated every time so that the thinning state as shown in FIG.

  For example, in the timer interrupt that occurs immediately after the timing Ta (1) (Ci = 1), the number of data that can be stored in the memory 22 is 1,024, the interrupt interval is 50 microseconds, the delay time Tdly and one cycle (16.16). 7 ms), the storage location is calculated by 1024 × (50 μS + Tdly) /16.7 mS, and the next timer interrupt (Ci = 2), the storage location is calculated by 1024 × (100 μS + Tdly) /16.7 mS. . For example, the number after the decimal point is rounded down to an integer (rounding or rounding up may be used).

  That is, the storage position of the reverse pattern value on the memory 22 is (1024 × (50 μS × Ci + Tdly) /16.7 mS), and the counter Ci that is counted up one by one each time the charge control process is executed. Is calculated based on the counter value. Thereby, the storage position of the reverse pattern value d1 is a position corresponding to the earliest time of the reverse pattern data area as a position shifted in time corresponding to the delay time Tdly, for example, as shown in FIG. The position is shifted by the shift amount Fsft from the (the left end of the reverse phase waveform Wmem shown in FIG. 4C) toward the latest time direction (the right end of the reverse phase waveform Wmem shown in FIG. 4C). In the thinned-out state shown in FIG. 4C, the process proceeds in the latest time direction of the antiphase waveform Wmem.

  In step S117, a reverse pattern value reading process is performed. In this process, the reverse pattern value already stored in the storage position of the reverse pattern value calculated in step S115 is read. That is, when calculating the reverse pattern value in the next step S119, it is performed in consideration of the past reverse pattern values accumulated so far.

  In step S119, a reverse pattern value calculation process is performed. In this process, an inverse pattern value is calculated by performing a calculation based on the information of the input voltage Vi acquired in step S102. For example, by calculating the reciprocal of the input voltage Vi, a reverse pattern value corresponding to the input voltage Vi can be obtained. In this embodiment, the reverse pattern value obtained in this way is converted to the past pattern value read in step S117. A reverse pattern value multiplied by N (integer) is added, and the addition result is divided by (N + 1) to obtain a new reverse pattern value taking into account the past reverse pattern value. The value of N is, for example, the number of executions of the charge control process required to complete a reversed-phase waveform Wmem with sufficient reverse pattern values, a counter value for counting the number of executions of the charge control process provided separately, etc. Set to

  Thereby, the current reverse pattern value calculated this time is added to the weighted past reverse pattern value, and a new reverse pattern value can be obtained as the average value. That is, since a new reverse pattern value is calculated by putting a weight on a past reverse pattern value that has already been stored (stored), for example, the current reverse pattern value is compared with the previous reverse pattern value such as the previous time or the previous time. Even when a large variation occurs in the pattern value, it is possible to suppress the influence of such variation on the calculated new reverse pattern value.

  In step S121, reverse pattern value storage processing is performed. In this process, the reverse pattern value calculated in step S119 is stored, that is, the reverse pattern value is stored in the storage position of the reverse pattern data area calculated in step S115 as the storage destination position. Thereby, for example, in the first cycle, each reverse pattern value d1 shown in FIG. 4C is stored, and in the next one cycle, each reverse pattern value d2 shown in FIG. 4D is stored. . Further, in the next one cycle, each reverse pattern value d3 shown in FIG. 4 (E) is stored, and after several tens of cycles, sufficient reverse pattern values d1 to dn are prepared, and the reverse pattern as shown in FIG. 4 (F) is obtained. The phase waveform Wmem is completed.

  The resulting anti-phase waveform Wmem shown in FIG. 4 (F) moves in the direction of time passage by the shift amount Fsft corresponding to the delay time Tdly, as shown in FIGS. 4 (C) to 4 (E). The reverse pattern values d1 to dn are stored at the storage position starting from the reference position of the alternate long and short dash line. Therefore, as shown in FIG. 4 (J), the reverse phase waveform Wmem stored from the earliest time (left edge of the paper shown in FIGS. 4 (G) to 4 (I)) as the starting point without such movement. Compared with ', the phase by the phase angle Fdly corresponding to the delay time Tdly does not advance. The output pattern (reverse pattern value) read from the reverse pattern data area of the memory 22 by the output pattern read processing described below does not become an inappropriate value.

  In step S123, a count-up process is performed. In this process, the counter value of the counter Ci is counted up every time the charge control process is executed, whereby the storage position of the reverse pattern value stored in the reverse pattern data area of the memory 22 is changed to the time. It is possible to proceed from the oldest time point to the latest time point (from the left end to the right end in FIG. 4).

  In step S125, a read destination position calculation process is performed. In this process, the position for reading the reverse pattern value stored in the reverse pattern data area of the memory 22 is calculated. In this process, from the storage position where the phase is advanced by an arbitrary phase angle with respect to the storage position in the reverse pattern data area of the memory 22 calculated in step S115, or from the storage position where the phase is delayed by an arbitrary phase angle, The read position is calculated so as to read the reverse pattern value. For example, if the phase angle that is advanced or delayed is converted into time, Tα is used, and the readout position is calculated by (1024 × (50 μS × Ci + Tdly + Tα) /16.7 mS) using the formula described in step S115. be able to. As a result, it is possible to absorb delays caused by hardware processing, software processing, and other factors, and it is possible to suppress a decrease in power factor associated therewith.

  In step S127, an output pattern reading process is performed, and in step S129, an output pattern output process is performed. That is, after reading the output pattern (reverse pattern value) from the reverse pattern data area of the memory 22 based on the read position calculated in step S125, as described above, this output pattern, the charging current Io, and the predetermined constant current Based on the value Icnt, an appropriate PWM signal Dpwm or PWM signal Upwm is generated and output to the step-down IGBT module 13 or the step-up IGBT module 15. Thereby, the step-down IGBT module 13 and the step-up IGBT module 15 can be controlled so that the charging current Io of the charging power supplied to the battery Batt becomes a predetermined constant current value Icnt.

  As described above, according to the charging apparatus 10 according to the present embodiment, the timer interrupt timing Ta for detecting the input voltage Vi of the full-wave rectified waveform Wrct by the input voltage detection unit 26 (input voltage acquisition process S102) is the zero cross timing Tb. If the timing Ta (1) is immediately after (S103; Yes), that is, if the reverse pattern value of the reverse phase waveform Wmem stored in the memory 22 is the first (first or first) reverse pattern value d1, zero crossing is performed. After calculating the delay time Tdly from the timing Tb to the immediately subsequent timing Ta (1) (delay time calculating process S109), the storage position (storage position) of the memory 22 that stores the reverse pattern value d1 at the immediately following timing Ta (1) is calculated. Then, the shift amount Fsft corresponding to the delay time Tdly is shifted in the time lapse direction (storage destination position calculation process S115). . In addition, the timing Ta of the timer interruption for detecting the input voltage Vi of the full-wave rectified waveform Wrct by the input voltage detection unit 26 (input voltage acquisition processing S102) is another timing Ta (2) after the immediate timing Ta (1). (S103; No), that is, when the reverse pattern value of the reverse phase waveform Wmem stored in the memory 22 is the reverse pattern values d2, d3, dn after the first (first) (second and later). The shift position Fsft corresponding to the delay time Tdly calculated at the immediately subsequent timing Ta (1) is used as the storage position (storage position) of the memory 22 that stores the reverse pattern values d2, d3, dn at the other timing Ta (2). The time is shifted in the direction of lapse of minutes (save destination position calculation processing S115).

  As a result, the memory 22 only corresponds to the delay time Tdly from the zero cross timing Tb to the timing Ta (1), that is, the delay time from the zero cross timing Tb until the input voltage Vi is detected by the input voltage detector 26. Is corrected by shifting the storage position of the first (first or first) reverse pattern value d1 to be stored in the time lapse direction (delay direction) and thereafter (second and subsequent) reverse pattern values d2, d3, and dn. In some cases, the correction is performed by shifting the time corresponding to the delayed time. Therefore, the storage position of the first (first) reverse pattern value d1 stored in the memory 22 is corrected without correcting such a time shift. Can be stored in the memory 22 in an appropriate reverse pattern value as compared with the case of storing at the oldest time. Therefore, in the charging device 10, since the pulse width modulation signals Dpwm and Upwm based on such an appropriate reverse pattern value can be obtained, it is possible to suppress disturbance in the power waveform due to temporal deviation.

  Further, according to the charging device 10 according to the present embodiment, the pulse width modulation signals Upwm and Dpwm are read out from the position where the phase is advanced or delayed by an arbitrary phase angle with respect to the storage position of the memory 22. It is generated based on the waveform information of Wmem. As a result, pulse width modulation signals Upwm and Dpwm based on a reverse phase waveform whose phase has been advanced or delayed by an arbitrary phase angle can be obtained. Therefore, in addition to suppressing the disturbance in the power waveform due to temporal deviation, the power factor Can also be suppressed.

  Furthermore, according to the charging device 10 according to the present embodiment, when the reverse pattern value is already stored in the storage position of the memory 22 when the reverse pattern value is stored in the memory 22, the reverse stored in the memory 22 is stored. An average value obtained by adding a new reverse pattern value to the pattern value obtained by predetermined weighting is stored in the storage position. As a result, a new reverse pattern value is stored with a weight placed on the reverse pattern value that has already been stored. For example, between the current reverse pattern value and the reverse pattern value stored in the memory 22 so far. Even if there is a large difference, the variation of the reverse pattern value can be suppressed as compared with the case where the current reverse pattern value is stored as it is.

  In the above-described embodiment, the three-phase AC power supply AC and the full-wave rectifier diode 12 are directly connected. However, for example, a three-phase transformer that steps down a three-phase 200 V AC voltage to 100 V may be interposed. In addition, although the configuration includes both the step-down IGBT module 13 and the step-up IGBT module 15, the charging device 10 is provided so as to have either one corresponding to the required specifications of the output voltage Vo and the output current Io. It may be configured. In any of these cases, the same operation and effect as the above-described embodiment can be obtained.

  In the above-described embodiment, the constant current control type charging device 10 that controls the charging voltage Vo so that the charging current Io of the charging power supplied to the battery Batt becomes a predetermined constant current value Icnt will be described as an example. However, even in a constant voltage control type charging device that controls the charging current Io so that the charging voltage Vo of the charging power supplied to the battery Batt becomes a predetermined constant voltage value Vcnt, the concept of current is expressed as voltage. By replacing the concept of voltage and the concept of voltage with the concept of current, the same operations and effects as the above-described embodiment can be obtained.

  Furthermore, in the above-described embodiment, as the storage destination position calculation process (S115), for example, the storage position on the memory 22 is obtained using the following equation (1024 × (50 μS × Ci + Tdly) /16.7 mS). Without being limited thereto, for example, immediately after the delay time calculation process (S109), the reference position set in the reverse pattern data area of the memory 22 based on the delay time Tdly calculated in step S109 and the one cycle time Tcyc, that is, A position shifted by an amount corresponding to the delay time Tdly may be obtained, and based on this, a reverse pattern value may be stored at predetermined intervals (gap) on the memory 22 as before. The “predetermined interval (gap)” in this case is obtained by dividing the number of reverse pattern values that can be stored in the reverse pattern data area by the number of reverse pattern values generated during one cycle (for example, 60 Hz). , 3 data (= 1024/333 times)).

  More specifically, for example, as shown in FIG. 4C, the storage (storage) destination of the reverse pattern value d1 immediately after the zero cross timing Tb (0) corresponds to the oldest time of the reverse pattern data area. A shift amount Fsft to be moved from the position to be moved (the left end of the reverse phase waveform Wmem shown in FIG. 4C) toward the latest time direction (the right end of the reverse phase waveform Wmem shown in FIG. 4C) is calculated. A reference position (the position of the alternate long and short dash line shown in FIG. 4C) is determined. For example, since the shift amount for one piece of data can be converted into a time by dividing one cycle time Tcyc by the storable number (1024 pieces) of the reverse pattern data area secured in the memory 22, the delay time Tdly Is divided by this time to obtain the number of data corresponding to the delay time Tdly. For example, when the frequency of the AC power is 60 Hz and the delay time Tdly is 50 microseconds, 3.08 (= 50 microseconds / (Tcyc / 1024)) (however, Tcyc = 16.667 milliseconds). . For this reason, the position moved in the latest time direction by three from the position corresponding to the oldest time in the reverse pattern data area is determined as the reference position.

  Further, the phase difference may be calculated as the shift amount. That is, based on the delay time Tdly calculated in step S109 and one cycle time Tcyc, the phase angle θdly (= Tdly × 360 / Tcyc) corresponding to the delay time Tdly is calculated, and this is used as the shift amount Fsft to determine the reference position. . In the case of the previous example (60 Hz, Tdly = 50 microseconds), the phase angle θdly is 1.08 degrees (= 50 microseconds × 360 degrees / Tcyc), which is the shift amount Fsft (phase angle θdly). In this case, by converting the interrupt time interval due to the timer interrupt into a phase angle, the phase angle corresponding to the product of the interrupt time interval and the counter value of the counter Ci plus the shift amount is set to the phase per data. By dividing by the angle (360 degrees / 1024), it is possible to calculate the storage position of the reverse pattern value for each predetermined interval (gap) based on this shift amount Fsft (phase angle θdly).

  A configuration in which a position shifted by an amount corresponding to such a delay time Tdly is obtained and a reverse pattern value is stored at predetermined intervals (gap) on the memory 22 on the basis of this position is as follows. After full-wave rectification, DC power converted by a DC-DC converter can be supplied to the storage battery, and the DC power is obtained by a pulse width modulation signal obtained based on a reverse phase waveform with respect to the full-wave rectification waveform of the AC power. A charging device for controlling a switching operation of a DC converter, wherein a zero-cross detection unit that detects a zero-cross timing of the input voltage waveform of the AC power; and a time period of a predetermined timing different from the zero-cross timing of the input voltage waveform A voltage detector for detecting a voltage of a full-wave rectified waveform; and the predetermined timing based on the voltage detected by the voltage detector A negative-phase corresponding value calculating unit that calculates a negative-phase corresponding value corresponding to the negative-phase waveform, and a plurality of the negative-phase corresponding value calculating units that are calculated for each time period as waveform information of the negative-phase waveform. A waveform storage unit that stores a negative phase corresponding value in a storage position positioned in time series order, and when the predetermined timing is a timing immediately after the zero cross timing, a lapse from the zero cross timing to the immediately following timing After calculating the time, the storage position of the waveform storage unit that stores the opposite-phase corresponding value at the immediately following timing is shifted in the elapsed time direction by an amount corresponding to the elapsed time, and the predetermined timing is greater than the immediately following timing. If the timing is later, the storage position of the waveform storage unit that stores the negative phase corresponding value at the predetermined timing Can be understood as a technical idea that the determined relative to the storage position after the shift immediately after timing ".

DESCRIPTION OF SYMBOLS 10 ... Charging device 12 ... Full wave rectifier diode 13 ... IGBT module for step-down (DC-DC converter)
15 ... IGBT module for boosting (DC-DC converter)
20 ... Control unit (computer)
21 ... CPU (reverse phase corresponding value calculation unit)
22: Memory (reverse phase corresponding value calculation unit, waveform storage unit)
25 ... Zero cross detection unit 26 ... Input voltage detection unit (voltage detection unit)
28 ... Output current detection unit 29 ... Output voltage detection unit AC ... 3-phase AC power source Batt ... Battery (storage battery)
Dpwm, Upwm ... PWM signal d1, d2, d3, dn ... Reverse pattern value Fsft ... Shift amount Icnt ... Predetermined constant current value Io ... Charging current Pz ... Zero cross point Sit ... Timer interrupt signal Szc ... Zero cross detection signal Ta ... Timer interrupt Timing (predetermined timing)
Ta (1): Immediate timing (immediate timing)
Ta (2) ... Other timing (timing after the timing immediately after)
Tb (0), Tb (-1), Tb (1), ... Zero cross timing Tcyc ... 1 cycle time Tdly ... Delay time (elapsed time from zero cross timing to immediately following timing)
Winv ... Reverse phase waveform (Reverse phase waveform)
Wrct ... Full-wave rectified waveform (Full-wave rectified waveform)
Wuv ... UV phase voltage waveform (AC power input voltage waveform)
Wvw ... VW phase voltage waveform (AC power input voltage waveform)
Wwu… WU phase voltage waveform (AC power input voltage waveform)
Vi: Input voltage (voltage of full-wave rectified waveform)
Vo ... Charging voltage Vuv ... UV phase voltage (AC power input voltage)
Vvw… VW phase voltage (AC power input voltage)
Vwu… WU phase voltage (AC power input voltage)
Ruv ... ripple width S102 (voltage detection step)
S109 (Step for calculating elapsed time, processing step immediately after zero crossing)
S115 (Step for determining position shifted in time direction, processing step immediately after zero crossing, processing step after zero crossing)
S119 (reverse phase corresponding value calculation step)
S121 (Reverse phase correspondence value storage step)
S127 (waveform information output step)
S129 (Waveform information output step)

Claims (5)

A pulse width modulation signal obtained based on a reverse phase waveform with respect to the full-wave rectified waveform of the AC power, which is configured to be able to supply the direct-current power converted by the DC-DC converter to the storage battery after full-wave rectification of the AC power. A charging device for controlling the switching operation of the DC-DC converter by:
A zero-cross detector that detects zero-cross timing of the input voltage waveform of the AC power;
A voltage detector that detects the voltage of the full-wave rectified waveform at a predetermined time period different from the zero-cross timing of the input voltage waveform;
A negative phase corresponding value calculating unit that calculates a negative phase corresponding value corresponding to the negative phase waveform at the predetermined timing based on the voltage detected by the voltage detecting unit;
A waveform storage unit that stores a plurality of the anti-phase correspondence values calculated by the anti-phase correspondence value calculation unit for each time period as waveform information of the anti-phase waveform in a storage position positioned in time series order. ,
When the predetermined timing is a timing immediately after the zero-cross timing, after calculating an elapsed time from the zero-cross timing to the immediate timing, the waveform storage unit stores the negative phase corresponding value at the immediate timing Shift the position by the amount corresponding to this elapsed time in the direction of time,
When the predetermined timing is later than the immediately following timing, the storage position of the waveform storage unit that stores the antiphase corresponding value at the predetermined timing corresponds to the elapsed time calculated at the immediately following timing. Therefore, the charging device is shifted in the direction of time passage.   The pulse width modulation signal is generated based on waveform information of the antiphase waveform read from a position where the phase is advanced or delayed by an arbitrary phase angle with respect to the storage position of the waveform storage unit. The charging device according to claim 1.   When storing the negative phase correspondence value in the waveform storage unit, if the negative phase correspondence value is already stored in the storage position of the waveform storage unit, the stored negative phase correspondence value is stored in the waveform storage unit. 3. The charging device according to claim 1, wherein an average value obtained by adding a new anti-phase correspondence value to a predetermined weight is stored in the storage position. A program for controlling a charging device configured to supply direct current power converted by a DC-DC converter to a storage battery after full-wave rectification of the alternating current power, and stores a waveform in a reverse phase waveform with respect to the full-wave rectified waveform of the alternating current power. A program for causing a computer to execute control for switching the DC-DC converter by a pulse width modulation signal obtained based on waveform information stored in a unit,
A voltage detection step of detecting the voltage of the full-wave rectified waveform at a time period of a predetermined timing different from the zero cross timing of the input voltage waveform of the AC power;
A negative phase corresponding value calculating step of calculating a negative phase corresponding value of the negative phase waveform at the predetermined timing based on the voltage detected by the voltage detecting step;
When the predetermined timing is a timing immediately after the zero cross timing, a step of calculating an elapsed time from the zero cross timing to the immediate timing and the negative phase corresponding value at the immediate timing as waveform information of the negative phase waveform A processing step immediately after zero crossing, including the step of determining the storage position in the storage position of the waveform storage unit positioned in chronological order by shifting the storage position to a position corresponding to the elapsed time, shifted in the time-elapsed direction,
When the predetermined timing is a timing after the immediately following timing, the storage position of the waveform storage unit that stores the negative phase corresponding value calculated by the negative phase corresponding value calculating step at the predetermined timing, After the zero cross, a processing step for determining the position shifted in the time elapsed direction by the amount corresponding to the elapsed time calculated by the step immediately after the zero cross;
A negative phase corresponding value storage step for storing the negative phase corresponding value calculated by the negative phase corresponding value calculating step at the storage position of the waveform storage unit determined by the processing step immediately after the zero cross or the processing step after the zero cross; ,
A waveform information output step for reading out the waveform information stored in the waveform storage unit and outputting the pulse width modulation signal to a pulse width modulation unit;
The program characterized by including.   In the waveform information output step, the waveform information is read from a position where the phase is advanced or delayed by an arbitrary phase angle with respect to the storage position of the waveform storage unit, and is output to the pulse width modulation signal. The program according to claim 4.

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