JP6487517B2 - Switching power supply - Google Patents

Description

  The present invention relates to a switching power supply device and a semiconductor device for controlling a switching element constituting the switching power supply device, and more particularly to a technique effective when applied to a switching power supply device including a PFC (Power Factor Correction) circuit.

  A switching power supply device that constitutes an AC / DC converter that converts an AC voltage into a DC voltage suppresses power factor deterioration and generation of harmonic noise caused by a phase difference between an input voltage and an input current supplied from the AC power supply. Therefore, PFC circuits are widely used.

  Conventionally, various switching power supply devices including a PFC circuit have been realized mainly by analog control. For example, Patent Literature 1 and Patent Literature 2 disclose the conventional technology of a switching power supply device including an analog-controlled PFC circuit.

  However, in recent years, various switching power supply circuits including PFC circuits are being replaced by control systems mainly using digital control because of demands for cost reduction and easy tuning. Specifically, a control unit for controlling on / off of a switching element (MOSFET or the like) for controlling a current flowing in a coil in a PFC circuit is changed from an analog IC (Integrated Circuit) having a conventional error amplifier to a microcontroller. (Hereinafter simply referred to as a microcomputer) and the like. For example, Patent Document 3 discloses a conventional technique of an AC / DC converter having a digital control type PFC circuit.

JP 2001-327166 A JP 2008-31355 A JP 2008-99440 A

  The control unit in the PFC circuit described above detects various voltages and currents in the PFC circuit, and generates a PWM (pulse width modulation) signal having a predetermined period based on the detection result. For example, in an analog control PFC circuit, a PWM signal having a desired duty ratio (pulse width) is generated based on an output voltage of an error amplifier and a predetermined periodic signal (triangular wave, sawtooth wave, etc.), and a digital control PFC In the circuit, for example, a PWM signal with a duty ratio corresponding to a setting condition of the CPU is generated by a PWM timer in a microcomputer. By controlling on / off of the switching element based on the PWM signal thus generated, a desired DC voltage is generated and the power factor is improved.

  As described above, when the switching element is switched on / off based on the PWM signal, a large current fluctuation occurs at the switching timing of the switching element due to a sharp rise or fall of the PWM signal, resulting in harmonics. Noise is generated. The generation of the harmonic noise causes a decrease in power factor, which is a cause of a decrease in power conversion efficiency in AC / DC conversion. In particular, as the power handled by the AC / DC converter increases, the power conversion efficiency decreases more significantly.

  Means for solving such problems will be described below, but other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  An outline of representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  That is, this switching power supply device controls the current flowing in the coil by turning on and off the switching element by PWM control, and obtains a desired DC voltage. In this switching power supply device, in the PWM on period for turning on the switching element by PWM control, the first period immediately after the start of the PWM on period has a period shorter than the PWM period and the pulse width is stepwise. Switching of the switching element is enabled by the first pulse signal that is increased. Further, in the switching power supply device, the switching element can be switched by the PWM signal based on the PWM control after the first period in the PWM ON period.

  The effects obtained by the representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  That is, according to this switching power supply device, harmonic noise can be reduced.

FIG. 1 is a block diagram illustrating a digital control switching power supply device as an AC / DC converter according to the first embodiment. FIG. 2 is a block diagram illustrating an internal configuration of the PWM timer unit according to the first embodiment. FIG. 3 illustrates a timing chart of various signals generated by the PWM timer unit 13A. FIG. 4 is a diagram illustrating a timing chart of the pulse signal VPLS_1 generated by the PWM timer unit according to the first embodiment. FIG. 5 is a diagram illustrating an example of the harmonic noise reduction effect of the switching power supply according to the first embodiment. FIG. 6 is a block diagram illustrating a digital control switching power supply device as an AC / DC converter according to the second embodiment. FIG. 7 is a block diagram illustrating an internal configuration of the PWM timer unit according to the second embodiment. FIG. 8 is a diagram illustrating a timing chart of the pulse signal VPLS_1 generated by the PWM timer unit according to the second embodiment.

1. First, an outline of a typical embodiment disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] (Switching power supply device that performs switching control by a pulse signal whose duty ratio increases stepwise in a cycle shorter than the PWM cycle immediately after the start of the PWM ON period)
The switching power supply (100, 200) according to the representative embodiment controls the current flowing through the coils (L1A, L2A) by turning on and off the switching elements (SW1, SW2) by PWM control, A DC voltage (VOUT) is obtained. The present switching power supply apparatus has a PWM period (TC) based on PWM control in a first period (T1) immediately after the start of the PWM on period in the PWM on period (TON) for turning on the switching element by PWM control. ), And the switching control of the switching element by the first pulse signal (VPLS_1) whose pulse width is increased stepwise is enabled. Further, the switching power supply device can perform switching control of the switching element by a PWM signal (VPWM) based on the PWM control after the first period has elapsed (T2, (T3)).

  According to this, at the start timing of the PWM ON period, the switching element is controlled so that the time for which the switching element is turned on is gradually increased. Therefore, as compared with the conventional control in which the switching element is simply turned on / off by the PWM signal. Thus, rapid current fluctuation of the coil at the start timing of the PWM on period can be suppressed. Thereby, the harmonic noise generated at the start timing of the PWM on period can be reduced.

[2] (The increasing rate of the pulse width of the first pulse signal is varied depending on the amount of noise)
In the switching power supply device (200) according to Item 1, an increase rate of the pulse width of the first pulse signal in the first period is reduced when switching noise superimposed on the DC voltage is larger than a reference value. And when the switching noise is smaller than a reference value, it is controlled to be large.

  According to this, the harmonic noise generated at the start timing of the PWM ON period by the PWM control can be further reduced.

[3] (The pulse width of the first pulse signal is determined based on the immediately preceding switching noise)
When the switching noise generated by switching the switching element by the first pulse signal output immediately before in the first period is greater than the reference value, The pulse width of the first pulse signal to be output is made smaller than a reference pulse width. In addition, when the switching noise is smaller than the reference value, the switching power supply device makes the pulse width of the first pulse signal to be output next larger than the reference pulse width.

  According to this, it is possible to easily realize the control for changing the increasing rate of the pulse width of the first pulse signal so as to reduce the switching noise.

[4] (The amount of noise is determined by the length of the period during which the output voltage is outside the predetermined range)
In the switching power supply device according to Item 2 or 3, the length of the period during which the DC voltage is out of the predetermined voltage range (W) is set as the magnitude of the switching noise.

  According to this, it becomes easy to measure the magnitude of the switching noise.

[5] (Switching is controlled by a pulse signal whose duty ratio increases stepwise in a cycle shorter than the PWM cycle immediately before the end of the PWM ON period)
In the switching power supply device according to any one of Items 1 to 4, the switching control of the switching element by the PWM signal is enabled in the second period (T2) after the elapse of the first period in the PWM ON period. In this switching power supply device, the third period (T3) from the end of the second period to the end of the PWM on period is a period shorter than the PWM period, and the pulse width is gradually reduced. The switching control of the switching element by the second pulse signal (VPLS) is enabled.

  According to this, at the end timing of the PWM on period by PWM control, the switching element is controlled so that the time for which the switching element is turned on is gradually reduced, so that the switching element is simply turned on / off by the PWM signal as in the prior art. Compared with the control to be performed, a rapid current fluctuation of the coil at the end timing of the PWM ON period can be suppressed. Thereby, harmonic noise generated at the end timing of the PWM on period can be reduced.

[6] (The reduction rate of the pulse width of the second pulse signal is variable depending on the amount of noise)
In the switching power supply device according to Item 5, the rate of decrease of the pulse width of the second pulse signal in the third period is controlled to be small when switching noise superimposed on the DC voltage is larger than a reference value, The switching noise is controlled so as to increase when the switching noise is smaller than a reference value.

  According to this, it is possible to further reduce the harmonic noise generated at the end timing of the PWM on period related to the PWM control.

[7] (The pulse width of the second pulse signal is determined based on the immediately preceding switching noise)
The switching power supply device according to Item 6 outputs next when the switching noise generated by switching the switching element by the second pulse signal output immediately before in the third period is larger than a reference value. The pulse width of the second pulse signal to be set is made larger than a reference pulse width. Further, when the switching noise is smaller than the reference value, the switching power supply device makes the pulse width of the second pulse signal to be output next smaller than the reference pulse width.

  According to this, it is possible to easily realize control for changing the reduction rate of the pulse width of the second pulse signal so that the switching noise is reduced.

[8] (Semiconductor device that outputs a pulse signal whose duty ratio increases stepwise in a cycle shorter than the PWM cycle immediately after the start of the PWM ON period)
A semiconductor device (5, 7) according to a typical embodiment is a switching power supply (100, 200) for converting an input voltage (VIN) into a target DC voltage (VOUT) and improving a power factor. This is a semiconductor device for controlling on / off of the switching elements (SW1, SW2). This semiconductor device has timer sections (13A, 13B, 23A, 23B) that generate control signals (VGD1, VGD2) for controlling on / off of the switching elements. The semiconductor device further turns on the switching element so that the output voltage is equal to the target DC voltage and the phase difference between the input voltage and the input current input to the switching power supply device is small. A data processing control unit (10) that calculates a PWM ON period (TON) and controls the timer unit based on the calculation result. The data processing control unit controls the timer unit so that a first period (T1) immediately after the start of the calculated PWM on period is greater than a PWM signal (VPWM) corresponding to the calculated PWM on period. The first pulse signal (VPLS_1) having a short cycle and a gradually increasing pulse width can be output as the control signal. Furthermore, the data processing control unit enables the PWM signal to be output as the control signal after the first period has elapsed.

  According to this, at the start timing of the PWM ON period of the switching element by the PWM control, a control signal is generated so that the time for which the switching element is turned on gradually increases, so that the switching element is controlled as in the conventional case. Compared to a semiconductor device that simply generates a PWM signal for this purpose, it is possible to suppress rapid current fluctuations in the coil at the start timing of the PWM on period. As a result, harmonic noise generated at the start timing of the PWM ON period can be reduced.

[9] (Immediately before the end of the PWM ON period, the switching element is driven by a pulse signal whose duty ratio decreases stepwise in a cycle shorter than the PWM cycle)
In the semiconductor device according to item 8, the data processing control unit controls the timer unit so that the cycle is shorter than the PWM signal and stepwise in the second period immediately before the end of the calculated PWM ON period. The second pulse signal (VPLS_2) having a small pulse width can be output as the control signal.

  According to this, at the end timing of the PWM on period of the switching element by PWM control, the drive signal is generated so that the time for which the switching element is turned on gradually decreases, so the PWM signal is simply generated as in the conventional case. Compared to a semiconductor device that performs this, it is possible to suppress a rapid current fluctuation of the coil at the end timing of the PWM ON period. As a result, harmonic noise generated at the end timing of the PWM ON period can be reduced.

[10] (Count the period during which the output voltage is outside the predetermined range, and determine the pulse width of the next first pulse signal based on the count value)
The semiconductor device (7) according to Item 8 or 9 includes a comparator unit (142) for determining whether or not the DC voltage is out of a predetermined voltage range (W), and the DC voltage is out of the predetermined voltage range. And a time measuring unit (143) for measuring a period of time. The data processing control unit outputs the next time when the timing result by the timing unit when the switching element is switched by the first pulse signal output immediately before in the first period is larger than a reference value. The pulse width of the first pulse signal to be made is made smaller than a reference pulse width. Further, the data processing control unit makes the pulse width of the first pulse signal to be output next larger than the reference pulse width when the time measurement result is smaller than the reference value.

  According to this, it becomes possible to further reduce the harmonic noise generated at the start timing of the PWM ON period.

[11] (Count the period during which the output voltage is outside the predetermined range, and determine the pulse width of the next second pulse signal based on the count value)
In the semiconductor device according to Item 10, the data processing control unit has a time measurement result by the time measuring unit when the switching element is switched by the second pulse signal output immediately before in the second period is larger than a reference value. In this case, the pulse width of the second pulse signal to be output next is set larger than the reference pulse width. The data processing control unit makes the pulse width of the second pulse signal to be output next smaller than the reference pulse width when the time measurement result is smaller than the reference value.

  According to this, it is possible to further reduce the harmonic noise generated at the end timing of the PWM ON period.

[12] (The basic PWM signal and the first and second pulse signals are switched and output according to the period)
In the semiconductor device (7) according to Item 11, the timer unit (23A, 23B) includes a first signal generation unit (130) that generates the PWM signal according to the PWM on period calculated by the data processing control unit. And a second signal generator (136) for generating the first pulse signal and the second pulse signal. The timer unit further outputs the first pulse signal generated by the second signal generation unit during the first period, and the second pulse signal generated by the second signal generation unit during the second period. And a signal selection unit (140) for outputting the PWM signal generated by the first signal generation unit in a period other than the first period and the second period.

  According to this, it becomes easy to generate a control signal in which the duty ratio changes in a period shorter than the PWM period only in the first and last periods in the PWM on period.

[13] (AC / DC converter)
The AC / DC converter (100, 200) according to the representative embodiment includes a rectifier circuit (3) that rectifies and outputs an alternating voltage (VAC). The AC / DC converter further inputs the voltage (VIN) rectified by the rectifier circuit, and controls the current flowing through the coils (L1A, L2A) by the switching elements (SW1, SW2). A voltage converter circuit (3) for converting the voltage into a target DC voltage (VTGT) and outputting the voltage is provided. The AC / DC converter further includes a control unit (5, 7). The control unit is configured so that the output voltage (VOUT) of the voltage converter circuit is equal to the target DC voltage and the phase difference between the input voltage (VIN) and the input current (IIN) of the voltage converter circuit is small. A PWM on period (TON) for turning on the switching element is calculated. The control unit generates control signals (VGD1, VGD2) for controlling on / off of the switching element based on the calculation result of the PWM on period. The controller further has a shorter period and a stepwise larger pulse width in the first period (T1) immediately after the start of the PWM on period than the PWM signal (VPWM) corresponding to the calculated PWM on period. The first pulse signal (VPLS_1) can be output as the control signal. In addition, the control unit can output the PWM signal as the control signal after the first period has elapsed.

  According to this, at the start timing of the PWM ON period of the AC / DC converter, the switching element is controlled so that the ON time is gradually increased. Compared with the control to turn off, the rapid current fluctuation of the coil at the start timing of the PWM on period can be suppressed. Thereby, the harmonic noise generated at the start timing of the PWM ON period of the AC / DC converter can be reduced.

[14] (Pulse width of the first pulse signal is determined based on switching noise generated immediately before)
In the AC / DC converter (200) according to Item 13, the control unit (7) causes the switching noise generated by switching the switching element with the first pulse signal output immediately before in the first period. If it is larger than the reference value, the pulse width of the first pulse signal to be output next is made smaller than the reference pulse width. When the switching noise is smaller than the reference value, the control unit makes the pulse width of the first pulse signal to be output next larger than the reference pulse width.

  According to this, it becomes possible to further reduce the harmonic noise generated at the start timing of the PWM ON period.

[15] (Just before the end of the PWM ON period, switching control is performed by a pulse signal whose duty ratio increases stepwise in a cycle shorter than the PWM cycle)
In the AC / DC converter according to Item 13 or 14, the controller (5, 7) has a period shorter than the PWM signal and stepwise in the second period (T3) immediately before the end of the calculated PWM ON period. The second pulse signal (VPLS_2) having a smaller pulse width can be output as the control signal.

  According to this, at the end timing of the PWM on period of the switching element by PWM control, the drive signal is generated so that the time for which the switching element is turned on gradually decreases, so the PWM signal is simply generated as in the conventional case. Compared to a semiconductor device that performs this, it is possible to suppress a rapid current fluctuation of the coil at the end timing of the PWM ON period. As a result, harmonic noise generated at the end timing of the PWM ON period can be reduced.

[16] (The pulse width of the second pulse signal is determined based on the switching noise generated immediately before).
In the AC / DC converter according to item 15, the control unit (6) causes the switching noise generated by switching the switching element by the second pulse signal output immediately before in the second period to be greater than a reference value. Is larger, the pulse width of the second pulse signal to be output next is made larger than the reference pulse width. When the switching noise is smaller than the reference value, the control unit makes the pulse width of the second pulse signal to be output next smaller than the reference pulse width.

  According to this, it is possible to further reduce the harmonic noise generated at the end timing of the PWM ON period.

[17] (Microcontroller)
The AC / DC converter according to any one of Items 13 to 16, wherein the control unit includes a microcontroller.

2. Details of Embodiments Embodiments will be further described in detail. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments for carrying out the invention, and the repetitive description thereof will be omitted.

<< Embodiment 1 >>
FIG. 1 is a block diagram illustrating a digital control switching power supply device as an AC / DC converter according to the first embodiment. The switching power supply device 100 shown in the figure converts the AC power supplied from the AC power supply 20 into a desired DC voltage and improves the power factor by turning on and off the switching elements SW1 and SW2 by PWM control. . The switching power supply apparatus 100 can be applied to, for example, an air conditioner or an automobile as part of a motor control system.

  As described above, when the switching element is simply switched on and off by PWM control, a large current fluctuation occurs when the switching element is switched on and off, and harmonic noise is generated. Therefore, in the present switching power supply device 100, the pulse width changes in a stepwise manner with a period shorter than the PWM period between the first and last short periods of the PWM on period for turning on the switching elements SW1 and SW2 by PWM control. The harmonic noise is reduced by controlling the switching elements SW1 and SW2 by the pulse signal to be transmitted. Hereinafter, a specific configuration of the switching power supply apparatus 100 will be described in detail.

  As shown in FIG. 1, the switching power supply device 100 includes a rectifying unit 2 and a PFC circuit 1.

  The AC power supply 20 is not particularly limited, but is a commercial AC power supply, and outputs a 50 Hz or 60 Hz sine wave AC voltage VAC (for example, 100 V). The rectifying unit 2 rectifies and outputs the AC voltage VAC supplied from the AC power supply 20. Specifically, the rectification unit 2 includes a diode bridge circuit 21 and a capacitor CRCT. The diode bridge circuit 21 is a full-wave rectifier circuit configured by combining a plurality of diodes, for example. The positive voltage rectified by the diode bridge circuit 21 is smoothed by the capacitor CRCT.

  The PFC circuit 1 is a critical mode PFC circuit, and includes, for example, a voltage converter circuit 3, an output voltage detection unit 4, and a control unit 5.

  The voltage converter circuit 3 receives the voltage rectified by the rectifier circuit 2 and controls the current flowing in the coil by the switching element, thereby converting the input voltage VIN into a target DC voltage and outputting the same. The voltage converter circuit 3 is not particularly limited, and is configured to realize an interleaved step-up type PFC circuit in which a coil, a switching element, etc. are doubled. For example, the coils L1A, L1B, L2A, L2B, switching elements SW1, SW2, rectifying elements D1, D2, and an output capacitor COUT are included. For example, the voltage converter circuit 3 converts a rectified voltage of 100 V into a DC voltage of 300 V.

  Hereinafter, the input voltage of the voltage converter circuit 3 is denoted by reference sign VIN, the output voltage is denoted by reference sign VOUT, and the input current of the voltage converter circuit 3 is denoted by reference sign INN. Reference numerals representing voltages such as reference VIN and VOUT also represent nodes to which the voltages are supplied.

  Coil L1A has one end connected to node VIN and the other end connected to node NSW1. The coil L1B is a circuit element for detecting a current flowing through the coil L1A, and is arranged so as to be magnetically coupled to the coil L1A. Coil L2A has one end connected to node VIN and the other end connected to node NSW2. The coil L2B is a circuit element for detecting a current flowing through the coil L2A, and is arranged so as to be magnetically coupled to the coil L2A.

  Switching element SW1 is provided between node NSW1 and the ground node, and controls the current flowing through coil L1A. Switching element SW2 is provided between node NSW2 and the ground node, and controls a current flowing through coil L2A. Although not particularly limited, the switching elements SW1 and SW2 are, for example, high-voltage MOS transistors, IGBTs (Insulated Gate Bipolar Transistors), or the like. In the figure, as an example, a case where the switching elements SW1 and SW2 are realized by N-channel MOS transistors is illustrated.

  The switching element SW1 is controlled to be turned on / off by the control voltage VGD1 output from the control unit 5. The switching element SW <b> 2 is controlled to be turned on / off by the control voltage VGD <b> 2 output from the control unit 5. For example, the switching element SW1 is turned on when the control voltage VGD1 is at the first logic level (for example, high level), and the control voltage VGD1 is at the second logic level (for example, low level). If off. The same applies to the switching element SW2. 1 illustrates a configuration in which the switching elements SW1 and SW2 perform direct switching control using the control voltages VGD1 and VGD2 from the control unit 5, but a gate driver is provided between the switching elements SW1 and SW2 and the control unit 5. A circuit may be provided and the switching elements SW1 and SW2 may be controlled to be switched through the gate driver circuit.

  The rectifying element D1 is provided between the node NSW1 and the output node VOUT, and forms a current path between the node NSW1 and the output node VOUT while the switching element SW1 is off. The rectifying element D2 is provided between the node NSW2 and the output node VOUT, and forms a current path between the node NSW2 and the output node VOUT while the switching element SW2 is off. The rectifying elements D1 and D2 are diodes, for example, and have an anode connected to the node NSW1 (NSW2) side and a cathode connected to the output node VOUT side. The output capacitor COUT is connected between the output node VOUT and the ground node, and stabilizes the output voltage VOUT.

  The output voltage detection unit 4 detects the output voltage VOUT and supplies the detection voltage VSEN to the control unit 5. The output voltage detection unit 4 includes, for example, resistors R1 and R2 connected in series between the output node VOUT and a ground node, and detects a voltage obtained by dividing the output voltage VOUT by the resistors R1 and R2. Let it be VSEN. By setting the resistance ratio R1 / R2 to, for example, “1/59”, the detection voltage VSEN of “5V” is generated from the output voltage VOUT of “300V”. In the figure, the output voltage detection unit 4 is provided outside the control unit 5, but may be included inside the control unit 5.

  The control unit 5 generates the control voltages VGD1 and VGD2 so that the output voltage VOUT of the voltage converter circuit 3 is equal to the target voltage and the phase difference between the input voltage VIN and the input current IIN is small. The control unit 5 is not particularly limited, and is configured by a semiconductor integrated circuit formed on a single semiconductor substrate such as single crystal silicon by a known CMOS integrated circuit manufacturing technique. The control unit 5 is a program processing device such as a microcomputer (MCU) or a DSP (Digital Signal Processor), for example. The control unit 5 may be realized with a one-chip configuration as described above, or may be realized with a multi-chip configuration, and the configuration is not particularly limited.

  The control unit 5 includes, for example, A / D conversion units (ADC) 14 to 16, a data processing control unit (CNT) 10, PWM timer units (PWM_TMR) 13A and 13B, an external interface circuit (not shown), and the like. The

  The A / D conversion unit 16 samples the detection voltage VSEN in accordance with, for example, the A / D conversion start signal output from the PWM timer units 13A and 13B, and performs the sampling according to the conditions set by the data processing control unit 10 The conversion result DVS is generated by converting the voltage into a digital signal. Thereby, information of the output voltage VOUT is obtained.

  The A / D conversion unit 14 samples the current flowing through the coil L1B magnetically coupled to the coil L1A, for example, in accordance with the A / D conversion start signal output from the PWM timer unit 13A, and the data processing control unit 10 The conversion result DIS1 is generated by converting the sampled current into a digital signal in accordance with the condition set by (1). Thereby, information on the current flowing through the coil L1A is obtained. Similarly, the A / D conversion unit 15 samples the current flowing through the coil L1B, for example, in accordance with the A / D conversion start signal output from the PWM timer unit 13B, and converts it into a digital signal, thereby converting the conversion result DIS2 into a digital signal. Generate. Thereby, information on the current flowing through the coil L2A is obtained.

  The data processing control unit 10 performs various arithmetic processes and performs overall control of each functional unit in the control unit 5. The data processing control unit 10 includes, for example, a CPU 11 and a memory unit (MRY) 12. The memory unit 12 includes a nonvolatile memory (for example, a ROM (Read Only Memory) and a flash memory) in which a program is stored, a volatile memory (RAM: Random Access Memory), various registers, and the like. Various arithmetic processes and controls are realized by the CPU 11 executing a program stored in a RAM or the like.

  The data processing control unit 10 executes arithmetic processing for determining the pulse widths of the control signals VGD1 and VGD2 based on the conversion results DIS1, DIS2, and DVS by the A / D conversion units 14 to 16, and based on the processing results By controlling the PWM timer unit 13, desired control signals VGD1 and VGD2 are generated. Specifically, the data processing control unit 10 performs PWM for turning on the switching elements SW1 and SW2 so that the output voltage VOUT is equal to the target voltage VTGT and the phase difference between the input voltage VIN and the input current IIN is small. The ON period is calculated, and a control condition corresponding to the calculation result is set in the PWM timer unit 13.

  More specifically, the data processing control unit 10 calculates the difference between the current value of the output voltage VOUT and the target voltage VTGT based on the conversion result DVS by the A / D conversion unit 16 so that the difference becomes smaller. Next, a PWM on period TON for turning on the switch elements SW1 and SW2 is determined. For example, when the output voltage VOUT is smaller than the target voltage VTGT, the output voltage VOUT is increased by extending the PWM ON period TON. On the other hand, when the output voltage VOUT is higher than the target voltage VTGT, the output voltage VOUT is lowered by shortening the PWM ON period of the switch elements SW1 and SW2. Further, the data processing control unit 10 monitors the current flowing through the coil L1A based on the conversion result DIS1 by the A / D conversion unit 14, detects the timing when the current becomes zero (0), and sets the switching element SW1. Decide when to turn on. Similarly, the current flowing through the coil L2A is monitored based on the conversion result DIS2 by the A / D conversion unit 15, the timing at which the current becomes zero is detected, and the timing at which the switching element SW2 is turned on is determined.

  The data processing control unit 10 sets a control condition for generating a desired PWM signal based on the PWM ON period TON calculated as described above and the timing for turning on the switch elements SW1 and SW2 determined as described above. Determine and set the PWM timer unit 13A, 13B.

  The PWM timer unit 13A generates the control signal VGD1 in accordance with the control conditions set by the data processing control unit 10. Similarly, the PWM timer unit 13B generates the control signal VGD2 in accordance with the control conditions set by the data processing control unit 10.

  In the present embodiment, the PWM timer unit 13A and the PWM timer unit 13B have the same circuit configuration, and each operation (counting operation by a counter, updating various registers, etc.) is shifted by a half cycle (phase is different). (timing shifted by π). As a result, the generated control signal VGD1 and control signal VGD2 are signals whose phases are shifted by “π”.

  FIG. 2 illustrates an internal configuration of the PWM timer unit 13A. Since the PWM timer 13B has the same configuration as the PWM timer 13A as described above, the PWM timer 13A will be typically described in detail.

  As shown in the figure, the PWM timer unit 13A includes a basic PWM signal generation unit 130, a pulse signal generation unit 136, and a selection unit (SEL) 140 as functional units for generating the control signal VGD1.

  The basic PWM signal generation unit 130 generates a pulse width modulated signal VPWM according to the control conditions set by the data processing control unit 10. The basic PWM signal generation unit 130 includes, for example, a signal generation circuit (PWM_GEN) 131, a compare register (REG_CMPA) 132, a compare register (REG_CMPB) 133, a PWM cycle setting register (REG_TC) 135, and a counter circuit (CNTR_A) 134. .

  In the PWM cycle setting register 135, the data processing control unit 10 sets a specified value of the PWM cycle TC based on the PWM control. Although not particularly limited, the PWM cycle TC is set to several tens μs to several hundreds μs, and the basic PWM signal VPWM is, for example, a signal of several kHz to several tens kHz.

  The counter circuit 134 performs a count operation for counting the input reference clock signal according to the set value of the PWM cycle setting register 135. The start and stop of the counting operation by the counter circuit 134 is controlled by an instruction from the data processing control unit 10. The counter circuit 134 operates, for example, as an up / down counter that repeatedly executes up-counting and down-counting at a cycle TC (several tens μs to several hundreds μs) designated by the PWM cycle setting register 135, and the count value 30 is It becomes a triangular wave with a constant period. Note that the reference clock signal to be counted by the counter circuit 134 is supplied from, for example, a clock signal generation unit (not shown) provided inside or outside the control unit 5, and the oscillation frequency is, for example, several MHz to several tens MHz. The

  In the compare register 132, a designated value of the PWM on period TON calculated by the data processing control unit 10, that is, a designated value of the duty ratio of the basic PWM signal VPWM is set. The compare register 133 is set with a designated value representing the length of periods T1 and T3 during which a pulse signal VPLS described later is output. The set value of the compare register 132 is expressed as “CA”, and the set value of the compare register 133 is expressed as “CB”. Note that CA <CB.

  The signal generation circuit 131 generates the basic PWM signal VPWM by comparing the count value 30 of the counter circuit 134 with the set values of the various registers 132, 133, and 134, and also selects the selection signal VSEL and the A / D converter 14. , 16 output an A / D conversion start signal.

  Specifically, the signal generation circuit 131 sets the basic PWM signal VPWM to, for example, a low level during a period in which the count value 30 of the counter circuit 134 is smaller than the set value CA of the compare register 132, and the count value 30 is set to the compare register 132. For example, the basic PWM signal VPWM is set to a high level during a period larger than the value CA. As a result, a basic PWM signal VPWM having a duty ratio (PWM on period TON) corresponding to the set value CA of the compare register 132 is generated. Further, the signal generation circuit 131 asserts the selection signal VSEL (for example, high level) during a period in which the count value 30 of the counter circuit 134 is larger than the set value CA of the compare register 132 and smaller than the set value CB of the compare register 133. The selection signal VSEL is negated (for example, at a low level) during a period when the count value 30 is larger than the set value CB of the compare register 133.

  The pulse signal generation unit 136 generates a pulse signal VPLS whose cycle is shorter than the PWM cycle TC and whose pulse width changes stepwise in accordance with the control conditions set by the data processing control unit 10. The pulse signal generation unit 136 includes, for example, a counter circuit (CNTR_B) 137, a pulse width setting register (REG_PW) 138, and a signal generation circuit (PLS_GEN) 139.

  The counter circuit 137 performs a counting operation for counting the input reference clock signal according to the setting condition by the data processing control unit 10. The counter circuit 137 operates, for example, as an up counter that repeats an operation of counting up to a designated value again when the count value is counted up to a designated value set by the data processing control unit 10, and the count value is a period. Becomes a certain sawtooth shape. The count cycle of the counter circuit 137 is made smaller than the count cycle (PWM cycle TC) of the counter circuit 134 described above. Note that the reference clock signal to be counted by the counter circuit 137 is supplied from a clock signal generation unit (not shown), similarly to the counter circuit 134.

  A value indicating the pulse width (duty ratio) of the pulse signal VPLS is set in the pulse width setting register 138. Hereinafter, the setting value of the pulse width setting register 138 is expressed as “CC”.

  The signal generation circuit 139 generates the pulse signal VPLS by comparing the count value 40 of the counter circuit 137 with the setting value CC of the pulse width setting register 138. For example, the signal generation circuit 139 sets the pulse signal VPLS to, for example, a high level when the count value 40 of the counter circuit 137 is smaller than the set value CC, and the pulse signal VPLS when the count value 40 is larger than the set value CC. For example, a low level is set. Thereby, a pulse signal VPLS having a duty ratio corresponding to the set value CC of the pulse width setting register 138 is generated. Although the details will be described later, the set value CC of the pulse width setting register 138 is sequentially updated by the data processing control unit 10 every count cycle of the counter circuit 137.

  The selection unit 140 selects either the basic PWM signal VPWM or the pulse signal VPLS based on the selection signal VSEL, and outputs it as the control signal VGD1. For example, the pulse signal VPLS is output as the control signal VGD1 while the selection signal VSEL is asserted, and the basic PWM signal VPWM is output as the control signal VGD1 while the selection signal VSEL is negated.

  FIG. 3 illustrates a timing chart of various signals generated by the PWM timer unit 13A. The figure shows a control signal VGD1 for two cycles. In the first cycle, the duty ratio of the basic PWM signal (PWM on period TON based on PWM control) is 70%, and in the next cycle, the duty ratio of the basic PWM signal is 65%. ing.

  As shown in the figure, at time t0, the data processing control unit 10 gives an instruction to start the count operation to the counter circuit 134, so that the counter circuit 134 starts up-counting. When the count value 30 of the counter circuit 134 matches the set value CA of the compare register 132 (for example, a value corresponding to the duty ratio of 70% of the basic PWM signal VPWM) at time t1, the signal generation circuit 131 generates the basic PWM signal VPWM. While switching from the low level to the high level, the selection signal VSEL is asserted (for example, set to the high level).

  Next, when the count value 30 of the counter circuit 134 matches the set value CB of the compare register 133 at time t2, the signal generation circuit 131 negates the selection signal VSEL while holding the high level of the basic PWM signal VPWM. (For example, low level). Although not particularly limited, this figure illustrates the case where the set value CB of the compare register 133 is set to a duty ratio 72% larger than the set value CA (duty ratio 70%). The set value CB of the compare register 133 can be variously changed according to the assumed magnitude of switching noise. For example, when the switching noise is assumed to be large, the set value CB is set to a value corresponding to a duty ratio of 73%, for example. When the switching noise is assumed to be small, the set value CB is set to a duty ratio, for example. It is also possible to set a value corresponding to 71%.

  On the other hand, in a period T1 from time t1 to time t2, the pulse signal generation unit 136 generates the pulse signal VPLS.

  Specifically, in the period T1, the counter circuit 137 repeatedly executes the up-count operation, and the set value of the pulse width setting register 138 is updated every count cycle. For example, the set value CC of the pulse width setting register 138 is updated every count cycle so that the duty ratio of the pulse signal VPLS increases stepwise as 10%, 30%, 50%, 70%,. Thereby, in the period T1, a pulse signal VPLS_1 having a cycle shorter than the PWM cycle TC and having a pulse width increased stepwise is generated.

  Here, a specific method for generating the pulse signal VPLS will be described in detail with reference to FIG.

  FIG. 4 is a diagram illustrating a timing chart of the pulse signal VPLS_1 generated by the PWM timer unit according to the first embodiment. This figure illustrates the update timing of various signals and registers in a period T1 from time t1 to time t2 in FIG. In the figure, it is assumed that a value indicating a duty ratio of 10% is set as an initial value as the setting value CC of the pulse width setting register 138.

  As shown in the figure, at time t1, the data processing control unit 10 instructs the counter circuit 137 to start the count operation, whereby the counter circuit 137 starts the count operation. At this time, since the count value 40 of the counter circuit 137 is lower than the set value CC of the pulse width setting register 138, the pulse signal VPLS becomes high level. Thereafter, when the count value 40 of the counter circuit 137 coincides with the set value CC of the pulse width setting register 138 at time t11, the pulse signal VPLS is switched to the low level. Thereafter, when the count value of the counter circuit 137 reaches the maximum value at time t13, the count value of the counter circuit 137 is cleared, and the counter circuit 137 starts counting up again. As a result, during the period from time t1 to time t3, the pulse signal VPLS_1 having the same cycle as the count cycle of the counter circuit 137 and a duty ratio of 10% is generated.

  The set value CC of the pulse width setting register 138 is updated, for example, at the timing when the count value of the counter circuit 137 is cleared. As a method of updating the set value CC of the pulse width setting register 138, for example, the following two control methods are conceivable. As the first control method, for example, the data processing control unit 10 directly changes the set value CC of the pulse width setting register 138 in synchronization with the timing t13 when the count value of the counter circuit 137 is reset. . As a second control method, for example, a buffer register (not shown) capable of temporarily storing data is provided in the pulse signal generation unit 136, and a value is stored in the pulse width setting register 138 via the buffer register. Is a method of setting. For example, first, at a predetermined timing before the count value of the counter circuit 137 is reset, the data processing control unit 10 sets a specified value of the pulse width (for example, a duty ratio of 30%) in the buffer register. Then, at the timing t13 when the count value 40 is reset, the value of the buffer register is loaded into the pulse width setting register 138. As the predetermined timing, for example, a timing at which the count value 40 of the counter circuit 137 coincides with an intermediate value (a count value corresponding to 50% duty of the pulse signal VPLS_1) CM can be cited as an example. According to the control method as described above, it is possible to change the duty ratio of each cycle of the pulse signal VPLS.

  When the count value 40 is reset at time t13 and the setting value of the pulse width setting register 138 is updated, the pulse signal VPLS is switched to the high level again. Thereafter, when the count value 40 of the counter circuit 137 coincides with the set value CC (duty ratio 30%) of the pulse width setting register 138 at time t14, the pulse signal VPLS is switched to the low level. As a result, a pulse signal VPLS_1 having a duty ratio of 30% is generated. When the count value 40 is reset at time t15, the set value CC of the pulse width setting register 138 is updated from the duty ratio 30% to the duty 50%. The subsequent operation is the same as the operation from time t13 to t16.

  By controlling the pulse signal generation unit 136 as described above, in the period T1 immediately after the start of the PWM on period TC in the PWM period TC, the period is shorter than the PWM period TC, and the pulse width increases stepwise. A pulse signal VPLS_1 can be generated.

  Here, returning to FIG. 3 again, the control after time t3 will be described.

  When the count value 30 of the counter circuit 134 reaches the maximum value CMAX at time t3, the counter circuit 134 switches from the up count to the down count. Thereafter, when the count value 30 of the counter circuit 134 again matches the set value CB of the compare register 133 at time t4, the signal generation circuit 131 reasserts the selection signal VSEL while holding the high level of the basic PWM signal VPWM. Yes (set to high level). When the count value 30 of the counter circuit 134 matches the set value CA (= a1) of the compare register 132 at time t5, the signal generation circuit 131 switches the basic PWM signal VPWM from the high level to the low level and also selects the selection signal VSEL. Is negated (low level).

  On the other hand, in a period T3 from time t4 to time t5, the pulse signal VPLS is generated. Specifically, when the data processing control unit 10 gives an instruction to start counting to the counter circuit 137 at time t4, the counter circuit 137 starts the counting operation. Further, the data processing control unit 10 sets a value (for example, a duty ratio of 70%) indicating the pulse width in the pulse width setting register 138 at time t4. The signal generation circuit 139 compares the count value 40 of the counter circuit 137 with the setting value CC of the pulse width setting register 138, and during the period when the count value 40 is smaller than the setting value CC of the pulse width setting register 138, the pulse signal VPLS. Is set to a high level, for example, and the pulse signal VPLS is set to a low level, for example, during a period when the count value 40 is greater than the set value CC. As a result, the pulse signal VPLS corresponding to the set value CC (for example, duty ratio 70%) of the pulse width setting register 138 is generated. Thereafter, the counter circuit 137 repeats the count operation until the timing (time t5) when the count value 30 of the counter circuit 134 matches the set value CA (= b1) of the compare register 132. Meanwhile, the data processing control unit 10 repeats updating the set value CC of the pulse width setting register 138 at a timing according to the count cycle of the counter circuit 137. For example, the value indicating the pulse width of the pulse signal VPLS is updated for each count cycle so that the duty ratio of the pulse signal VPLS decreases stepwise to 70%, 50%, 30%, 10%,. As a result, a pulse signal VPLS_2 is generated in a period T3 from time t4 to time t5, which has a period shorter than the PWM period TC and whose pulse width is reduced stepwise. A specific method for generating the pulse signal VPLS_2 is the same as the method for generating the pulse signal VPLS_1 described above (FIG. 4).

  The selection unit 140 outputs the pulse signal VPLS as the control signal VGD1 in the period T1 from the time t1 to the time t2 and the period T3 from the time t4 to the time t5 when the selection signal VSEL is asserted, and the selection signal VSEL is negated. In a period T2 from the time t2 to t4, the basic PWM signal VPWM is output as the control signal VGD1.

  When the count value 30 reaches the minimum value CMIN (= 0) at time t6, the generation of the control signal VGD1 for one cycle is completed. Then, when the counter circuit 134 starts counting again, generation of the control signal VGD1 of the next one cycle is started. The control after time t6 is the same as the control contents from time t1 to t5 except that the set values of the compare registers 132 and 133 are set to the duty ratios 65% and 66% of the basic PWM signal VPWM. It is.

  By controlling the PWM timer unit 13A as described above, in the first and last short periods T1 and T3 of the PWM on period TON, a pulse signal whose period is shorter than the PWM period TC and whose pulse width changes stepwise. VPLS_1 and VPLS_2 are output as the control signal VGD1, and the basic PWM signal VPWM is output as the control signal VGD1 in the other period T2 in the PWM ON period TON. Note that the PWM timer unit 13B has the same control content as the PWM timer unit 13A except that the control timing is different. Therefore, the control signal VGD2 is also generated in the same manner as the control signal VGD1.

  FIG. 5 illustrates a switching noise reduction effect by the switching power supply apparatus 100 according to the present embodiment. (A) of the figure shows a waveform example of the output voltage VOUT when the switching element is simply driven by the PWM signal as in the conventional switching power supply apparatus. (B) of the same figure shows the waveform example of the output voltage VOUT of the switching power supply apparatus 100 which concerns on this Embodiment.

  As shown in the figure, according to the switching power supply according to the present embodiment, switching is performed by a pulse signal VPLS in which the pulse width is switched stepwise between the beginning and end of the PWM on period TON in the PWM cycle TC. By driving the element, switching noise can be reduced, and harmonic noise in the switching power supply device can be reduced.

<< Embodiment 2 >>
FIG. 6 is a block diagram illustrating a digital control switching power supply device as an AC / DC converter according to the second embodiment.

  The switching power supply apparatus 200 shown in the figure has a function of changing the pulse width of the pulse signal VPLS according to the magnitude of noise superimposed on the output voltage VOUT, and is in phase with the switching power supply apparatus 100 according to the first embodiment. Different. In addition, the same code | symbol is attached | subjected to the component same as the switching power supply device 100 among the components of the switching power supply device 200, and the detailed description is abbreviate | omitted.

  In the PFC circuit 6 shown in FIG. 6, the PWM timers 23 </ b> A and 23 </ b> B in the control unit 7 further have a function of monitoring the detection voltage VSEN and detecting noise superimposed on the output voltage VOUT of the switching power supply device 200. In the present embodiment, the PWM timer unit 23A and the PWM timer unit 23B have the same circuit configuration, and the PWM timer unit 23A will be described in detail as a representative.

  FIG. 7 is a block diagram illustrating an internal configuration of the PWM timer unit 23A. As shown in the figure, the PWM timer unit 23A is a functional unit for generating the control signal VGD1, in addition to the basic PWM signal generation unit 130, the pulse signal generation unit 136, and the selection unit (SEL) 140, as well as noise. A detection unit 141 is provided.

  The noise detection unit 141 includes a window comparator unit (WND_CMP) 142, a counter circuit (CNTR_C) 143, and a noise detection result register (REG_NS) 144.

  The window comparator unit 142 determines whether or not the detection voltage VSEN is within a predetermined voltage range W, and outputs a determination result signal VNS. Specifically, the window comparator unit 142 determines that noise is not superimposed on the output voltage VOUT when the detection voltage VSEN is within the predetermined voltage range W, and the determination result that the signal level becomes, for example, a low level The signal VNS is output. On the other hand, when the detection voltage VSEN is out of the predetermined voltage range W, it is determined that noise is superimposed on the output voltage VOUT, and a determination result signal VNS whose signal level becomes, for example, a high level is output. The voltage range W is, for example, a voltage range centered on a target voltage (for example, 300 V) of the output voltage VOUT of the switching power supply apparatus 200, and serves as an index for determining whether noise is superimposed on the output voltage VOUT. The voltage range W can be changed in a programmable manner, and is determined, for example, based on a variation amount of the output voltage VOUT allowed in a system to which the switching power supply device 200 is applied.

  The counter circuit 143 measures a period in which noise is superimposed on the output voltage VOUT. Specifically, the counter circuit 143 starts up-counting when a determination result indicating that noise is superimposed is output from the window comparator unit 142 (for example, when the determination result signal VNS becomes high level), When a determination result indicating that is not superimposed is output (for example, when the determination result signal VNS becomes low level), the up-count is stopped and the count value is cleared. As a result, the magnitude of the noise can be expressed by the length of the period in which the noise is superimposed on the output voltage VOUT.

  The noise detection result register (REG_NS) 144 stores the count value of the counter 143. For example, when the determination result signal VNS of the window comparator unit 142 is switched from the high level to the low level as a trigger, the count value of the counter circuit 143 at that time is written into the noise detection result register 144.

  The data processing control unit 10 sets basic control conditions in the basic PWM signal generation unit 130 so that the output voltage VOUT is equal to the target voltage VTGT and the phase difference between the input voltage VIN and the input current IIN is small. A PWM signal VPWM is generated. The control contents for the basic PWM signal generation unit 130 are the same as those in the first embodiment. For example, the basic PWM signal VPWM and the selection signal VSEL are generated at the same timing as in FIG.

  In addition, the data processing control unit 10 controls the pulse signal generation unit 136 to generate the pulse signal VPLS. Specifically, the data processing control unit 10 generates a desired pulse signal VPLS by determining the pulse width of the pulse signal VPLS based on the magnitude of noise detected by the noise detection unit 141. Hereinafter, specific control contents for determining the pulse width of the pulse signal VPLS will be described in detail with reference to FIG.

  FIG. 8 is a diagram illustrating a timing chart of the pulse signal VPLS_1 according to the second embodiment. As described above, since the control method for generating the basic PMW signal VPWM and the selection signal VSEL is the same as that in the first embodiment, the PWM cycle TC and the PWM on period TON are the same as those in FIG. On the other hand, the update timing of various signals and registers in the period T1 from time t1 to time t2 and the period T3 from time t3 to t4 in FIG. Therefore, FIG. 8 representatively shows the update timing of various signals and registers in the period T1 according to the second embodiment. In the figure, it is assumed that a value indicating a duty ratio of 10% is set as an initial value as the setting value CC of the pulse width setting register 138.

  As shown in FIG. 8, at time t <b> 1, the count operation of the counter circuit 137 is started when the data processing control unit 10 gives an instruction to start the count operation to the counter circuit 137 as in the first embodiment. The pulse signal VPLS_1 (control signal VGD1) becomes high level. As a result, the switching element SW1 is turned on, and the current flowing through the coil L1 and the switching element SW1 varies, so that the output voltage VOUT varies. When the output voltage VOUT deviates from the voltage range W at time t21 due to the voltage fluctuation, the window comparator unit 142 of the noise detection unit 141 sets the detection result signal VNS to the high level, and the counter circuit 143 starts measuring time. Thereafter, when the output voltage VOUT falls within the voltage range W at time t22, the window comparator unit 142 switches the detection result signal VNS from the high level to the low level. As a result, the counter circuit 143 stops timing and the count value of the counter circuit 143 is written to the noise detection result register 144. At this time, the ground comparator unit 142 further issues an interrupt request INT to the data processing control unit 10 (CPU 11). The issued interrupt request INT is input to an interrupt control circuit (not shown), and when the interrupt control circuit outputs an interrupt signal to the data processing control unit 10, the data processing control unit 10 executes interrupt processing. Specifically, the data processing control unit 10 takes in the data of the noise detection result register 144 (noise amount superimposed on the output voltage VOUT) in the periods T1 and T3, and based on the data, the pulse width (duty) of the pulse signal VPLS_1. Ratio) is set in the pulse width setting register 138. More specifically, the data processing control unit 10 determines the pulse width of the next pulse signal VPLS so that the increase rate of the pulse width of the pulse signal VPLS_1 is small if the amount of noise is larger than the assumed value, and the noise If the amount is smaller than the assumed value, the pulse width of the next pulse signal VPLS is determined so that the increasing rate of the pulse width of the pulse signal VPLS_1 is increased.

  For example, in the period T1, the reference pulse width of the pulse signal VPLS_1 to be output for the first time is “10%”, the reference pulse width of the pulse signal VPLS_1 to be output for the second time is “30%”, and should be output for the third time. Assume that the reference pulse width of the pulse signal VPLS_1 is initially set so that the pulse width increases stepwise, such as “50%”,.

  In this case, for example, if the data processing control unit 10 determines that the amount of noise when the switching element SW1 is driven by the pulse signal VPLS_1 (duty ratio 10%) output for the first time in the period T1 is larger than the reference value. A value (for example, 28%) smaller than the reference pulse width “30%” initially set as the pulse width of the pulse signal VPLS_1 to be output for the second time is set in the pulse width setting register 138. Thereby, the period during which the switching element SW1 is turned on by the second pulse signal VPLS_1 is shortened, so that the amount of current change when the switching element is on can be reduced. On the other hand, when the data processing control unit 10 determines that the noise amount of the first pulse signal VPLS_1 is smaller than the reference value, the data processing control unit 10 uses the reference pulse width “30%” initially set as the pulse width of the second pulse signal VPLS_1. A larger value (for example, 32%) is set in the pulse width setting register 138. Thereby, it is possible to approach normal PWM control while suppressing the amount of noise. The timing for updating the pulse width setting register 138 is not particularly limited as long as it is a timing before the next one-cycle pulse signal VPLS_1 is generated. FIG. 8 illustrates a case where the pulse width setting register 138 is updated at a timing t23 and a value indicating the duty “28%” is set.

  After that, at timing t24, generation of a pulse signal VPLS_1 (duty ratio 28%) of the next one cycle is started. As a result, the switching element SW1 is turned on, and the current flowing through the coil L1 and the switching element SW1 varies, so that the output voltage VOUT also varies. If the output voltage VOUT deviates from the voltage range W at time t25 due to the voltage fluctuation, the window comparator unit 142 of the noise detection unit 141 sets the detection result signal VNS to high level, and the counter circuit 143 starts measuring time. Thereafter, when the output voltage VOUT falls within the voltage range W at time t26, the window comparator unit 142 switches the detection result signal VNS from the high level to the low level. As a result, the counter circuit 143 stops timing and the count value of the counter circuit 143 is written to the noise detection result register 144. At this time, similarly to the above-described timing t22, the interrupt request INT is issued, and the data processing control unit 10 starts calculating the pulse width (duty ratio) of the pulse signal VPLS_1. For example, if the amount of noise when the switching element SW1 is driven by the pulse signal VPLS_1 (duty ratio 28%) output for the second time in the period T1 is larger than the reference value, the data processing control unit 10 performs the third time. A value (for example, 48%) smaller than the reference pulse width “50%” initially set as the pulse width of the pulse signal VPLS_1 is set in the pulse width setting register 138. On the other hand, when the amount of noise is smaller than the reference value, a value (for example, 52%) larger than the initially set reference pulse width “50%” is set in the pulse width setting register 138. FIG. 8 illustrates a case where the pulse width setting register 138 is updated at a timing t27 and a value indicating the duty ratio “52%” is set. Thereby, after timing t28, a signal having a duty ratio of “52%” is output as the third pulse signal VPLS_1 in the period T1. The subsequent processing is the same as the processing content from timing t24 to t28, and a pulse signal VPLS_1 having a pulse width determined based on the amount of noise is generated until time t2.

  As described above, when control is performed to increase the pulse width of the control signals VGD1, VGD2 (pulse signal VPLS) stepwise in the first period T1 of the PWM ON period TON in the PWM cycle TC, the rate of increase of the pulse width Is changed according to the magnitude of the actually measured switching noise, so that the switching noise can be further reduced.

  Also in the last period T2 of the PWM on period TON, the pulse signal VPLS_2 is generated by the same control method as in the period T1 described above. For example, in the period T2, if the amount of noise detected by the noise detection unit 141 is larger than the assumed value, the pulse width of the next pulse signal VPLS is calculated so that the rate of decrease of the pulse width of the pulse signal VPLS_2 is reduced, If the amount of noise is smaller than the assumed value, the pulse width of the next pulse signal VPLS_2 is calculated so that the reduction rate of the pulse width of the pulse signal VPLS_2 is increased. For example, in the period T2, the reference pulse width of the pulse signal VPLS_2 to be output the first time is “70%”, the reference pulse width of the pulse signal VPLS_2 to be output the second time is “50%”, and should be output the third time Consider a case where the reference pulse width of the pulse signal VPLS_2 is initially set so that the pulse width decreases stepwise, such as “30%”,.

  For example, when the data processing control unit 10 determines that the amount of noise when the switching element SW1 is driven by the pulse signal VPLS_2 (duty ratio 70%) output for the first time in the period T2 is larger than the reference value, the second time A value (for example, 51%) larger than the reference pulse width “50%” that is initially set as the pulse width of the pulse signal VPLS_2 to be output to is set in the pulse width setting register 138. Thereby, the period during which the switching element SW1 is turned off by the second pulse signal VPLS_2 is shortened, so that the amount of current change when the switching element is off can be reduced. On the other hand, when the data processing control unit 10 determines that the noise amount of the first pulse signal VPLS_2 is smaller than the reference value, the data processing control unit 10 sets a value (for example, 49%) smaller than the reference pulse width “50%” to the pulse width setting register 138. Set to. According to this, it is possible to approach normal PWM control while suppressing the amount of noise.

  Thus, also in the last period T2 of the PWM ON period TON in the PWM cycle TC, the pulse width reduction rate of the control signals VGD1 and VGD2 (pulse signal VPLS_2) is changed according to the magnitude of the actually measured switching noise. Thus, switching noise can be further reduced.

  As described above, according to the switching power supply apparatus 200 according to the second embodiment, the switching element is generated by the pulse signal VPLS whose pulse width changes stepwise in the first period T1 and the last period T3 of the PWM on period TON in the PWM cycle TC. The switching noise can be further reduced by changing the amount of increase and decrease of the pulse width according to the actually measured noise amount, and further reduce the harmonic noise in the switching power supply device. Is possible.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, in the switching power supply apparatuses 100 and 200 according to the first and second embodiments, the pulse signal VPLS whose pulse width changes stepwise in the first period T1 and the last period T3 of the PWM on period TON in the PWM cycle TC. Although the configuration for performing the switching control is illustrated, only one of the periods T1 and T3 may be configured to perform the switching control by the pulse signal VPLS. For example, the first period T1 may be driven by the pulse signal VPLS, and the intermediate period T2 and the last period T3 may be driven by the basic PWM signal VPWM. Further, the first period T1 and the intermediate period T2 may be configured to be switched by the basic PWM signal VPWM and to be switched by the pulse signal VPLS only for the last period T3.

  The pulse signals VPLS_1 and VPLS_2 may be any signals as long as the period during which the switching elements SW1 and SW2 are turned on in the periods T1 and T3 can be changed in a stepwise manner. It is not limited to changing signals. For example, the switching noise can be reduced even if the pulse signals VPLS_1 and VPLS_2 are signals whose pulse period is increased or decreased in stages.

  In the second embodiment, the configuration in which the pulse widths of the pulse signals VPLS_1 and VPLS_2 are updated for each pulse in accordance with the amount of noise is illustrated. It may be. Specifically, in FIG. 3, the second time based on the noise amount (for example, the maximum value or average value of the noise amount during the same period) measured in the period T1 between the times t1 and t2 in the first PWM cycle TC. The pulse width of the pulse signal PLS_1 output during the period from time t7 to t8 in the PWM cycle TC is determined. For example, when the duty ratio of the pulse signal PLS_1 in the period T1 from time t1 to t2 is changed to 10%, 30%, and 50%, if the amount of noise in the period T1 is larger than the assumed value, the time t7 to t8 Control may be performed such that the duty ratio of the pulse signal PLS_1 in the period is 5%, 15%, 35%, 55%, and the number of pulses output during the same period is increased by decreasing the duty ratio. According to this, the switching noise generated in the PWM ON period TON in the second PWM cycle TC can be reduced.

  In the first and second embodiments, the case where the PFC circuits 1 and 6 are critical mode PFC circuits is illustrated, but a continuous mode PFC circuit may be used. Further, the voltage converter circuit 3 constituting the PFC circuits 1 and 6 may be a synchronous rectification type, and the rectifier elements D1 and D2 may be constituted by synchronous rectification MOS transistors.

  The present invention can be widely applied not only to AC / DC converters that convert AC voltage to DC voltage, but also to various switching power supply devices that constitute DC / DC converters.

100 Switching power supply (AC / DC converter)
20 AC power supply VAC AC voltage 1 PFC circuit 2 Rectifier 21 Diode bridge circuit CRCT capacity VIN Input voltage IIN Input current 3 Voltage converter circuit L1A, L1B, L2A, L2B Coil SW1, SW2 Switching element D1, D2 Rectifier COUT Output capacity NSW1 , NSW2 Node 4 Output voltage detection unit R1, R2 Resistance VOUT Output voltage VSEL Detection voltage 5 Control unit 10 Data processing control unit 11 CPU
DESCRIPTION OF SYMBOLS 12 Memory part 13A, 13B PWM timer part 14-16 A / D conversion part DIS1, DIS2, DVS Conversion result VGD1, VGD2 Control signal 130 Basic PWM signal generation part 131 Signal generation circuit 132, 133 Compare register 134 Counter circuit 135 PWM cycle Setting register 136 Pulse signal generation unit 137 Counter circuit 138 Pulse width setting register 139 Signal generation circuit (PLS_GEN)
140 selection unit VPWM basic PWM signal VPLS, VPLS_1, VPLS_2 pulse signal VSEL selection signal 30, 40 count value 200 switching power supply (AC / DC converter)
6 PFC circuit 7 Control unit 23A, 23B PWM timer unit 141 Noise detection unit 142 Window comparator unit 143 Counter circuit 144 Noise detection result register VNS detection result signal INT Interrupt request

Claims (3)

A switching power supply device that obtains a desired DC voltage by controlling a current flowing in a coil by turning on and off a switching element by PWM control,
The switching power supply device
In the PWM on period for turning on the switching element by the PWM control,
A first period immediately after the start of the PWM on-period;
A second period after the elapse of the first period; and
A third period from the elapse of the second period to the end of the PWM on period;
A first register storing first information for determining
The switching power supply device
A first pulse signal whose pulse width is increased stepwise in a period shorter than a PWM period based on the PWM control in the first period based on the first information stored in the first register. The switching element is switched by
In the second period based on the first information stored in the first register, the switching element is switched by a PWM signal,
In the third period based on the first information stored in the first register, the switching element is driven by a second pulse signal having a period shorter than the PWM period and gradually reducing the pulse width. Switching
Switching power supply. In claim 1,
The rate of increase in the pulse width of the first pulse signal in the first period is:
The switching noise superimposed on the DC voltage is controlled to be small when it is larger than a reference value,
The switching noise is controlled to be large when it is smaller than a reference value.
Switching power supply. In claim 1,
The rate of decrease in the pulse width of the second pulse signal in the third period is:
The switching noise superimposed on the DC voltage is controlled to be small when it is larger than a reference value,
The switching noise is controlled to be large when it is smaller than a reference value.
Switching power supply.

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