JP2013153190A5

JP2013153190A5 - Method for manufacturing compound semiconductor device

Info

Publication number: JP2013153190A5
Application number: JP2013053256A
Authority: JP
Filing date: 2013-03-15
Publication date: 2013-11-21
Anticipated expiration: 2027-06-20

Description

本発明は、化合物半導体装置の製造方法に関する。 The present invention relates to a method of manufacturing a compound semiconductor equipment.

本発明の目的は、ゲート電極の近傍での耐圧が高められた化合物半導体装置の製造方法を提供することにある。 An object of the present invention is to provide a manufacturing method of a compound semiconductor equipment breakdown voltage is increased in the vicinity of the gate electrode.

本発明の一観点によれば、基板の上に、化合物半導体よりなる電子走行層と、前記電子走行層上に化合物半導体よりなる電子供給層とを形成する工程と、前記電子供給層の上に、ソース電極とドレイン電極を互いに間隔をおいて形成する工程と、前記電子供給層の上に感光性ポリシラザンの第１の塗布膜を形成する工程と、前記第１の塗布膜をジャスト露光時間よりも長い露光時間、露光し、現像することにより、前記電子供給層の上に開口を備えた保護絶縁膜を形成する工程と、前記開口内の前記電子供給層上にゲート電極を形成する工程とを有する化合物半導体装置の製造方法が提供される。 According to one aspect of the present invention, on a substrate, and the electron transit layer made of a compound semiconductor, comprising the steps of: compound form forming an electron supply layer made of semiconductor on the electron transit layer, on the electron supply layer A step of forming a source electrode and a drain electrode spaced apart from each other, a step of forming a first coating film of photosensitive polysilazane on the electron supply layer, and a first exposure time for the first coating film. A step of forming a protective insulating film having an opening on the electron supply layer by exposing and developing for a longer exposure time, and a step of forming a gate electrode on the electron supply layer in the opening A method for manufacturing a compound semiconductor device is provided.

なお、上記の化合物半導体装置の製造方法においては、前記電子供給層を形成した後であって、前記ソース電極と前記ドレイン電極とを形成する前において、前記電子供給層の上に感光性ポリシラザンの第２の塗布膜を形成する工程と、前記第２の塗布膜の一部領域を除く他領域に光を当てることにより、該一部領域の前記第２の塗布膜を未露光にしつつ、前記他領域の前記第２の塗布膜を露光する工程と、前記露光の後、前記第２の塗布膜を吸湿させることにより、前記一部領域と前記他領域のそれぞれに対応した高誘電率部と低誘電率部とを備えたゲート絶縁膜を形成する工程とを有してもよい。更に、前記ゲート電極は、前記ゲート絶縁膜の前記高誘電率部上に形成されて、前記ゲート電極の下面の面積が、前記ゲート絶縁膜の前記高誘電率部の面積よりも広くてもよい。 In the above method for manufacturing a compound semiconductor device, after forming the electron supply layer and before forming the source electrode and the drain electrode , photosensitive polysilazane is formed on the electron supply layer. forming a second coating film, by shed light on other regions excluding a partial region of the second coating film, while the unexposed said second coating film of the partial region, the a step of exposing the second coating film of another region, after the exposure, by moisture absorption of the second coating layer, the part region and the high dielectric constant portion corresponding to each of the other region A step of forming a gate insulating film provided with a low dielectric constant portion . Furthermore, the gate electrode may be formed on the high dielectric constant portion of the gate insulating film, and an area of a lower surface of the gate electrode may be larger than an area of the high dielectric constant portion of the gate insulating film. .

Claims

On the substrate, and the electron transit layer made of a compound semiconductor, comprising the steps that form the electron supply layer made of compound semiconductor in the electron transit layer,
Forming a source electrode and a drain electrode spaced apart from each other on the electron supply layer;
Forming a photosensitive polysilazane first coating film on the electron supply layer;
Forming a protective insulating film having an opening on the electron supply layer by exposing and developing the first coating film for an exposure time longer than a just exposure time ; and
Forming a gate electrode on the electron supply layer in the opening;
A method for producing a compound semiconductor device, comprising:

After forming the electron supply layer and before forming the source electrode and the drain electrode,
Forming a second coating film of photosensitive polysilazane on the electron supply layer;
Exposing the second coating film in the other region while exposing the second coating film in the partial region to be unexposed by irradiating light to the other region except the partial region of the second coating film And a process of
Forming a gate insulating film having a high dielectric constant portion and a low dielectric constant portion corresponding to each of the partial region and the other region by absorbing the second coating film after the exposure; When,
The method of manufacturing a compound semiconductor device according to claim 1, wherein:

The gate electrode is formed on the high dielectric constant portion of the gate insulating film,
3. The method of manufacturing a compound semiconductor device according to claim 2, wherein an area of the lower surface of the gate electrode is larger than an area of the high dielectric constant portion of the gate insulating film.

4. The method of manufacturing a compound semiconductor device according to claim 1, wherein the exposure time is set to 20 to 30% longer than the just exposure time. 5.