JP2013149682A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving the withstand-voltage performance.SOLUTION: A semiconductor device 10 includes a semiconductor substrate 25 having an element region 12 and a termination region 14 surrounding the circumference of the element region. In the termination region 14, a plurality of guard rings 16, 18, and 20 going around the external side of the element region are formed. The side surfaces of the outer peripheral sides of the guard rings 16, 18, and 20 have a shape such that the depth from the top surface of the semiconductor substrate gradually shallows toward the outer peripheral side from the inner peripheral side. In the guard rings 16, 18, and 20, the angle of the corner formed by the side surface of the outer peripheral side and the bottom surface is larger than the angle of the corner formed by the side surface of the inner peripheral side and the bottom surface.

Description

  The technology disclosed in this specification relates to a semiconductor device and a manufacturing method thereof.

  In order to increase the breakdown voltage of a semiconductor device, a semiconductor device in which a guard ring is formed in a termination region surrounding the periphery of an element region (active region) has been developed. For example, in the semiconductor device of Patent Document 1, a plurality of guard rings that are gradually shallower from the element region side to the counter element region side are formed in the termination region of the semiconductor substrate. As a result, the depletion layer is smoothly formed from the element region side toward the non-element region side. As a result, the electric field concentration is relaxed, and the high breakdown voltage of the semiconductor device is achieved. Here, the “non-element region side” means a region that is not an element region (that is, a non-element region). For example, when an element region is formed at the center of a semiconductor substrate and a non-element region is formed outside the element region, the “element region side” means the center side of the semiconductor substrate, and the “anti-element region side” "Means the outer peripheral side of the semiconductor substrate.

JP 2004-95659 A

  In a semiconductor device in which a guard ring is formed in the termination region, the shape (angle, curvature) of the corner of the guard ring on the side opposite to the element side (that is, the corner formed by the bottom surface of the guard ring and the side surface on the side opposite to the element) Etc.), the curvature of the boundary surface between the depletion layer and the drift layer formed at the time of reverse bias (hereinafter sometimes referred to as the boundary surface of the depletion layer) changes, which affects the breakdown voltage performance. In particular, when the depletion layer extends and the depletion layer extends to the guard ring located closest to the anti-element region, the shape of the corner on the anti-element region side of the guard ring located closest to the anti-element region (angle) , Curvature, etc.) greatly affects the breakdown voltage of the semiconductor device. Therefore, in order to improve the breakdown voltage, the boundary of the depletion layer formed at the time of reverse bias is made appropriate by making the shape (angle, curvature, etc.) of the corner of the guard ring located closest to the anti-element region closer to the anti-element region. It is necessary to reduce the curvature of the surface.

  In the semiconductor device of Patent Document 1, in order to reduce the curvature of the boundary surface of the depletion layer, it is necessary to reduce the curvature of the corner of the guard ring on the side opposite to the element region. However, in this semiconductor device, the corner of the guard ring on the element region side and the corner of the counter element region side have the same curvature. For this reason, if it is going to make the curvature of the corner | angular part by the side of the anti-element region of a guard ring small, the curvature of the corner | angular part by the side of the element region of a guard ring will also become small. As a result, the guard ring expands in both directions on the counter element region side and the element region side. Therefore, the distance between the adjacent guard rings is shortened, which may reduce the breakdown voltage of the semiconductor device.

  It is an object of the present specification to provide a semiconductor device capable of improving withstand voltage performance and a manufacturing method for manufacturing the semiconductor device.

  A semiconductor device disclosed in this specification includes a semiconductor substrate having an element region and a termination region surrounding the periphery of the element region. In the termination region, a plurality of guard rings that make a round around the outside of the element region are formed. Among the plurality of guard rings, the guard ring positioned at least on the side opposite to the element region includes a first side surface on the element region side, a bottom surface having one end connected to the lower end of the first side surface, and a lower end on the other end of the bottom surface. Has a second side surface on the side opposite to the element region. The second side surface has a shape in which the depth from the upper surface of the semiconductor substrate gradually decreases from the element region side toward the non-element region side. The guard ring located closest to the anti-element region has an angle of a corner formed by the second side surface and the bottom surface in a cross section perpendicular to the direction in which the guard ring extends when the semiconductor substrate is viewed in plan view. It is larger than the angle of the corner formed by one side surface and the bottom surface.

  Here, the “angle of the corner” formed by the side surface and the bottom surface means an angle of 180 ° or less of the angle of the corner portion formed by the side surface and the bottom surface in the cross section. When the side surface and / or the bottom surface are curved in the cross section, the curve is approximated by a straight line, and the angle of the corner obtained using the approximated straight line is the “corner angle”. For example, when the side surface is curved while the bottom surface is a straight line in the cross section, the side surface is approximated by a straight line, and the angle formed by the approximated straight line and the bottom surface is the “corner angle”. Various known methods can be used for approximating the curve with a straight line. For example, a straight line connecting one end and the other end of the curve may be used as the approximate straight line.

  In this semiconductor device, the second side surface of the guard ring located closest to the anti-element region is shaped so that the depth from the upper surface of the semiconductor substrate gradually decreases from the element region side toward the anti-element region side. . In addition, the corner of the guard ring on the side opposite to the element region (the corner formed by the second side surface and the bottom surface) is increased, and the corner on the element region side (the corner formed by the first side surface and the bottom surface) is increased. The angle is small. Therefore, since the angle of the corner of the guard ring located closest to the anti-element region is large, the curvature of the boundary surface of the depletion layer to be formed can be reduced. On the other hand, since the angle of the corner portion on the element region side of the guard ring is small, it is possible to suppress the distance from the adjacent guard ring from being shortened. By these, the pressure resistance performance can be improved.

  In the semiconductor device described above, the first side surface has a shape that is orthogonal to the upper surface of the semiconductor substrate or that the depth from the upper surface of the semiconductor substrate gradually decreases from the element region side toward the non-element region side. It may be. According to such a structure, it can suppress suitably that the distance between adjacent guard rings becomes short.

  In the above semiconductor device, the semiconductor substrate may be formed of silicon carbide.

  The present specification also discloses a novel manufacturing method for manufacturing the semiconductor device. That is, in the manufacturing method disclosed in this specification, a mask layer forming step of forming a mask layer on the upper surface of the semiconductor substrate, and after forming the mask layer, impurity ions are applied to the semiconductor substrate from above the semiconductor substrate through the mask layer. The step of injecting is provided. In the mask layer forming step, the thickness of the mask layer corresponding to the guard ring is formed according to the shape of the guard ring, and the thickness of the mask layer is thin in the portion where the guard ring is deeply formed. The mask layer is formed thick in the portion where the film is formed shallowly.

  In this manufacturing method, the thickness of the mask layer corresponding to the guard ring corresponds to the shape of the guard ring. That is, since the mask layer is thin at the portion where the guard ring is formed deeply, impurity ions are implanted to a deep position of the semiconductor substrate. On the other hand, since the mask layer is thick in the portion where the guard ring is shallow, impurity ions are implanted into a shallow position of the semiconductor substrate. Therefore, a guard ring having a desired shape can be formed without performing ion implantation a plurality of times. Note that in the portion where the guard ring is formed most deeply, the mask layer may not be formed (that is, the thickness of the mask layer is 0), or the mask layer may be formed.

  In the above manufacturing method, the mask layer forming step is located on the most anti-element region side, a step of forming a mask layer on the entire upper surface of the semiconductor substrate, a step of forming a resist film on the entire upper surface of the mask layer, and Exposing the resist film through a photomask having at least an opening corresponding to the guard ring; developing the exposed resist film; and dry etching the mask layer using the developed resist film as an etching mask. You may have. In the step of exposing the resist film, it is preferable to irradiate light obliquely from the non-element region side to the element region side.

  According to such a configuration, since the light is irradiated obliquely from the non-element region side toward the element region side, the resist film is exposed by the obliquely irradiated light, and the obliquely exposed portion is removed by development. The Therefore, a mask layer corresponding to the shape of the second side surface of the guard ring can be formed by subsequent dry etching.

The top view of the semiconductor device concerning a present Example. II-II sectional view taken on the line of FIG. FIG. 2 is a schematic diagram illustrating a shape of a depletion layer in a termination region of the semiconductor device in FIG. 1. FIG. 6 illustrates an example of a method for manufacturing a semiconductor device according to an embodiment (part 1). FIG. 6 illustrates an example of a method for manufacturing a semiconductor device according to an embodiment (part 2). FIG. 6 is a diagram for explaining in detail each step from the state of FIG. 4 to the state of FIG. 5 (part 1); FIG. 6 is a diagram for explaining in detail each step from the state of FIG. 4 to the state of FIG. 5 (part 2). FIG. 6 is a diagram for explaining in detail each step from the state of FIG. 4 to the state of FIG. 5 (part 3); FIG. 6 is a diagram for explaining in detail each step from the state of FIG. 4 to the state of FIG. 5 (part 4); FIG. 5 is a diagram for explaining in detail each step from the state of FIG. 4 to the state of FIG. 5 (No. 5). 3A and 3B illustrate an example of a method for manufacturing a semiconductor device according to the embodiment (part 3). FIG. 13 is a diagram for explaining in detail each step from the state of FIG. 5 to the state of FIG. 11 (part 1); FIG. 12 is a diagram for explaining in detail each step from the state of FIG. 5 to the state of FIG. 11 (part 2); FIG. 13 is a diagram for explaining in detail each step from the state of FIG. 5 to the state of FIG. 11 (part 3); FIG. 14 is a diagram for explaining in detail each step from the state of FIG. 5 to the state of FIG. 11 (part 4); FIG. 4 illustrates an example of a method for manufacturing a semiconductor device according to an embodiment (No. 4). FIG. 6 illustrates another example of a method for manufacturing a semiconductor device according to an embodiment (part 1). FIG. 6 is a second diagram illustrating another example of the method for manufacturing the semiconductor device according to the embodiment. FIG. 6 illustrates another example of the semiconductor device manufacturing method according to the embodiment (No. 3). FIG. 6 is a diagram for explaining another example of the method for manufacturing a semiconductor device according to the embodiment (No. 4). FIG. 5 illustrates another example of the semiconductor device manufacturing method according to the embodiment (No. 5). FIG. 6 illustrates another example of the semiconductor device manufacturing method according to the embodiment (No. 6). FIG. 7 is a view for explaining another example of the method for manufacturing a semiconductor device according to the embodiment (No. 7).

  The main features of the embodiments described below are listed. The technical elements described below are independent technical elements and exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Absent.

(Characteristic 1) The guard ring located closest to the anti-element region has a corner portion formed by the second side surface and the bottom surface in a cross section perpendicular to the direction in which the guard ring extends when the semiconductor substrate is viewed in plan view. , Larger than the angle of the corner formed by the first side surface and the bottom surface.

(Feature 2) The guard ring located closest to the anti-element region has a curvature of a corner formed by the second side surface and the bottom surface in a cross section perpendicular to the direction in which the guard ring extends when the semiconductor substrate is viewed in plan view. , Smaller than the curvature of the corner formed by the first side surface and the bottom surface. When the side surface and the bottom surface are connected by a curve, the curvature at the corner of the curve is the “curvature at the corner”. On the other hand, when the side surface and the bottom surface both extend in a straight line and intersect, the curvature at the corner of the approximate curve obtained by curve approximation of the side surface and the bottom surface is the “curvature of the corner”.

(Characteristic 3) The guard ring located closest to the anti-element region has a first distance from the lower end to the upper end of the second side surface in a cross section orthogonal to the direction in which the guard ring extends when the semiconductor substrate is viewed in plan view. It is longer than the distance from the lower end to the upper end of the side.

(Feature 4) In the guard ring positioned closest to the anti-element region, the first side surface is orthogonal to the upper surface of the semiconductor substrate, or gradually from the upper surface of the semiconductor substrate toward the anti-element region side from the element region side. The shape is shallower. The second side surface has a shape in which the depth from the upper surface of the semiconductor substrate gradually decreases from the element region side toward the non-element region side.

  As shown in FIGS. 1 and 2, the semiconductor device 10 according to the first embodiment is formed on a semiconductor substrate 25 made of SiC. As shown in FIG. 2, the semiconductor substrate 25 includes a wafer substrate 24 and a drift layer 26 stacked on the wafer substrate 24. The wafer substrate 24 is disposed on the lower surface side of the semiconductor substrate 25. As the wafer substrate 24, for example, an n-type 4H—SiC substrate can be used.

  The drift layer 26 is stacked on the upper surface side of the semiconductor substrate 25. The drift layer 26 is n-type, and its impurity concentration is thinner than that of the wafer substrate 24. The drift layer 14 is thinner than the wafer substrate 12. The drift layer 14 can be formed by growing an epitaxial layer on the wafer substrate 12.

  A back electrode 28 is formed on the entire lower surface of the semiconductor substrate 25 (the lower surface of the wafer substrate 24). The back electrode 28 is in ohmic contact with the wafer substrate 24. The back electrode 28 can be formed of, for example, Ti, Mo, Ni (nickel), W (tungsten), or the like.

An insulating film 22 is formed on the upper surface of the semiconductor substrate 25 (the upper surface of the drift layer 26). The insulating film 22 can be formed of, for example, silicon oxide (SiO ₂ ). An opening 22 a is formed in the insulating film 22. A surface electrode 30 is formed in the opening 22a. The surface electrode 30 is configured by a Schottky electrode that forms a Schottky junction with the drift layer 26 and a wiring electrode formed on the Schottky electrode. The Schottky electrode can be formed of, for example, Mo (molybdenum), Ti (titanium), or Ni (nickel). The wiring electrode can be made of, for example, Al (aluminum). A passivation film 34 is formed on the outer periphery of the surface electrode 30 and the insulating film 32. The passivation film 34 can be formed of polyimide, for example.

  As shown in FIG. 1, an element region 12 and a termination region 14 surrounding the element region 12 are formed in the semiconductor substrate 25. A Schottky barrier diode is formed in the element region 12. The Schottky barrier diode includes a back electrode 28, a wafer substrate 24, a drift layer 26, and a front electrode 30 (see FIG. 2). Three guard rings 16, 18, and 20 are formed in the termination region 14. The guard rings 16, 18, and 20 are arranged at intervals from the inner peripheral side to the outer peripheral side, and each makes a round of the element region 12.

  The guard rings 16, 18, and 20 are p-type semiconductor regions doped with p-type impurities. As shown in FIG. 2, the guard ring 22 is formed in a range exposed on the surface of the drift layer 26. As the p-type impurity doped in the guard ring 20, for example, aluminum ions (Al ions) can be used. The p-type impurity concentrations of the guard rings 16, 18, and 20 are the same. The guard rings 16, 18, and 20 have the same shape. That is, each guard ring 16, 18, 20 is formed in the same depth range from the upper surface of the semiconductor substrate 25, and its width (in the direction from the inner periphery side to the outer periphery side of the semiconductor substrate 25 (in the cross section shown in FIG. 2). The width in the y direction) is also the same (see FIG. 2). The p-type impurity concentration and depth (dimension in the z direction) of the guard rings 16, 18, and 20 have a desired shape in the depletion layer formed when a reverse voltage is applied to the semiconductor device 10. It can set suitably as follows.

  As shown in FIG. 3, each guard ring 16, 18, 20 includes side surfaces 16 a, 18 a, 20 a on the element region side (that is, the inner peripheral side) and side surfaces 16 c on the counter element region side (that is, the outer peripheral side). 18c, 20c, bottom surfaces 16b, 18b, 20b and top surfaces 16d, 18d, 20d. Upper surfaces 16 d, 18 d, and 20 d of the guard rings 16, 18, and 20 are exposed on the upper surface of the semiconductor substrate 25. Upper surfaces 16d, 18d, and 20d of the guard rings 16, 18, and 20 are in contact with the insulating film 22, and are insulated from the surface electrode 30 by the insulating film 22 (see FIG. 2). Ends on the inner peripheral side of the upper surfaces 16d, 18d, and 20d are connected to upper ends of the side surfaces 16a, 18a, and 20a. The outer peripheral ends of the upper surfaces 16d, 18d, and 20d are connected to the upper ends of the side surfaces 16c, 18c, and 20c.

  The bottom surfaces 16 b, 18 b, and 20 b of the guard rings 16, 18, and 20 are in contact with the drift layer 26 and are substantially parallel to the upper surface of the semiconductor substrate 25. Ends on the inner peripheral side of the bottom surfaces 16b, 18b, and 20b are connected to lower ends of the side surfaces 16a, 18a, and 20a. End portions on the outer peripheral side of the bottom surfaces 16b, 18b, and 20b are connected to lower end portions of the side surfaces 16c, 18c, and 20c.

  The side surfaces 16 a, 18 a, and 20 a on the inner peripheral side of the guard rings 16, 18, and 20 are in contact with the drift layer 26. The side surfaces 16 a, 18 a, and 20 a are substantially orthogonal to the upper surface of the semiconductor substrate 25. Since the bottom surfaces 16b, 18b, 20b of the guard rings 16, 18, 20 are substantially parallel to the top surface of the semiconductor substrate 25, the side surfaces 16a, 18a, 20a and the bottom surfaces 16b, 18b, 20b are also substantially orthogonal. . Therefore, when the semiconductor substrate 25 is viewed in plan, a cross section orthogonal to the direction in which the guard rings 16, 18, 20 extend (for example, a cross section shown in FIGS. 2 and 3 (yz cross section) (hereinafter, this cross section is orthogonal to the guard ring). In this case, the angle of the corner A formed by the side surfaces 16a, 18a, 20a and the bottom surfaces 16b, 18b, 20b is approximately 90 °.

  Side surfaces 16 c, 18 c, and 20 c on the outer peripheral side of the guard rings 16, 18, and 20 are in contact with the drift layer 26. The side surfaces 16c, 18c, and 20c are formed in a curved surface shape that gradually decreases in depth from the upper surface of the semiconductor substrate 25 from the inner peripheral side toward the outer peripheral side. That is, the side surfaces 16c, 18c, and 20c are inclined with respect to the upper surface of the semiconductor substrate 25, and are also inclined with respect to the bottom surfaces 16b, 18b, and 20b of the guard rings 16, 18, and 20. Accordingly, in the cross section perpendicular to the guard ring, the angle formed by the side surfaces 16c, 18c, 20c and the bottom surfaces 16b, 18b, 20b is an obtuse angle of 90 ° or more. Specifically, since the side surfaces 16c, 18c, and 20c are curved, a straight line that approximates the curve of the side surfaces 16c, 18c, and 20c (for example, a straight line that connects the upper and lower ends of the side surfaces 16a, 18c, and 20c) and the bottom surface 16b. , 18b, and 20b have an obtuse angle of 90 ° or more.

  As is clear from the above description, in each guard ring 16, 18, and 20, the corner B formed by the outer side surfaces 16c, 18c, and 20c and the bottom surfaces 16b, 18b, and 20b in the cross section perpendicular to the guard ring. Is larger than the angle of the corner A formed by the side surfaces 16a, 18a, 20a on the inner peripheral side and the bottom surfaces 16b, 18b, 20b. Further, in the cross section orthogonal to the guard ring, the curvature of the corner B formed by the outer side surfaces 16c, 18c, 20c and the bottom surfaces 16b, 18b, 20b is the inner side surfaces 16a, 18a, 20a and the bottom surface 16b. , 18b, 20b is smaller than the curvature of the corner A. Here, since the inner side surfaces 16a, 18a, 20a and the bottom surfaces 16b, 18b, 20b are both straight lines, the curvature at the corners of the approximate curve obtained by curve approximation of these straight lines is “the corner portion A. Curvature ". Furthermore, in the guard ring orthogonal cross section, the distance from the lower end to the upper end of the outer peripheral side surfaces 16c, 18c, 20c is longer than the distance from the lower end to the upper end of the inner peripheral side surfaces 16a, 18a, 20a. .

  In the semiconductor device 10 described above, a forward bias is applied between the front electrode (anode electrode) 30 and the back electrode (cathode electrode) 28 (that is, a voltage higher than the voltage applied to the back electrode 28 is applied to the front electrode 30. Current) flows from the front electrode 30 to the back electrode 28. On the other hand, when a reverse bias is applied between the front electrode 30 and the back electrode 28 (that is, a voltage higher than the voltage applied to the front electrode 30 is applied to the back electrode 28), the front electrode 30 and the drift layer 26 are applied. Current from the drift layer 26 to the surface electrode 30 does not flow. Further, in the termination region 14 at the time of reverse bias, as shown in FIG. 3, a depletion layer D is formed by a pn junction between the guard rings 16, 18, 20 and the drift layer 26.

  Here, each guard ring 16, 18, 20 is formed in a curved shape in which the outer side surfaces 16 c, 18 c, 20 c gradually decrease in depth from the upper surface of the semiconductor substrate 25 from the inner peripheral side toward the outer peripheral side. Has been. Moreover, the angle of the corner | angular part B formed by the side surfaces 16c, 18c, and 20c on the outer peripheral side and the bottom surfaces 16b, 18b, and 20b is large, and the curvature is small. For this reason, as shown in FIG. 3, the depletion layer D is smoothly formed so as to gradually move toward the surface of the drift layer 26 from the inner peripheral side toward the outer peripheral side. In particular, the curvature of the boundary surface of the depletion layer D is reduced in a portion surrounded by a dotted line C shown in FIG. Thereby, concentration of the electric field can be prevented.

  Further, the corner B formed by the outer peripheral side surfaces 16c, 18c, 20c and the bottom surfaces 16b, 18b, 20b has an obtuse angle, while the inner peripheral side surfaces 16a, 18a, 20a and the bottom surfaces 16b, 18b, 20b. The angle of the corner part A formed by is substantially a right angle. That is, the curvature of the corner A formed by the inner peripheral side surfaces 16a, 18a, 20a and the bottom surfaces 16b, 18b, 20b is formed by the outer peripheral side surfaces 16c, 18c, 20c and the bottom surfaces 16b, 18b, 20b. It is larger than the curvature of the corner B. For this reason, it is suppressed that the space | interval (namely, the space | interval of the guard ring 16 and the guard ring 18, the space | interval of the guard ring 18 and the guard ring 20) between adjacent guard rings becomes narrow.

  As described above, in the semiconductor device 10 of the present embodiment, the curvature of the boundary surface of the depletion layer D can be reduced while suppressing the interval between adjacent guard rings from being narrowed. For this reason, it is possible to improve the breakdown voltage while suppressing an increase in the area of the termination region 14. That is, when the angle of the corner A on the inner peripheral side of the guard rings 16, 18, and 20 is an obtuse angle, the interval between adjacent guard rings is narrowed. Therefore, in order to obtain a desired withstand voltage, if an interval between adjacent guard rings is to be secured, the distance between the centers of the adjacent guard rings (that is, the distance between the center of the guard ring 16 and the center of the guard ring 18). , The distance between the center of the guard ring 18 and the center of the guard ring 20) must be increased, and as a result, the area of the termination region 14 increases. In the semiconductor device 10 according to the present embodiment, it is possible to suppress the interval between the adjacent guard rings from being narrowed, so that the breakdown voltage can be improved while suppressing the area of the termination region 14 from increasing.

  Next, an example of a method for manufacturing the above-described semiconductor device 10 will be described. First, as shown in FIG. 4, a 4H—SiC n-type wafer substrate 24 is prepared, and a drift layer 26 is formed on the wafer substrate 24 by epitaxial growth.

Next, as shown in FIG. 5, a patterned mask layer 36 is formed on the drift layer 26. That is, the mask layer 36 having the opening 36 a is formed on the drift layer 26. Specifically, first, as shown in FIG. 6, a mask layer (for example, an oxide film (SiO ₂ )) 36 is deposited on the entire upper surface of the drift layer 26 by chemical vapor deposition (CVD). Next, as shown in FIG. 7, a resist film 38 is formed on the entire upper surface of the mask layer 36 by spin coating or the like. Next, as shown in FIG. 8, the resist film 38 is exposed and developed using a photomask 40. Here, the photomask 40 has an opening 40a at a position corresponding to the opening 36a of the mask layer 36 shown in FIG. Therefore, when the resist film 38 is exposed and developed, an opening 38 a corresponding to the opening 36 a is formed in the resist film 38. Next, as shown in FIG. 9, using the resist film 38 as an etching mask, the mask layer 36 is subjected to dry etching (for example, reactive ion etching (RIE) using a reactive gas made of CHF ₃ or CF ₄ ). . Thereby, the mask layer 36 exposed in the opening 38a is removed. Thereafter, as shown in FIG. 10, the resist film 38 is removed. As a result, an opening 36 a is formed in the mask layer 36.

  Next, as shown in FIG. 11, the outer side surface 36 b of the opening 36 a of the mask layer 36 is inclined with respect to the drift layer 26. That is, the mask layer 36 on the outer peripheral side of the opening 36a is formed so that the thickness of the mask layer 36 increases from the inner peripheral side toward the outer peripheral side. Specifically, first, as shown in FIG. 12, a resist film 42 is formed on the entire upper surface of the mask layer 36 in which the openings 36a are formed. A recess 42 a corresponding to the opening 36 a of the mask layer 36 is formed on the upper surface of the resist film 42. Next, the resist film 42 is exposed and developed using the photomask 44. The photomask 44 has an opening 44 a corresponding only to the outer peripheral side region among the openings 36 a of the mask layer 36. Therefore, when the resist film 42 is exposed and developed, the opening 42b formed in the resist film 42 opens only on the outer peripheral side of the opening 36a. Therefore, only the outer peripheral side surface of the opening 36a in the mask layer 36 is exposed to the opening 42b. Next, as shown in FIG. 14, the mask layer 36 is etched by wet etching (for example, wet etching using HF). Since only the outer side surface of the opening 36a is exposed to the opening 42b, only the outer side surface 36b of the opening 36a of the mask layer 36 is removed by wet etching. As a result, the outer side surface 36b of the opening 36a is inclined. Thereafter, when the resist film 42 is removed, the state shown in FIG. 15 (that is, the state shown in FIG. 11) is obtained.

  In the state shown in FIG. 11, the opening 36 a of the mask layer 36 has a shape corresponding to the shape of the guard rings 16, 18, and 20. That is, in the region where the guard rings 16, 18, and 20 are formed deeply (region corresponding to the bottom surfaces 16b, 16c, and 16d), the thickness of the mask layer 36 is zero. On the other hand, in the region where the guard rings 16, 18, 20 are gradually shallow (the region corresponding to the outer side surfaces 16c, 18c, 20c), the thickness of the mask layer 36 is gradually increased from the inner side toward the outer side. It has become.

  Next, as shown in FIG. 16, p-type impurity ions (for example, Al ions) are uniformly implanted into the entire surface of the drift layer 26 using the mask layer 36 as a mask. In the region where the thick mask layer 36 is formed, impurity ions stop in the mask layer 36 and no impurity ions are implanted into the drift layer 26. On the other hand, in the region where the thickness of the mask layer 36 changes (region corresponding to the side surface 36b on the outer peripheral side of the opening 36a), impurity ions are implanted to a depth corresponding to the thickness of the mask layer 36 of the drift layer 26. In the region where the mask layer 36 is not formed, impurity ions are implanted deep into the drift layer 26. Thereby, impurity ions are implanted to a depth corresponding to the shape of the opening 36 a of the mask layer 36. Next, the remaining mask layer 36 is removed by wet etching, and the implanted impurity ions are activated at a high temperature. As a result, the region into which the impurity ions are implanted becomes a p-type semiconductor region (that is, the guard rings 16, 18, and 20).

  Next, a metal layer (for example, a nickel layer) is formed on the lower surface of the wafer substrate 24 using a sputtering apparatus, and the metal layer is silicided by annealing. Thereby, the back electrode 28 is formed on the lower surface of the wafer substrate 24. Next, an insulating film 22 is formed on the entire surface of the drift layer 26, and an opening 22 a is formed in the insulating film 22. Next, a Schottky electrode (for example, molybdenum) is formed on the surface of the drift layer 26 exposed in the opening 22a using a vacuum deposition apparatus, and a wiring electrode (for example, an aluminum electrode) is formed on the Schottky electrode. Form a film. Thereby, the surface electrode 30 is formed. Finally, a passivation film 34 is formed on the outer periphery of the surface electrode 30 and on the insulating film 32.

  As described above, in the method of manufacturing the semiconductor device 10 according to the present embodiment, the mask layer 36 corresponding to the shape of the guard rings 16, 18, and 20 is formed, and p-type impurities are implanted into the drift layer 26 through the mask layer 36. . Therefore, it is possible to form the guard rings 16, 18, and 20 whose outer peripheral sides are inclined while suppressing an increase in the number of steps.

  Finally, the correspondence between the configuration of the above embodiment and the claims is described. The wafer substrate 24 and the drift layer 26 correspond to an example of “semiconductor substrate”, the side surface 20a corresponds to an example of “first side surface”, the bottom surface 20b corresponds to an example of “bottom surface”, and the side surface 20c corresponds to an example of “second”. This corresponds to an example of “side surface”.

  As mentioned above, although the specific example which actualized the technique of an indication in this specification was described in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.

  For example, in the embodiment described above, the guard rings 16, 18, and 20 are formed by the method shown in FIGS. 5 to 16, but the method for forming the guard rings 16, 18, and 20 is not limited to the above method. For example, the guard rings 16, 18, and 20 can be formed by the method shown in FIGS. That is, first, the mask layer 36 is deposited on the entire upper surface of the drift layer 26 (state shown in FIG. 17 → state shown in FIG. 18). Next, as shown in FIG. 19, a resist film 38 is formed on the entire upper surface of the mask layer 36.

  Next, as shown in FIG. 20, the resist film 38 is exposed and developed using a photomask 46. The photomask 46 has openings 46 a corresponding to the guard rings 16, 18, and 20. Further, when exposing the resist film 38, light is irradiated obliquely from the outer peripheral side to the inner peripheral side of the semiconductor substrate. In order to irradiate light obliquely through the photomask 46, an opening 38 b inclined obliquely is formed in the resist film 38.

Next, as shown in FIG. 21, using the resist film 38 as an etching mask, the mask layer 36 is dry-etched (for example, reactive ion etching using a reactive gas made of CHF ₃ or CF ₄ ). Here, since the reactive gas enters the inclined inner side of the resist film 38 on the inner peripheral side of the opening 38b, the mask layer 36 is satisfactorily removed. As a result, the inner surface 36 c of the opening of the mask layer 36 becomes a surface substantially orthogonal to the drift layer 26. On the other hand, on the outer peripheral side of the opening 38b, the mask layer 36 is removed so as to gradually increase in thickness from the inner peripheral side toward the outer peripheral side due to the influence of the shape of the resist film 38. That is, the outer surface 36b of the opening of the mask layer 36 is a surface inclined from the inner peripheral side toward the outer peripheral side.

  Next, the resist film 38 is removed, and impurity ions are implanted into the drift layer 26 using the mask layer 36 as a mask, as shown in FIG. Thereby, impurity ions are implanted into a region indicated by reference numeral 116 (118, 120) in FIG. Then, when the mask layer 36 is removed and the implanted impurity ions are activated at a high temperature, guard rings 16, 18, and 20 are formed as shown in FIG.

  According to the above method, by exposing and developing the resist film 38 at an angle, openings corresponding to the shapes of the guard rings 16, 18, and 20 can be formed in the mask layer 36 by subsequent dry etching. As a result, the mask layer 36 can be formed with fewer steps, and the guard rings 16, 18, and 20 can be formed more effectively.

  In the above-described embodiments, the outer peripheral side surfaces 16c, 18c, and 20c of the guard rings 16, 18, and 20 are formed in a curved shape. However, the technique disclosed in this specification is limited to such a form. I can't. For example, the side surface on the outer peripheral side of the guard ring may be formed in a planar shape (a shape that is linear in the cross section shown in FIGS. 2 and 3). Even in such a case, by making the angle between the outer circumferential side surface of the guard ring and the bottom surface of the guard ring an obtuse angle, the curvature of the boundary surface of the depletion layer formed at the time of reverse bias can be reduced, and the withstand voltage can be reduced. Can be improved.

  In the above-described embodiment, the side surfaces 16a, 18a, 20a on the inner peripheral side of the guard rings 16, 18, 20 are substantially orthogonal to the upper surface of the semiconductor substrate 25. It is not limited to such a form. For example, the inner peripheral side surface of the guard ring may be formed in a shape in which the depth from the upper surface of the semiconductor substrate 25 gradually decreases from the inner peripheral side to the outer peripheral side of the semiconductor substrate 25. That is, you may make the angle of the corner | angular part of the inner peripheral side of a guard ring smaller than 90 degrees. According to such a form, since the distance between adjacent guard rings can be made longer, the breakdown voltage can be further improved. In order to incline the inner peripheral side surface of the guard ring as described above, impurity ions may be implanted obliquely with respect to the upper surface of the semiconductor substrate. That is, impurity ions may be implanted obliquely from the outer peripheral side to the inner peripheral side of the semiconductor substrate. Further, the side surface on the inner peripheral side of the guard ring may be formed in a curved shape instead of a flat shape.

  In the semiconductor device 10 of the above-described embodiment, the outer peripheral side surfaces 16c, 18c, and 20c of each of the plurality of guard rings 16, 18, and 20 are inclined. In the side guard ring 20, the outer peripheral side surface 20c only needs to be inclined. Therefore, in the inner guard rings 16 and 18, the outer peripheral side surfaces 16 c and 18 c are not necessarily inclined.

  In the semiconductor device 10 according to the above-described embodiment, the Schottky barrier diode is formed in the element region 12. However, the technique disclosed in the present specification is not limited to such an example, and various techniques including a guard ring are provided. It can be applied to a semiconductor device. For example, a PN diode, MOSFET, diode integrated MOSFET, IGBT, or the like can be formed in the element region.

  Further, the number and configuration of guard rings formed in the termination region 14 can take various forms. For example, the number, width, etc. of the guard ring can be appropriately determined according to characteristics required for the semiconductor device.

  Further, the technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

10: Semiconductor device 12: Element region 14: Termination regions 16, 18, 20: Guard ring 24: Wafer substrate 26: Drift layer

Claims (5)

A semiconductor substrate having an element region and a termination region surrounding the element region;
In the termination region, a plurality of guard rings that make a circuit around the outside of the element region are formed,
Among the plurality of guard rings, the guard ring positioned at least on the side opposite to the element region includes a first side surface on the element region side, a bottom surface having one end connected to the lower end of the first side surface, and a lower end on the other end of the bottom surface. Has a second side surface on the side opposite to the element region to which
The second side surface has a shape in which the depth from the upper surface of the semiconductor substrate gradually decreases from the element region side toward the counter element region side,
The guard ring located on the most anti-element region side has an angle of a corner formed by the second side surface and the bottom surface in a cross section perpendicular to the direction in which the guard ring extends when the semiconductor substrate is viewed in plan view. And a semiconductor device larger than the angle of the corner formed by the bottom surface.   The first side surface is orthogonal to the upper surface of the semiconductor substrate, or has a shape in which the depth from the upper surface of the semiconductor substrate gradually decreases from the element region side toward the non-element region side. The semiconductor device described.   The semiconductor device according to claim 1, wherein the semiconductor substrate is made of silicon carbide. A semiconductor substrate having an element region and a termination region surrounding the element region;
In the termination region, a plurality of guard rings that make a circuit around the outside of the element region are formed,
Among the plurality of guard rings, the guard ring positioned at least on the side opposite to the element region includes a first side surface on the element region side, a bottom surface having one end connected to the lower end of the first side surface, and a lower end on the other end of the bottom surface. Has a second side surface on the side opposite to the element region to which
The second side surface has a shape in which the depth from the upper surface of the semiconductor substrate gradually decreases from the element region side toward the counter element region side,
The guard ring located on the most anti-element region side has an angle of a corner formed by the second side surface and the bottom surface in a cross section perpendicular to the direction in which the guard ring extends when the semiconductor substrate is viewed in plan view. And a method of manufacturing a semiconductor device that is larger than the angle of the corner formed by the bottom surface,
A mask layer forming step of forming a mask layer on the upper surface of the semiconductor substrate;
And a step of implanting impurity ions into the semiconductor substrate from above the semiconductor substrate through the mask layer after forming the mask layer,
In the mask layer forming step, the thickness of the mask layer corresponding to the guard ring is formed according to the shape of the guard ring, and the thickness of the mask layer is thin in the portion where the guard ring is deeply formed. A method of manufacturing a semiconductor device, wherein the mask layer is formed thick in a portion where the film is formed shallow. The mask layer forming process
Forming a mask layer over the entire top surface of the semiconductor substrate;
Forming a resist film over the entire upper surface of the mask layer;
Exposing a resist film through a photomask having at least an opening corresponding to a guard ring located on the most anti-element region side;
Developing the exposed resist film;
Using the developed resist film as an etching mask, and dry-etching the mask layer, and
The method of manufacturing a semiconductor device according to claim 4, wherein in the step of exposing the resist film, light is irradiated obliquely from the non-element region side toward the element region side.

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