JP2013143818A - Semiconductor fuse device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor fuse device in which the circuit impedance is kept low without providing a noise elimination circuit, while enhancing the normal/abnormal detection rate of a system load or the wiring.SOLUTION: The semiconductor fuse device comprises: a semiconductor switching element interposed between a power supply and a system load which is supplied with power from the power supply, and interrupting the power supply and the system load at least when an overcurrent of the system load is detected; a capacitor connected in parallel with the system load; discharge monitoring means for detecting a discharge time required for the voltage across the capacitor to go below a predetermined threshold after starting interruption in a state where the semiconductor switching element is interrupting the power supply and the system load, or a residual voltage existing across the capacitor at a moment in time when a predetermined discharge time has elapsed; and normal/abnormal determination means for determining normal/abnormal of the system load or the wiring for connection with the system load based on the discharge time or the residual voltage thus detected.

Description

  The present invention relates to a semiconductor fuse device, and in particular, by driving a semiconductor switching element interposed between a power supply and a system load supplied with power from the power supply, at least when an overcurrent of the system load is detected, The present invention relates to a semiconductor fuse device that interrupts the circuit.

  2. Description of the Related Art Conventionally, a semiconductor fuse device that cuts off a power supply and a system load supplied with power from the power supply when an overcurrent is detected is known (for example, see Patent Document 1). This semiconductor fuse device compares a semiconductor switching element interposed between a power source and a system load, and compares the output voltage to the system load with a predetermined reference voltage when the semiconductor switching element conducts (that is, when the switch is on). And a circuit. The semiconductor switching element stops power supply to the system load by cutting off the power supply and the system load based on the comparison result by the comparison circuit.

JP 2001-157356 A

  However, in the configuration in which the overload current of the system load is detected based on the ON voltage of the semiconductor switching element, it is necessary to greatly amplify the voltage with an operational amplifier or the like so that a minute voltage change can be identified. For this reason, in such a configuration, the impedance of the circuit becomes high, and the semiconductor switching element may malfunction due to external electrical noise transmitted from an external connection load or the like. In order to prevent this, it is conceivable to provide a noise removal circuit that blocks external electrical noise. However, the noise removal circuit increases the cost and the scale of the apparatus.

  The present invention has been made in view of the above points, and can improve the detection rate of normality / abnormality of system load and wiring, and can suppress the circuit impedance low without providing a noise removal circuit. An object is to provide an apparatus.

  The object is to provide a semiconductor switching element that is interposed between a power source and a system load supplied with power from the power source, and that shuts off the power source and the system load at least when an overcurrent of the system load is detected, and the system load. A capacitor connected in parallel with the semiconductor switching element in a state in which the power source and the system load are shut off, and after the start of shutoff, a discharge time required for the voltage across the capacitor to fall below a predetermined threshold, Or a discharge monitoring means for detecting a residual voltage generated at both ends of the capacitor when a predetermined discharge time has elapsed, and the system based on the discharge time or the residual voltage detected by the discharge monitoring means Normal / abnormality determination means for determining normality / abnormality of a load or wiring connected to the system load. It is achieved by's equipment.

  ADVANTAGE OF THE INVENTION According to this invention, a circuit impedance can be restrained low, without providing a noise removal circuit, improving the detection rate of normality / abnormality of a system load or wiring.

1 is a configuration diagram of a semiconductor fuse device according to a first embodiment of the present invention. It is a figure for demonstrating the operation | movement at the time of interruption | blocking in the semiconductor fuse apparatus of a present Example. It is a figure showing the time change of the capacitor both ends voltage according to normality / abnormality implement | achieved in the semiconductor fuse apparatus of a present Example. It is a flowchart of an example of the control routine performed in the semiconductor fuse apparatus of a present Example. It is a figure showing the time change of the capacitor both ends voltage according to normality / abnormality implement | achieved in the semiconductor fuse apparatus which is 2nd Example of this invention. It is a flowchart of an example of the control routine performed in the semiconductor fuse apparatus of a present Example.

  Hereinafter, specific embodiments of a semiconductor fuse device according to the present invention will be described with reference to the drawings.

  FIG. 1 shows a configuration diagram of a semiconductor fuse device 10 according to a first embodiment of the present invention. The semiconductor fuse device 10 of this embodiment is mounted on a vehicle, for example, and is a device that shuts off the power supply 12 and the system load 14 at least when an overcurrent is detected and stops the power supply to the system load 14. . The power source 12 is, for example, a battery that outputs a predetermined DC voltage (for example, 12 volts) + B mounted on a general vehicle. The system load 14 is an electric load (load resistance value R) that is mounted on a vehicle, for example, powered by the power source 12 and operates at the predetermined DC voltage + B.

  As shown in FIG. 1, the semiconductor fuse device 10 includes a semiconductor switching element 16 interposed between a power supply 12 and a system load 14. The semiconductor switching element 16 is an n-channel FET (for example, an n-channel MOS-FET) as an output transistor made of a semiconductor. Hereinafter, the semiconductor switching element 16 is referred to as an FET 16. The drain of the FET 16 is connected to the power supply 12 and the source thereof is connected to one end of the system load 14. The other end of the system load 14 is grounded. That is, the system load 14 is connected to the source of the FET 16 and the ground terminal. The FET 16 conducts / cuts off the power flow path from the power supply 12 to the system load 14 by turning on / off.

  The semiconductor fuse device 10 also includes a capacitor 18 connected in parallel to the system load 14. The capacitor 18 is a large capacity capacitor (capacitance value C) such as an electrolytic capacitor. One end of the capacitor 18 is connected to the source of the FET 16 and the other end is grounded. That is, the capacitor 18 is connected to the source of the FET 16 and the ground terminal.

  The semiconductor fuse device 10 also includes a voltage monitoring circuit 20 that monitors a voltage V generated across the capacitor 18 (that is, a potential generated at the source of the FET 16) V. The voltage monitoring circuit 20 includes an IC or microcomputer (hereinafter referred to as IC / microcomputer) 22, resistors 24, 26, 28, 30, a diode 32, and a semiconductor switching element 34.

  The IC / microcomputer 22 is connected to the gate of the FET 16 described above. The IC / microcomputer 22 generates and outputs a relay ON / OFF signal for driving the FET 16 on / off, and controls the driving of the FET 16. The IC / microcomputer 22 normally generates a relay ON / OFF signal so that the FET 16 is PWM-driven when the operation of the system load 14 is requested, and supplies the generated relay ON / OFF signal to the gate of the FET 16.

  The IC / microcomputer 22 also detects normal / abnormal short-circuit / abnormal disconnection of the system load 14 or wiring connected to the system load 14 based on the voltage across the capacitor 18, and the normal / abnormal short-circuit. / The relay ON / OFF signal supplied to the gate of the FET 16 is controlled based on the detection result of the abnormal disconnection.

  The semiconductor switching element 34 is a pnp bipolar transistor made of a semiconductor. Hereinafter, the semiconductor switching element 34 is simply referred to as a transistor 34. The base of the transistor 34 is connected to the IC / microcomputer 22 via the resistor 24, and the emitter thereof is connected to the power source 12. The collector of the transistor 34 is grounded via the resistor 26 and is connected to one end of the resistor 28.

  The other end of the resistor 28 is connected to the anode of the diode 32 and to one end of the resistor 30. The cathode of the diode 32 is connected to one end of the capacitor 18, that is, the source of the FET 16 (or one end of the system load 14). The diode 32 is a circuit that blocks current flow from the capacitor 18 side to the resistors 26 to 30 side. The other end of the resistor 30 is connected to the IC / microcomputer 22. The IC / microcomputer 22 monitors the voltage V across the capacitor 18 based on the voltage level generated at the other end of the resistor 30.

  Next, the operation of the semiconductor fuse device 10 of this embodiment will be described with reference to FIGS. FIG. 2 is a diagram for explaining an operation when the power source 12 and the system load 14 are shut off in the semiconductor fuse device 10 of this embodiment. FIG. 3 shows a time change of the voltage V across the capacitor 18 for each normal / abnormal short circuit / abnormal disconnection realized in the semiconductor fuse device 10 of this embodiment. FIG. 4 shows a flowchart of an example of a control routine executed by the IC / microcomputer 22 in the semiconductor fuse device 10 of this embodiment.

  In this embodiment, when the operating condition of the system load 14 is established, the IC / microcomputer 22 normally generates a relay ON / OFF signal so that the FET 16 is PWM-driven and outputs it to the gate. When a relay ON / OFF signal instructing PWM driving is supplied to the gate of the FET 16, the FET 16 is PWM driven. It should be noted that the duty ratio in the PWM drive of the FET 16 may be a predetermined predetermined value, or may be changed according to an operation request of the system load 14.

  When the relay ON signal is supplied to the gate, the FET 16 is turned on so as to make the power supply 12 and the system load 14 conductive. In this case, since the voltage + B of the power source 12 is applied to the system load 14 and the power from the power source 12 is supplied, the system load 14 operates. On the other hand, when the relay OFF signal is supplied to the gate, the FET 16 is turned off so as to cut off the power supply 12 and the system load 14. In this case, the voltage application from the power supply 12 to the system load 14 is stopped and the power supply from the power supply 12 to the system load 14 is stopped, so that the operation of the system load 14 is stopped. In this respect, the operation of the system load 14 is in accordance with the duty ratio of the PWM drive of the FET 16.

  When the power supply 12 and the system load 14 are turned on by turning on the FET 16, the power from the power supply 12 is supplied to the system load 14 and to the capacitor 18. In this case, since the electric charge is stored in the capacitor 18, the voltage V across the capacitor 18 increases. On the other hand, when the power supply 12 and the system load 14 are cut off due to the FET 16 being turned off, the power supply from the power supply 12 to the system load 14 and the capacitor 18 is stopped. However, as shown in FIG. The electric charge stored in the capacitor 18 moves toward. In this case, since the capacitor 18 is discharged, the voltage V across the capacitor 18 decreases.

  When the system load 14 and the wiring connected to the system load 14 are in a normal state, the discharge of the capacitor 18 when the FET 16 is off depends on the capacitance value C of the capacitor 18 and the load resistance value R of the system load 14. This is performed with a time constant CR, and the voltage V across the capacitor 18 gradually decreases with time as shown by the solid line in FIG. On the other hand, when the FET 16 is turned off and the system load 14 or wiring is abnormally short-circuited to the ground terminal, the charge accumulated in the capacitor 18 moves to the ground terminal in a short time and overcurrent flows. However, as shown by the alternate long and short dash line in FIG. Further, when the FET 16 is turned off and an abnormal disconnection occurs in the system load 14 or wiring, it becomes difficult to move the electric charge stored in the capacitor 18, so that the decrease in the voltage V across the capacitor 18 is indicated by a two-dot chain line in FIG. As shown in the figure, it becomes gentle and the discharge of the capacitor 18 continues for a long period of time as compared with the case where the discharge is performed with the time constant CR.

  Therefore, in this embodiment, the IC / microcomputer 22 determines whether the system load 14 or the load is based on the voltage V across the capacitor 18 when the FET 16 is off (or when the duty is off), that is, when the power supply 12 and the system load 14 are cut off. A normal / abnormal short circuit / abnormal disconnection of the wiring connected to the system load 14 is detected.

  Specifically, the IC / microcomputer 22 supplies a high voltage to the base of the transistor 34 when supplying the relay ON signal to the FET 16. In such a situation, since the current supplied to the system load 14 and the capacitor 18 flows between the drain and source of the FET 16, the source potential V is in the vicinity of the voltage + B of the power source 12, while the emitter 34 to the collector of the transistor 34. Since no current flow occurs, the voltage applied to the anode of the diode 32 is low. In this case, since no forward voltage is generated in the diode 32, current flow from the source side of the FET 16 (the cathode side of the diode 32) to the resistors 26 to 30 side (the anode side of the diode 32) is blocked. When the FET 16 is on, the IC / microcomputer 22 does not detect the voltage level generated at the other end of the resistor 30, does not monitor the voltage V across the capacitor 18, and performs the above normal / abnormal short circuit / abnormal disconnection. Do not detect.

  On the other hand, the IC / microcomputer 22 supplies a low voltage to the base of the transistor 34 when supplying the relay OFF signal to the FET 16. In such a situation, discharging from the capacitor 18 toward the system load 14 is performed, and current flows from the emitter to the collector of the transistor 34, so that the voltage applied to the anode of the diode 32 is raised. In this case, the voltage level generated at the other end of the resistor 30 corresponds to the voltage V across the capacitor 18. When the FET 16 is off, the IC / microcomputer 22 monitors the voltage V across the capacitor 18 based on the voltage level input from the other end of the resistor 30, and detects the normal / abnormal short circuit / abnormal disconnection. .

  In this embodiment, the IC / microcomputer 22 determines whether or not the signal supplied to the FET 16 has been switched from the relay ON signal to be turned on to the relay OFF signal to be turned off from the previous processing to the current processing. (Step 100). As a result, when it is determined that the relay ON signal or the relay OFF signal is maintained, the process of step 100 is repeatedly executed again. On the other hand, when it is determined that the signal supplied to the FET 16 has been switched from the relay ON signal to the relay OFF signal, the discharge from the capacitor 18 is started thereafter, so the time after the discharge from the capacitor 18 (hereinafter, Time measurement of T (referred to as discharge time) is started (step 102). The discharge time T is counted continuously while the relay ON signal is not supplied to the FET 16 and the relay OFF signal is supplied.

  The IC / microcomputer 22 detects the voltage V across the capacitor 18 based on the voltage level generated at the other end of the resistor 30 every predetermined time after the start of the measurement of the discharge time T (step 104). It is determined whether or not the voltage V across the capacitor 18 is below a predetermined threshold value Vth (step 106). The predetermined threshold value Vth is set to a value obtained by multiplying the voltage V across the capacitor 18 when the FET 16 is turned on by 37% corresponding to the time constant CR between the capacitor 18 and the system load 14.

  As a result, if it is determined that V <Vth is not satisfied, that is, V ≧ Vth is satisfied, it is then determined whether or not the discharge time T counted at the determination time exceeds the timeout time Tmax ( Step 108). The timeout time Tmax is set to a time longer than the time constant CR between the capacitor 18 and the system load 14, and the voltage V across the capacitor 18 falls below a predetermined threshold Vth after the FET 16 is switched from on to off. It is the longest time allowed as a normal value of the time required until the time (that is, the upper limit value of a predetermined normal range). If it is determined that T> Tmax is not established as a result of the process of step 108, the process of step 104 is executed again, assuming that the discharge time T has not reached the timeout time Tmax.

  On the other hand, if it is determined that V <Vth is established, it is next determined whether or not the discharge time T, which is timed at the time of the determination, is below a lower limit value Tmin of a predetermined normal range (step 110). . The lower limit value Tmin is set to a time shorter than the time constant CR between the capacitor 18 and the system load 14, and the voltage V across the capacitor 18 falls below a predetermined threshold value Vth after the FET 16 switches from on to off. This is the shortest time allowed as a normal value of the time required until.

  When determining that T <Tmin is not established, the IC / microcomputer 22 determines that the system load 14 and the wiring connected to the system load 14 are in a normal state (step 112). On the other hand, if it is determined that T <Tmin is satisfied and the discharge time T has not reached the predetermined normal range, the voltage V across the capacitor 18 decreases rapidly after the FET 16 is switched from on to off. Therefore, it is determined that an abnormal short circuit to the ground terminal has occurred in the system load 14 or wiring, and an overcurrent has flowed into the system load 14 (step 114). If it is determined in step 108 that T> Tmax is satisfied and the discharge time T exceeds the time-out time Tmax and exceeds a predetermined normal range, the voltage V across the capacitor 18 is switched from on to off of the FET 16. After the switching, it is determined that the voltage gradually decreases as compared with the normal time. Therefore, it is determined that an abnormal disconnection has occurred in the system load 14 or the wiring (step 116).

  Thus, in this embodiment, when the FET 16 is off (or when the duty is off), the voltage V across the capacitor 18 is monitored, and after the FET 16 is switched from on to off, that is, between the power supply 12 and the system load 14. A discharge time T required for the voltage V across the two terminals to fall below a predetermined threshold value Vth after the start of shut-off is detected, and normal / abnormal conditions such as system load 14 and wiring are determined based on the relationship between the detected discharge time T and the time constant CR. A short circuit / abnormal disconnection can be determined. Specifically, when the discharge time T is within a predetermined normal range based on the time constant CR between the capacitor 18 and the system load 14, it is determined as normal, and the discharge time T does not reach the predetermined normal range. In this case, it is determined that an abnormal short circuit to the ground terminal has occurred, and when the discharge time T exceeds the predetermined normal range, it can be determined that an abnormal disconnection has occurred. Therefore, according to the present embodiment, the detection rate of normal / abnormal short-circuit / abnormal disconnection of the system load 14 and wiring can be improved.

  In this embodiment, monitoring of the voltage V across the capacitor 18 and determination of normal / abnormal short circuit / abnormal disconnection of the system load 14 and wiring based on the voltage V are performed when the FET 16 is turned off. For this reason, according to the configuration of this embodiment, unlike the configuration in which the voltage monitoring and determination described above are performed when the FET 16 is turned on, the voltage monitoring necessary for determining normality / abnormality of the system load 14 and wiring is performed. The circuit impedance can be kept low, and the external electrical noise transmitted from the outside does not greatly affect the voltage to be monitored. It is not necessary to provide it. Therefore, according to the semiconductor fuse device 10 of the present embodiment, the circuit load can be kept low without providing a noise removal circuit while improving the detection rate of normal / abnormal short circuit / abnormal disconnection of the system load 14 and wiring. As a result, the cost can be kept low and the scale of the apparatus can be reduced for determining the normality / abnormality.

  Further, in the present embodiment, not only when the abnormal disconnection occurs on the upstream side of the system load 14 (that is, the wiring between the system load 14 and the source connection end of the capacitor 18), Even when it occurs on the downstream side (that is, the wiring between the system load 14 and the ground terminal), the voltage V across the capacitor 18 gradually decreases when the FET 16 is turned off. Therefore, according to this embodiment, it is possible to determine not only the abnormal disconnection that occurs on the upstream side of the system load 14 but also the abnormal disconnection that occurs on the downstream side of the system load 14.

  In the present embodiment, monitoring of the voltage V across the capacitor 18 and determination of normal / abnormal short circuit / abnormal disconnection of the system load 14 and wiring based on the voltage V across the capacitor 18 are performed in parallel with the system load 14. A large-capacitance capacitor 18 that is charged when the FET 16 is turned on is provided. The capacitor 18 can absorb a surge voltage based on a coil component of the system load 14 that may be generated when the FET 16 is turned on / off. Therefore, according to the present embodiment, it is possible to prevent the FET 16 itself and other loads from being destroyed due to the generation of the surge voltage, and to prevent back electromotive force for absorbing the surge voltage. In some cases, it may be unnecessary to additionally connect the circuit to the system load 14 in parallel.

  In this embodiment, the IC / microcomputer 22 determines that an abnormal short circuit or an abnormal disconnection has occurred as a result of determining the normal / abnormal short circuit / abnormal disconnection of the system load 14 or the wiring connected to the system load 14 as described above. Then, a relay OFF signal is generated and output so that the FET 16 is turned off and the power supply 12 and the system load 14 are cut off, and a signal supplied to the gate of the FET 16 is set as a relay OFF signal. The supply of the relay OFF signal to the FET 16 may be performed until the abnormality is canceled or continuously for a predetermined time. Therefore, according to the present embodiment, the operation of the system load 14 can be stopped by turning off the FET 16 at the time of abnormal short circuit or abnormal disconnection, and unnecessary power supply from the power supply 12 can be avoided.

  By the way, in the first embodiment, the FET 16 corresponds to the “semiconductor switching element” recited in the claims, and the IC / microcomputer 22 switches from on to off when the FET 16 is on. Thereafter, by detecting the discharge time T required for the voltage V across the capacitor 18 to fall below the predetermined threshold value Vth, the “discharge monitoring means” described in the scope of claims includes steps 108 to 116 in the routine shown in FIG. By executing the processing, when the “normal / abnormal determination means” described in the claims determines that an abnormal short circuit or disconnection has occurred in the system load 14 or the like, by supplying a relay OFF signal to the FET 16 The “control means” recited in the claims is realized.

  FIG. 5 shows a time change of the voltage V across the capacitor 18 for each normal / abnormal short circuit / abnormal disconnection realized in the semiconductor fuse device 10 according to the second embodiment of the present invention. FIG. 6 shows a flowchart of an example of a control routine executed by the IC / microcomputer 22 in the semiconductor fuse device 10 of this embodiment. That is, the semiconductor fuse device 10 of this embodiment is realized by causing the IC / microcomputer 22 to execute the routine shown in FIG. 6 instead of the routine shown in FIG. In FIG. 6, steps that execute the same processing as the routine shown in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  In this embodiment, when the IC / microcomputer 22 starts measuring the discharge time T from the capacitor 18 in the above step 102, thereafter, the IC / microcomputer 22 determines whether or not the discharge time T exceeds a predetermined discharge time Tth (step 200). The predetermined discharge time Tth is set to a time constant CR substantially corresponding to the capacitance value C of the capacitor 18 and the load resistance value R of the system load 14.

  As a result, if it is determined that T> Tth does not hold, the process of step 200 is repeated. On the other hand, if it is determined that T> Tth is established, next, the both-end voltage (residual voltage) V based on the capacity remaining in the capacitor 18 is detected based on the voltage level generated at the other end of the resistor 30 at the time of the determination. (Step 202). Then, the detected level of the voltage V across the capacitor 18 is determined (step 204). Specifically, it is determined whether or not the voltage V between both ends is lower than a lower limit value Vmin of a predetermined normal range or higher than an upper limit value Vmax of a predetermined normal range.

  The lower limit value Vmin is a minimum voltage allowed as a normal value of the voltage across the capacitor 18 that occurs when a predetermined discharge time Tth has elapsed since the FET 16 was switched from on to off. The upper limit value Vmax is a maximum voltage allowed as a normal value of the voltage across the capacitor 18 that occurs when a predetermined discharge time Tth has elapsed since the FET 16 was switched from on to off.

  If it is determined that Vmin ≦ V ≦ Vmax is established, the IC / microcomputer 22 determines that the system load 14 and the wiring connected to the system load 14 are in a normal state (step 206). On the other hand, if it is determined that the remaining voltage V of the capacitor 18 falls below a predetermined normal range because V <Vmin is established, the voltage V across the capacitor 18 is quickly switched after the FET 16 is switched from on to off. Since it is determined that the voltage has decreased, it is determined that an abnormal short circuit to the ground terminal has occurred in the system load 14 or the wiring (step 208). Further, when it is determined that V> Vmax is established and the residual voltage V of the capacitor 18 exceeds a predetermined normal range, the voltage V across the capacitor 18 is switched from on to off after the FET 16 is switched from the normal state to the normal state. Since it is determined that the voltage gradually decreases, it is determined that an abnormal disconnection has occurred in the system load 14 or the wiring (step 210).

  Thus, in this embodiment, when the FET 16 is turned off, the voltage V across the capacitor 18 is monitored. Specifically, after the FET 16 is switched from on to off, that is, the power supply 12 and the system load 14 are started to be shut off. Thereafter, when a predetermined discharge time Tth elapses, a residual voltage V generated at both ends of the capacitor 18 is detected. Based on the detected residual voltage V, normal / abnormal short circuit / abnormal disconnection of the system load 14 and wiring, etc. Can be determined. Specifically, when the residual voltage V is within a predetermined normal range based on the time constant CR between the capacitor 18 and the system load 14, it is determined as normal, and the residual voltage V is below the predetermined normal range. Determines that an abnormal short circuit to the ground end has occurred, and if the discharge time T exceeds the predetermined normal range, it can be determined that an abnormal disconnection has occurred. Therefore, according to the present embodiment, the detection rate of normal / abnormal short-circuit / abnormal disconnection of the system load 14 and wiring can be improved.

  Also in this embodiment, as in the first embodiment, monitoring of the voltage V across the capacitor 18 and determination of normal / abnormal short-circuit / abnormal disconnection of the system load 14 and wiring based on the voltage V across the capacitor 18 are performed by the FET 16. Done at the time of off. Therefore, also in the semiconductor fuse device 10 of the present embodiment, the circuit load can be kept low without providing a noise removal circuit while improving the detection rate of normal / abnormal short circuit / abnormal disconnection of the system load 14 and wiring. As a result, the cost can be kept low and the scale of the apparatus can be reduced for determining the normality / abnormality.

  Also in this embodiment, as in the first embodiment, an abnormal disconnection occurred on the upstream side of the system load 14 (that is, the wiring between the system load 14 and the source connection end of the capacitor 18). Not only when, but also when it occurs on the downstream side of the system load 14 (that is, the wiring between the system load 14 and the ground terminal), the voltage V across the capacitor 18 gradually decreases when the FET 16 is turned off. It is possible to determine not only the abnormal disconnection that occurs on the upstream side of the system load 14 but also the abnormal disconnection that occurs on the downstream side of the system load 14.

  Also in this embodiment, similarly to the first embodiment, monitoring of the voltage V across the capacitor 18 and determination of normal / abnormal short circuit / abnormal disconnection of the system load 14 and wiring based on the voltage V across the capacitor 18 are performed. In addition, since a large-capacitance capacitor 18 connected in parallel to the system load 14 and charged when the FET 16 is turned on is provided, the FET 16 itself and other loads are destroyed due to the generation of the surge voltage. In some cases, it is unnecessary to additionally connect a back electromotive force prevention circuit for absorbing the surge voltage to the system load 14 in parallel.

  Also in this embodiment, as in the first embodiment, when the IC / microcomputer 22 determines that an abnormal short circuit or an abnormal disconnection of the system load 14 or the wiring connected to the system load 14 has occurred as described above, the FET 16 Since the relay OFF signal is generated and outputted so as to cut off the power supply 12 and the system load 14 by turning off the FET 16, the operation of the system load 14 can be stopped by turning off the FET 16 at the time of abnormal short circuit or abnormal disconnection. In addition, useless power supply from the power source 12 can be avoided.

  By the way, in the second embodiment described above, the IC / microcomputer 22 detects the voltage V across the capacitor 18 when a predetermined discharge time Tth elapses after the FET 16 is switched from on to off. Thus, the “discharge monitoring means” described in the claims executes the processing of steps 204 to 210 in the routine shown in FIG. When it is determined that an abnormal short circuit or an abnormal disconnection has occurred in the load 14 or the like, the “control means” described in the claims is realized by supplying a relay OFF signal to the FET 16.

  In the first and second embodiments, the switching drive of the transistor 34 is synchronized with the switching drive of the FET 16, and specifically, the transistor 34 is connected to the voltage across the capacitor 18 when the FET 16 is turned on. V is driven so that it is not monitored, while transistor 34 is driven so that the voltage V across capacitor 18 is monitored when FET 16 is turned off, thereby continuing both ends of capacitor 18 while FET 16 is turned off. Although the voltage V is monitored, the present invention is not limited to this. The switching drive of the transistor 34 is intermittently performed while the FET 16 is turned off, so that the voltage V across the capacitor 18 when the FET 16 is turned off. Monitoring may be performed in a sampling manner.

  That is, while the FET 16 is turned off, the driving state of the transistor 34 is driven at a predetermined sampling frequency so that the voltage V across the capacitor 18 is not monitored and driven so that the voltage V across the capacitor 18 is monitored. Switch with. According to such a modification, a current can flow from the transistor 34 side to the capacitor 18 and the system load 14 side via the diode 32 at the monitoring timing of the voltage V across the capacitor 18 by driving the transistor 34. Therefore, the charging of the capacitor 18 and the operation of the system load 14 accompanying the driving of the transistor 34 can be suppressed.

  In the first and second embodiments, when the FET 16 is turned off, the discharge time T required for the voltage V across the capacitor 18 to fall below the predetermined threshold Vth after the switching from on to off is set to a predetermined value. Compared with the lower limit value Tmin and the timeout value Tmax of the normal range, or the voltage V across the capacitor 18 at the time when the predetermined discharge time Tth has passed, is compared with the lower limit value Vmin and the upper limit value Vmax of the predetermined normal range. Thus, normal / abnormal short circuit / abnormal disconnection of the system load 14 or wiring is determined. However, the abnormal short circuit or disconnection may be determined by distinguishing between the case where the abnormal short circuit occurs or the case where the abnormal disconnection occurs due to chattering.

  When the abnormal short circuit continues, when the FET 16 is turned off, the discharge time T required for the voltage V across the capacitor 18 to fall below the predetermined threshold Vth is almost zero, while the abnormal short circuit occurs in a chattering manner. When the FET 16 is turned off, a certain amount of discharge time is required until the voltage V across the capacitor 18 falls below the predetermined threshold value Vth. If abnormal disconnection continues, when the FET 16 is turned off, the discharge time T required for the voltage V across the capacitor 18 to fall below the predetermined threshold Vth is very long or the voltage V across the voltage V exceeds the predetermined threshold Vth. If the abnormal disconnection occurs in a chattering manner, the discharge time T required for the voltage V across the capacitor 18 to fall below the predetermined threshold Vth when the FET 16 is turned off continues the abnormal disconnection. Short compared to what is happening.

  When the abnormal short circuit continues, when the FET 16 is turned off, the voltage V across the capacitor 18 at the time when the predetermined discharge time Tth has passed is almost zero, while the abnormal short circuit occurs in a chattering manner. When the FET 16 is turned off, the voltage V across the capacitor 18 at a point in time when a predetermined discharge time Tth has elapsed becomes a certain large value. If the abnormal disconnection continues, when the FET 16 is turned off, the voltage V across the capacitor 18 at the time when the predetermined discharge time Tth has passed is not so different from the voltage + B of the power supply 12, while the abnormal disconnection occurs. When chattering occurs, the voltage V across the capacitor 18 when the predetermined discharge time Tth has elapsed when the FET 16 is off is smaller than when the abnormal disconnection continues.

  Therefore, when the FET 16 is turned off, after the switching from on to off, the discharge time T required for the voltage V across the capacitor 18 to fall below the predetermined threshold Vth is compared with the lower limit value and upper limit value of the predetermined normal range. The voltage V across the capacitor 18 at the time when a predetermined discharge time Tth has elapsed is compared with a threshold value for distinguishing continuous abnormal short-circuit or abnormal disconnection from chattering abnormal short-circuit or abnormal disconnection. The system load 14 or by comparing with a threshold value for distinguishing continuous abnormal short circuit or abnormal disconnection from chattering abnormal short circuit or abnormal disconnection while comparing with a lower limit value and an upper limit value of a predetermined normal range. Normal / continuous abnormal short circuit / chattering abnormal short circuit / continuous abnormal disconnection / chattering abnormal disconnection such as wiring It may be.

  In the first and second embodiments, the abnormal short circuit of the system load 14 or the wiring is determined based on the voltage V across the capacitor 18 when the FET 16 is off. Further, the determination may be made based on the drain-source voltage Vds when the FET 16 is on. In such a modification, the FET 16 is turned off when it is determined that an abnormal short circuit has occurred. The abnormal short circuit determination based on the voltage V across the capacitor 18 when the FET 16 is off and the drain-source connection when the FET 16 is on. This may be performed when both of the abnormal short circuit determination based on the voltage Vds (AND condition) are satisfied, and may not be performed when either one is not satisfied, or the voltage V across the capacitor 18 when the FET 16 is OFF. Is performed when one of the abnormal short circuit determination based on the above and the abnormal short circuit determination based on the drain-source voltage Vds when the FET 16 is on (OR condition) is satisfied, and may not be performed when both are not satisfied. . According to such a modification, it is possible to improve the accuracy and reliability of the abnormal short-circuit determination such as the system load 14 or the wiring, and the drive control of the FET 16 can be performed finely and appropriately.

  In this modification, instead of determining the abnormal short-circuit based on the drain-source voltage Vds when the FET 16 is on, the overcurrent detection interposed between the source of the FET 16 and the system load 14 is detected. The determination may be made based on the voltage across the overcurrent detection resistor when the FET 16 is turned on after providing the resistor.

  In these modified examples, the IC / microcomputer 22 detects the drain-source voltage Vds or the voltage across the overcurrent detection resistor when the FET 16 is on, and the “on voltage detection means” is described in the claims. Are both the abnormal short-circuit determination result based on the voltage V across the capacitor 18 when the FET 16 is off and the abnormal short-circuit determination result based on the drain-source voltage Vds or the both-ends voltage of the overcurrent detection resistor when the FET 16 is on. Based on this, by supplying a relay ON / OFF signal to the FET 16, the “control means” described in the claims is realized.

  Further, in the first and second embodiments, the FET 16 is an n-channel MOS-FET, but it may be a junction FET.

DESCRIPTION OF SYMBOLS 10 Semiconductor fuse apparatus 12 Power supply 14 System load 16 Semiconductor switching element (FET)
18 Capacitor 22 IC / Microcomputer + B DC voltage T Discharge time Tth Predetermined discharge time V Capacitor voltage Vth Predetermined threshold

Claims (5)

A semiconductor switching element interposed between a power source and a system load supplied with power from the power source, and shuts off the power source and the system load at least when an overcurrent of the system load is detected;
A capacitor connected in parallel to the system load;
In the state where the semiconductor switching element shuts off the power supply and the system load, a discharge time required for the voltage across the capacitor to fall below a predetermined threshold after the start of the shutoff, or a predetermined discharge time has elapsed. Discharge monitoring means for detecting a residual voltage generated across the capacitor at the time,
Normal / abnormality determination means for determining normality / abnormality of the system load or wiring connected to the system load based on the discharge time or the residual voltage detected by the discharge monitoring means;
A semiconductor fuse device comprising:   The normality / abnormality determination means determines that the discharge time detected by the discharge monitoring means is normal when the discharge time is within a predetermined normal range, and an abnormal short circuit occurs when the discharge time does not reach the predetermined normal range. 2. The semiconductor fuse device according to claim 1, wherein the determination is made, and if the predetermined normal range is exceeded, it is determined that an abnormal disconnection has occurred.   The normality / abnormality determination means determines that the residual voltage detected by the discharge monitoring means is normal when it is within a predetermined normal range, and determines that an abnormal short circuit has occurred when it is below the predetermined normal range. The semiconductor fuse device according to claim 1, wherein if it exceeds the predetermined normal range, it is determined that an abnormal disconnection has occurred.   Control means for supplying a control signal for shutting off the power supply and the system load to the semiconductor switching element when the normality / abnormality determination means determines that an abnormality has occurred in the system load or the wiring. The semiconductor fuse device according to claim 1, wherein the semiconductor fuse device is a semiconductor fuse device. A voltage across the semiconductor switching element or an overcurrent detection resistor interposed between the semiconductor switching element and the system load is detected with the semiconductor switching element conducting the power supply and the system load. On-voltage detection means for
5. The control unit controls a control signal supplied to the semiconductor switching element based on both a determination result by the normal / abnormal determination unit and a detection result by the on-voltage detection unit. Semiconductor fuse device.

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