JP2013138906A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine preventing fraudulent generation of a jackpot by forcibly initializing a backup RAM using an external connection board or the like.SOLUTION: Values of counters (counter circuit of a random number circuit, jackpot determination calculation counter as a software counter) for generating a jackpot determination random number are updated. A game control microcomputer determines shift of a game to a jackpot game status, based on a jackpot determination random number generated using the updated values of the counters. A game machine includes a game starting switch for outputting a game start directing signal according to directional operation for starting control of a game. After a memory content of a RAM is initialized in initialization processing, the values of the counters are started to be updated on condition that the game start directing signal is output from the game starting switch.

Description

  The present invention relates to a gaming machine in which a player can play a predetermined game and can shift to a specific gaming state that is advantageous to the player based on the result of the game being in a predetermined mode.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of prize balls are paid out to the player. There is something to be done. Furthermore, there is provided a variable display unit capable of changing the display state, and configured to give a predetermined game value to the player when the display result of the variable display unit is in a predetermined specific display mode. is there.

  The game value is the right that the state of the variable winning ball apparatus provided in the gaming area of the gaming machine becomes advantageous for a player who is easy to win, and the right for becoming advantageous for a player. In other words, or a condition for winning a prize ball is easily established.

  In the gaming machine, when a predetermined transition condition is established, the gaming state is shifted to a specific gaming state that is advantageous to the player. For example, in a pachinko gaming machine, a display result of a variable display unit that displays a special symbol becomes a combination of a predetermined specific display mode (a big hit symbol), which is usually referred to as “big hit”. When the big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the game shifts to a big hit gaming state where the hit ball is easy to win.

  In such a gaming machine, a clear switch for clearing the backup RAM is provided, and based on the fact that the clear switch is on when power supply to the gaming machine is started, the gaming state before power-off is restored. In some cases, the data stored in the backup RAM is cleared (initialized) without performing the recovery process (see, for example, Patent Document 1).

  In addition, some gaming machines are provided with a game start switch, and are configured so that a game cannot be started unless the game start switch is operated after power supply to the game machine is started. For example, in Patent Document 2, a game can be started based on the fact that the consent button provided on the upper plate of the gaming machine is turned on after the power supply to the gaming machine is started. Have been described.

JP 2001-286649 A (paragraph 0098-0099, FIG. 16) JP 2003-38833 A (paragraph 0043, paragraph 0062, FIG. 2, FIG. 5)

  In the gaming machine described in Patent Document 1, when the backup RAM is initialized based on the fact that the clear switch is turned on at the start of power supply to the gaming machine, a random number used for jackpot determination or the like is used. The value is also initialized, and there is a possibility that the jackpot is illegally targeted by connecting the illegal external connection board to the gaming machine and inputting the signal illegally at the timing when the jackpot is generated .

  Patent Document 2 describes that the game can be started on condition that the game start switch is turned on, but the game machine is forcibly turned off to illegally hit the jackpot. It is impossible to prevent a situation where the occurrence is targeted.

  Therefore, an object of the present invention is to provide a gaming machine that can prevent an act of illegally generating a big hit by forcibly initializing a backup RAM using an external connection board or the like.

  The gaming machine according to the present invention is advantageous to the player based on the fact that the player can play a predetermined game and the result of the game is in a predetermined mode (for example, a jackpot symbol is displayed). A data storage means (e.g., RAM 55) that is capable of transitioning to a specific gaming state (e.g., a big hit gaming state) that retains data even when power supply to the gaming machine is stopped by a backup power source; Initialization operation means (for example, a clear switch 921) for outputting an initialization instruction signal (for example, a detection signal of the clear switch 921) in response to an instruction operation for initializing the storage contents of the data storage means, and initialization Based on the output of the initialization instruction signal from the operation means, initialization processing means (for example, a game control microphone) for initializing the recorded contents of the data storage means A part for executing steps S10 to S13 in the computer 560) and a counter (for example, a jackpot determination random number MR1) used for determining whether or not to shift to the specific gaming state (for example, jackpot determination random number MR1) Counter 521 of random number circuit 5003. Counter updating means (for example, clock signal output circuit of random number circuit 5003) for updating the value of the jackpot determination calculation random number (random 2-1) for counting up the jackpot determination calculation A part in which the counter 521 of the random number circuit 5003 updates the count value based on the fact that the clock signal SI1 for random number generation is output from the counter 524. The step S24 in the game control microcomputer 560 is executed to count the jackpot determination calculation counter. The part that executes processing to update the value.) Based on the determination random number generated using the counter value updated by the counter updating means, the game state determination means for determining whether or not to shift to the specific game state (for example, step S62 in the game control microcomputer 560). , S63), and the initialization operation means is also used as a game start operation means for outputting a game start instruction signal in response to an instruction operation for starting game control. .

  In the gaming machine according to claim 1, the counter updating means for updating a counter value for generating a random number for determination used for determining whether or not to shift to the specific gaming state, and the counter updating means are updated. A game state determination unit that determines whether or not to shift to a specific game state based on a random number for determination generated using the value of the counter, and an initialization operation unit for starting game control Since it is configured to be used as a game start operation means for outputting a game start instruction signal in response to an instruction operation, it is initialized by forcibly initializing the backup RAM using an external connection board or the like. By inputting a signal from the external connection board (hanging board) at the timing when it is determined to shift to the specific gaming state (big hit gaming state) Ri can be prevented that being targeted.

It is the front view which looked at the pachinko game machine from the front. It is a rear view which shows a pachinko gaming machine. It is a block diagram which shows the circuit structural example of a game control board (main board). It is a block diagram showing an example of circuit configuration of an effect control board, a lamp driver board and an audio output board. It is a block diagram which shows the structural example of a power supply board. It is a disassembled perspective view which shows a board | substrate storage case. It is a disassembled perspective view which shows a board | substrate storage case. It is a disassembled perspective view which shows the assembly | attachment state of a board | substrate storage case and a main board | substrate. It is a perspective view which shows the attachment state of the main board | substrate with respect to a case cover. It is a perspective view which shows the connection condition of the wiring side connector. It is a perspective view which shows the attachment condition of a connector control member. It is a longitudinal cross-sectional view which shows the state which closed the case main body and the case cover. It is a perspective view which shows the sealing state of a board | substrate storage case. It is sectional drawing which shows the AA cross section of the board | substrate storage case shown in FIG. It is a partially broken side view which shows a board | substrate storage case. It is sectional drawing which shows the BB cross section and CC cross section of the board | substrate storage case shown in FIG. It is a block diagram showing a circuit configuration of the main board and a signal line of an effect control command transmitted from the main board to the effect control board. It is a block diagram which shows the structural example of a random number circuit. It is explanatory drawing which shows the example of an update rule selection register. It is explanatory drawing which shows the example of an update rule memory. It is explanatory drawing which shows the example in case a count value permutation change circuit changes the permutation of the count value which a counter outputs. It is explanatory drawing which shows the example of a count value permutation change register. It is explanatory drawing which shows the example of a random number maximum value setting register. It is explanatory drawing which shows the example of a period setting register. It is explanatory drawing which shows the example of a count value update register. It is explanatory drawing which shows the example of a random number update system selection register and random number update system selection data. It is explanatory drawing which shows the example of a random number circuit starting register. It is a circuit diagram which shows one structural example of a random value memory circuit. It is a timing chart which shows the timing when each signal is input into a random value storage circuit, and the timing when a random value storage circuit outputs each signal. It is explanatory drawing which shows an example of the address map of the storage area in the microcomputer for game control. It is explanatory drawing which shows an example of the address map in a user program management area. It is explanatory drawing which shows an example of initial value change system setting data. It is explanatory drawing which shows the structural example of a user program. It is explanatory drawing which shows the structural example of a random number circuit setting program. It is explanatory drawing which shows the operation | movement which CPU updates the value of random R or reads the value of random R, when the 1st random number update system is selected. It is explanatory drawing which shows the operation | movement which CPU reads the value of random R, when the 2nd random number update system is selected. It is a flowchart which shows the main process which CPU in the microcomputer for game control performs. It is a flowchart which shows the main process which CPU in the microcomputer for game control performs. It is explanatory drawing which shows an example of the content of an effect control command. It is a flowchart which shows a random circuit setting process. It is a flowchart which shows a random number maximum value reset process. It is a flowchart which shows an initial value change process. It is a flowchart which shows a 2 ms timer interruption process. It is a flowchart which shows a random circuit initial value update process. It is a flowchart which shows a count value permutation change process. It is explanatory drawing which shows each software random number. It is explanatory drawing which shows the big hit determination table and the big hit classification determination table. It is a flowchart which shows a special symbol process process. It is a flowchart which shows a starting port switch passage process. It is a flowchart which shows a starting port switch passage process. It is explanatory drawing which shows the structural example of a pending | holding storage specific information storage area (holding specific area). It is explanatory drawing which shows the creation method of random MR1 compared with jackpot determination value. It is a flowchart which shows a special symbol normal process. It is a flowchart which shows a special symbol normal process. It is a flowchart which shows a fluctuation pattern setting process. It is a flowchart which shows a display result specific command transmission process. It is a flowchart which shows the special symbol change process. It is a flowchart which shows a special symbol stop process. It is a flowchart which shows the big winning opening opening pre-processing. It is a flowchart which shows a big winning opening open process. It is a flowchart which shows a big winning opening open process. It is a flowchart which shows a big hit end process. It is a flowchart which shows the presentation control main process which CPU for presentation control performs. It is a flowchart which shows a command analysis process. It is a flowchart which shows a command analysis process. It is explanatory drawing which shows the random number which the microcomputer for production control uses. It is a flowchart which shows production control process processing. It is a flowchart which shows a random number update process. It is explanatory drawing which shows the example of the table for random number addition value determination. It is a block diagram which shows the example of the circuit structure in the main board | substrate (game control board | substrate) in the case of using both a clear switch and a game start switch. It is a flowchart which shows the main process in the case of using both a clear switch and a game start switch. It is the front view which looked at the slot machine from the front.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. First, the overall configuration of a pachinko gaming machine 1 that is an example of a gaming machine will be described. FIG. 1 is a front view of the pachinko gaming machine 1 as seen from the front. FIG. 2 is a rear view showing the pachinko gaming machine.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be opened and closed. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) that can be opened and closed with respect to the outer frame, a mechanism plate (not shown) to which mechanism parts and the like are attached, and various parts (games to be described later) attached to them. A structure including the board 6).

  On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, there are provided a surplus ball receiving tray 4 for storing game balls that cannot be accommodated in the hitting ball supply tray 3, and a hitting operation handle (operation knob) 5 for firing the hitting ball. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. In addition, a game area 7 is formed on the front surface of the game board 6 in which a game ball that has been struck can flow down.

  An effect display device 9 composed of a liquid crystal display device (LCD) is provided near the center of the game area 7. The display screen of the effect display device 9 includes an effect symbol display area for performing variable display of the effect symbol in synchronization with the variable display of the first special symbol or the second special symbol. Therefore, the effect display device 9 corresponds to a variable display device that performs variable display of effect symbols. In the effect symbol display area, there is a symbol display area for variably displaying, for example, three decoration (effect) identification information of “left”, “middle”, and “right”. The symbol display area includes “left”, “middle”, and “right” symbol display areas 9L, 9C, and 9R, but the position of the symbol display area 9A is not fixed on the display screen of the effect display device 9. Alternatively, the three areas of the symbol display areas 9L, 9C, and 9R may be separated. The effect display device 9 is controlled by an effect control microcomputer mounted on the effect control board. When the first special symbol display 8a is executing variable display of the first special symbol, the effect control microcomputer causes the effect display device 9 to execute the effect display along with the variable display, and the second special symbol display 8a executes the second special display. When the variable display of the second special symbol is executed on the symbol display 8b, the effect display is executed by the effect display device in accordance with the variable display, so that it is possible to easily grasp the progress of the game.

  On the left side of the lower part of the game board 6, a first special symbol display (first variable display portion) 8a for variably displaying the first special symbol as identification information is provided. In this embodiment, the first special symbol display 8a is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9. In other words, the first special symbol display 8a is configured to variably display numbers (or symbols) from 0 to 9. On the lower right side of the game board 6, a second special symbol display (second variable display portion) 8b for variably displaying the second special symbol as identification information is provided. The second special symbol display 8b is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9. That is, the second special symbol display 8b is configured to variably display numbers (or symbols) from 0 to 9.

  The small display is formed in a square shape, for example. In this embodiment, the type of the first special symbol and the type of the second special symbol are the same (for example, both 0 to 9), but the types may be different. Further, the first special symbol display 8a and the second special symbol display 8b may be configured to variably display numbers (or two-digit symbols) of, for example, 00 to 99, for example.

  Hereinafter, the first special symbol and the second special symbol may be collectively referred to as a special symbol, and the first special symbol indicator 8a and the second special symbol indicator 8b are collectively referred to as a special symbol indicator (variable display unit). There are things to do.

  For the variable display of the first special symbol or the second special symbol, the first start condition or the second start condition, which is the variable display execution condition, is satisfied (for example, the game ball has the first start winning opening 13 or the second start winning opening) 14), a variable display start condition (for example, when the number of reserved memories is not 0 and the variable display of the first special symbol and the second special symbol is not executed) , A state where the big hit game is not executed) is established, and when the variable display time elapses, a display result (stop symbol) is derived and displayed. Note that winning means that a game ball has entered a predetermined area such as a winning opening. Deriving and displaying a display result is to stop and display a symbol (an example of identification information) (excluding stop before so-called re-variation). In this embodiment, the variable display start condition is established in the order in which the start prizes are generated regardless of the prizes in the first start prize slot 13 and the second start prize slot 14. The variable display start condition may be established by giving priority to one of winning in the winning opening 13 and winning in the second start winning opening 14. For example, when giving priority to winning in the first start winning opening 13, the variable display of the first special symbol and the second special symbol is not executed, and the jackpot game is not executed. For example, even when the second reserved memory number is not zero, the variable display of the first special symbol is continuously executed until the first reserved memory number becomes zero.

  In the vicinity of the first special symbol display 8a, during the variable display time of the first special symbol by the first special symbol display 8a, the variable display of the first decorative symbol as a decorative (design) symbol is performed. A first decorative symbol display 9a is provided. In this embodiment, the first decorative symbol display 9a is composed of two LEDs. The first decorative symbol display 9a is controlled by an effect control microcomputer mounted on the effect control board. Further, in the vicinity of the second special symbol display 8b, during the variable display time of the second special symbol by the second special symbol display 8b, the variable display of the second decorative symbol as a symbol for decoration (production) is performed. There is provided a second decorative symbol display 9b. The second decorative symbol display 9b is composed of two LEDs. The second decorative symbol display 9b is controlled by an effect control microcomputer mounted on the effect control board.

  The first decorative symbol and the second decorative symbol may be collectively referred to as a decorative symbol, and the first decorative symbol display 9a and the second decorative symbol display 9b may be collectively referred to as a decorative symbol display. .

  The variation of the decorative pattern (variable display) is realized by continuing the state where the two LEDs are alternately lit. The variable display of the first special symbol on the first special symbol display 8a and the variable display of the first decorative symbol on the first decorative symbol display 9a are synchronized. The variable display of the second special symbol on the second special symbol display 8b is synchronized with the variable display of the second decorative symbol on the second decorative symbol display 9b. Synchronous means that the variable display start time and end time are the same, and the variable display period is the same. In addition, when the big hit symbol is stopped and displayed on the first special symbol display 8a, the LED on the side that recalls the big hit on the first decorative symbol display 9a remains lit. When the big-hit symbol is stopped and displayed on the second special symbol display 8b, the LED on the side that recalls the big-hit on the second decorative symbol display 9b remains lit. The functions of the first decorative symbol display 9a and the second decorative symbol display 9b may be realized by the effect display device 9. That is, the first decorative symbol and the second decorative symbol may be controlled to be variably displayed as images on the display screen of the effect display device 9.

  A winning device having a first start winning port 13 is provided below the effect display device 9. The game ball won in the first start winning opening 13 is guided to the back of the game board 6 and detected by the first start opening switch 13a.

  A variable winning ball device 15 having a second starting winning port 14 through which a game ball can be won is provided below a winning device having a first starting winning port (first starting port) 13. The game ball that has won the second start winning opening (second start opening) 14 is guided to the back of the game board 6 and detected by the second start opening switch 14a. The variable winning ball device 15 is opened by a solenoid 16. When the variable winning ball device 15 is in the open state, the game ball can be awarded to the second starting winning port 14 (it is easier to start winning), which is advantageous for the player. In the state where the variable winning ball apparatus 15 is in the open state, it is easier for the game ball to win the second start winning opening 14 than the first starting winning opening 13. In addition, in a state where the variable winning ball device 15 is in the closed state, the game ball does not win the second start winning opening 14. Therefore, in a state where the variable winning ball device 15 is in the closed state, it is easier for the game ball to win the first starting winning port 13 than the second starting winning port 14. In the state where the variable winning ball apparatus 15 is in the closed state, it may be configured that the winning is possible (that is, it is difficult for the gaming ball to win) although it is difficult to win a prize.

  Hereinafter, the first start winning opening 13 and the second start winning opening 14 may be collectively referred to as a start winning opening or a starting opening.

  When the variable winning ball device 15 is controlled to be in the open state, the game ball heading for the variable winning ball device 15 is very likely to win the second start winning port 14. The first start winning opening 13 is provided directly under the effect display device 9, but the interval between the lower end of the effect display device 9 and the first start winning opening 13 is further reduced, or the first start winning opening is set. The nail arrangement around the first start winning opening 13 is made difficult to guide the game balls to the first starting winning opening 13 so that the winning rate of the second starting winning opening 14 is increased. It is also possible to make the direction higher than the winning rate of the first start winning opening 13.

  In this embodiment, as shown in FIG. 1, the variable winning ball apparatus 15 that opens and closes only the second start winning opening 14 is provided. Any of the start winning ports 14 may be provided with a variable winning ball device that performs an opening / closing operation.

  On the side of the first decorative symbol display 9a, the number of effective winning balls that have entered the first start winning opening 13, that is, the first reserved memory number (the reserved memory is also referred to as the start memory or the start prize memory) is displayed. A first special symbol storage memory display 18a comprising four displays is provided. The first special symbol storage memory display 18a increases the number of indicators to be turned on by 1 every time there is an effective start winning. Then, each time the variable display on the first special symbol display 8a is started, the number of indicators to be turned on is reduced by one.

  On the side of the second decorative symbol display 9b is a second special symbol reserved memory display 18b comprising four indicators for displaying the number of effective winning balls that have entered the second start winning opening 14, that is, the second reserved memory number. Is provided. The second special symbol storage memory display 18b increases the number of indicators to be lit by 1 every time there is an effective start winning. Then, each time the variable display on the second special symbol display 8b is started, the number of indicators to be turned on is reduced by one.

  In addition, the display screen of the effect display device 9 displays an area (hereinafter referred to as a summed pending storage display unit 18c) that displays a total number (total number of pending pending memories) that is the sum of the first reserved memory number and the second reserved memory number. .) Is provided. Since the summation pending storage display unit 18c for displaying the total number is provided, it is possible to easily grasp the total number of execution conditions that are not satisfied with the variable display start condition. In addition, since the total reserved memory display unit 18c is provided, the first special symbol reserved memory display 18a and the second special symbol reserved memory display 18b may not be provided.

  The effect display device 9 is for decoration (for effects) during the variable display time of the first special symbol by the first special symbol display 8a and during the variable display time of the second special symbol by the second special symbol display 8b. A variable display of the effect symbol as the symbol is performed. The variable display of the first special symbol on the first special symbol display 8a and the variable display of the effect symbol on the effect display device 9 are synchronized. Further, the variable display of the second special symbol on the second special symbol display 8b and the variable display of the effect symbol on the effect display device 9 are synchronized. Further, when the jackpot symbol is stopped and displayed on the first special symbol display 8a and when the jackpot symbol is stopped and displayed on the second special symbol display 8b, the effect display device 9 reminds the jackpot The combination of is stopped and displayed.

  On the right side of the decorative portion around the effect display device 9, an upper effect LED 85a, a middle effect LED 85b, and a lower effect LED 85c are provided. The upper effect LED 85a, the middle effect LED 85b, and the lower effect LED 85c execute display effects related to a pseudo-continuous effect as a specific effect (each re-variation period (including the initial variation period) during one variation period). Blinks when an effect is performed. On the left side, a movable member 78 that is attached to the rotating shaft of the motor 86 and moves when the motor 86 rotates is provided. The movable member 78 operates when a pseudo-series effect is executed. In addition, a vibration motor (not shown) that signals a mounting portion of each LED is provided in the vicinity of the upper effect LED 85a, the middle effect LED 85b, and the lower effect LED 85c.

  Further, as shown in FIG. 1, a special variable winning ball device 20 is provided below the variable winning ball device 15. The special variable winning ball apparatus 20 includes an opening / closing plate, and when the specific display result (big hit symbol) is derived and displayed on the first special symbol display 8a, and the specific display result (big hit symbol) on the second special symbol display 8b. When the open / close plate is controlled to be open by the solenoid 21 in the specific game state (big hit game state) that occurs when the symbol is derived and displayed, the big winning opening serving as the winning area is opened. The game ball that has won the big winning opening is detected by the count switch 23.

  The game area 6 is also provided with winning ports (ordinary winning ports) 29, 30, 33, 39 for paying out a predetermined number of premium game balls determined in advance based on winning of the game balls. The game balls won in the winning openings 29, 30, 33, 39 are detected by the winning opening switches 29a, 30a, 33a, 39a.

  A normal symbol display 10 is provided on the right side of the game board 6. The normal symbol display 10 variably displays a plurality of types of identification information (for example, “◯” and “x”) called normal symbols.

  When the game ball passes through the gate 32 and is detected by the gate switch 32a, variable display of the normal symbol display 10 is started. In this embodiment, variable display is performed by alternately lighting the upper and lower lamps (the symbols can be visually recognized when turned on). For example, if the lower lamp is turned on at the end of the variable display, it is a hit. . When the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In other words, the state of the variable winning ball apparatus 15 is a state that is advantageous from a disadvantageous state for the player when the normal symbol is a stop symbol (a state in which a game ball can be awarded at the second start winning port 14). To change. In the vicinity of the normal symbol display 10, a normal symbol holding storage display 41 having a display unit with four LEDs for displaying the number of winning balls that have passed through the gate 32 is provided. Each time there is a game ball passing through the gate 32, that is, every time a game ball is detected by the gate switch 32a, the normal symbol storage memory display 41 increases the number of LEDs to be turned on by one. Each time variable display on the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one.

  On the left and right sides of the game area 7 of the game board 6, there are provided decorative LEDs 25 that are displayed blinking during the game, and at the lower part there is an outlet 26 for taking in a hit ball that has not won. In addition, two speakers 27 that utter sound effects and sounds as predetermined sound outputs are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a frame LED 28 provided on the front frame is provided.

  In the gaming machine, a ball striking device (not shown) that drives a driving motor in response to a player operating the batting operation handle 5 and uses the rotational force of the driving motor to launch a gaming ball to the gaming area 7. ) Is provided. A game ball launched from the ball striking device enters the game area 7 through a ball striking rail formed in a circular shape so as to surround the game area 7, and then descends the game area 7. When the game ball enters the first start winning opening 13 and is detected by the first start opening switch 13a, if the variable display of the first special symbol can be started (for example, the variable display of the special symbol ends, 1), the variable display (variation) of the first special symbol is started on the first special symbol display 8a, and the variable display of the first decorative symbol is displayed on the first decorative symbol display 9a. The effect display device 9 starts variable display of effect symbols. In other words, the variable display of the first special symbol, the first decorative symbol, and the effect symbol corresponds to winning in the first start winning opening 13. If the variable display of the first special symbol cannot be started, the first reserved memory number is increased by 1 on the condition that the first reserved memory number has not reached the upper limit value.

  When the game ball enters the second start winning opening 14 and is detected by the second start opening switch 14a, if the variable display of the second special symbol can be started (for example, the special symbol variable display ends, 2), the second special symbol display 8b starts variable display (variation) of the second special symbol, and the second decorative symbol display 9b displays variable display of the second decorative symbol. The effect display device 9 starts variable display of effect symbols. That is, the variable display of the second special symbol, the second decorative symbol, and the effect symbol corresponds to winning in the second start winning opening 14. If the variable display of the second special symbol cannot be started, the second reserved memory number is increased by 1 on condition that the second reserved memory number has not reached the upper limit value.

  Further, in this embodiment, when the display result of the special symbol variation becomes the probability variation big hit or sudden probability variation big hit, the gaming state is shifted to the probability variation state. In this probability variation state, control is performed so as to attain a high probability state with a high probability of being determined to be a big hit as compared to at least the normal state. In addition, in the probability variation state, while controlling to a high probability state, the variation time of the special symbol is shortened, the probability that the stop symbol in the ordinary symbol display 10 becomes a winning symbol is increased, or the variation time of the ordinary symbol is increased. The opening time and the number of times of opening of the variable winning ball apparatus 15 may be increased. In this case, any one or more of these may be executed in the probability changing state, or all of them may be executed.

  Further, in this embodiment, after the big hit game is finished, it is controlled to a time short state where at least the variation time of the normal symbol is shortened. It should be noted that, in the short time state, the variation time of the special symbol is shortened, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, or the opening time and the number of times of opening of the variable winning ball apparatus 15 are increased. You may make it do. In this case, any one or more of these may be executed in the time-saving state, or all of them may be executed.

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. As shown in FIG. 2, on the back side of the pachinko gaming machine 1, there are a variable display control unit including an effect control board 80 on which an effect control microcomputer 110 for controlling the effect display device 9 is mounted, a game control microcomputer, and the like. Various game control boards (main boards) 31, voice output boards 70, LED driver boards (not shown), and payout control boards 37 on which a payout control microcomputer for performing ball payout control is mounted A board is installed. The game control board 31 is stored in the board storage case 200. The game control board 31 is provided with a game start switch 90 for instructing the start of the game.

  Further, on the back side of the pachinko gaming machine 1, a power supply substrate 910 and a touch sensor substrate 91A on which power supply circuits for generating various power supply voltages such as DC30V, DC21V, DC12V, and DC5V are mounted. The power supply board 910 is supplied with the game control board 31 and each electrical component control board (the effect control board 80 and the payout control board 37) in the pachinko gaming machine 1 and each electrical component (power is supplied) provided in the pachinko gaming machine 1. A power switch as a power supply permission means for executing or shutting off the power supply to the component that operates by the operation), and a clear switch 921 for clearing the RAM 55 of the game control microcomputer 560 of the game control board 31. It has been. Further, a replaceable fuse is provided inside the power switch (inside the substrate).

  The case cover in the substrate storage case 200 for storing the main substrate 31 is formed with a plurality of square tubular fixed portions 255a to 255d at locations facing the screw holes of the case body 201 in the substrate storage case 200. ing. The first fixed portion 255 is constituted by these fixing portions. In addition, the role of the 1st to-be-adhered part 255 etc. are mentioned later. The main board 31 is provided with a game start switch 90 for instructing the start of the game.

  An electrical component control means including an electrical component control microcomputer is mounted on the electrical component control board. The electrical component control means is an electrical component (game device: ball payout device 97, effect display device 9, LED, etc.) provided in the pachinko gaming machine 1 in accordance with a command signal (control signal) as a command from the game control means or the like. The light emitter, speaker 27, etc.). Hereinafter, the game control board 31 may be included in the electric component control board for explanation. In that case, the electrical component control means mounted on the electrical component control board includes a game control means and a means for controlling the electrical components provided in the pachinko gaming machine 1 in accordance with a command signal from the game control means or the like. Point to each. A board on which a microcomputer other than the game control board 31 is mounted may be referred to as a sub board.

  On the back side of the pachinko gaming machine 1, a terminal board 159 having terminals for outputting various information to the outside of the pachinko gaming machine 1 is installed above. The terminal board 159 includes at least a ball break terminal for introducing the output of the ball break detection switch 167 and outputting it externally, a prize ball terminal for outputting award ball information (prize ball number signal), and a ball. A ball lending terminal for externally outputting lending information (ball lending number signal) is provided.

  The game ball stored in the storage tank 38 passes through a guide rail (not shown), and reaches a ball payout device 97 covered with a payout case 40A through a curve rod. Above the ball payout device 97, a ball break switch 187 is provided as a game medium break detection means. When the ball break switch 187 detects a ball break, the payout operation of the ball payout device 97 stops. The ball break switch 187 is a switch that detects the presence or absence of a game ball in the game ball passage. (Proximate part). When the ball break detection switch 167 detects a shortage of game balls, the game balls are replenished to the pachinko gaming machine 1 from the replenishment mechanism provided on the gaming machine installation island.

  When a large number of game balls as prizes based on winning a prize or a game ball based on a ball lending request are paid out and the hitting ball supply tray 3 is full, the game balls are guided to the surplus ball receiving tray 4 through the surplus ball guiding path. Further, when the game ball is paid out, a sensing lever (not shown) presses the full tank switch as the storage state detection means, and the full tank switch as the storage state detection means is turned on. In this state, the rotation of the payout motor in the ball payout device is stopped, the operation of the ball payout device is stopped, and the driving of the ball hitting device is also stopped.

  FIG. 3 is a block diagram showing an example of the circuit configuration of the main board (game control board) 31. FIG. 3 also shows the payout control board 37, the effect control board 80, and the like. A game control microcomputer (corresponding to game control means) 560 for controlling the pachinko gaming machine 1 according to a program is mounted on the main board 31. The game control microcomputer 560 includes a ROM 54 for storing a game control (game progress control) program and the like, a RAM 55 as storage means used as a work memory, a CPU 56 for performing control operations in accordance with the program, and an I / O port unit 57. including. In this embodiment, the ROM 54 and the RAM 55 are built in the game control microcomputer 560. That is, the game control microcomputer 560 is a one-chip microcomputer. The one-chip microcomputer only needs to incorporate at least the CPU 56 and the RAM 55, and the ROM 54 may be external or built-in. The I / O port unit 57 may be externally attached.

  Further, the game control microcomputer 560 has a built-in random number circuit 5003 for generating hardware random numbers (random numbers generated by the hardware circuit). In this embodiment, as will be described later, the game control microcomputer 560 determines whether or not to win the game based on the jackpot determination random number generated using the hardware random number generated by the random number circuit 5003. . For example, in the random number circuit 5003, the counter 521 updates the count value C one by one based on the input of the random number generation clock signal SI1 output from the clock signal output circuit 524 via the selector 528. Then, the game control microcomputer 560 generates a big hit determination random number using the count value C updated by the counter 521 as a hardware random number, and determines whether or not to make a big hit.

  Note that the game control microcomputer 560 may not include the random number circuit 5003. In this case, for example, the game control microcomputer 560 reads a hardware random number from a random number circuit externally attached to the game control microcomputer 560, and based on the jackpot determination random number generated using the hardware random number. Then, it may be determined whether or not to win.

  The RAM 55 is a backup RAM as a non-volatile storage means, part or all of which is backed up by a backup power source created on the power supply substrate 910. That is, even if the power supply to the gaming machine is stopped, a part or all of the contents of the RAM 55 is stored for a predetermined period (until the capacitor as the backup power supply is discharged and the backup power supply cannot be supplied). In particular, at least data corresponding to the game state, that is, the control state of the game control means (special symbol process flag, etc.), data indicating the number of unpaid prize balls, each software random number such as a random number for determination (random number for jackpot determination calculation described later) (Random 2-1), normal random number per symbol determination (Random 6), and counters for counting each software random number (a big hit determination calculation counter, a normal symbol determination counter, etc. described later) Are stored in the backup RAM. A jackpot determination random number MR1 calculated using a jackpot determination calculation random number (random 2-1) and a hardware random number described later (see step S2015) is also stored in the backup RAM. The data corresponding to the control state of the game control means is data necessary for restoring the control state before the occurrence of a power failure or the like based on the data when the power is restored after a power failure or the like occurs. Further, data corresponding to the control state and data indicating the number of unpaid prize balls are defined as data indicating the progress state of the game. In this embodiment, it is assumed that the entire RAM 55 is backed up.

  In the game control microcomputer 560, the CPU 56 executes control in accordance with the program stored in the ROM 54, so that the game control microcomputer 560 (or CPU 56) executes (or performs processing) hereinafter. Specifically, the CPU 56 executes control according to a program. The same applies to microcomputers mounted on substrates other than the main substrate 31.

  The random number circuit 5003 is a hardware circuit that is used to generate a random number for determination to determine whether or not to win a jackpot based on the display result of variable symbol special display. The random number circuit 5003 updates numerical data in accordance with a set update rule within a numerical range in which an initial value (for example, 0) and an upper limit value (for example, 65535) are set, and starts at a random timing Based on the fact that the winning time is the reading (extraction) of the numerical data, it has a random number generation function in which the numerical data to be read becomes a random value.

  The random number circuit 5003 has a numeric data update range selection / setting function (initial value selection / setting function and upper limit selection / setting function), numeric data update rule selection / setting function, and numeric data update rule selection. It has various functions such as a switching function. With such a function, the randomness of the generated random numbers can be improved.

  Further, the game control microcomputer 560 has a function of setting an initial value of numerical data updated by the random number circuit 5003. For example, a predetermined calculation is performed using the ID number of the game control microcomputer 560 stored in a predetermined storage area such as the ROM 54 (an ID number assigned with a different value for each product of the game control microcomputer 560). The numerical data obtained by the execution is set as an initial value of the numerical data updated by the random number circuit 5003. By performing such processing, the randomness of the random number generated by the random number circuit 5003 can be further improved.

  Further, an input driver circuit 58 for supplying detection signals from the gate switch 32a, the start port switch 13a, the count switch 23, and the winning port switches 29a, 30a, 33a, 39a to the game control microcomputer 560 is also mounted on the main board 31. Yes. The main board also includes an output circuit 59 for driving the solenoid 16 for opening and closing the variable winning ball device 15 and the solenoid 21 for opening and closing the special variable winning ball device 20 that forms a big winning opening in accordance with a command from the game control microcomputer 560. 31. A game start switch 90 for instructing the start of the game is also mounted on the main board 31.

  In addition, the game control microcomputer 560 includes a first special symbol display 8a, a second special symbol display 8b that variably displays special symbols, a normal symbol display 10 that variably displays normal symbols, and a first special symbol hold memory. Display control of the display 18a, the second special symbol storage memory display 18b, and the normal symbol storage memory display 41 is performed.

  An information output circuit (not shown) that outputs an information output signal such as jackpot information indicating the occurrence of a jackpot gaming state to an external device such as a hall computer is also mounted on the main board 31.

  In this embodiment, the effect control means (configured by the effect control microcomputer) mounted on the effect control board 80 instructs the effect contents from the game control microcomputer 560 via the relay board 77. Upon receiving the effect control command, display control is performed on the first decorative symbol display device 9a and the second decorative symbol display device 9b that variably display the decorative symbol, and the effect display device 9 that variably displays the effect symbol.

  In addition, the effect control means mounted on the effect control board 80 controls the display of the decoration LED 25 provided on the game board and the frame LED 28 provided on the frame side via the lamp driver board 35. The sound output from the speaker 27 is controlled via the sound output board 70.

  FIG. 4 is a block diagram illustrating a circuit configuration example of the relay board 77, the effect control board 80, the lamp driver board 35, and the audio output board 70. In the example shown in FIG. 4, the lamp driver board 35 and the audio output board 70 are not equipped with a microcomputer, but may be equipped with a microcomputer. Further, without providing the lamp driver board 35 and the audio output board 70, only the effect control board 80 may be provided for effect control.

  The effect control board 80 includes an effect control CPU 101 and an effect control microcomputer 100 including a RAM for storing information related to effects such as effect symbol process flags. The RAM may be externally attached. In this embodiment, the RAM in the production control microcomputer 100 is not backed up. In the effect control board 80, the effect control CPU 101 operates in accordance with a program stored in a built-in or external ROM (not shown), and receives a capture signal from the main board 31 input via the relay board 77 ( In response to the (effect control INT signal), an effect control command is received via the input driver 102 and the input port 103. Further, the effect control CPU 101 causes the VDP (video display processor) 109 to perform display control of the effect display device 9 based on the effect control command.

  In this embodiment, a VDP 109 that performs display control of the effect display device 9 in cooperation with the effect control microcomputer 100 is mounted on the effect control board 80. The VDP 109 has an address space independent of the production control microcomputer 100, and maps a VRAM therein. VRAM is a buffer memory for developing image data. Then, the VDP 109 outputs the image data in the VRAM to the effect display device 9 via the frame memory.

  The effect control CPU 101 outputs to the VDP 109 a command for reading out necessary data from a CGROM (not shown) in accordance with the received effect control command. The CGROM stores character image data and moving image data displayed on the effect display device 9, specifically, a person, characters, figures, symbols (including effect symbols), and background image data in advance. ROM. The VDP 109 reads image data from the CGROM in response to the instruction from the effect control CPU 101. The VDP 109 executes display control based on the read image data.

  The effect control command and the effect control INT signal are first input to the input driver 102 on the effect control board 80. The input driver 102 passes the signal input from the relay board 77 only in the direction toward the inside of the effect control board 80 (does not pass the signal in the direction from the inside of the effect control board 80 to the relay board 77). It is also a unidirectional circuit as a regulating means.

  As a signal direction regulating means, the signal inputted from the main board 31 is allowed to pass through the relay board 77 only in the direction toward the effect control board 80 (the signal is not passed in the direction from the effect control board 80 to the relay board 77). The unidirectional circuit 74 is mounted. For example, a diode or a transistor is used as the unidirectional circuit. FIG. 4 illustrates a diode. A unidirectional circuit is provided for each signal. Furthermore, since the effect control command and the effect control INT signal are output from the main board 31 via the output port 571 that is a unidirectional circuit, the signal from the relay board 77 toward the inside of the main board 31 is restricted. That is, the signal from the relay board 77 does not enter the inside of the main board 31 (the game control microcomputer 560 side). The output port 571 is a part of the I / O port unit 57 shown in FIG. Further, a signal driver circuit that is a unidirectional circuit may be further provided outside the output port 571 (on the relay board 77 side).

  The effect control CPU 101 drives the motor 86 to operate the movable member 78 via the output port 106. In addition, vibration motors 87 a, 87 b, 87 c that are provided in the vicinity of the upper effect LED 85 a, the middle effect LED 85 b, and the lower effect LED 85 c and signal the mounting portion of each LED are driven via the output port 106. The vibration motor 87a vibrates the upper effect LED 85a, the vibration motor 87b vibrates the middle effect LED 85b, and the vibration motor 87c vibrates the lower effect LED 85c.

  Further, the effect control CPU 101 outputs a signal for driving the LED to the lamp driver board 35 via the output port 105. Further, the production control CPU 101 outputs sound number data to the audio output board 70 via the output port 104.

  Furthermore, the production control microcomputer 100 has a built-in random number circuit 107 for generating hardware random numbers (random numbers generated by the hardware circuit). The random number circuit 107 updates the numerical data according to the set update rule within the numerical range in which the initial value (for example, 0) and the upper limit value (for example, 65535) are set. In this embodiment, the production control microcomputer 100 determines an addition value based on the random number value generated by the random number circuit 107, and adds the determined addition value to obtain a predetermined production content (for example, production design). The final determination design random number (specifically, random numbers SR1-1 to SR1-3 shown in FIG. 66) is updated.

  In the lamp driver board 35, a signal for driving the LED is input to the LED driver 352 via the input driver 351. The LED driver 352 supplies a current to a light emitter provided on the frame side such as the frame LED 28 based on a signal for driving the LED. Further, current is supplied to the decoration LED 25, the upper effect LED 85a, the middle effect LED 85b, and the lower effect LED 85c provided on the game board side.

  In the voice output board 70, the sound number data is input to the voice synthesis IC 703 via the input driver 702. The voice synthesizing IC 703 generates voice or sound effect according to the sound number data, and outputs it to the amplifier circuit 705. The amplification circuit 705 outputs an audio signal obtained by amplifying the output level of the speech synthesis IC 703 to a level corresponding to the volume set by the volume 706 to the speaker 27. The voice data ROM 704 stores control data corresponding to the sound number data. The control data corresponding to the sound number data is a collection of data showing the output form of the sound effect or sound in a time series in a predetermined period (for example, the changing period of the effect design).

  Next, the configuration of the power supply substrate 910 will be described with reference to the block diagram of FIG. The power supply board 910 is provided with a power switch 914 for permitting or shutting off power supply to each electric component control board or mechanism component in the gaming machine. Note that the power switch 914 may be provided outside the power supply board 910 in the gaming machine. When the power switch 914 is in a closed state (on state), AC power (AC 24 V) is applied to the input side (primary side) of the transformer 911. The transformer 911 is for electrically insulating the AC power supply (AC24V) and the inside of the power supply substrate 910, and its output voltage is also AC24V. A varistor 918 as an overvoltage protection circuit is installed on the input side of the transformer 911.

  The power supply board 910 is installed independently of the electric component control board (the main board 31, the payout control board 37, the effect control board 80, etc.), and generates a voltage used by each board and the mechanical parts in the gaming machine. In this example, AC24V, VSL (DC + 30V), VLP (DC + 24V), VDD (DC + 12V) and VCC (DC + 5V) are generated. Further, a capacitor 916 serving as a storage holding means for holding the stored contents in the backup power supply (VBB), that is, the backup RAM, is charged from DC + 5V (VCC), that is, a power supply line for driving an IC or the like on each substrate. Further, a backflow prevention diode 917 is inserted between the +5 V line and the backup +5 V (VBB) line. Note that VSL is generated by rectifying and boosting AC 24 V with a rectifying element in the rectifying and smoothing circuit 915. VSL becomes a solenoid driving power source. VLP is a lamp lighting voltage, and is generated by rectifying AC24V with a rectifier element in the rectifier circuit 912.

  The DC-DC converter 913 serving as a power supply voltage generating means has one or a plurality of switching regulators (two regulator ICs 924A and 924B are shown in FIG. 5), and generates VDD and VCC based on VSL. Relatively large capacitors 923A and 923B are connected to the input sides of the regulator ICs (switching regulators) 924A and 924B. Accordingly, when the power supply to the gaming machine from the outside is stopped, the DC voltages such as VSL, VDD, VCC, etc., decrease relatively slowly.

  As shown in FIG. 5, AC24V output from the transformer 911 is supplied to the connector 922B as it is. The VLP is supplied to the connector 922C. VCC, VDD and VSL are supplied to connectors 922A, 922B and 922C.

  The cable connected to the connector 922A is connected to the main board 31. The cable connected to the connector 922B is connected to the payout control board 37. Therefore, VBB is also supplied to the connector 922A. For example, a cable connected to the connector 922 </ b> C is connected to the lamp driver board 35. Each voltage is supplied to the effect control board 80 via the lamp driver board 35.

  In addition, a clear switch 921 having a push button structure is mounted on the power supply board 910. When the clear switch 921 is pressed, a low level (ON state) clear signal is output and output to the main board 31 via the connector 922A. If the clear switch 921 is not pressed, a high level (off state) signal is output. The clear switch 921 may have a configuration other than the push button structure. Further, the clear switch 921 may be provided other than the power supply board 910 in the gaming machine.

  Further, the power supply board 910 generates a reset signal for the microcomputer mounted on the electric component control board, amplifies the reset signal from the power supply monitor circuit 920 that outputs a power-off signal, and the power supply monitor circuit 920. And an output driver circuit 925 that amplifies the power-off signal and outputs the amplified signal to the connector 922B. The reset signal for the effect control microcomputer is transmitted to the effect control board 80 via the lamp driver board 35. Further, when the reset circuit is mounted on each electric component control board, the voltage value that makes the reset signal high may be made different (for example, the case of the main board 31 is made highest). The timing at which the reset signal for the game control microcomputer 560 becomes high level is the latest).

  A power-off signal from the power monitoring circuit 920, that is, a detection signal from the power monitoring means is input to the game control microcomputer 560 via an input port mounted on the main board 31. That is, the gaming control microcomputer 560 can confirm the occurrence of the stop of the power supply to the gaming machine by monitoring the input signal of the input port.

  Next, the structure of the substrate storage case 200 that stores the main substrate 31 will be described. FIG. 6 is an exploded perspective view showing the substrate storage case, and FIG. 7 is an exploded perspective view showing the substrate storage case, but shows an example in which the substrate storage case 200 is sealed for the second time. FIG. 8 is an exploded perspective view showing the assembled state of the substrate storage case 200 and the main substrate 31. FIG. 9 is a perspective view showing a state in which the main board 31 is attached to the case cover 202. FIG. 10 is a perspective view showing a connection state of the wiring side connector. FIG. 11 is a perspective view showing an attachment state of the connector restricting member. FIG. 12 is a longitudinal sectional view showing a state in which the case main body 201 and the case cover 202 are closed. FIG. 13 is a perspective view showing a sealed state of the substrate storage case 200. 14 is a cross-sectional view showing a cross section AA of the substrate storage case 200 shown in FIG. FIG. 15 is a partially broken side view showing the substrate storage case 200. FIG. 16A is a cross-sectional view showing a BB cross section of the substrate storage case 200 shown in FIG. FIG. 16B is a cross-sectional view showing a CC cross section of the substrate storage case 200 shown in FIG. As shown in FIG. 2, in this embodiment, the game start switch 90 is provided on the main board 31, but the board storage case for storing the main board 31 shown in FIGS. In 200, the game start switch 90 is not shown.

  As shown in FIG. 6, the substrate storage case 200 includes a case main body 201 that covers the back side of the main substrate 31 and a case cover 202 that covers the mounting surface 31 a (see FIG. 12) side of the main substrate 31. 31 is assembled so as to sandwich it. A board-side connector to which an electronic component such as a game control microcomputer 560 or a wiring-side connector provided at one end of a wiring extending from another board is connected to the mounting surface 31a of the main board 31. 238a to 238c are mounted. In this embodiment, three board-side connectors 238a to 238c are illustrated, but the number of connectors to be mounted is arbitrary, and actually three or more connectors may be mounted.

  The board storage case 200 is attached to the outside of the case cover 201 and is a connector regulating member 500 for preventing the wiring side connectors (harness side connectors) 290a to 290c connected to the board side connectors 238a to 238c from being pulled out. It has. The main board 31 is housed in a sealed state inside the board housing case 200 while being attached to the back side of the case cover 202.

  The case body 201 is made of a transparent synthetic resin and is formed into a rectangular parallelepiped shape having a bottom plate 201a formed in a substantially rectangular shape and side walls 203 to 206 formed so as to surround the periphery of the bottom plate 201a. ing. On the inner surfaces of the side walls 205 and 206, a plurality of support ribs 207 facing the up and down direction for supporting the periphery of the back surface of the main substrate 31 in the sealed state (closed state) shown in FIG. In addition, a positioning rib 270 that faces the vertical direction for positioning the case cover 202 is formed at the longitudinal center position on the inner surfaces of the side wall 203 and the blocking wall 216.

  As shown in FIG. 6, one short side wall 203 has a central side wall 203a located at the approximate center in the longitudinal direction, bulging walls 203b and 203c located on the left and right sides of the central side wall 203a, and a central side wall 203a. And a connecting wall 203d that connects the bulging walls 203b and 203c to each other. That is, the bulging walls 203b and 203c and the connecting wall 203d form substantially rectangular bulging portions 208a and 208b bulging outward from the inside of the main body on the left and right sides in the longitudinal direction of the central side wall 203a. ing.

  Inside the bulging portions 208a and 208b are formed bulging spaces S2 and S3 that respectively communicate with a substantially rectangular substrate storage space S1 formed inside the case body 201. That is, the inside is configured to be hollow. In the bulging space S2 of one bulging portion 208a, a screw accommodating portion 209 that accommodates a plurality (three in this embodiment) of spare one-way screws 281 is provided.

  The screw storage portion 209 includes a plate-like portion 209a that is slightly lower than the side wall 203 standing from the bottom plate 201a of the case body 201, and a plurality of cylindrical shapes that are formed at predetermined intervals in the longitudinal direction of the plate-like portion 209a. Part 209b. Each cylindrical portion 209b is formed with an insertion hole 209c having a predetermined depth slightly larger than the diameter of the screw portion of the spare one-way screw 281 and smaller than the diameter of the head. A spare one-way screw 281 can be inserted into and stored in the insertion hole 209c from the upper surface opening (see FIG. 16A).

  The plate-like portion 209a has both ends in the longitudinal direction continuous to the inner surfaces of the side wall 206 and the connecting wall 203d. The plate-like portion 209a is disposed so as to partition the substrate storage space S1 and the bulging space S2 in parallel with the bulging wall 203b. In addition, locking holes 210 that can lock the locking claws 251 of the case cover 202 are formed in the lower portions of the bulging walls 203b and 203c (see FIG. 16A).

  The spare one-way screw 281 is screwed by rotation in one direction. However, it is a screw having a function that cannot be rotated even if it is rotated in the other direction, that is, the screw cannot be loosened. Specifically, it is composed of a screw part 283 having a male screw part formed on the outer periphery and a head part 284 provided at the upper end of the screw part 283, and the diameter of the head part 284 is larger than the diameter of the screw part 283. It has a diameter (see FIG. 16A). The one-way screw 280 is configured in the same manner as the spare one-way screw 281. However, the color of the one-way screw 280 used for fixing first is different from the color of the spare one-way screw 281.

  On the outside of the central side wall 203a, a second fixed portion 212 is formed in which a plurality of (four in this embodiment) screw holes 211a to 211d to which the one-way screw 280 is screwed are formed. As shown in FIGS. 6 and 15, the fixed portion 212 is installed between the connecting walls 203d and 203d outside the central side wall 203a, and the screw holes 211a to 211d are arranged at predetermined intervals in the longitudinal direction. The formed fixing piece 212a and a cylindrical portion 212b suspended from a position corresponding to each of the screw holes 211a to 211d on the lower surface of the fixing piece 212a. The screw holes 211a to 211d are formed in a cylindrical shape from the fixing piece 212a. It is formed to a predetermined depth over the portion 212b.

  The fixing piece 212 a is connected to the side wall 203. Three sides of the fixed piece 212 a are in contact with the central side wall 203 a and both connecting walls 203 d of the side wall 203. The long side of the fixing piece 212a opposite to the central side wall 203a is formed on the same plane as the bulging walls 203b and 203d. That is, it is formed so as not to protrude outward from the bulging portions 208a and 208b on both sides. Therefore, even if the case main body 201 is accidentally dropped, the second fixed portion 212 is protected by the bulging portions 208a and 208b on both sides and is not damaged.

  As shown in FIG. 6 and FIG. 12, the other short side wall 204 is formed so as to hang downward from the tip of the inward piece 204a and an inward piece 204a provided inward from the upper end thereof. A drooping piece 204b is continuously provided. A locked recess 215 (see FIG. 12) that opens downward to lock the rotating pivot piece of the case cover 202 is formed in the longitudinal direction by the inner surfaces of the side wall 204, the inward piece 204a, and the hanging piece 204b. Yes.

  Further, as shown in FIG. 12, an opening is formed below the locked recess 215 in the bottom plate 201a. A closed wall 216 having a height lower than that of the side wall 204 is provided so as to rise from the opening edge, and the space between the lower end of the side wall of the case cover 202 and the upper surface of the bottom plate 201a is covered from the outside in the sealed state. .

  On the lower surface of the bottom plate 201a, when attaching the case body 201 to a substrate storage case attachment plate (not shown) provided in the pachinko gaming machine 1, a plurality of attachment plate latches that can be engaged with the substrate storage case attachment plate A claw 217 and a positioning piece 218 for positioning at the time of attachment are provided so as to protrude.

  The case cover 202 is formed of a transparent synthetic resin, and as shown in FIGS. 6 and 7, surrounds the upper plate 220 formed in a substantially rectangular shape and three edges of the peripheral edge of the upper plate 220. The side walls 230 to 232 are formed in a rectangular parallelepiped shape whose lower surface is opened. One of the two long sides of the upper plate 220 is recessed downward in the longitudinal direction, and a strip-shaped recess 234 having a predetermined width is formed in a part of the upper plate 220.

  Specifically, as shown in FIGS. 8 and 14, the upper plate 220 includes a low covering surface portion 220 a provided at a position where a surface (back surface) facing the mounting surface 31 a substantially contacts the mounting surface 31, and It is composed of a high covering surface portion 220b provided at a position farther from the mounting surface 31a than the low covering surface portion 220a, and an inclined covering surface portion 220c connecting the low covering surface portion 220a and the high covering surface portion 220b. A concave portion 234 is formed by the inclined covering surface portion 220c.

  As shown in FIG. 8, the low covering surface portion 220a is a strip-shaped connector mounting region S10 formed along one long side of the mounting surface 31a of the main board 31 formed in a substantially rectangular shape in plan view (FIG. 8). And a connector opening 236a for passing the connection port 238d of the plurality of board-side connectors 238a to 238c mounted in the connector mounting region S10 and the upper portion of the main body to the outside of the case cover 202. To 236c are formed.

  Further, the back surface of the low covering surface portion 220a substantially comes into contact with the mounting surface 31a of the main substrate 31 as shown in FIG. 14 with the main substrate 31 attached. In addition, in each of the connector openings 236a to 236c, the opening edge and the various connectors 238a to 238a to prevent foreign matter such as wire or wiring from entering between the opening edge and the main body side surface of the various connectors 238a to 238c. For example, the gap between the main body side surface of 238c is formed within about 1 mm.

  The high covering surface portion 220b is a main component mounting area (an area other than the area shown by hatching in the drawing) other than the connector mounting area S10 on the mounting surface 31a of the main board 31, that is, an electronic component such as a game control microcomputer 560 and various circuits. In order to cover the upper part of the region where the etc. are mounted, it is arranged at a position higher than the low covering surface portion 220a, that is, at a position farther from the mounting surface 31a than the low covering surface portion 220a.

  The inclined covering surface portion 220c is provided so as to be inclined downward from one side edge of the high covering surface portion 220b toward one side edge of the low covering surface portion 220a. A plurality of engagement holes 502 into which a plurality of locking claws 501 formed in the connector restricting member 500 are engaged are formed at predetermined intervals in the longitudinal direction at the upper portion on the high covering surface portion 220b side.

  As shown in FIG. 9, two mounting posts 240 having screw holes 240a to which board mounting screws 239 for mounting the main board 31 are mounted project on one diagonal line at the four back corners of the upper plate 220. (Only one is shown in FIG. 9). In addition, positioning protrusions (not shown) for positioning at the time of mounting are provided so as to protrude two on the other diagonal, so that the main substrate 31 can be mounted on the back side of the case cover 202. Yes.

  When the main board 31 is attached, the main board 31 is pressed against the back surface side of the case cover 202 with the mounting surface 31a of the main board 31 facing the back surface of the case cover 202, that is, with the mounting surface 31a facing upward. . Then, the positioning holes 243 formed at the two corners corresponding to the positioning convex portions on the main board 31 are inserted into the positioning convex portions so that the connectors 238a to 238c pass through the connector openings 236a to 236c, respectively. In the state of being inserted and positioned, the board mounting screws 239 are attached to the screw mounting holes 242 formed at the two corners corresponding to the mounting posts 240 of the main board 31, and the board mounting screws 239 are screwed to the screw holes 240a. To do.

  In a state where the main substrate 31 is attached to the case cover 202, the back surface of the low-covering surface 220a of the upper plate 220 and the mounting surface 31a face each other and substantially abut (see FIG. 14). Therefore, even if a foreign object such as a wire or a wire is inserted between the opening edge of each connector opening 236a to 236c and the main body side surface of each connector 238a to 238c, a main board on which a game control microcomputer or the like is mounted It is difficult to enter toward the center of 31 and fraud is effectively prevented.

  In addition, a rectangular pillar-shaped cap that holds a cap suspension support body 245 (see FIGS. 6 and 7) in which a plurality of caps 265 that cover the head 284 of the one-way screw 280 are connected to a predetermined rear surface of the high covering surface 220b. A holding part (not shown) is provided downward. The cap 265 in the cap suspension support body 245 covers the head 284 of the spare one-way screw 281 and has a total number (three) of the spare one-way screw 281.

  As shown in FIG. 7, the cap 265 is provided with a pair of locking pieces 268 having locking claws 267 formed at the lower end. By locking the locking claw 267 to the stepped portion 266 formed on the inner surface of the fixed portions 255b to 255d, the cap 265 is held so as to close the upper surface openings of the fixed portions 255b to 255d. The locking claw 267 is for fitting into a step portion 266 provided inside the fixed portions 255b to 255d to prevent the cap 265 from being pulled out.

  On the upper surface of the upper plate 220, as shown in FIGS. 6 and 7, a model name display recess 247 for attaching a model name seal (not shown) indicating the model name of the pachinko gaming machine 1, An inspection name display recess 248 is provided for attaching an inspection history seal (not shown) in which items such as “inspector” and “inspection date” written when the main board 31 is inspected are attached. Yes.

  In portions corresponding to the bulging portions 208a and 208b on the side of the case body 201 on the side wall 230, bulging portion covers 250a and 250b that are slightly smaller than the bulging portions 208a and 208b are formed so as to bulge outward. Has been. The bulging portion covers 250a and 250b enter inside the bulging walls 203b and 203c and the connecting wall 203d constituting the bulging portions 208a and 208b in the sealed state, and close the upper portions of the bulging spaces S2 and S3.

  The bulging portion covers 250a and 250b are formed in a hollow shape, and the internal space of one of the bulging portion covers 250b is separated from the substrate storage space in the case cover 202 by the side wall 230 and becomes an independent space. . The inner space of the other bulging portion cover 250a is cut out at a portion corresponding to the bulging portion cover 250a on the side wall 230, and communicates with the substrate storage space of the case cover 202 (see FIG. 16A).

  The wall portions corresponding to the locking holes 210 formed in the bulging portions 208a and 208b in the bulging portion covers 250a and 250b can be elastically deformed via two slits cut out upward from the lower end. A locking piece 252 is formed. An outward locking claw 251 that can be locked in the locking hole 210 is formed at the lower end of the locking piece 252, and is locked when the upper surface of the case body 201 is closed by the case cover 202, that is, in a sealed state. The claw 251 is locked in the locking hole 210.

  Further, as shown in FIG. 16A, on the upper wall rear surface 254 of the bulge portion cover 250a corresponding to the screw storage portion 209, screw restriction ribs 253 extending in the longitudinal direction of the bulge portion cover 250a are provided. It is provided downward (see FIG. 6). Specifically, the screw regulating rib 253 is parallel to the plate-like portion 209a immediately above the plate-like portion 209a of the screw storage portion 209 in a state where the upper surface of the case body 201 is closed by the case cover 202, that is, in a sealed state. The upper wall rear surface 254 of the bulging portion cover 250a is provided downward from a position facing the plate-like portion 209a. That is, a predetermined length is extended from the position facing the upper surface opening of the insertion hole 209c on the upper wall rear surface 254 toward the upper surface opening of the insertion hole 209c. Specifically, the lower end has a length close to the head 284 of each spare one-way screw 281 inserted into the insertion hole 209c.

  In the sealed state, the screw accommodating portion 209 of the spare one-way screw 281 accommodated in the screw accommodating portion 209 by the screw restricting rib 253 extending downward from the upper wall rear surface 254 of the bulging portion cover 250a. Deviations from are prevented. That is, it is reliably prevented that the spare one-way screw 281 deviates from the screw storage portion 209 and enters the substrate storage space S1 to damage the substrate.

  As shown in FIG. 6, a plurality (four in this embodiment) of rectangular tubular fixed portions 255 a to 255 d are provided between the bulging portion covers 250 a and 250 b on the side wall 203. A plurality of screw holes 211a to 211d are formed at locations facing each of the screw holes 211a to 211d. The first fixed portion 255 is constituted by these fixing portions.

  As shown in FIGS. 15 and 16B, each of the fixed portions 255a to 255d includes a square columnar screw insertion portion 256 into which the one-way screw 280 and the spare one-way screw 281 can be inserted, a screw insertion portion 256 and a side wall. 230 and a connecting portion (a part of the case cover 202) 257 that connects to 230. Then, the screw insertion portion 256 is arranged with a predetermined distance away from the side wall 230 via the connecting portion 257. Therefore, the connecting portion 257 can be cut with a tool such as a nipper. Further, a plurality of connecting portions 257 are provided outward from the outer surface of the side wall 230 that is one side edge of the case cover 202, and fixed portions 255 a to 255 d are provided at the tips of the connecting portions 257.

  The screw insertion portion 256 is a bottomed cylindrical body whose upper surface is open, and has a size capable of accommodating the one-way screw 280 therein. The bottom plate 258 has a diameter of the head 284 of the one-way screw 280. A mounting hole 259 having a smaller diameter is formed. The mounting hole 259 is disposed at a position opposite to the screw holes 211a to 211d in the sealed state.

  As shown in FIGS. 6 and 12, the side wall 231 corresponding to the side wall 204 formed with the locked recess 215 on the case body 201 side has an upward engagement that can be locked to the locked recess 215 at the tip. A locking piece 261 provided with a stop 260 in the longitudinal direction is provided outward.

  The case main body 201 and the case cover 202 configured as described above have the inner surface of the side wall 205 of the case main body 201 and the low covering surface portion of the case cover 202 in a state where the upper surface opening of the case main body 201 is closed by the case cover 202. A gap portion 505 through which the vertical plate 500b can be inserted is formed along the inner surface of the side wall 205 between the end surface of the long side 220d (see FIG. 10) which is the side facing the inner surface of the side wall 205 in 220a. 14).

  Next, the structure of the connector restricting member 500 will be described. The connector restricting member 500 is formed of a plate member made of a transparent synthetic resin material, and is configured to be attachable to the outside of the case cover 202 as shown in FIG. The width dimension of the plate material is slightly shorter than the width dimension in the longitudinal direction of the long side 202 d of the case cover 202. The connector restricting member 500 includes an upper plate 500a formed slightly larger than the low covering surface 220a of the case cover 202 when mounted, a vertical plate 500b provided downward from the outer end of the upper plate 500a, and a vertical plate. A lower plate 500c provided in the same direction so as to be parallel to the upper plate 500a from the lower end of 500b is formed in a substantially U-shape.

  The long side 500d of the upper plate 500a can be inserted into each of the plurality of engagement holes 502 and can be elastically deformed. Further, a locking piece having an upward locking claw 501 formed at the tip is provided so as to protrude substantially parallel to the upper plate 500a, and the locking piece is passed through the case hole 202 through the engagement hole 502. In FIG. 2, the locking claw 501 is locked to the upper edge of the engagement hole 502 on the back surface of the case cover 202.

  In the upper plate 500a, elongated rectangular wiring insertion openings 503a to 503c capable of passing the wirings 291a to 291c extending from the wiring side connectors 290a to 290c are formed in the longitudinal direction. Wiring insertion slits 504a to 504c through which the wirings 291a to 291c can pass are provided from the wiring insertion openings 503a to 503c toward the long side 500d.

  Each wiring 291a-291c is what is called a flat cable. Therefore, the wiring insertion openings 503a to 503c and the wiring insertion slits 504a to 504c are formed in a horizontally long rectangular shape. That is, the wiring insertion openings 503a to 503c are formed such that the long side and the short side are shorter than the long side and the short side of the main body of the wiring side connectors 290a to 290c, and it is impossible to pass the wiring side connectors 290a to 290c. And the wirings 291a to 291c are formed to be allowed to pass therethrough. Further, the wiring insertion slits 504a to 504c are formed to have a width dimension that can be inserted from the long side 500d side in a state where the wirings 291a to 291c are parallel to the wiring insertion slits 504a to 504c.

  Therefore, the wirings 291a to 291c can be arranged in the wiring insertion openings 503a to 503c by inserting the wirings 291a to 291c into the wiring insertion slits 504a to 504c from the long side 500d side and drawing them to the wiring insertion openings 503a to 503c. it can.

  The wiring insertion slits 504a to 504c are formed in parallel to each other so as to incline with respect to the opening long edge sides of the wiring insertion openings 503a to 503c, and in the longitudinal center of the opening long edge side. It extends obliquely from the position toward the long side 500d. As a result, since the wires 291a to 291c drawn through the wire insertion slits 504a to 504c can be obliquely entered into the wire insertion openings 503a to 503c, the wires can be smoothly inserted into the wire insertion openings 503a to 503c. Can enter.

  Further, since the wiring insertion slits 504a to 504c are provided from the central position in the longitudinal direction of the long edge of the opening, the wirings 291a to 291c are arranged in a state where the wirings 291a to 291c are disposed in the wiring insertion openings 503a to 503c. Both ends in the column direction are not separated from the connection portions with the wiring insertion slits 504a to 504c, and the wirings 291a to 291c do not return back into the wiring insertion slits 504a to 504c. That is, the width of the wiring insertion slits 504a to 504c is narrower than one side of the wiring insertion openings 503a to 503c.

  The lower plate 500c is provided in the same direction as the upper plate 500a from the lower end of the vertical plate 500b, and its width is slightly shorter than the width dimension of the short side of the main substrate 31. That is, it is a length that can cover almost the entire back surface 31b (opposite surface of the mounting surface 31a) of the main substrate 31 (see FIG. 14).

  The connector regulating member 500 formed in this way is used to insert the wirings 291a to 291c from the wiring side connectors 290a to 290c connected to the board side connectors 238a to 238c through the wiring insertion slits 504a to 504c. After passing through the openings 503a to 503c, the case cover 202 is brought close to the case cover 202 from the side, the locking claw 501 is inserted into the engagement hole 502, and one end is locked to the case cover 202. Can be temporarily fixed.

  In this state, the upper plate 500a covers the upper and outer sides of the low covering surface portion 220a with the upper plate 500a and the vertical plate 500b, and the back surface 31b of the main board 31 is covered with the lower plate 500c.

  Next, with the case main body 201 and the case cover 202 configured in this manner, the main board 31 is housed in a sealed state, and the wiring side connectors 290a to 290c are pulled out by the connector restricting member 500. Explain the regulatory situation.

  When the main substrate 31 is stored in a sealed state, first, the cap suspension support 245 is attached to a cap holding portion (not shown) provided on the back surface of the case cover 202, and then the main substrate 31 is attached to the case cover 202. Attach to the back side. Specifically, as shown in FIG. 9, the main board 31 is pushed to the back surface side of the case cover 202 with the mounting surface 31 a facing the back surface of the case cover 202, that is, with the mounting surface 31 a facing upward. Hit it. Then, the positioning holes 243 formed at the two corners corresponding to the positioning convex portions 241 in the main board 31 so that the board side connectors 238a to 238c pass through the connector openings 236a to 236c, respectively. In a state of being positioned through the portion 241, the board mounting screws 239 are mounted in the screw mounting holes 242 formed in the two corners corresponding to the mounting posts 240 of the main board 31, and the board mounting screws 239 are mounted in the screw holes 240 a. Screw on.

  As shown in FIG. 10, in the state where the main board 31 is attached to the back side of the case cover 202, the upper parts of the board side connectors 238 a to 238 c are exposed to the outside of the case cover 202 from the connector openings 236 a to 236 c. The That is, since the connection port 238d formed on the upper surface of the main body of each of the board side connectors 238a to 238c is opened upward to the outside of the case cover 202, each board can be passed without passing the wiring side connectors 290a to 290c through the case cover 202. Each wiring side connector 290a-290c can be inserted and connected to the connection port 238d of the side connectors 238a-238c.

  Next, as shown in FIG. 11, the wirings 291a to 291c from the wiring side connectors 290a to 290c connected to the board side connectors 238a to 238c are inserted into the wiring insertion slits 504a to 504c from the long side 500d side. After inserting and passing through the wiring insertion openings 503a to 503c, the case cover 202 is made to approach from the side, the locking claw 501 is inserted into the engagement hole 502, and one end is locked to the case cover 202. Temporarily fix the case cover 202.

  In this way, the wirings 291a to 291c can be easily passed through the wiring insertion openings 503a to 503c in a state where the wiring side connectors 290a to 290c of the wirings 291a to 291c are connected to the board side connectors 238a to 238c. . In addition, it is not necessary to pass a wiring side connector (not shown) provided at the end of the wirings 291a to 291c opposite to the wiring side connectors 290a to 290c through the wiring insertion openings 503a to 503c. For example, even when the ends of the wirings 291a to 291c opposite to the wiring side connectors 290a to 290c are directly connected to another board (not shown) without using a connector or the like, the wiring side connector 290a ˜290c does not need to pass through the wiring insertion openings 503a to 503c, and it is not necessary to form a large opening in the upper plate 500a. Therefore, the strength reduction of the connector restricting member 500 is prevented.

  In the case main body 201, as shown in FIG. 8, the spare one-way screw 281 is stored in the insertion hole 209c (see FIG. 16A) of the screw storage portion 209. At this time, the threaded portion 283 can be easily housed simply by passing the threaded portion 283 into the insertion hole 209c from above the top opening of each insertion hole 209c. In this stored state, the screw portion 283 is completely stored in the insertion hole 209c, and only the head portion 284 is held in a state of protruding outward from the upper surface opening of the insertion hole 209c (see FIG. 16A). . Therefore, when using the stored one-way screw 281 for spare use, the head 284 can be easily taken out by simply picking it.

  Next, the upper surface opening of the case body 201 is closed with the case cover 202 to which the main board 31 is integrally attached and the connector restricting member 500 is temporarily fixed to the outside. Specifically, as shown in FIG. 12, the case cover 202 is inclined so that the locking piece 260 protruding outward from one short side of the case cover 202 faces downward, that is, With the back surface 31b of the main substrate 31 facing the case body 201, the locking piece 260 is inserted between the upper end of the blocking wall 216 and the lower end of the hanging piece 204b in the case body 201. Then, with the locking strip 260 locked in the locked recess 215, the case cover 202 is rotated around the locking portion in the direction of the arrow in the figure, and the case cover 202 is rotated toward the case body 201. It fits in the space surrounded by the side walls 203-206.

  The bulging portion covers 250a and 250b are fitted into the bulging spaces S2 and S3 of the bulging portions 208a and 208b of the case main body 201, and both the locking claws 251 are respectively locked to the opening upper edge of the locking hole 210. The As a result, one short side of the case cover 202 is locked by the locking strip 260 and the locked recess 215, and the other short side is locked by the locking claw 251 and the locking hole 251. The case cover 202 is temporarily fixed to the case main body 201. In this state, the case cover 202 can be easily opened by pushing the respective locking claws 251 inward from the outside of the locking holes 210 to release the locked state.

  In this state, the lower ends of the screw regulating ribs 253 provided downward from the upper wall rear surface 254 of the bulging portion cover 250a are the heads of the three spare one-way screws 281 housed in the screw housing portion 209. Arranged close to the portion 284. Therefore, it is possible to prevent the spare one-way screw 281 from deviating from the screw storage portion 209 and entering the board storage space S1, damaging the wiring pattern of the main board 31 and disconnecting it.

  In addition, since the lower ends of the side walls 230 to 233 of the case cover 202 are deeply inserted below the upper ends of the side walls 203 to 206 of the case main body 201, a wire or the like is inserted between the case main body 201 and the case cover 202. It becomes difficult to enter foreign objects.

  Further, since the screw storage portion 209 is provided in the bulging space S2 of the bulging portion 208a, the main substrate 31 is disposed at a position lower than the upper end of the screw storage portion 209 in the substrate storage space S1. However (see FIG. 16B), there is no interference with the screw storage portion 209.

  Further, as shown in FIG. 14, a vertical plate of the connector restricting member 500 is formed in a gap portion 505 formed between the inner surface of the side wall 205 of the case body 201 and the long side 220d of the low covering surface portion 220a of the case cover 202. It is arranged with 500b inserted. Further, the entire lower surface of the lower plate 500 c is placed on the upper surface of the bottom plate 201 a of the case body 201. The connector restricting member 500 is stably held with respect to the case body 201, and the back surface 31b of the main board 31 is covered with the lower plate 500c.

  In other words, the connector restricting member 500 whose one end is locked to the case cover 202 via the locking claw 501 has the lower plate 500c and the lower portion of the vertical plate 500b constituting a part thereof in the case. Be placed.

  Further, in this state, the first fixed portion 255 of the case cover 202 is disposed above the second fixed portion 212 of the case body 201. In other words, when each of the fixed portions 255a to 255d is placed on the upper surface of the fixing piece 212a, the screw holes 211a to 211d and the mounting holes 259 are aligned, and the one-way screw 280 can be passed. . Here, the one-way screw 280 is inserted from the upper surface opening of the screw insertion portion 256 of any one of the four fixed portions 255a to 255d (for example, the fixed portion 255a), and the tip of the screw portion 283 is attached to the mounting hole. In the state of being inserted into 259, the one-way screw 280 is screwed clockwise with a tool such as a flathead screwdriver.

  In the example shown in FIG. 6, the one-way screw 280 is inserted from the upper surface opening of the screw insertion portion 256 of the fixed portion 255a. Then, the one-way screw 280 is screwed clockwise.

  Then, as shown in FIG. 15, the threaded portion of the external thread formed on the outer periphery of the threaded portion 283 causes the threaded portion 283 to penetrate the attachment hole 259 and penetrate into the fixing piece 212a and the tubular portion 212b. Screwed into the screw hole 211a, the fixed piece 212a and the fixed portion 255a, that is, the second fixed portion 212 and the first fixed portion 255 are fixed (caulked) via the one-way screw 280.

  In other words, the case cover 202 has one of the short sides fixed to the case main body 201 by the locking ridge 260 being locked by the locked recess 215 and the other short side fixed through the one-way screw 280. The main cover 31 is stored in a sealed state in the substrate storage case 200 with the mounting surface 31a and the back surface 31b covered by the case main body 201 and the case cover 202. The

  After the one-way screw 280 is completely screwed in, the adhesive Z is injected into the screw insertion portion 256 from above, and then the cap 244 is fitted into the upper surface opening of the fixed portion 255a to form the upper surface of the head 284. The one-way screw 280 can be made difficult to remove by covering the groove or the like.

  In this embodiment, the cap 244 used for the first sealing is a colored cap, and the spare cap 265 connected to the cap suspension support 245 is used for the first sealing. The cap 244 used is of a different color (may be transparent). Therefore, even if a spare cap 265 obtained from a used machine of the gaming machine can be attached to the adherend portion 255a after some illegal act has been done, this is immediately recognized.

  Instead of using the colored cap 244, or using the colored cap 244, a colored adhesive may be used as the adhesive Z. When the colored adhesive is injected into the screw insertion portion 256 made of a transparent synthetic resin material, when there is any access to the one-way screw 280, there is a trace of the colored adhesive Z being scraped off. Since it becomes easy to visually recognize by color, it becomes easy to find a trace of fraud even from the outside of the transparent screw insertion portion 256.

  Further, instead of injecting the adhesive into the screw insertion portion 256, the cap 244 may be fixed by thermal welding or ultrasonic welding after the cap 244 is placed on the upper surface opening of the fixed portion 255a. . When fixed by welding, it is fixed more firmly than when fixed by an adhesive.

  Also, when trying to open the case cover 202 after releasing this sealed state, the one-way screw 280 cannot be removed by turning it counterclockwise, so that either the case body 201 or a part of the case cover 202 is destroyed. Alternatively, the connecting portion 257 can be cut with a tool such as a nipper and the screw insertion portion 256 of the fixed portion 255a fixed to the fixing piece 212a via the one-way screw 280 can be separated from the case cover 202.

  That is, regardless of the method of destruction or cutting, when the case cover 202 is opened after the sealed state is released, traces of destruction or cutting remain. As a result, for example, even when the case cover 202 is opened by an illegal act, it can be discovered that the illegal act has been performed early. Therefore, even if it is replaced with a main board having a ROM in which an illegal game control program is stored, it can be discovered and dealt with early. Therefore, it can be avoided that the game is played in that state and the game store suffers a disadvantage.

  When the connecting portion 257 is cut with a tool such as a nipper and the sealed state is normally released, the spare one-way screw 281 stored in the screw storage portion 209 is taken out, and the three fixed portions 255b to 255b. The spare one-way screw 281 is inserted from the upper surface opening of the screw insertion portion 256 of any one (for example, the fixed portion 255b) of 255d, and the tip of the screw portion 283 is attached to the attachment hole 259 (FIGS. 15 and 16 ( In the state inserted in a)), the spare one-way screw 281 is screwed clockwise with a tool such as a flat-blade screwdriver. Then, one cap 265 is removed from the plurality of caps 265 connected to the cap suspension support body 245, and the cap 265 is fitted into the upper surface opening of the fixed portion 255b to form a groove or the like formed on the upper surface of the head 284. Coating. When the cap 265 is mounted, the cap 265 is locked by locking a locking claw 267 provided at the lower end of the cap 265 to a step 266 formed on the inner surface of the fixed portion 255b (see FIG. 7). The upper surface opening of the adherend portion 255b is held so as to be closed.

  The cap 265 is provided with a locking claw 267 so as to protrude from the cap 265, but the cap 244 used for fixing first is not provided with the locking claw 267. Further, as shown in FIG. 7, a step portion 266 is formed on the inner surface of the fixed portions 255b to 255d used for the second and subsequent fixing, but the fixed portion used for the first fixing as shown in FIG. The step portion 266 is not formed in the portion 255a. That is, the shapes of the cap 244 and the fixed portion 255a used for the first fixing are different from the shapes of the cap 265 and the fixed portions 255b to 255d used for the second and subsequent fixing. Accordingly, the cap 265 cannot be attached to the fixed portion 255a. Therefore, in order not to leave the trace of opening the case cover, in order to conceal the illegal act, the joint by the one-way screw 280 is illegally released with a special tool or the like dedicated to one-way screw removal. Even if the joint portion is joined with the spare one-way screw 281 obtained from the used machine of the gaming machine after the cheating action is performed, the fixed portion 255a is further secured with the spare cap 265 obtained from the used machine of the gaming machine. It is difficult to cover the top surface. Therefore, it becomes difficult to conceal that fraud has been performed.

  In this embodiment, the shape of the cap 244 and the shape of the spare cap 265 are changed, and the shape of the fixed portion 255a and the shapes of the fixed portions 255b to 255d used for the second and subsequent fixing are changed. In this way, the storage portion is formed so that the other fixing portion covering member (cap 265 in this example) cannot be attached to one storage portion (fixed portion 255a in this example). The shape of the spare cap 265 is the same, and the shape of the fixed portion 255a is the same as the shapes of the fixed portions 255b to 255d used for the second and subsequent fixings. It is possible to realize that the fixing portion covering member forms the storage portion so that it cannot be attached to one storage portion. For example, the to-be-adhered part 255a is made into the shape which has the latching claw which protrudes similarly to the to-be-adhered parts 255b-255d. Further, the cap 244 has a shape in which a step portion is formed on the inner surface, like the spare cap 265. At the time of the first fixing, the cap 244 is attached to the fixed portion 255a (the engaging claw of the fixed portion 255a is engaged with the stepped portion of the fixed portion 255a), and heat welding or ultrasonic welding is performed. As a result, the cap 244 is fixed to the fixed portion 255a. Then, at the time of heat welding or ultrasonic welding, the shape of the stepped portion collapses, and the locking claw is deformed into a shape that cannot be engaged. Or, the stepped portion does not exist. In such a situation, even if a fraudulent act is performed after removing the cap 244 from the fixed part 255a by some means and removing the one-way screw 280, it is obtained from, for example, a used machine of a gaming machine in order to conceal the fraud It is difficult to cover the upper surface of the adherend portion 255a with the spare cap 265. This is because the stepped portion that receives the locking claw 267 protruding from the cap 265 has already been deformed in the fixed portion 255a as described above. Therefore, it is possible to make it difficult to conceal fraud. As a result, cheating can be made difficult.

  FIGS. 15 and 16 show an example in which the one-way screw 280 is used. However, in the case where the spare one-way screw 281 is used, the case body is similar to the case where the one-way screw 280 is used. 201 and the case cover 202 can be fixed. However, since the color of the spare one-way screw 281 is different from the color of the one-way screw 280, even if the joint portion is joined with the spare one-way screw 281 obtained from a used machine of the gaming machine after cheating, , Cheating is easy.

  Further, since the case cover 202 is fixed to the case main body 201 so as not to be opened by the one-way screw 280, the connector restricting member 500 temporarily fixed to the outside of the case cover 202 is removed from the case cover 202. While being held undetachable, removal of the wiring side connectors 290a to 290c connected to the board side connectors 238a to 238c is restricted by contact with the upper plate 500a.

  Specifically, as shown in FIG. 14, in the sealed state in which the case cover 202 is fixed to the case main body 201 so as not to be opened, the connector restricting member 500 has the lower plate 500 c that connects the back surface 31 b of the main board 31. By being arranged below the cover so as to cover, the upward movement is restricted by contact with the main substrate 31 attached to the back side of the case cover 202 fixed to the case body 201.

  In addition, the vertical plate 500 b continuously connected upward from the lower plate 500 c is sandwiched between the long side 220 d of the case cover 202 and the inner surface of the side wall 205 of the case main body 201, and the locking claw 501 is engaged with the engaging hole 502. By being stopped, sliding movement of the case main body 201 on the bottom plate 201a is restricted, and deformation of the upper plate 500a is also prevented. In particular, since the outer surface of the vertical plate 500b is held in close contact with the inner surface of the side wall 205 in the vertical direction, deformation of the vertical plate 500b to the outside is also prevented. That is, the lower plate 500c, the vertical plate 500b, the long side 220d of the case cover 202, and the side wall 205 constitute a restricting member holding means.

  By restricting the upward and horizontal movement of the connector restricting member 500, the connector restricting member 500 is prevented from being detached from the case cover 202, and is stably held in the substrate storage case 200. The upper surface 500a of the connector restricting member 500 held by the board storage case 200 covers the upper surface of the low covering surface portion 220a of the case cover 202, and the upper portion of the vertical plate 500b, the inclined covering surface portion 220c, the case cover 202. The upper peripheral surface of the low covering surface portion 220a is covered by a part of the portion. Therefore, the board side connectors 238a to 238c and the wiring side connectors 290a to 290c are blocked from the outside. Accordingly, fraudulent acts on the connection portion of the connector are prevented.

  Further, as shown in FIG. 14, since the upper plate 500a is disposed near the upper side of the wiring side connectors 290a to 290c connected to the board side connectors 238a to 238c, the wiring side connectors 290a to 290c are connected to the board side connectors 238a to 238a. When trying to pull out from 238c, the periphery of the extended portion of the wirings 291a to 291c on the upper surface of the main body of the wiring side connectors 290a to 290c is the periphery of the wiring insertion openings 503a to 503c on the back surface of the upper plate 500a (contact regulation). Part). That is, since the movement of the wiring side connectors 290a to 290c in the removal / removal direction is restricted by the upper plate 500a, it is possible to connect the wiring on which unauthorized parts other than the authorized ones are connected to the board side connectors 238a to 238c. It can be effectively prevented.

  In addition, since the lower plate 500c is formed to have a size that can cover the back surface 31b of the main substrate 31, in the sealed state, it is possible to suppress an illegal act against the wiring pattern formed on the back surface 31b, and also the stability. improves. In this embodiment, the lower plate 500c is formed to have a size capable of covering the back surface 31b of the main board 31. However, the upward movement of the connector restricting member 500 is prevented from contacting the back surface 31b of the main board 31. As long as it has a length that can be regulated by contact, it does not have to be formed in a size that can cover the entire back surface 31b.

  Next, after the second fixed portion 212 and the first fixed portion 255 are fixed through a one-way screw 280 to form a sealed state, the main substrate 31 is taken out due to a failure or inspection of the main substrate 31. A case where the sealed state is released and the sealed state is set again will be described.

  It should be noted that a plurality of screw holes 211a to 211d and fixed portions 255a to 255d are formed so that they can be repeatedly sealed, for example, when the manufacturer ships the main board 31 to an amusement store or the like. In order to store the main substrate 31 in the substrate storage case 200 in a sealed state, after using one screw hole 211a to 211d and the fixed portions 255a to 255d, the main substrate 31 is mounted at the game store as described above. This is because the sealed state may be released in the case of replacement due to failure or when the main board 31 is taken out for inspection or the like. After that, when the sealing state is set again, the other screw holes 211a to 211d and the to-be-fixed portions 255a to 255d are used.

  In the case of resealing, when the case cover 202 is opened, one cap 265 is separated from the cap suspension 245 and removed, and the spare one-way screw 281 is removed from the screw storage portion 209. Take out the book. Then, the upper surface opening of the case body 201 is closed by the case cover 202. Here, the spare one-way screw 281 is inserted into any one of the fixed portions 255b to 255d whose connection portion 257 has not yet been cut, and is screwed into the screw hole 211b. The sealed portion 255 can be fixed to the sealed portion 255 to form a sealed state.

  As described above, since the plurality of screw holes 211a to 211d as the second fixed portion 212 and the fixed portions 255a to 255d as the first fixed portion 255 are provided, a part of the case main body 201 or the case cover 202 is provided. Even after the sealed state is released, the sealed state can be repeatedly configured a plurality of times without cutting the connecting portion 257 without destroying the substrate, and without replacing the substrate storage case 200.

  FIG. 17 is a block diagram showing a circuit configuration of the main board 31 and signal lines of an effect control command transmitted from the main board 31 to the effect control board 80. As shown in FIG. 17, in this embodiment, the game control microcomputer 560 mounted on the main board 31 produces an effect control command by using eight signal lines CD0 to CD7 for transmitting the effect control signal. Transmit to the control board 80. In addition, a signal line of an effect control INT signal for transmitting and receiving a strobe signal is also wired between the main board 31 and the effect control board 80.

  As shown in FIG. 17, the main board 31 is connected to wiring from the first start port switch 13a and the second start port switch 14a. The main board 31 is also provided with wiring from the special variable winning ball apparatus 20 which is a big winning opening, and various switches 29a, 30a, 33a, 39a for detecting the winning of game balls to other winning openings. It is connected. Further, the main board 31 is connected to a solenoid 16 for opening / closing the variable winning ball apparatus 15 and wirings to the solenoid 21 for opening / closing the special variable winning ball apparatus 20. The input from the first start port switch 13a and the second start port switch 14a is also directly input as a latch signal to the random number circuit 5003 mounted on the game control microcomputer 560.

  The main board 31 includes a game control microcomputer 560, an input driver circuit 58, and an output circuit 59. The game control microcomputer 560 includes a clock circuit 5001, a reset controller 5002 functioning as a system reset means, a random number circuit 5003, a ROM 54 storing a game control program, a RAM 55 used as a work memory, and a CPU 56 operating according to the program. A CTC 5004 for sending an interrupt request signal (interrupt request signal by timer interrupt) to the CPU 56 and an I / O port unit 57 are incorporated.

The clock circuit 5001 is provided separately from a system clock circuit (not shown) that outputs a system clock signal. In this embodiment, a clock signal of a predetermined frequency (for example, 10.0 MHz) generated by an oscillator built in the gaming machine (provided outside the gaming control microcomputer 560) is input to the gaming control microcomputer 560. The frequency is divided by each part of the game control microcomputer 560 and input to each part such as the random number circuit 5003. The clock circuit 5001 of the game control microcomputer 560 outputs to the random number circuit 5003 a reference clock signal CLK having a predetermined cycle generated by dividing the clock signal input from the oscillator by 2 ⁷ (= 128). In this embodiment, the game control microcomputer 560 operates based on a system clock signal of a predetermined frequency (for example, 6.0 MHz) output from a built-in system clock circuit. Therefore, in this embodiment, the frequency of the reference clock signal CLK output from the clock circuit 5001 to the random number circuit 5003 is different from the operating frequency of the game control microcomputer 560. With such a configuration, it is possible to prevent the count value update cycle from being recognized from the outside of the gaming control microcomputer 560, and it is determined that the game state is shifted to the big hit gaming state after initialization. The effect of preventing a big hit from being targeted by inputting a signal from an external connection board (hanging board) at the timing can be further improved.

Note that even when the game control microcomputer 560 does not include the random number circuit 5003 and an external random number circuit is used for the game control microcomputer 560, the clock circuit 5001 outputs a system clock signal. It is provided separately from a system clock circuit (not shown). The clock circuit 5001 generates a predetermined frequency generated by dividing a clock signal of a predetermined frequency (for example, 10.0 MHz) input from an oscillator provided outside the game control microcomputer 560 by 2 ⁷ (= 128). A reference clock signal CLK having a period is configured to be output to an external random number circuit. With this configuration, even when an external random number circuit is used, the frequency of the reference clock signal CLK output from the clock circuit 5001 to the external random number circuit and the operation of the game control microcomputer 560 The frequency can be different. When an external random number circuit is used, the clock circuit 5001 may be built in the game control microcomputer 560 or may be provided outside the game control microcomputer 560.

  Further, the clock circuit 5001 does not divide the clock signal input from the oscillator provided outside the game control microcomputer 560, and directly uses the random number circuit 5003 (or the game control microcomputer 560 as the reference clock signal CLK). May be output to an external random number circuit). Even in such a case, if the frequency of the clock signal generated by the oscillator (for example, 10.0 MHz) and the frequency of the system clock signal output by the system clock circuit (for example, 6.0 MHz) are different, the random number circuit The frequency of the reference clock signal CLK output to 5003 (or a random number circuit external to the game control microcomputer 560) and the operation frequency of the game control microcomputer 560 may be different.

  Further, for example, the clock circuit 5001 is not provided separately from the system clock circuit, but the CPU 56 and the random number circuit 5003 (or a random number circuit external to the game control microcomputer 560) are used by using a common clock circuit. A clock signal may be output. In this case, for example, frequency dividers having different frequency division numbers are provided between the clock circuit and the CPU 56 and between the clock circuit and the random number circuit 5003 (or a random number circuit external to the game control microcomputer 560). What is necessary is just to provide. For example, a signal obtained by dividing the clock signal output from the clock circuit by a frequency divider by 2 is input to the random number circuit 5003 (or a random number circuit external to the game control microcomputer 560), and the clock circuit outputs A signal obtained by dividing the clock signal to be divided by 3 by the 3 frequency divider may be input to the CPU 56. Even in such a case, the frequency of the reference clock signal CLK output to the random number circuit 5003 (or a random number circuit external to the game control microcomputer 560) is different from the operating frequency of the game control microcomputer 560. Can be configured. Further, the clock signal input to the random number circuit 5003 (or a random number circuit external to the game control microcomputer 560) may be configured to be shorter than the clock signal input to the CPU 56.

  The clock signal input to the CPU 56 and the random number circuit may be configured as follows.

(1) For example, when the random number circuit 5003 is built in the game control microcomputer 560, the game is separated from the oscillator provided outside the game control microcomputer 560 to generate the operation clock signal of the CPU 56. A clock signal from an oscillator provided outside the control microcomputer 560 may be input to the game control microcomputer 560. Then, the game control microcomputer 560 may input the input clock signal to the random number circuit 5003 and update the counter 521 in the random number circuit 5003.

(2) Further, for example, when the random number circuit 5003 is built in the game control microcomputer 560, an oscillator clock provided from the game control microcomputer 560 is used to generate an operation clock signal for the CPU 56. The clock signal may be input to the game control microcomputer 560. Then, the game control microcomputer 560 may input the input clock signal to the CPU 56 and the random number circuit 5003 to update the counter 521 in the random number circuit 5003. In this case, after being inputted to the game control microcomputer 560, the clock signal may be divided before being inputted to the CPU 56, and the clock signal may be divided before being inputted to the random number circuit 5003.

(3) Also, for example, when a random number circuit is provided outside the game control microcomputer 560, a clock signal from one oscillator provided outside the game control microcomputer 560 is branched. The game control microcomputer 560 and an external random number circuit may be input. Then, the clock signal is frequency-divided outside the game control microcomputer 560 or the clock signal is frequency-divided inside the game control microcomputer 560 and input to the CPU 56 as an operation clock signal and input to an external random number circuit. Before this, the clock signal may be divided and input to an external random number circuit.

(4) Further, for example, when the random number circuit is provided outside the game control microcomputer 560, an operation clock signal oscillator of the game control microcomputer 560 and an external random number circuit counter are provided. An oscillator for updating may be separately provided outside the game control microcomputer 560, and the frequency of the clock signal generated by each oscillator may be different.

  As shown in the above (1) to (4), in any case, in order to operate the game control microcomputer 560, an oscillator for generating a clock signal to be input to the game control microcomputer 560 is provided. The operation clock signal frequency-divided so that the CPU 56 operates by the clock signal generated by the oscillator and the random number circuit (the random number circuit 5003 built in the game control microcomputer 560 is also a random number external to the game control microcomputer 560. The frequency may be different from that of the clock signal input to the circuit. In particular, when the frequency of the clock signal input to the random number circuit is higher, it is possible to prevent the update period of the random number from being recognized by a signal such as a command output from the game control microcomputer 560. So it is more preferable.

  When a low level signal is input for a predetermined period, the reset controller 5002 outputs a predetermined initialization signal to the CPU 56 and the random number circuit 5003 to reset the game control microcomputer 560 as a system.

  In this embodiment, the random number circuit 5003 is a random number circuit that generates a 16-bit pseudo random number. The random number circuit 5003 has a function of generating a random number having a value in a range that can be generated by 16 bits (that is, a range from 0 to 65535).

  Next, the configuration of the random number circuit 5003 will be described. FIG. 18 is a block diagram illustrating a configuration example of the random number circuit 5003. As shown in FIG. 18, the random number circuit 5003 includes a counter 521, a comparator 522, a count value permutation changing circuit 523, a clock signal output circuit 524, a count value update signal output circuit 525, a random number update method selection signal output circuit 527, a selector. 528, a random number circuit activation signal output circuit 530, a first random value storage circuit (first latch circuit) 531a, and a second random value storage circuit (second latch circuit) 531a. Hereinafter, the random number circuit 5003 mounted on the game control microcomputer 5003 will be described, but the basic functions and operations of the random number circuit 107 mounted on the effect control microcomputer 100 are also the same.

  In this embodiment, the hardware random number generated by the random number circuit 5003 determines whether the display result of variable display of a plurality of types of identification information is a specific display result (for example, the display symbol of the special symbol display device 8). It is used to generate a jackpot determining random number for determining whether or not the combination is a jackpot symbol combination. Further, as will be described later, the game control microcomputer 560 generates a jackpot determination random number using the hardware random number (random R) generated by the random number circuit 5003 and the software random number (random 2-1). . When the CPU 56 of the game control microcomputer 560 determines that the specific display result is based on the generated jackpot determination random number, the game state is shifted to a specific game state advantageous to the player (for example, a jackpot game state). Let It should be noted that a random number for determination other than the jackpot symbol, such as a random number for probability variation for determining whether or not the random number generated by the random number circuit 5003 is a probability variation, or a random number for variation pattern determination for determining a variation pattern of a special symbol. May be used to generate

  The counter (hardware counter) 521 receives a predetermined signal selected by the selector 528 and outputs a count value C in response to the signal input from the selector 528. In this case, the counter 521 inputs a predetermined initial value, and cyclically updates the count value C from the initial value to a predetermined final value according to a certain rule, and outputs it. Further, when the count value C is updated to the final value, the counter 521 outputs a notification signal indicating that the count value C has been updated to the final value to the CPU 56. In this embodiment, when a notification signal is output from the counter 521, the CPU 56 updates the initial value.

  In this embodiment, every time a signal is input from the selector 528 (every time a rising edge in the signal from the selector 528 is input), the counter 521 increments the count value C from “0” to “65535” by one. Count up. Further, when the counter 521 counts up the count value C to “65535”, the counter 521 outputs a notification signal indicating that the count value C has been updated to the final value to the CPU 56. Then, the CPU 56 inputs a notification signal from the counter 521 and updates the initial value. The counter 521 counts up the count value C again from the initial value updated by the CPU 56 to “65535”. Further, when counting up to “65535”, the counter 521 starts counting from “0” again. Then, the counter 521 outputs a notification signal to the CPU 56 when it counts up to a value (final value) immediately before the updated initial value. In this embodiment, the comparator 522 outputs a notification signal to the counter 521 when all the count values are input, as will be described later. In this case, when the notification signal is input from the comparator 522, the counter 521 resets the count value to “0”.

  The comparator 522 determines whether the input count value is larger than the random number maximum value set in the random number maximum value setting register 535, and the count value is larger than the random number maximum value (exceeded the random number maximum value). ), A notification signal may be output to the counter 521. In this case, for example, when the comparator 522 determines that the count value exceeds the random number maximum value, the notification signal is output to the counter 521 before the clock signal output circuit 524 next outputs the random number generation clock signal SI1. . For example, consider a case where the random number maximum value “256” is set in the random number maximum value setting register 535. In this case, when the counter 521 counts up from “0” to “256” and further outputs the count value “257”, the comparator 522 determines that the input count value “257” exceeds the random number maximum value “256”. Determine and output a notification signal to the counter 521. When the notification signal is input from the comparator 522, the counter 521 updates the count value to “258” and outputs it without waiting for the input of the random number generation clock signal SI1 from the clock signal output circuit 524. By repeatedly executing the above processing, the comparator 522 determines that the count value exceeds the maximum random number value while inputting the count value “257” to “65535”, and stores the count value in the repeat counter 521. Output a notification signal. The counter 521 repeatedly updates and outputs the count value without waiting for the input of the random number generation clock signal SI1 from the clock signal output circuit 524 while the notification signal is input from the comparator 522. By doing so, until the clock signal output circuit 524 next outputs the random number generation clock signal SI1, the count value is controlled to be counted up from “257” to “65535” at a high speed, Control is performed so that random numbers from “257” to “65535” are skipped (not stored in the first random value storage circuit 531a and the second random value storage circuit 531b).

  The count value permutation change circuit 523 includes a count value permutation change register (RSC) 536, an update rule selection register (RRC) 542, and an update rule memory 543. The count value permutation change register 536 stores count value permutation change data “01h” for changing the permutation (order of arrangement from the initial value to the final value), which is the update order of the count value C counted up by the counter 521. . When the numerical value permutation change data “01h” is stored in the count value permutation change register 536, the count value permutation change circuit 523 displays the count value C permutation that the counter 521 counts up and updates. The permutation is changed to a different permutation from when “01h” is not stored. In this case, when the numerical value permutation change data “01h” is stored, the count value permutation changing circuit 523 switches the update rule used for changing the permutation of the count values. In addition, when the counter 521 starts updating the count value after switching the update rule used for changing the count value permutation, the count value permutation change data in the count value permutation change register 536 is initialized from “01h” by the CPU 56. The value is returned to “0 (= 00h)” (cleared).

  Instead of clearing the count value permutation data by the CPU 56, the count value permutation data may be cleared on the random number circuit 5003 side. For example, when the register value is set in the update rule selection register (RRC) 542 based on the count value permutation change data “01h” being written in the count value permutation change register 536, the count value permutation change circuit 523 The register value of the count value permutation change register 536 may be cleared.

  FIG. 19 is an explanatory diagram illustrating an example of the update rule selection register 542. The update rule selection register 542 is a register that sets an update rule used for rearranging the order of count values output from the counter 521 (changing the permutation). In this embodiment, an update rule used for changing the permutation of count values output from the counter 521 is set by setting a register value in the update rule selection register 542. As shown in FIG. 19, the update rule selection register 542 is an 8-bit register, and the initial value is set to “0 (= 00h)”. The update rule selection register 542 is configured in a state where bits 0 to 3 can be written and read. In addition, the update rule selection register 542 is configured in a state where bits 4 to 7 cannot be written or read. Therefore, even if control is performed to write values to bits 4 to 7 of the update rule selection register 542, it is invalid, and all the values read from bits 4 to 7 are “0 (= 0000b)”.

  The value (register value) of the update rule selection register 542 is changed from “0 (= 00h)” to “15” in response to the count value permutation change data “01h” being written in the count value permutation change register 536. (= 0Fh) ”is updated cyclically. That is, each time the count value permutation data “01h” is written to the count value permutation change register 536, the register value of the update rule selection register 542 is incremented by “1” from “0”. Return to "0".

  FIG. 20 is an explanatory diagram showing an example of the update rule memory 543. As shown in FIG. 20, the update rule memory 543 stores the value (register value) of the update rule selection register 542 and the count value update rule in association with each other. In the example shown in FIG. 20, for example, when the register value 1 is set in the update rule selection register 542, it can be seen that the permutation of the count values output by the counter 521 is changed using the update rule B. In FIG. 20, the update rule A is the same update rule as that by which the counter 521 updates the count value C, and is stored in the update rule memory 543 in association with the register value “0”. Also, in the update rule memory 543, update rules B to P different from the update rule in which the counter 521 updates the count value C are stored in association with the register values “1” to “15”.

  When the count value permutation change data “01h” is written in the count value permutation change register 536, the count value permutation change circuit 523 first counts from the counter 521 until the final count value “65535” is first input. The count value is output as it is according to the currently set update rule. When the count value permutation changing circuit 523 receives the final count value “65535” from the counter 521, the count value permutation changing circuit 523 changes the count value update rule. When the initial value is changed by the CPU 56, the count value permutation changing circuit 523 inputs the final value after the change (the value immediately before the initial value) from the counter 521, and updates the count value. Will be changed.

  The count value permutation change circuit 523 selects an update rule corresponding to the register value of the update rule selection register 542 from the update rule memory 543, and sets it as an update rule used for changing the count value permutation. The count value permutation changing circuit 523 changes the permutation from the initial value of the count value to the final value according to the set update rule when the counter 521 starts updating the count value again from the initial value “0”. To do. When the initial value is changed by the CPU 56, the count value permutation changing circuit 523 starts counting in accordance with the set update rule when the counter 521 starts updating the count value in order from the changed initial value. The permutation from the initial value to the final value will be changed. Then, the count value permutation change circuit 523 outputs a count value according to the changed permutation.

  In this embodiment, when the maximum random number to be generated is limited by setting the maximum random number in a random number maximum value setting register 535 described later, the count value permutation changing circuit 523 counts The value C is limited to the maximum random number or less, and the permutation is changed and output. For example, it is assumed that the random number maximum value “256” is set in the random number maximum value setting register 535, and the count value permutation changing circuit 523 changes the update rule A to the update rule B to change the count value permutation. Shall. In this case, the count value permutation changing circuit 523 changes the count value permutation to “256 → 255” according to the update rule B based on the random number maximum value “256” set in the random number maximum value setting register 535 of the comparator 522. → → → 0 "and output.

  As described above, when the count value permutation change data “01h” is written in the count value permutation change register 536, the count value permutation change circuit 523 changes the update rule to use the permutation of the count value C. Change and output. Therefore, the randomness of the random number generated by the random number circuit 5003 can be improved.

  FIG. 21 is an explanatory diagram illustrating an example in which the count value permutation changing circuit 523 changes the permutation of count values output from the counter 521. As shown in FIG. 21, the CPU 56 writes the count value permutation change data “01h” in the count value permutation change register 536 at a predetermined timing. Then, 1 is added to the register value of the update rule selection register 542. For example, the register value of the update rule selection register 542 is updated from “0” to “1”. When the register value is updated, the count value permutation changing circuit 523 updates the “update rule A” corresponding to the register value “0” before the update until the final value “65535” of the count value is input from the counter 521 for the first time. The count value is updated according to "." At this time, the count value permutation changing circuit 523 outputs the count values in the permutation of “0 → 1 →... → 65535” according to the update rule A.

  When the final value “65535” of the count value is input from the counter 521, the count value permutation changing circuit 523 selects “update rule B” corresponding to the updated register value “1” from the update rule memory 543. To set. When the count value permutation changing circuit 523 starts to input the count values after the initial value “0” from the counter 521 again, the count value permutation changing circuit 523 changes the permutation of the count values according to the selected “update rule B” and outputs it. In this example, the count value permutation changing circuit 523 changes the permutation from “0 → 1 →... → 65535” to “65535 → 65534 →... → 0” and outputs the count value.

  Thereafter, the count value permutation change register 536 is reset in response to the count value permutation change circuit 523 starting the count value updating operation in accordance with the updated update rule, as will be described later. Then, until the next count value permutation change data “01h” is written to the count value permutation change register 536, the count value permutation change circuit 523 counts the permutation as “65535 → 65534 →... → 0”. Continue to output values.

  When the count value permutation change data “01h” is written again to the count value permutation change register 536 by the CPU 56, the register value of the count value permutation change register 536 is updated from “1” to “2”. When the final value “65535” of the count value is input from the counter 521, the count value permutation changing circuit 523 selects and sets “update rule C” corresponding to the register value “2” from the update rule memory 543. . When the count value permutation changing circuit 523 starts to input the count value after the initial value “0” again from the counter 521, the count value permutation changing circuit 523 updates and outputs the count value permutation according to the “update rule C” selected and set. In this example, the count value permutation changing circuit 523 changes the permutation from “65535 → 65534 →... → 0” to “1 → 3 →... → 65535 → 0 →. Is output.

  As described above, after the count value permutation change register 536 is reset, the count value permutation data “01h” is written again in the count value permutation change register 536, so that the count value permutation can be further changed.

  FIG. 22 is an explanatory diagram illustrating an example of the count value permutation change register 536. The count value permutation change register 536 is a register that sets count value permutation change data “01h” for changing the permutation of count values counted up by the counter 521. As shown in FIG. 22, the count value permutation change register 536 is a readable 8-bit register, and the initial value is set to “0 (= 00h)”. Further, count value permutation change register 536 is configured such that only bit 0 can be written and read. That is, count value permutation change register 536 is configured such that bits 1 to 7 cannot be written or read. Therefore, even if control is performed to write values to bits 1 to 7 of the count value permutation change register 536, it is invalid, and all the values read from bits 1 to 7 are “0 (= 0000000b)”.

  Note that the value of the count value permutation change register 536 is reset by the CPU 56 in response to the count value permutation change circuit 523 starting a count value update operation in accordance with the updated update rule. In this case, the CPU 56 returns the value written in the count value permutation change register 536 from the count value permutation change data “01h” to the initial value “0 (= 00h)”.

  The comparator 522 includes a random number maximum value setting register (RMX) 535 that stores random number maximum value setting data for designating the maximum value of random R (random number maximum value). The comparator 522 limits the update range of the count value updated by the counter 521 according to the random number maximum value indicated in the random number maximum value setting data stored in the random number maximum value setting register 535. In this embodiment, the comparator 522 has a random number maximum value (for example, “00FFh”) indicated by the count value input from the counter 521 and the random number maximum value setting data (for example, “00FFh”) stored in the random number maximum value setting register 535. 256 "). When the comparator 522 determines that the input count value is equal to or less than the maximum random number value, the comparator 522 outputs the input count value to the first random value storage circuit 531a and the second random value storage circuit 531b.

  In this embodiment, the comparator 522 specifically performs the following control. The comparator 522 obtains the initial value of the count value from the CPU 56 when updating the initial value of the count value, and obtains the number of count values from the initial value to the maximum random number. For example, when the initial value of the count value is “157” and the maximum random number value is “256”, the comparator 522 calculates the number of count values from the initial value to the maximum random number value as “100”. The comparator 522 counts up how many count values have been input from the initial value as the count values are input from the count value permutation changing circuit 523. When the number of input count values from the initial value reaches “100”, the comparator 522 determines that all count values from the initial value “157” to the maximum value “256” have been input. Then, the comparator 522 outputs a notification signal indicating that all count values have been input to the counter 521. By determining based on the number of count values, even when the count value permutation circuit 523 has changed the count value permutation, the comparator 522 limits the update range of the count value to the maximum random number or less. When all count values are input, a notification signal can be output to the counter 521.

  An operation in which the comparator 522 limits the update range of the count value will be described. In this example, the case where the count value permutation changing circuit 523 selects the update rule A and the random number maximum value “256” is set in the random number maximum value setting register 535 will be described.

  While the counter 521 is updating the count value from “0” to “256”, the count value permutation changing circuit 523 updates based on the random number maximum value “256” set in the random number maximum value setting register 535. In accordance with rule A, the count values from “0” to “256” are output to the comparator 522 as they are. In this case, the count value permutation changing circuit 523 receives the value of the random number maximum value “256” from the comparator 522, determines whether the count value input from the counter 521 is larger than the random number maximum value, and the update rule is changed. Even when it is set (for example, update rule B), the count values from “257” to “65535” are compared based on the random number maximum value “256” set in the random number maximum value setting register 535. The data is not output to the device 522. For example, when the initial value is set to “0” and the count value is updated to the final value “256”, the counter 521 outputs a notification signal to the CPU 56. When the notification signal is output, the CPU 56 changes the initial value of the count value of the counter 521. In this example, it is assumed that the initial value is changed to “50” by the CPU 56.

  Note that the comparator 522 may determine whether the count value is greater than the random number maximum value “256”, instead of the count value permutation changing circuit 523. In this case, for example, the comparator 522 determines whether or not the count value is greater than the random number maximum value set in the random number maximum value setting register 535, and determines that the count value is greater than the random number maximum value. Is output to the counter 521. When the comparator 522 determines that the count value exceeds the random number maximum value, the comparator 522 outputs a notification signal to the counter 521 before the clock signal output circuit 524 next outputs the random number generation clock signal SI1. By doing so, the comparator 522 counts up the count value from “257” to “65535” at high speed until the clock signal output circuit 524 next outputs the random number generation clock signal SI1. Thus, the counter 521 is controlled. By doing so, the count value is output to the first random number value storage circuit 531a and the second random number value storage circuit 531b only when the value from the count value permutation change circuit 523 is less than “257”, and the count value When the value from the permutation changing circuit 523 is “257” or more, the count value can be updated at high speed.

  Based on the update rule A, while the count value is input from “0” to “255” from the count value permutation changing circuit 523, the comparator 522 inputs the count value below the maximum random number “256”. Therefore, the input count value is output to the first random value storage circuit 531a and the second random value storage circuit 531b as it is. Next, when the count value input from the count value permutation changing circuit 523 reaches “256”, the comparator 522 outputs the input count value to the first random number value storage circuit 531a and the second random number value storage circuit 531b. At the same time, a notification signal indicating that all count values from the initial value to the maximum value have been input is output to the counter 521. Specifically, the comparator 522 receives an initial value (“0” in this example) of the count value from the CPU 56 when changing the initial value of the count value, and the random number maximum value (the main value) from the initial value “0”. In the example, the number of count values up to “256” (in this example, “257”) is obtained. When the number of count values input from the count value permutation changing circuit 523 reaches 257, a notification signal indicating that all count values have been input is output to the counter 521. In this example, since the CPU 56 changes the initial value to “50”, the counter 521 does not reset the count value even when the notification signal is input from the comparator 522, and the changed initial value “50”. The count value is updated.

  While the counter 521 updates the count value from the changed initial value “50” to “256”, the count value permutation changing circuit 523 sets the random number maximum value “256” set in the random number maximum value setting register 535. Based on the update rule A, the count values from “50” to “256” are output to the comparator 522 as they are. Further, the count value permutation changing circuit 523 does not output the count values from “257” to “65535” to the comparator 522 based on the random number maximum value “256” set in the random number maximum value setting register 535. When the count value to be updated by the counter 521 makes one round (when updated 257 times), when the count value permutation change data is written in the count value permutation change register 536, the count value permutation change circuit 523 Change the permutation of count values and output. For example, when the update rule is changed to the update rule B, the count value permutation changing circuit 523 changes the count value permutation from “256 → 255 →... → 50” and outputs the result.

  While the count values from “256” to “50” are input from the count value permutation changing circuit 523, the comparator 522 uses the input count values as they are as the first random value storage circuit 531a and the second random number storage circuit. To 531b. Next, when the count value input from the count value permutation changing circuit 523 reaches “50”, the comparator 522 outputs the input count value to the first random number value storage circuit 531a and the second random number value storage circuit 531b. At the same time, a notification signal indicating that all count values from the initial value to the maximum value have been input is output to the counter 521. Specifically, the comparator 522 receives the initial count value (“50” in this example) from the CPU 56 when the initial count value is changed, and the random number maximum value (this In the example, the number of count values up to “256” (in this example, “207”) is obtained. When the number of count values input from count value permutation changing circuit 523 reaches 207, a notification signal indicating that all count values have been input is output to counter 521.

  Even when the count value permutation changing circuit 523 changes the count value permutation, the comparator 522 outputs a notification signal to the counter 521 when the number of count values reaches 207. By doing so, even if the permutation of the count values is changed, the notification signal is counted based on the input of all the count values from the initial value “50” to the maximum value “256”. 521 can be output.

  When the notification signal is input from the comparator 522, the counter 521 resets the initial value of the count value and returns it to “0”. Then, the counter 521 updates the count value from “0”. When the value of the counter 521 is updated again from “0”, the count value permutation changing circuit 523 outputs the count values from “49” to “0” to the comparator 522 based on the count value from the counter 521. The comparator 522 outputs the count value to the first random value storage circuit 531a and the second random value storage circuit 531b based on the input of the count value from the count value permutation circuit 523. When the counter 521 updates the count value to the final value (“49” in this example), the counter 521 outputs a notification signal to the CPU 56. When the notification signal is output, the initial value of the count value of the counter 521 is changed again by the CPU 56.

  By repeating the operation as described above, the comparator 522 causes the counter 521 to continuously count up the count value from “0” to the maximum random number “256”, and the value from “0” to “256”. Are stored as random R (random value) in the first random value storage circuit 531a and the second random value storage circuit 531b. In other words, the comparator 522 limits the update range of the count value to the random number maximum value “256” or less, and causes the counter 521 to update the count value.

  FIG. 23 is an explanatory diagram illustrating an example of the random number maximum value setting register 535. As shown in FIG. 23, in the random number circuit 5003, the random number maximum value setting register 535 is a 16-bit register, and the initial value is set to “65535 (= FFFFh)”. Further, in the random number circuit 5003, the random number maximum value setting register 535 is configured in a state in which all of the bits 0 to 15 can be written and read.

  When random number maximum value setting data “0000h” to “01FEh” for designating a value smaller than the lower limit value “512” is written in the random number maximum value setting register 535, the CPU 56 sets the initial value in the random number maximum value setting register 535 to the initial value. The random number maximum value setting data “FFFFh” specifying the value “65535” is reset. That is, the random number maximum value that can be set in the random number maximum value setting register 535 is from “512” to “65535”, and when the CPU 56 determines that a value smaller than the lower limit value “512” is set, the random number maximum value Is reset to a predetermined value “65535”. The CPU 56 controls the random number maximum value setting register 535 in which the random number maximum value setting data is written to be unwritable until the game control microcomputer 560 is system reset by the reset controller 5002. Instead of controlling the CPU 56 to disable writing, the random number maximum value setting register 535 may be formed so that writing is not possible until a reset signal is input after data is written.

  The clock signal output circuit 524 includes a cycle setting register (RPS) 537 that stores cycle setting data for designating the cycle of the clock signal output to the selector 528 (that is, the count value update cycle). The clock signal output circuit 524 divides the reference clock signal CLK input from the clock circuit 5001 mounted on the game control microcomputer 560 based on the period setting data stored in the period setting register 537, and generates a random number circuit. A clock signal (random number generating clock signal SI1) used to generate a random number value is generated inside 5003. By doing so, the clock signal output circuit 524 operates to output the random number generation clock signal SI1 for updating the count value C to the counter 521 on condition that the clock signal has been input a predetermined number of times. . The period setting data is data for setting how many times the reference clock signal CLK input from the clock circuit 5001 is divided. The clock output circuit 524 outputs the generated random number generation clock signal SI1 to the selector 528. For example, when the cycle setting data “0Fh (= 16)” is written in the cycle setting register 537, the clock signal output circuit 524 divides the reference clock signal CLK input from the clock circuit 5001 by 16, and generates random numbers. A clock signal SI1 is generated. In this case, the cycle of the random number generating clock signal SI1 generated by the clock signal output circuit 524 is “cycle of system clock signal × 128 × 16”.

  FIG. 24 is an explanatory diagram showing an example of the period setting register 537. As shown in FIG. 24, the period setting register 537 is an 8-bit register, and the initial value is set to “256 (= FFh)”. The cycle setting register 537 is configured in a state where both writing and reading are possible.

  In addition, a predetermined lower limit value is determined for the value of the cycle setting data set in the cycle setting register 537. In this embodiment, when the cycle setting data “00h to 06h” designating a value smaller than the lower limit value “system clock signal cycle × 128 × 7” is written in the cycle setting register 537, the CPU 56 In 537, the cycle setting data “07h” for specifying the lower limit value “system clock signal cycle × 128 × 7” is reset. That is, the period that can be set in the period setting register 537 is “system clock signal period × 128 × 7” to “system clock signal period × 128 × 256”, and the CPU 56 is set to a value smaller than the lower limit value. If it is determined that the cycle setting data is correct, the cycle setting data is reset. The CPU 56 controls the period setting register 537 in which the period setting data is written to be unwritable until the game control microcomputer 560 is system-reset by the reset controller 5002. Instead of controlling the CPU 56 to disable writing, the period setting register 537 may be formed so that writing is not possible until a reset signal is input after data is written.

  Note that, without setting the cycle setting data as the lower limit value in the cycle setting register 537, for example, the clock signal output circuit 524 outputs the reference clock signal CLK to the counter 521 as it is based on the set cycle setting data. May be. In this case, the CPU 56 does not need to perform processing for setting the value of the cycle setting data set in the cycle setting register 537 by comparing it with the lower limit value. The counter 521 updates the count value C every time the reference clock signal CLK is input from the clock signal output circuit 524.

  The count value update signal output circuit 525 includes a count value update register (RGN) 538 that stores count value update data “01h”. The count value update data is data for requesting update of the count value. The count value update signal output circuit 525 outputs the count value update signal SI3 to the selector 528 in response to the count value update data “01h” being written in the count value update register 538.

  FIG. 25 is an explanatory diagram illustrating an example of the count value update register 538. As shown in FIG. 25, the count value update register 538 is an unreadable 8-bit register, and is configured so that only bit 0 can be written. Therefore, even if control is performed to write a value to bits 1 to 7 of the count value update register 538, it is invalidated.

  The random number update method selection signal output circuit 527 includes a random number update method selection register (RTS) 540 that stores random number update method selection data. The random number update method selection data is data for designating one of the random number update methods that is a method for updating the value of the random R. The random number update method selection signal output circuit 527 responds to the random number update method selection data written in the random number update method selection register 540 with a random number corresponding to the random number update method specified by the written random number update method selection data. An update method selection signal is output to the selector 528.

  FIG. 26A is an explanatory diagram illustrating an example of the random number update method selection register 540. As shown in FIG. 26A, the random number update method selection register 540 is an 8-bit register, and the initial value is set to “00h”. The random number update method selection register 540 is configured in a state where bits 0 to 1 can be written and read. The random number update method selection register 540 is configured in a state where bits 2 to 7 cannot be written or read. Therefore, even if control is performed to write a value to bits 2 to 7 of the random number update method selection register 540, it is invalid, and all the values read from bits 2 to 7 are “0 (= 000000b)”.

  FIG. 26B is an explanatory diagram of an example of random number update method selection data written to the random number update method selection register 540. As shown in FIG. 26B, the random number update method selection data is composed of 2-bit data. The random number update method selection data “01b” is used to specify the first random number update method. The random number update method selection data “10b” is used to specify the second random number update method. In this embodiment, the first random number update method is a method of updating the count value triggered by the output of the count value update signal SI3 from the count value update signal output circuit 525. The second random number update method is a method of updating the count value triggered by the output of the random number generation clock signal SI1 from the clock signal output circuit 524. Further, when the random number update method selection data “01b” or “10b” is written in the random number update method selection register 540, the random number circuit 5003 is ready to be activated. On the other hand, when the random number update method selection data “00b” or “11b” is written in the random number update method selection register 540, the random number circuit 5003 cannot be activated.

  The selector 528 selects either the count value update signal SI 3 output from the count value update signal output circuit 525 or the random number generation clock signal SI 1 output from the clock signal output circuit 524 and outputs the selected signal to the counter 521. When a random number update method selection signal (also referred to as a first random number update method selection signal) corresponding to the first random number update method is input from the random number update method selection signal output circuit 527, the selector 528 outputs a count value update signal. The count value update signal SI3 output from the circuit 525 is selected and output to the counter 521. On the other hand, when a random number update method selection signal (also referred to as a second random number update method selection signal) corresponding to the second random number update method is input from the random number update method selection signal output circuit 527, the selector 528 outputs a clock signal. The random number generation clock signal SI 1 output from the circuit 524 is selected and output to the counter 521. When the first update method selection signal is input from the random number update method selection signal output circuit 527, the selector 528 receives a clock signal according to the count value update signal SI3 output from the count value update signal output circuit 525. A numerical value update instruction signal for instructing update of numerical data synchronized with the random number generation clock signal SI1 output from the output circuit 524 may be output to the counter 521.

  The random number circuit activation signal output circuit 530 includes a random number circuit activation register (RST) 541 that stores random number circuit activation data “80h”. The random number circuit activation data is data for requesting activation of the random number circuit 5003. When random number circuit activation data “80h” is written to the random number circuit activation register 541, the random number circuit activation signal output circuit 530 outputs a predetermined random number circuit activation signal to the counter 521 and the clock signal output circuit 537, and the counter 521 and the clock The signal output circuit 524 is turned on. The random number circuit 5003 is activated by starting the count value update operation by the counter 521 and the internal clock signal output operation by the clock signal output circuit 524.

  FIG. 27 is an explanatory diagram showing an example of the random number circuit activation register 541. As shown in FIG. 27, the random number circuit activation register 541 is an 8-bit register, and the initial value is set to “00h”. The random number circuit activation register 541 is configured such that only bit 7 can be written and read. The random number circuit activation register 541 is configured in a state in which bits 0 to 6 cannot be written or read. That is, even if control is performed to write a value to bit 0 to bit 6 of the random number circuit activation register 541, it is invalid, and all the values read from bit 0 to bit 6 are “0 (= 000000b)”.

  The first random value storage circuit 531a and the second random value storage circuit 531b are, for example, 16-bit registers, and store a random R value that is a hardware random number used for generating a big hit determination random number in the game control process. In response to the detection signal from the first start port switch 13a being input as the latch signal SL1, the first random value storage circuit 531a sets the count value C output from the counter 521 via the comparator 522 to the random R value. Store as a value. The first random number storage circuit 531a reads the count value C updated by the counter 521 and stores the value of random R every time the detection signal from the first start port switch 13a is input as the latch signal SL1. Further, the second random number value storage circuit 531b randomly calculates the count value C output from the counter 521 via the comparator 522 in response to the detection signal from the second start port switch 14a being input as the latch signal SL2. Store as R value. Then, every time the detection signal from the second start port switch 13b is input as the latch signal SL2, the second random value storage circuit 531b reads the count value C updated by the counter 521 and stores the random R value.

  Hereinafter, when the first random value storage circuit 531a and the second random value storage circuit 531b are comprehensively expressed, or when referring to either the first random value storage circuit 531a or the second random value storage circuit 531b. In addition, it is simply referred to as a random value storage circuit 531.

  Further, in this embodiment, when a random number circuit setting process (see step S14) to be described later is executed, the random value storage circuit 531 performs comparison from the counter 521 in response to the input of the latch signal SL0 from the CPU 56. The count value C output through the device 522 is stored as a random R value.

  FIG. 28 is a circuit diagram showing a configuration example of the random value storage circuit 531. As shown in FIG. 28, the random value storage circuit 531 includes two AND circuits 2001 and 2003, two NOT circuits 2002 and 2004, 16 flip-flop circuits 2101 to 2116, and 16 OR circuits. 2201-2216.

  As shown in FIG. 28, the input terminal of the AND circuit 2001 is connected to the output terminal of the latch signal generation circuit 533 and the output terminal of the NOT circuit 2004, and the output terminal is connected to the input terminal of the NOT circuit 2002 and the flip-flop circuit 2101. Are connected to clock terminals Clk1 to Clk16. The input terminal of the NOT circuit 2002 is connected to the output terminal of the AND circuit 2001, and the output terminal is connected to one input terminal of the AND circuit 2003.

  The input terminal of the AND circuit 2003 is connected to the output terminal of the NOT circuit 2002 and the CPU 56 mounted on the game control microcomputer 560, and the output terminal is connected to the input terminal of the NOT circuit 2004. An input terminal of the NOT circuit 2004 is connected to an output terminal of the AND circuit 2003, and an output terminal is connected to one input terminal of the AND circuit 2001 and one input terminal of the OR circuits 2201 to 2216.

  The input terminals D1 to D16 of the flip-flop circuits 2101 to 2116 are connected to the output terminal of the comparator 522. The clock terminals Clk1 to Clk16 of the flip-flop circuits 2101 to 2116 are connected to the output terminal of the AND circuit 201, and the output terminals Q1 to Q16 are connected to the other input terminals of the OR circuits 2201 to 2216.

  The input terminals of the OR circuits 2201 to 2216 are connected to the output terminal of the NOT circuit 2004 and the output terminals of the flip-flop circuits 2101 to 2116, and the output terminals are connected to the CPU 56 mounted on the game control microcomputer 560. .

  The operation of the random value storage circuit 531 will be described. FIG. 29 is a timing chart showing the timing at which each signal is input to the random value storage circuit 531 and the timing at which the random value storage circuit 531 outputs each signal. As shown in FIG. 29, when the output control signal SC (high level signal in this example) is not input from the CPU 56 mounted in the game control microcomputer 560 (that is, to one input terminal of the AND circuit 203). When the input is at a low level, the latch signal SL from the first start port switch 13a or the second start port switch 14a (specifically, the latch signal SL1 from the first start port switch 13a or the second start port switch 14a) When the latch signal SL2 is input (at timings T1, T2, and T7 in the example shown in FIG. 29), the inputs to the two input terminals of the AND circuit 2001 are both at a high level. Therefore, the signal SR output from the output terminal of the AND circuit 2001 is at a high level. The signal SR output from the AND circuit 2001 is input to the clock terminals Clk1 to Clk16 of the flip-flop circuits 2101 to 2116.

  The flip-flop circuits 2101 to 2116 respond to the rising edges of the signal SR input from the clock terminals Clk1 to Clk16, and receive the bit data C1 to C1 of the count value C input from the comparator 522 via the input terminals D1 to D16. C16 is latched and stored as bit data R1 to R16 of a random value. The flip-flop circuits 2101 to 2116 output random R bit data R1 to R16 to be stored from the output terminals Q1 to Q16.

  When the output control signal SC is not input (in the example shown in FIG. 29, the period up to the timing T3 and the period after the timing T6), the input to one input terminal of the AND circuit 2003 is at the low level. The signal SG output from the output terminal of the circuit 2003 is at a low level. The signal SG output from the AND circuit 2003 is inverted in the NOT circuit 2004 to be a high level signal. A high level signal is input from the NOT circuit 2004 to one input terminal of each of the OR circuits 2201 to 2216.

  As described above, since the input to one of the input terminals of the OR circuits 2201 to 2216 is at a high level, the OR is input regardless of whether the signal input to the other input terminal is at a high level or a low level. The circuits 2201 to 2216 output high level signals. That is, the signals SO1 to SO16 output from the OR circuits 2201 to 2216 are all at a high level regardless of whether the values of the input random R bit data R1 to R16 are “0” or “1”. (“1”). By doing so, the value output from the random value storage circuit 531 is always “65535 (= 1111111111111111b)”, and the random R cannot be read from the random value storage circuit 531. That is, even if an attempt is made to read a random number from the random value storage circuit 531, only the same value “65535” can always be read from the random value storage circuit 531, and when the output control signal SC is not input, the random value storage circuit 531 becomes an unreadable (disabled) state.

  When the output control signal SC is input from the CPU 56 when the latch signal SL is not input from the latch signal generation circuit 533 (in the example shown in FIG. 29, the period from the timing T4 to the timing T6), the AND circuit 2003 Since the inputs to the two input terminals are both at the high level, the signal SG output from the output terminal of the AND circuit 2003 is at the high level. The signal SG output from the AND circuit 2003 is inverted in the NOT circuit 2004 to be a low level signal. A low level signal is input from the NOT circuit 2004 to one input terminal of each of the OR circuits 2201 to 2216.

  As described above, since the input to one input terminal of the OR circuits 2201 to 2216 is at a low level, when the signal input to the other input terminal is at a high level, the output from the output terminals of the OR circuits 2201 to 2216 is high. A level signal is output. In addition, when a signal input to the other input terminal of the OR circuits 2201 to 2216 is at a low level, a low level signal is output from the OR circuits 2201 to 2216. That is, the values of the random R bit data R1 to R16 input to the other input terminals of the OR circuits 2201 to 2216 are unchanged from the output terminals of the OR circuits 2201 to 2216 (that is, the values of the bit data R1 to R16 are “ “1” is output when it is “1” and “0” when it is “0”). By doing so, random R can be read from the random value storage circuit 531. That is, when the output control signal SC is input, the random value storage circuit 531 is in a readable (enable) state.

  However, if the latch signal SL is input from the first start port switch 13a or the second start port switch 14a before the output control signal SC is input from the CPU 56, the input to one input terminal of the AND circuit 2003 is performed. Therefore, even if the output control signal SC is input with the latch signal SL being input (in the example shown in FIG. 29, the period from the timing T3 to the timing T4), the AND circuit 2003 The signal SG output from the output terminal remains at a low level. The signal SG output from the AND circuit 2003 is inverted in the NOT circuit 2004 to be a high level signal. A high level signal is input from the NOT circuit 2004 to one input terminal of each of the OR circuits 2201 to 2216.

  As described above, since the input to one of the input terminals of the OR circuits 2201 to 2216 is at a high level, the OR is input regardless of whether the signal input to the other input terminal is at a high level or a low level. The signals SO1 to SO16 output from the circuits 2201 to 2216 are all at a high level. Even though the output control signal SC is input, the random R cannot be read from the random value storage circuit 531. That is, when the latch signal SL is input, the random value storage circuit 531 cannot receive the output control signal SC.

  When the output control signal SC is input from the CPU 56 before the latch signal SL is input from the first start port switch 13a or the second start port switch 14a, the input to one input terminal of the AND circuit 2001 is input. Therefore, even if the latch signal SL is input with the output control signal SC being input (timing T5 in the example shown in FIG. 29), it is output from the output terminal of the AND circuit 2001. The signal SR remains at a low level. Therefore, the signal SR input to the clock terminals Clk1 to Clk16 of the flip-flop circuits 2101 to 2116 does not rise from the low level to the high level, and the random R bit data R1 to R16 stored in the flip-flop circuits 2101 to 2116. Although the latch signal SL is input, the stored random number is not updated. That is, when the output control signal SC is input, the random value storage circuit 531 cannot receive the latch signal SL.

  FIG. 30 is an explanatory diagram showing an example of an address map of a storage area in the game control microcomputer 560. As shown in FIG. 30, the area from address 0000h to address 1FFFh in the storage area of the game control microcomputer 560 is allocated to the ROM 54. An area from addresses 7E00h to 7FFFh is allocated to the RAM 55. Further, the area from the address FD00h to the address FE00h is allocated to a built-in register such as the random number maximum value setting register 535.

  As shown in FIG. 30, the area from address 0000h to 1FFFh allocated to the ROM 54 includes a user program area and a user program management area. A program (user program) 550 created in advance by a user (for example, a game machine manufacturer) is stored in the user program area in the area of addresses 0000h to 1F7Fh. Further, data (user program execution data) necessary for the CPU 56 to execute the user program 550 is stored in the user program management area in the area of addresses 1F80h to 1FFFh. An area from addresses 7E00h to 7FFFh allocated to the RAM 55 is used as a work area (work area). Among the work areas, the areas from 7E00h to 7EFFh are counters for counting software random numbers (specifically, random 2-1 to random 7 described later) (for example, a jackpot determination calculation counter described later). And a jackpot type determination counter) are used as a software random number counter storage area. The area from address 7F00h to address 7FFFh is used as an area other than the software random number counter storage area (for example, an area in which the value of the software random number extracted from each counter is stored).

  In this embodiment, as will be described later, in the initialization process at the time of power-on (see step S11), in the area of the RAM 55, the area from address 7F00h to address 7FFFh (software random number counter storage in the work area is stored). Processing for clearing only data stored in other areas other than the area is performed, and data stored in the area (software random number counter storage area) of addresses 7E00h to 7EFFh (specifically, each software A counter for counting a random number (for example, a jackpot determination calculation counter or a normal symbol determination counter described later) is processed so as not to be cleared. Note that counters such as jackpot determination calculation counters and normal symbol determination counters are processed so as not to be cleared, and each software random number value extracted after being updated using these counters itself Are stored in other areas and cleared during the initialization process (see step S11).

  Note that not all the software random number counters are cleared in the initialization process at the time of power-on (see step S11), but a later-described jackpot determination calculation random number (random 2-1) among software random numbers is used. Only the jackpot determination calculation counter for counting may not be cleared, and the counters for counting other software random numbers may be cleared. Even in such a configuration, it is sufficient that a big hit is targeted by inputting a signal from the external connection board (hanging board) at a timing at which it is determined that the game will be shifted to the big hit gaming state after initialization. Can be prevented. For example, for the random number for normal symbol determination (random 6), which will be described later, since there is little profit due to the normal symbol variation display result being hit, a signal is input from the external connection board (hanging board). It is unlikely that the hit will be targeted. Therefore, the normal symbol per-determination counter for counting the normal symbol per-determination random number (random 6) has little effect even if it is cleared in the initialization process. Therefore, even if it is configured not to clear only the jackpot determination calculation counter, by inputting a signal from the external connection board (hanging board) at a timing when it is determined to shift to the jackpot gaming state after initialization. It is possible to sufficiently prevent the big hit from being targeted.

  In addition, the start address of the area in which initialization is performed in the area of the RAM 55 may be an address that is continuous with the area that is not initialized. By doing so, it is possible to prevent a useless RAM area from being generated. In addition, the software random number counter storage area may be located at the last address of the work area address. In this case, initialization is performed in order from the lower address to the higher address. It may be. Alternatively, the addresses from the work area start address to the software random number counter storage area may be initialized in order. The software random number counter storage area may be set to be an address in the middle of the work area.

  FIG. 31 is an explanatory diagram showing an example of an address map in the user program management area. As shown in FIG. 31, the initial value changing method selected by the user among the initial value changing methods which are methods for changing the initial value input to the counter 521 of the random number circuit 5003 is included in the area of address 1F97h. The initial value change method setting data for designating is stored. Further, in the areas 1F98h and 1F99h, RAM address data for specifying an address in the RAM 55 (designated RAM address) designated in advance by the user among addresses 7F00h to 7FFFh allocated to the RAM 55 is stored. The In this case, of the values indicating the designated RAM address, the lower value of the designated RAM address is stored in the 1F98h address, and the higher value of the designated RAM address is stored in the 1F99h address.

  FIG. 32 is an explanatory diagram of an example of initial value change method setting data. As shown in FIG. 32, the initial value change data is composed of 8-bit data. The initial value change data “00h” is data specifying that the initial value is not changed as the initial value change method. In this embodiment, when the initial value change data “00h” is set, the counter 521 of the random number circuit 5003 updates the count value from a predetermined initial value “0” to a predetermined final value. Become. Further, the initial value change data “01h” is data specifying that the initial value input to the counter 521 is changed to a value based on an ID number for identifying the game control microcomputer 560 as an initial value change method. It is. In this embodiment, when the initial value change data “01h” is set, the initial value of the counter value updated by the counter 521 is changed from “0” to a value based on the ID number. The count value is updated from the initial value to a predetermined final value.

  The user program 550 stored in the user program area will be described. FIG. 33 is an explanatory diagram showing a configuration example of the user program 550. As shown in FIG. 33, in this embodiment, the user program 550 includes a random number circuit setting program 551 composed of a plurality of types of program modules, a display result determination program 552, a count value permutation change program 554, And a numerical value update program 555.

  The random number circuit setting program 551 is a program for executing a random number circuit setting process for performing an initial setting for causing the random number circuit 5003 to update the random R value. That is, the CPU 56 functions as random number circuit initial setting means by executing processing according to the random number circuit setting program 551.

  FIG. 34 is an explanatory diagram showing a configuration example of the random number circuit setting program 551. As shown in FIG. 34, the random number circuit setting program 551 includes a random number maximum value setting module 551a, a random number update method selection module 551b, a cycle setting module 551c, a random number circuit activation module 551d, as a plurality of types of program modules. An initial value changing module 551e and a random number circuit selecting module 551f are included.

  The random number maximum value setting module 551a is a program module for causing the random number circuit 5003 to set the maximum value of the random R preset by the user (for example, the manufacturer of the gaming machine). The CPU 56 executes processing according to the random number maximum value setting module 551a, thereby writing random number maximum value setting data for specifying the maximum value of the random R preset by the user in the random number maximum value setting register 535. By doing so, the CPU 56 sets the maximum value of the random R preset by the user in the random number circuit 5003. For example, when “255” is set in advance as the maximum value of the random R by the user, the CPU 56 writes the random number maximum value setting data “00FFh” in the random number maximum value setting register 535 and the random R maximum value “255”. Is set in the random number circuit 5003.

  The random number update method selection module 551b is a program module for causing the random number circuit 5003 to set the random number update method (first random number update method or second random number update method) selected by the user. The CPU 56 writes the random number update method selection data “01b” or “10b” designating the random number update method selected by the user in the random number update method selection register 540 by executing the process according to the random number update method selection module 551b. By doing so, the CPU 56 sets the random number update method selected by the user in the random number circuit 5003. Therefore, the game control microcomputer 560 has a function of selecting either the first random number update method or the second random number update method as the random number update method used by the random number circuit 5003 for the random number update.

  The cycle setting module 551c is a program for causing the random number circuit 5003 to set the cycle of the internal clock signal preset by the user (that is, the cycle in which the clock signal output circuit 524 outputs the clock signal to the selector 528 and the inverting circuit 532). It is a module. The CPU 56 writes processing in the cycle setting register 537 for designating the cycle of the internal clock signal preset by the user by executing processing in accordance with the cycle setting module 551c. By doing so, the CPU 56 sets the cycle of the internal clock signal preset by the user in the random number circuit 5003. For example, when the cycle of the internal clock signal is set in advance as “system clock signal cycle × 128 × 16” by the user, the CPU 56 writes the cycle setting data “0Fh” in the cycle setting register 537 and sets the internal clock signal The period “system clock signal period × 128 × 16” is set in the random number circuit 5003.

  The random number circuit activation module 551d is a program module for activating the random number circuit 5003. The CPU 56 activates the random number circuit 5003 by writing the random number circuit activation data “80h” into the random number circuit activation register 541 by executing processing according to the random number circuit activation module 551d.

  The initial value change module 551e is a program module for changing the initial value of the count value updated by the counter 521. The CPU 56 functions as an initial value changing unit by executing processing according to the initial value changing module 551e. The CPU 56 executes the initial value changing module 551e to change the initial value of the count value updated by the counter 521 by the initial value changing method selected by the user. By doing so, the CPU 56 has a function of selecting an initial value changing method.

  In this embodiment, when initial value change method setting data “01h” is stored in the area of address 1F97h in the user program management area, the CPU 56 sets the initial value of the count value for each game control microcomputer 560. The value is changed to a value calculated based on the assigned unique ID number.

  For example, the game control microcomputer 560 associates, in a predetermined storage area of the ROM 54, the ID number of the game control microcomputer 560 with a calculated value obtained by performing a predetermined calculation based on the ID number. I remember it. In this case, for example, if the ID number of the game control microcomputer 560 is “100”, the calculated value “150” obtained by adding the predetermined value “50” to the ID number “100” is set in advance as the ID number. Are stored in association with each other. Further, for example, the calculated value “50” obtained by subtracting the predetermined value “50” from the ID number “100” is stored in advance in association with the ID number. Further, for example, only a predetermined value may be stored in advance in association with the ID number. Then, the CPU 56 of the game control microcomputer 560 adds a value “150” obtained by adding an ID number (for example, “100”) to a predetermined value (for example, “50”) stored in advance, and sets the initial count value. The CPU 56 may also use a value “50” obtained by subtracting a predetermined value (eg, “50”) stored in advance from the ID number (eg, “100”) as an initial value of the count value. It is good.

  When the initial value change method setting data “01h” is stored, the CPU 56 changes the initial value of the count value to the calculated value based on the ID number stored in advance. By doing so, the randomness of the random number generated by the random number circuit 5003 can be further improved, and the initial value of the random number can be made difficult to recognize only by looking at the ID number of the game control microcomputer 560. . Therefore, it is possible to more reliably prevent the transition condition to the big hit state from being illegally established by an action such as generating a captured signal using a radio signal to the gaming machine, and improving security. Can be improved.

  For example, when initial value change method setting data “01h” is stored, the CPU 56 calculates the ID number of the game control microcomputer 560 and a predetermined value (for example, adds a predetermined value to the ID number). The initial value of the count value is changed to the calculated value obtained. In this case, for example, the CPU 56 may calculate a value that is randomly changed using a random number as an ID number, thereby randomly updating a value used for the calculation and obtaining an initial value. By doing so, the randomness of the random numbers generated by the random number circuit 5003 can be further improved.

  The random value update program 555 is a program for updating the value of the random R stored in the random value storage circuit 531 when the first random number update method is selected as the random number update method. The CPU 56 functions as a random value updating unit by executing processing according to the random value updating program 555. When the first random number update method is selected, the CPU 56 executes the random number value update program 555 and writes the count value update data “01h” in the count value update register 538, whereby the count value is stored in the counter 521. And the value of the random R stored in the random value storage circuit 531 is updated. When the second random number update method is selected as the random number update method, the counter 521 is updated with the random number generation clock signal output from the clock signal output circuit 537, and the random value storage circuit 531 is updated. The value of random R stored in is updated.

  The display result determination program 552 is a program for determining whether or not the display result in the special symbol display device 8 is a jackpot symbol. The CPU 56 functions as a display result determination unit by executing processing according to the display result determination program 552.

  In this embodiment, the CPU 56 responds that a condition (execution condition) for the game ball to win the first start winning opening 13 or the second start winning opening 14 and execute the variable display of the special symbol is established. The process is executed according to the display result determination program 552. Then, the CPU 56 reads the updated random R value from the random value storage circuit 531 to generate a jackpot determination random number, and determines whether or not the display result in the special symbol display device 8 is a jackpot symbol.

  FIG. 35 is an explanatory diagram showing an operation in which the CPU 56 updates the random R value or reads the random R value when the first random number update method is selected. As shown in FIG. 35, when the first random number update method is selected, the CPU 56 writes the count value update data “01h” to the count value update register 538, thereby storing the random number value storage circuit 531. The value of R (for example, “2”) is updated. Then, the CPU 56 receives a random R value from the random value storage circuit 531 in response to the fact that the game ball has won the variable winning ball device 15 and the condition (execution condition) for executing the variable symbol special display is established. (For example, “2”) is read.

  When the random R value stored in the random value storage circuit 531 is further updated, an interval equal to or longer than the period of the system clock signal output from the clock circuit 5001 has elapsed since the random R value was updated during the previous update. Sometimes, the count value update data “01h” must be written to the count value update register 538. This is because it is necessary to secure time for reading the updated random R value from the random value storage circuit 531.

  FIG. 36 is an explanatory diagram showing an operation in which the CPU 56 reads the value of the random R when the second random number update method is selected. As shown in FIG. 36, when the second random number update method is selected, the timer circuit 534 writes the random value fetch data “01h” into the random value fetch register 539, and the counter 521 outputs the result. The count value (for example, “2”) is taken into the random value storage circuit 531 and the random R value stored in the random value storage circuit 531 is updated. Then, the CPU 56 reads the updated random R value (for example, “2”) from the random value storage circuit 531.

  Specifically, when the second random number update method is selected, the counter 521 updates the count value C using the input of the random number generation clock signal SI1 as a trigger. Thereafter, when the first start port switch 13a or the second start port switch 14a is turned on, the latch signal SL (specifically, the latch signal SL1 from the first start port switch 13a or the second start port switch 14a) The latch signal SL2) is output to the random value storage circuit 531 (specifically, the first random value storage circuit 531a or the second random value storage circuit 531b). Then, the random value storage circuit 531 reads and stores the count value output from the counter 521 with the input of the latch signal SL as a trigger. Then, the CPU 56 reads the value of random R stored in the random value storage circuit 531. Specifically, based on the fact that the CPU 56 has output the output control signal SC to the random value storage circuit 531, the random R value can be read from the random value storage circuit 531, and the CPU 56 can read the random number circuit 5003. A random R value is read from the numerical value storage circuit 531. That is, the random value storage circuit 531 outputs a random R value in response to the output control signal SC from the CPU 56, and the CPU 56 reads the random R value output from the random value storage circuit 531. Even when an external random number circuit is used for the game control microcomputer 560, similarly, the random number storage circuit 531 of the external random number circuit is set to random R according to the output control signal SC from the CPU 56. The value of is output. Then, the CPU 56 reads the random R value output from the random number storage circuit 531 of the external random number circuit.

  The count value permutation change program 554 writes count value permutation change data “01h” to the count value permutation change register 536, and executes count value permutation change processing for changing the permutation of count values stored in the random value storage circuit 531. It is a program for. The CPU 56 functions as numerical data permutation changing means by executing processing according to the count value permutation changing program 554. The CPU 56 executes the count value permutation change program 554 and writes the count value permutation change data “01h” in the count value permutation change register 536, whereby the count value permutation change circuit 523 outputs and inputs to the random value storage circuit 531. The permutation of the count values to be changed.

  Next, the operation of the gaming machine will be described. FIG. 37 and FIG. 38 are flowcharts showing main processing executed by the game control microcomputer 560 on the main board 31. When power is supplied to the gaming machine and power supply is started, the input level of the reset terminal to which the reset signal is input becomes high level, and the gaming control microcomputer 560 (specifically, the CPU 56) After executing the security check process, which is a process for confirming whether the contents of the program are valid, the main process after step S1 is started. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, the interrupt mode is set to interrupt mode 2 (step S2), and a stack pointer designation address is set to the stack pointer (step S3). Then, after initialization of the built-in device (CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits)) is performed (step S4), the RAM 55 is accessible. (Step S5). In the interrupt mode 2, the address synthesized from the value (1 byte) of the specific register (I register) built in the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is This mode indicates an interrupt address.

  Next, the CPU 56 checks the state of the output signal of the clear switch (mounted on the power supply board 910) input via the input port (step S6). When the ON is detected in the confirmation, the CPU 56 executes normal initialization processing (steps S10 to S13).

  The CPU 56 may confirm the state of the output signal of the clear switch 921 in step S6, store the output state, and execute a delay process for delaying for a predetermined time (for example, 0.1 second). Then, after execution of the delay process, it is confirmed whether the ON state of the clear switch 921 has been detected based on the stored contents. The work area may be cleared. With such a configuration, when the power to the gaming machine is turned on, the initialization process executed on the production control microcomputer 100 side or the payout control microcomputer side mounted on the payout control board 37 is completed and the command can be received. After waiting for this, the initialization process on the game control microcomputer 560 side can be executed. Further, since the state of the clear switch 921 is first memorized and then the process proceeds to the initialization process after the delay process, the clear switch is set until the command control microcomputer 100 side or the payout control microcomputer side can receive commands. It is possible to save time and effort to keep pressing 921.

  If the clear switch is not on, check whether data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) was performed when power supply to the gaming machine was stopped (Step S7). When it is confirmed that such protection processing is not performed, the CPU 56 executes initialization processing. Whether there is backup data in the backup RAM area is confirmed, for example, by the state of the backup flag set in the backup RAM area in the power supply stop process.

  After confirming that the power supply stop process has been performed, the CPU 56 checks the data in the backup RAM area (step S8). In this embodiment, a parity check is performed as a data check. Therefore, in step S8, the calculated checksum is compared with the checksum calculated and stored by the same process in the power supply stop process. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, an initialization process that is executed when the power is turned on is not performed when the power supply is stopped.

  If the check result is normal, the CPU 56 recovers the game state restoration process (steps S41 to S43) for returning the internal state of the game control means and the control state of the electrical component control means such as the effect control means to the state when the power supply is stopped. Process). Specifically, the start address of the backup setting table stored in the ROM 54 is set as a pointer (step S41), and the contents of the backup setting table are sequentially set in the work area (area in the RAM 55) (step S42). ). The work area is backed up by a backup power source. In the backup setting table, initialization data for an area that may be initialized in the work area is set. As a result of the processing in steps S41 and S42, the saved contents of the work area that should not be initialized remain as they are. The part that should not be initialized is, for example, data indicating the gaming state before the power supply is stopped (special symbol process flag, probability variation flag, time reduction flag, etc.), and the area where the output state of the output port is saved (output port buffer) ), Data indicating the number of unpaid prize balls, and software random numbers such as determination random numbers (for example, the value of the jackpot determination calculation counter). However, the jackpot determination random number MR1 calculated in step S2015 of the start port switch passing process described later is initialized and cleared.

  Further, the CPU 56 transmits a power failure restoration designation command (power failure restoration 1 designation command) as an initialization command at the time of power supply restoration to the effect control board 80 (step S43). Then, the process proceeds to step S14.

  In this embodiment, it is confirmed whether the data in the backup RAM area is stored using both the backup flag and the check data. However, only one of them may be used. That is, either the backup flag or the check data may be used as an opportunity for executing the game state restoration process.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S10). In the initialization process of step S10, the CPU 56 sets the start address (address 7F00h, see FIG. 30) of the area other than the software random number counter storage area in the work area (work area) of the RAM 55 area as a pointer. Then, clear data (for example, “0”) is sequentially set in the work area in the RAM 55. By performing such processing, processing for clearing only the data stored in the area from address 7F00h to address 7FFFh (the work area other than the software random number counter storage area) is performed, and addresses 7E00h to 7EFFh are performed. The data stored in the address area (software random number counter storage area) is processed so as not to be cleared. Also, the initial address of the initialization setting table stored in the ROM 54 is set as a pointer (step S11), and the contents of the initialization setting table are sequentially set in the work area in the RAM 55 (step S12).

  By the processing in steps S11 and S12, an initial value is set to a flag for selectively performing processing according to the control state, such as a special symbol process flag.

  Further, the CPU 56 initializes a sub board (a board on which a microcomputer other than the main board 31 is mounted) (a command indicating that the game control microcomputer 560 has executed an initialization process). Is also transmitted to the effect control board 80 (step S13). For example, when the effect control microcomputer 100 mounted on the effect control board 80 receives the initialization designation command, the effect display device 9 displays a screen for notifying that the control of the gaming machine has been initialized. Display, that is, initialization notification. In the initialization process, the CPU 56 also transmits a customer waiting demonstration designation (demonstration) command.

  Next, the CPU 56 checks whether or not the game start switch 90 is on (step S44). If it is in the off state (N in step S44), the CPU 56 again determines whether or not the game start switch 90 is in the on state after a delay time of a predetermined time (for example, 0.1 second) (step S45). Confirm (step S46). If it is in the on state (Y in step S46), the process returns to step S44, and the processes in steps S44 to S46 are repeated.

  As described above, by executing the processing of steps S44 to S46, the game start switch 90 is temporarily turned off for a predetermined time (for example, 0.1 seconds) or more after executing the initialization processing of steps S10 to S13. After confirming that it is in the state, the process proceeds to the next step S47 and subsequent steps.

  In step S45, a process of adding or subtracting the value of a predetermined counter is performed. In step S46, the counter value becomes a predetermined value (for example, 0 is added in order from 0 to reach 50). Or on the condition that the value is subtracted from 50 in order and becomes 0), the process may proceed to step S47 and subsequent steps. In this case, if the on state of the game start switch 90 is detected before the counter value reaches the predetermined value, the predetermined counter value is 0 (when added) or 50 (when subtracted). Returning to step S44, the process may be executed again from step S44.

  If the game start switch 90 is off in step S46 (N in step S46), the CPU 56 thereafter detects the on state of the game start switch 90 (Y in step S47), for a predetermined time (for example, 0.1). Seconds) (step S48), it is checked again whether or not the game start switch 90 is on (step S49). If it is an off state (N of step S49), it will return to step S47 and will repeat the process of steps S47-S49. If the game start switch 90 is on (Y in step S49), the process proceeds to the next step S14.

  As described above, the processing after step S14 is performed on condition that the game start switch 90 is turned on after executing the initialization processing of steps S10 to S13 by executing the processing of steps S47 to S49. Migrate to Specifically, on condition that the game start switch 90 is turned on, the random number circuit 5003 is activated in the random number circuit setting process in step S14 described later, and the update of the hardware random number is started. In addition, a determination random number update process in step S24 of a timer interrupt process which will be described later is started, and the update of the software random number is started.

  In this embodiment, only when the initialization process of steps S10 to S13 is executed, the case where the process is shifted to the process after step S14 on condition that the game start switch 90 is turned on is shown. The same process may be executed when the game state restoration process of steps S41 to S43 is executed. That is, when the game control microcomputer 560 executes the game state restoration process of steps S41 to S43, the game control microcomputer 560 proceeds to step S44 and executes the same process as steps S44 to S49, and the game start switch 90 is turned on. It is also possible to shift to the processing after step S14 on the condition that

  Further, in this embodiment, as will be described later, for jackpot determination using two random numbers, that is, a random number 2-1 (random number for jackpot determination calculation) which is a software random number and a hardware random number read from the random number circuit 5003. Although it is configured to calculate a random number (random MR1) (see step S2015 of the start port switch passing process), in such a configuration, software including random 2-1 (random number for jackpot determination calculation) At least one of the update of the random number and the update of the hardware random number by the random number circuit 5003 (or a random number circuit external to the game control microcomputer 560) is started after the game start switch 90 is turned on. It may be. For example, when an external random number circuit is used, when the power to the gaming machine is turned on, the random number circuit is started as it is regardless of the control by the gaming microcomputer 560. The processing may not be executed, and only the update of the software random number may be started after the game start switch 90 is turned on. Even in such a configuration, since at least the software random number is not operated unless the game start switch 90 is operated, the update of the counter value for generating the jackpot determination random number (MR1) is started. The timing can be varied, and the timing for determining to shift to the big hit gaming state can be made difficult to predict.

  In step S48, a process of adding or subtracting the value of a predetermined counter is performed, and the process proceeds to step S14 and subsequent steps on condition that the value of the counter becomes a predetermined value in step S49. Good.

  Next, the CPU 56 executes random number circuit setting processing for initial setting of the random number circuit 5003 (step S14). For example, the CPU 56 performs setting according to the random number circuit setting program to cause the random number circuit 5003 to update the value of the random R. In the random number circuit setting process in step S14, a process for writing random number circuit activation data to the random number circuit activation register 541 is executed (see step S1507), and a process for starting the random number circuit 5003 is executed.

  Even if the game control microcomputer 560 does not include the random number circuit 5003 and an external random number circuit is used for the game control microcomputer 560, the CPU 56 follows the same process as in step S14. Settings are made to update the value of random R in an external random number circuit. When an external random number circuit is used, the random number R may be set to start updating the random R even before the game start switch 90 is turned on.

  Then, the CPU 56 sets a CTC register built in the game control microcomputer 560 so that a timer interrupt is periodically taken every predetermined time (for example, 2 ms) (step S15). That is, a value corresponding to, for example, 2 ms is set in a predetermined register (time constant register) as an initial value. In this embodiment, it is assumed that a timer interrupt is periodically taken every 2 ms.

  Next, the CPU 56 repeatedly executes the display random number update process (step S17) and the initial value random number update process (step S18) in the main process. When the display random number update process and the initial value random number update process are executed, the interrupt disabled state is set (step S16). Set (step S19). In this embodiment, the display random number is a random number for determining a variation pattern or the like, and the display random number update process is a process for updating the count value of the counter for generating the display random number. . The initial value random number update process is a process for updating the count value of the counter for generating the initial value random number. In this embodiment, the initial value random number is an initial value of a count value of a counter (ordinary symbol determination random number generation counter) for generating a random number for determining whether or not to hit a normal symbol. This is a random number for determining an initial value of a count value of a counter (a jackpot determination calculation counter) for generating a jackpot determination calculation random number (random 2-1), which will be described later. A game control process for controlling the progress of the game, which will be described later (the game control microcomputer 560 controls game devices such as an effect display device, a variable winning ball device, a ball payout device, etc. provided in the game machine itself. In a process for transmitting a command signal to cause another microcomputer to control, or a game device control process), the count value of the random number generation counter for jackpot determination or the like is one round (minimum value that can be taken by random numbers) When the value is incremented by the number of values between the value and the maximum value), an initial value is set in the counter.

  FIG. 39 is an explanatory diagram showing an example of the contents of the effect control command transmitted by the game control microcomputer 560. In the example shown in FIG. 39, the command 80XX (H) is an effect control command (variation pattern command) for designating a variation pattern of the effect symbol that is variably displayed on the effect display device 9 in response to the variable display of the special symbol. (Corresponding to the variation pattern XX, respectively). That is, when a unique number is assigned to each variation pattern that can be used, there is a variation pattern command corresponding to each variation pattern specified by the number. “(H)” indicates a hexadecimal number. The effect control command for designating the variation pattern is also a command for designating the start of variation. Therefore, upon receiving the command 80XX (H), the effect control microcomputer 100 controls the first decorative symbol display 9a or the second decorative symbol display 9b so as to start the decorative symbol variable display, and the effect display device. In step 9, control is performed so as to start variable display of effect symbols.

  The commands 8C01 (H) to 8C04 (H) are effect control commands indicating whether or not to make a big hit and the type of the big hit game. The effect control microcomputer 100 determines the display results of the decorative symbols and the effect symbols in response to the reception of the commands 8C01 (H) to 8C04 (H). It is called a command.

  Command 8D01 (H) is an effect control command (first symbol variation designation command) indicating that variable display (variation) of the first special symbol is started. Command 8D02 (H) is an effect control command (second symbol variation designation command) indicating that variable display (variation) of the second special symbol is started. The first symbol variation designation command and the second symbol variation designation command may be collectively referred to as a special symbol specifying command (or symbol variation designation command). Note that information indicating whether to start variable display of the first special symbol or variable display of the second special symbol may be included in the variation pattern command.

  Command 8F00 (H) is an effect control command (symbol confirmation designation command) indicating that the variable display (fluctuation) of effect symbols (and decoration symbols) is terminated and the display result (stop symbol) is derived and displayed. When receiving the symbol confirmation designation command, the effect control microcomputer 100 ends the variable display (fluctuation) of the effect symbol and the decorative symbol and derives and displays the display result.

  Command 9000 (H) is an effect control command (initialization designation command: power-on designation command) transmitted when power supply to the gaming machine is started. Command 9200 (H) is an effect control command (power failure recovery designation command) transmitted when power supply to the gaming machine is resumed. When the power supply to the gaming machine is started, the gaming control microcomputer 560 transmits a power failure recovery designation command if data is stored in the backup RAM, and if not, initialization designation is performed. Send a command.

  Command 9F00 (H) is an effect control command (customer waiting demonstration designation command) for designating a customer waiting demonstration.

  The commands A001 to A003 (H) are effect control commands for displaying the fanfare screen, that is, designating the start of the big hit game (big hit start designation command: fanfare designation command). The jackpot start designation command includes a jackpot start 1 designation command, a jackpot start designation 2 designation command, and a sudden start designation command corresponding to the type of jackpot. The command A1XX (H) is an effect control command (special command during opening of a big winning opening) indicating a display during the opening of the big winning opening for the number of times (round) indicated by XX. A2XX (H) is an effect control command (designation command after opening the big winning opening) indicating the closing of the big winning opening for the number of times (round) indicated by XX.

  Command A301 (H) displays a jackpot end screen, that is, specifies the end of the jackpot game, and also specifies an effect control command (special jackpot end 1 designation command: ending) that specifies that the game is a non-probable big hit (usually a big hit) 1 designation command). Command A302 (H) is an effect control command for displaying the jackpot end screen, that is, the end of the jackpot game and specifying that it is a probable big hit (big hit end 2 designation command: ending 2 designation command). is there. Command A303 (H) is an effect control command (surprise end specification command: ending 3 specification command) that specifies the end of a game of sudden probability change.

  The command C000 (H) is an effect control command (first start winning designation command) that designates that the first start winning has been won. The command C100 (H) is an effect control command (second start winning designation command) for designating that the second starting win has been won. The first start prize designation command and the second start prize designation command may be collectively referred to as a start prize designation command.

  The command C2XX (H) is an effect control command (total pending storage number designation command) for designating a total number (total pending storage number) that is the sum of the first reserved memory number and the second reserved memory number. “XX” in the command C2XX (H) indicates the total pending storage number. The command C300 (H) is an effect control command (total pending storage count subtraction designation command) that designates that the total pending storage count is decremented by one. In this embodiment, the game control microcomputer 560 transmits a total pending memory count subtraction designation command when subtracting the total pending memory count, but does not use the total pending memory count subtraction designation command, and does not use the total pending memory count subtraction designation command. When the stored number is subtracted, the combined pending storage number after the subtraction may be designated by a combined pending storage number designation command.

  Command E000 (H) is an effect control command (random number abnormality designation command) for designating occurrence of abnormality in random number circuit 5003. In this embodiment, as will be described later, the game control microcomputer 560 detects the occurrence of an abnormality in the random number circuit 5003 in the random number circuit setting process (see step S14) and the start port switch passing process (see step S332). Based on that, a random number abnormality designation command is transmitted to the production control microcomputer 100. Then, the production control microcomputer 100 notifies the random number circuit 5003 that an abnormality has occurred based on the reception of the random number abnormality designation command. Note that the game control microcomputer 560 detects the occurrence of an abnormality in the random number circuit 5003 in the random number circuit setting process (see step S14) and detects the occurrence of an abnormality in the random number circuit 5003 in the start port switch passing process (see step S332). Separate random number abnormality designation commands may be transmitted depending on the detected case.

  The effect control microcomputer 100 (specifically, the effect control CPU 101) mounted on the effect control board 80 receives the above-described effect control command from the game control microcomputer 560 mounted on the main board 31. Then, the display state of the image display device 9 is changed according to the contents shown in FIG. 39, the display state of the lamp is changed, or the sound number data is output to the audio output board 70.

  For example, the game control microcomputer 560 designates the variation pattern of the effect symbol whenever there is a start prize and variable display of the special symbol is started on the first special symbol display 8a or the second special symbol display 8b. The variation pattern command and the display result specifying command are transmitted to the production control microcomputer 100.

  In this embodiment, the effect control command has a 2-byte structure, the first byte represents MODE (command classification), and the second byte represents EXT (command type). The first bit (bit 7) of the MODE data is always set to “1”, and the first bit (bit 7) of the EXT data is always set to “0”. Note that such a command form is an example, and other command forms may be used. For example, a control command composed of 1 byte or 3 bytes or more may be used.

  In addition, as the transmission method of the effect control command, the effect control command data is output from the main board 31 to the effect control board 80 via the relay board 77 by the eight parallel signal lines of the effect control signals CD0 to CD7, In addition to the effect control command data, a method of outputting a pulse-shaped (rectangular wave-shaped) capture signal (effect control INT signal) for instructing capture of the effect control command data is used. The 8-bit effect control command data of the effect control command is output in synchronization with the effect control INT signal. The effect control microcomputer 100 mounted on the effect control board 80 detects that the effect control INT signal has risen, and starts a 1-byte data capturing process through an interrupt process.

  In the example shown in FIG. 39, the variable pattern command and the display result specifying command are displayed as a decorative symbol variable display (variation) corresponding to the variation of the first special symbol on the first special symbol indicator 8a and the second special symbol indicator. The image display device 9 that can be used in common with the variable display (variation) of the decorative symbol corresponding to the variation of the second special symbol in 8b, and that produces effects in accordance with the variable display of the first special symbol and the second special symbol. When controlling the effect parts, it is possible to prevent an increase in the types of commands transmitted from the game control microcomputer 560 to the effect control microcomputer 100.

  Note that the command 8D01 (H) (first symbol variation designation command) and the command 8D02 (H) (second symbol variation designation command) are executed by the effect control microcomputer 100 by the first special symbol display 8a. Whether the first design symbol display unit 9a that performs variable display of the first design as a design for decoration (production) during the variable display time of the design changes the design of the design, by the second special design display 8b. It is used to determine whether or not the decorative symbol is changed in the second decorative symbol display unit 9b that performs variable display of the second decorative symbol during the variable display time of the second special symbol.

  Next, the random number circuit setting process (step S14) in the main process will be described. FIG. 40 is a flowchart showing random number circuit setting processing. Even if the game control microcomputer 560 does not include the random number circuit 5003 and an external random number circuit is used for the game control microcomputer 560, the CPU 56 follows the same processing as in FIG. Settings are made to update the value of random R in an external random number circuit. When an external random number circuit is used, the random number R shown in FIG. 40 may be set to start updating the random R even before the game start switch 90 is turned on.

  In the random number circuit setting process, the CPU 56 first executes processing according to the random number maximum value setting module 551a included in the random number circuit setting program 551, and sets random number maximum value setting data for designating a random number maximum value preset by the user. Write to the random number maximum value setting register 535 (step S1500). By doing so, the random number maximum value of random R preset by the user is set in the random number circuit 5003. In this embodiment, “65535” is set as the maximum random number.

  Further, the CPU 56 checks whether or not the random number maximum value set in the random number maximum value setting register 535 in step S1500 is not less than a predetermined lower limit value. The random number maximum value resetting process for resetting the random number maximum value set in 535 is executed (step S1501).

  Further, the CPU 56 executes processing in accordance with the initial value changing module 551e included in the random number circuit setting program 551, and executes initial value changing processing for changing the initial value of the count value updated by the counter 521 of the random number circuit 5003 (step). S1502).

  Further, the CPU 56 executes processing according to the random number update method selection module 551b included in the random number circuit setting program 551, and writes the random number update method selection data to the random number update method selection register 540 (step S1503). By doing so, the random number update method of the random number circuit 5003 is set. In this embodiment, the CPU 56 writes the random number update method selection data “10h” in the random number update method selection register 540. That is, in this embodiment, the second random number update method is set as the random number update method of the random number circuit 5003.

  Further, the CPU 56 executes processing according to the cycle setting module 551c included in the random number circuit setting program 551, and sets the cycle setting data (the reference clock signal by how many minutes) that specifies the cycle of the random number generation clock signal SI1 preset by the user. Data for setting whether or not to circulate) is written in the period setting register 537 (step S1504). By doing so, the cycle of the random number generating clock signal SI1 preset by the user is set in the random number circuit 5003.

  Further, the CPU 56 sets whether or not to update the initial value input to the counter 521 when the count value is updated to a predetermined final value by the counter 521 of the random number circuit 5003 (step S1505). For example, the game control microcomputer 560 sets in advance a setting value indicating whether or not to update the initial value input to the counter 521 when the count value is updated to a predetermined final value by the counter 521. And stored in a predetermined area of the ROM 54. Whether or not the CPU 56 updates the initial value input to the counter 521 when the counter 521 updates the count value to a predetermined final value in accordance with a predetermined set value stored in a predetermined storage area of the ROM 54. Set In this embodiment, when determining that the initial value input to the counter 521 is updated in step S1505, the CPU 56 updates the count value up to a predetermined final value (when a notification signal is input from the counter 521). An initial value update flag indicating that the initial value is updated is set. In this embodiment, a case will be described in which the initial value update flag is set according to a predetermined set value in step S1505. Then, the CPU 56 updates the initial value of the count value output from the counter 521 based on the initial value update flag being set in the random number circuit initial value update process described later.

  Instead of changing the initial value of the count value by the CPU 56, the random value circuit 5003 may change the initial value of the count value to a predetermined value based on the update of the count value to the final value. For example, the random number circuit 5003 includes an initial value update data register that stores initial value update data indicating that the initial value is updated, and an initial value change circuit that changes the initial value. Value update data is set in the initial value update data register. In this case, when the counter 521 updates the count value to the final value, it outputs a notification signal to the initial value change circuit. Then, the initial value change circuit checks whether or not initial value update data is set in the initial value update data register. Then, when the initial value change circuit confirms that the initial value update data is set, the initial value change circuit changes the initial value of the count value to a predetermined value. Note that the initial value changing circuit may change the initial value of the count value whose permutation has been changed in the count value permutation changing process described later.

  Further, the CPU 56 sets whether or not to change the permutation of the count values updated by the counter 521 when the count values are updated to a predetermined final value by the counter 521 of the random number circuit 5003 (step S1506). For example, the game control microcomputer 560 sets in advance a set value indicating whether or not to change the permutation of the count values output by the counter 521 when the counter 521 updates the count value to a predetermined final value. Is stored in a predetermined area of the ROM 54. Then, the CPU 56 changes the permutation of count values output by the counter 521 when the count value is updated by the counter 521 to a predetermined final value according to a predetermined set value stored in a predetermined storage area of the ROM 54. Set whether or not. In this embodiment, if the CPU 56 determines in step S1506 that the permutation of the count values output from the counter 521 is to be changed, the CPU 56 changes the permutation of the count values when the count values are updated to a predetermined final value. The indicated count value permutation change flag is set. In this embodiment, a case where the count value permutation change flag is set in step S1506 according to a predetermined set value will be described. Then, the CPU 56 changes the permutation of the count values output by the counter 521 based on the fact that the count value permutation change flag is set in the count value permutation changing process described later.

  Instead of changing the permutation of the count values under the control of the CPU 56, the permutation of the count values may be changed on the random number circuit 5003 side based on the update of the count values up to the final value. For example, the random number circuit 5003 includes a permutation change data register that stores permutation change data indicating that the permutation of count values is to be changed. In step S1506, the CPU 56 sets the permutation change data in the permutation change data register. In this case, when the counter 521 updates the count value to the final value, the notification signal is output to the count value permutation change circuit 523, and the count value permutation change circuit 523 that has received the notification signal receives the permutation change data in the permutation change data register. Check whether it is set. When the count value permutation changing circuit 523 confirms that the permutation change data is set, it changes the permutation of the count values.

  The CPU 56 executes processing in accordance with the random number circuit activation module 551d included in the random number circuit setting program 551, and writes the random number circuit activation data “80h” in the random number circuit activation register 541 (step S1507). By doing so, the CPU 56 activates the random number circuit 5003. In this embodiment, on the condition that the on state of the game start switch 90 is detected (see steps S47 to S49), the random number circuit setting process is executed, and the random number circuit 5003 is activated in step S1507, and the hardware The update of the wear random number is started.

  Next, the CPU 56 outputs a latch signal SL0 (a latch signal output from the CPU 56 to the random value storage circuit (latch circuit) 531) to the random number storage circuits 531a and 531b of the random number circuit 5003 (step S1508). Next, after a delay time of a predetermined time (for example, 0.1 seconds) (step S1509), the output control signal SC is output to the random value storage circuits 531a and 531b of the random number circuit 5003 (step S1510). Next, the CPU 56 reads the random R value stored as the random number value from each of the random value storage circuits 531a and 531b, and checks whether or not each bit value of the read random value has changed from 0 to 1 ( Step S1511). In this case, for example, a flag corresponding to each bit value of a 16-bit random value is prepared in advance, and the flag value corresponding to the bit in which the change in value is detected is changed from 0 to 1. When all the bit values of the random number values read from the random value storage circuits 531a and 531b change (Y in step S1512), for example, all the flag values corresponding to the respective bit values of the 16-bit random value are changed from 0. If it is changed to 1, the random number circuit setting process is terminated.

  Even if the game control microcomputer 560 does not have the built-in random number circuit 5003 and an external random number circuit is used for the game control microcomputer 560, the CPU 56 follows the same processing as in step S1508. The latch signal SL0 is output to the random number storage circuit of the external random number circuit, and after a predetermined time delay (see step S1509), the output control signal SC is output to the random number storage circuit of the external random number circuit (step S1509). (See S1510). Then, the CPU 56 reads the random R value stored as the random number value from the random number value storage circuit of the external random number circuit, and checks whether each bit value of the read random number value has changed from 0 to 1 (See step S1511).

  If there is a bit value that has not yet changed among the bit values of the random number value read from each of the random number value storage circuits 531a and 531b (N in step S1512), the CPU 56 determines that the random number circuit 5003 has failed. The value of the random number abnormality determination counter for use in the determination is incremented by 1 (step S1513). Then, it is confirmed whether or not the value of the random number abnormality determination counter after the addition is equal to or greater than a predetermined value (for example, 65535) (step S1514). If the value of the random number abnormality determination counter is not equal to or greater than the predetermined value, the processes after step S1508 are repeatedly executed. If the value of the random number abnormality determination counter is equal to or greater than the predetermined value, the CPU 56 performs control to transmit a random number abnormality designation command to the effect control microcomputer 100 (step S1515). Instead of transmitting the random number abnormality designation command, the CPU 56 may repeatedly execute the processing of steps S1508 to S1512 until all the bit values of the random number value are changed, thereby executing the loop processing.

  Even if the game control microcomputer 560 does not include the random number circuit 5003 and an external random number circuit is used for the game control microcomputer 560, the CPU 56 performs the same processing as in steps S1508 to S1515. To determine whether or not an abnormality has occurred in the external random number circuit. If it is determined that an abnormality has occurred in the external random number circuit, a random number abnormality designation command may be transmitted by executing the same process as in step S1515.

  Next, the random number maximum value resetting process (step S1501) in the random number circuit setting process will be described. FIG. 41 is a flowchart showing the random number maximum value resetting process. In the random number maximum value resetting process, the CPU 56 reads the random number maximum value set in the random number maximum value setting register 535 (step S1531).

  The CPU 56 determines whether or not the read random number maximum value is equal to or less than a predetermined lower limit value (step S1532). In this embodiment, the random number maximum value that can be set in the random number circuit 5003 is from “512” to “65535”, and the CPU 56 determines that the random number maximum value read from the random number maximum value setting register 535 of the random number circuit 5003 is the lower limit. It is determined whether or not the value is “512” or less.

  When the read random number maximum value is less than or equal to the lower limit value, the CPU 56 resets the random number maximum value set in the random number maximum value setting register 535 to a predetermined value (step S1533). In this case, when determining that the random number maximum value read from the random number maximum value setting register 535 of the random number circuit 5003 is equal to or lower than the lower limit value “512”, the CPU 56 sets the random number maximum value set in the random number maximum value setting register 535 to a predetermined value. Reset the value to “65535”.

  As described above, when the random number maximum value set in the random number maximum value setting register 535 is equal to or smaller than the predetermined lower limit value, the random number maximum value is reset to a predetermined value. Therefore, it is possible to prevent an excessively small value from being set as the maximum value of the random number due to a malfunction of the game control microcomputer 560 or an action such as generating a capture signal using a radio signal for the game machine. be able to. Therefore, it is possible to prevent a situation in which a random number having an excessively small value range from the minimum value to the maximum value is generated.

  In this embodiment, after setting the random number maximum value in the random number maximum value setting register 535 in step S1500, the random number maximum value set in the random number maximum value reset processing in step S1501 is equal to or less than a predetermined lower limit value. However, before setting the random number maximum value in the random number maximum value setting register 535, it may be determined whether it is equal to or less than a predetermined lower limit value. In this case, for example, when executing the process of step S1500, the CPU 56 determines whether or not the value indicated by the random number maximum value setting data preset by the user is equal to or less than a predetermined lower limit value. When the value indicated in the random number maximum value setting data is larger than the predetermined lower limit value, the CPU 56 writes the value indicated in the random number maximum value setting data in the random number maximum value setting register 535 as it is. When the value indicated in the random number maximum value setting data is equal to or smaller than the predetermined lower limit value, the CPU 56 sets a predetermined value (for example, “65535”) instead of the value indicated in the random number maximum value setting data. Write to register 535.

  Next, the initial value changing process (step S1502) in the random number circuit setting process will be described. FIG. 42 is a flowchart showing the initial value changing process. In the initial value changing process, the CPU 56 first reads the initial value changing method setting data stored in the area 1F97h in the user program execution data area, and specifies the initial value changing method selected by the user. In this case, the CPU 56 determines whether or not the value of the read initial value change method setting data is “01h” (step S1541), thereby specifying the initial value change method selected by the user.

  When the value of the initial value change method setting data is “01h”, the CPU 56 sets the initial value input to the counter 521 of the random number circuit 5003 to a value set based on the ID number unique to the game control microcomputer 560. Change (step S1542). For example, the game control microcomputer 560 associates, in a predetermined storage area of the ROM 54, the ID number of the game control microcomputer 560 with a calculated value obtained by performing a predetermined calculation based on the ID number. I remember it. In step S1542, the CPU 56 changes the initial value of the count value to the calculated value based on the ID number stored in advance. Further, for example, in step S1542, the CPU 56 calculates the ID number of the game control microcomputer 560 and a predetermined value (for example, the ID number (for example, “100”) to a predetermined value (for example, “100”). The initial value of the count value is set to the calculated value (for example, “200”). When the initial value input to the counter 521 is changed, the CPU 56 sets an initial value change flag indicating that the initial value of the count value has been changed (step S1543).

  When the CPU 56 changes the initial value input to the counter 521 in step S1542, the CPU 56 checks the value of the random number maximum value setting register 535 of the comparator 522 of the random number circuit 5003, and the value set based on the ID number is determined. It is determined whether or not it is greater than the maximum random number. If it is determined that the value set based on the ID number is equal to or greater than the maximum random number, the CPU 56 does not change the initial value input to the counter 521 (for example, resets the initial value to “0”). By doing so, it is possible to prevent a situation where the initial value of the count value is set to a value equal to or greater than the maximum random number.

  If the value of the initial value change method setting data is not “01h” in step S1541 (that is, the value of the initial value change method setting data stored in the area 1F97h of the user program execution data area is “00h”). In the case), the CPU 56 does not change the initial value of the count value, ends the initial value changing process as it is, and proceeds to step S1503.

  When the timer interrupt occurs, the CPU 56 executes the timer interrupt process in steps S20 to S36 shown in FIG. In the timer interrupt process, first, a power-off detection process for detecting whether or not a power-off signal is output (whether or not an on-state is turned on) is executed (step S20). The power-off signal is output, for example, when the power monitoring circuit 920 mounted on the power board detects a decrease in the voltage of the power supplied to the gaming machine. In the power-off detection process, when detecting that the power-off signal has been output, the CPU 56 executes a power supply stop process for saving necessary data in the backup RAM area. Next, detection signals from the gate switch 32a, the first start port switch 13a, the second start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, 39a are input via the input driver circuit 58, These state determinations are performed (switch processing: step S21).

  Next, the CPU 56 checks whether or not the initial value is updated when the count value is updated to a predetermined final value in the random number circuit setting process (see step S1505), and the counter of the random number circuit 5003 is checked. Processing for updating the initial value input to 521 is performed (random circuit initial value updating processing: step S22).

  Next, the CPU 56 has a first special symbol display 8a, a second special symbol display 8b, a normal symbol display 10, a first special symbol hold storage display 18a, a second special symbol hold storage display 18b, a normal symbol. A display control process for controlling the display of the on-hold storage display 41 is executed (step S23). About the 1st special symbol display 8a, the 2nd special symbol display 8b, and the normal symbol display 10, a drive signal is output with respect to each display according to the content of the output buffer set by step S34, S35. Execute control.

  Also, a process of updating the count value of each counter for generating each determination random number such as a random number for determining a normal hit symbol used for game control (for example, updating the count value of a later-described jackpot determination calculation counter) Process) (random number update process for determination: step S24). The CPU 56 further performs a process of updating the count value of the counter for generating the initial value random number and the display random number (initial value random number update process, display random number update process: steps S25 and S26). In this embodiment, on the condition that the on state of the game start switch 90 is detected (see steps S47 to S49), a timer interrupt is set (see step S15), and the timer interrupt process is determined. The random number update process (see step S24) is executed, and the update of the software random number is started.

  When the random number circuit initial value update process and the display random number update process are performed, the CPU 56 performs a count value permutation change process in which the count value permutation change circuit 523 changes the permutation of the count values output from the counter 521 of the random number circuit 5003 ( Step S27). In this embodiment, whether or not to execute the count value permutation change process is determined depending on whether or not the count value permutation change flag is set in step S1506 of the random number circuit setting process. Then, the CPU 56 executes the count value permutation change process based on the fact that the count value permutation change flag is set.

  Further, the CPU 56 performs special symbol process processing (step S28). In the special symbol process, corresponding processing is executed according to a special symbol process flag for controlling the first special symbol indicator 8a, the second special symbol indicator 8b, and the special winning award in a predetermined order. The CPU 56 updates the value of the special symbol process flag according to the gaming state.

  Next, normal symbol process processing is performed (step S29). In the normal symbol process, the CPU 56 executes a corresponding process according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The CPU 56 updates the value of the normal symbol process flag according to the gaming state.

  Further, the CPU 56 performs a process of sending an effect control command to the effect control microcomputer 100 (effect control command control process: step S30).

  Further, the CPU 56 performs information output processing for outputting data such as jackpot information, start information, probability variation information supplied to the hall management computer, for example (step S31).

  Further, the CPU 56 performs prize ball processing for setting the number of prize balls based on detection signals from the first start port switch 13a, the second start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, 39a. Execute (Step S32). Specifically, the payout control is performed in accordance with winning detection based on any one of the first starting port switch 13a, the second starting port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, 39a being turned on. A payout control command (award ball number signal) indicating the number of winning balls is output to a payout control microcomputer mounted on the substrate 37. The payout control microcomputer drives the ball payout device 97 in accordance with a payout control command indicating the number of winning balls.

  In this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided. However, the CPU 56 relates to on / off of the solenoid in the RAM area corresponding to the output state of the output port. The contents are output to the output port (step S33: output process).

  Further, the CPU 56 performs special symbol display control processing for setting special symbol display control data for effect display of the special symbol in the output buffer for setting the special symbol display control data according to the value of the special symbol process flag ( Step S34). For example, if the variation speed is 1 frame / 0.2 seconds until the end flag is set when the start flag set in the special symbol process is set, the CPU 56, for example, every 0.2 seconds passes. Then, the value of the display control data set in the output buffer is incremented by one. Further, the CPU 56 outputs a drive signal in step S22 in accordance with the display control data set in the output buffer, whereby the first special symbol display unit 8a and the second special symbol display unit 8b Variable display of the second special symbol is executed.

  Note that, in step S34, the special symbol process flag value does not start the variation of the special symbol based on the start flag being set, but the value of the special symbol variation process after the variation pattern is determined (specifically, 3) (or a value indicating the display result specifying command transmission process (specifically, 2)), the change of the special symbol may be started. Then, based on the fact that the value of the special symbol process flag has become a value indicating the special symbol stop process (specifically, 4), the variation of the special symbol may be stopped. By doing so, the start flag and the end flag can be eliminated, and the required capacity of the RAM 55 can be reduced.

  Further, the CPU 56 performs a normal symbol display control process for setting normal symbol display control data for effect display of the normal symbol in an output buffer for setting the normal symbol display control data according to the value of the normal symbol process flag ( Step S35). For example, when the start flag related to the variation of the normal symbol is set, the CPU 56 switches the display state (“◯” and “×”) for the variation rate of the normal symbol every 0.2 seconds until the end flag is set. With such a speed, the value of the display control data set in the output buffer (for example, 1 indicating “◯” and 0 indicating “x”) is switched every 0.2 seconds. Further, the CPU 56 outputs a normal signal on the normal symbol display 10 by outputting a drive signal in step S22 according to the display control data set in the output buffer.

  In step S35, instead of starting the change of the normal symbol based on the start flag being set, the value of the normal symbol process flag becomes a value indicating the normal symbol changing process. Ordinary symbol variation may be started. Then, based on the fact that the value of the normal symbol process flag becomes a value indicating the normal symbol stop process, the variation of the normal symbol may be stopped. By doing so, the start flag and the end flag can be eliminated, and the required capacity of the RAM 55 can be reduced.

  Thereafter, the interrupt permission state is set (step S36), and the process ends.

  The game control microcomputer 560 does not execute the random number circuit initial value update process in step S22 or the count value permutation change process in step S27 in the timer interrupt process, and also performs the random number circuit setting process (step in the main process). The processing for setting the maximum random number in steps S1500 and S1501 in step S14) may not be executed. That is. With regard to hardware random numbers, the initial value of the random number circuit, the permutation, and the maximum random number value may not be changed, and the hardware random number may be continuously updated in the range of 0 to 65535.

  Next, the random number circuit initial value update process (step S22) in the timer interrupt process will be described. FIG. 44 is a flowchart showing random number circuit initial value update processing. In the random number circuit initial value update process, the CPU 56 checks the state of the notification signal indicating that the count value C output from the counter 521 of the random number circuit 5003 has been updated to the final value (step S220). When it is detected that the notification signal is in the on state, the CPU 56 checks whether or not the initial value update flag is set (step S221). That is, in the random number circuit setting process, the CPU 56 checks whether or not the setting for updating the initial value is made when the count value is updated to a predetermined final value (see step S1505).

  When the initial value update flag is set, the CPU 56 determines to update the initial value input to the counter 521 when the counter 521 of the random number circuit 5003 updates the count value to a predetermined final value. When the initial value update flag is set, the CPU 56 checks whether or not the initial value change flag is set (step S222). That is, the CPU 56 determines whether or not the initial value of the count value is currently changed (that is, whether or not it is changed to a value based on the ID number of the game control microcomputer 560).

  When the initial value change flag is set (that is, when the initial value is currently changed based on the ID number of the game control microcomputer 560), the CPU 56 uses the initial value input to the counter 521 as the game control. The value based on the ID number of the microcomputer 560 is returned to the original value (for example, “1”) (step S223). Then, the CPU 56 resets the initial value change flag (step S224) and ends the initial value update process.

  If the initial value change flag is not set (that is, the initial value is not currently changed), the CPU 56 changes the initial value input to the counter 521 to a value based on the ID number of the game control microcomputer 560. (Step S225). In this case, for example, if the ID number of the game control microcomputer 560 is “100”, the initial value input to the counter 521 is calculated by adding a predetermined value “100” to the ID number “100”. Change to the value “200”. Further, for example, the initial value input to the counter 521 is changed to the calculated value “50” obtained by subtracting the predetermined value “50” from the ID number “100”. Then, the CPU 56 sets an initial value change flag (step S226) and ends the initial value update process.

  When updating the initial value input to the counter 521 in step S225, the CPU 56 checks the value of the random number maximum value setting register 535 of the comparator 522 of the random number circuit 5003, and the value set based on the ID number is determined. It is determined whether or not it is greater than the maximum random number. If the CPU 56 determines that the value set based on the ID number is equal to or greater than the maximum random number, the CPU 56 does not update the initial value input to the counter 521 with a predetermined value (for example, updates with the predetermined value “0”). do not do). By doing so, it is possible to prevent a situation where the initial value of the count value is set to a value equal to or greater than the maximum random number.

  If it is determined in step S220 that the notification signal is in the OFF state, or if it is determined in step S221 that the initial value update flag is not set, the CPU 56 does not update the initial value input to the counter 521. Then, the random number circuit initial value update process is finished as it is, and the routine goes to Step S23.

  Next, the count value permutation change process (step S27) in the timer interrupt process will be described. FIG. 45 is a flowchart showing the count value permutation change process. The CPU 56 performs a count value permutation change process by executing a process according to the count value permutation change program 554. In the count value permutation process, the CPU 56 checks the state of the notification signal indicating that the count value C output from the counter 521 of the random number circuit 5003 has been updated to the final value (step S241). When it is detected that the notification signal is in the on state, the CPU 56 checks whether or not the count value permutation change flag is set (step S242). That is, the CPU 56 determines whether or not the setting for changing the permutation of the count values updated by the counter 521 when the count values are updated to a predetermined final value is made in the random number circuit setting process (see step S1506). Check.

  When the count value permutation change flag is set, the CPU 56 determines that the permutation of the count values updated by the counter 521 is changed when the counter 521 of the random number circuit 5003 updates the count value to a predetermined final value. Then, the CPU 56 writes the count value permutation change data “01h” in the count value permutation change register 536 (step S243). That is, the CPU 56 causes the count value permutation change circuit 523 to change the permutation of the count values C input to the random value storage circuit 531 by writing the count value permutation change data “01h”.

  As described above, in the count value permutation changing process, when the random number is updated to a predetermined final value, the permutation of the count value updated by the counter 521 is changed, so that the randomness generated by the random number circuit 5003 is more random. Can be improved.

Next, software random numbers updated by the game control microcomputer 560 will be described. FIG. 46 is an explanatory diagram showing each software random number. Each software random number is used as follows.
(2-1) Random 2-1 (MR2-1): used to calculate a jackpot determination random number (for jackpot determination calculation)
(2-2) Random 2-2 (MR2-2): Determines the type of jackpot (probability big hit, sudden probability change big hit, normal big hit) (for big hit type judgment)
(2-3) Random 2-3 (MR2-3): Decide whether or not to reach (for reach determination)
(3) Random 3 (MR3): The initial value of random 2-1 is determined (for determining the random 2-1 initial value).
(4) Random 4 (MR4): The type (type) of the variation pattern is determined (for variation pattern type determination)
(5) Random 5 (MR5): A variation pattern (variation time) is determined (for variation pattern determination)
(6) Random 6 (MR6): Determines whether or not to generate a hit based on the normal symbol (for normal symbol hit determination)
(7) Random 7 (MR7): The initial value of random 6 is determined (for determining the initial value of random 6)

  In step S24 in the game control process shown in FIG. 43, the game control microcomputer 560 uses (2-1) a jackpot determination calculation random number, (2-2) a jackpot type determination random number, and (5). The counter is incremented (added by 1) to generate a random number for determination per ordinary symbol. For example, to count up (add 1) the value of the jackpot determination calculation counter for counting the jackpot determination calculation random number (random 2-1) or to count the jackpot type determination random number (random 2-2) The value of the big hit type determination counter is counted up (added by 1). That is, they are determination random numbers, and other random numbers are display random numbers (random 2-2, random 4, random 5) or initial value random numbers (random 3, random 7). For example, in step S17 in the main process shown in FIG. 38 and in step S26 in the game control process shown in FIG. 43, the game control microcomputer 560 (2-2) a jackpot type determination random number, (3) And (4) a counter for generating a variation pattern determination random number is incremented (added by 1). For example, to increase the value of the big hit type determination counter for counting the big hit type determination random number (random 2-2) (to add 1) or to increase the variation pattern type determination random number (random 4) The value of the variation pattern type determination counter is counted up (added by 1), or the value of the variation pattern determination counter for counting up the random number for variation pattern determination (random 5) is counted up (added by 1). To do. Further, for example, in step S18 in the main process shown in FIG. 38 and step S25 in the game control process shown in FIG. 43, a random number for counting up the random 2-1 initial value determining random number (random 3) is counted. 2-1 Counts up the value of the initial value determination counter (adds 1) or counts up the value of the random 6 initial value determination counter for counting up the random 6 initial value determination random number (random 7) ( 1).

  Note that the values of the determination random number counter updated in step S24, the display random number counter updated in steps S17 and S26, and the initial value random number counter updated in steps S18 and S25 are shown in FIG. Are stored in the software random number counter storage area in the area of the RAM 55 shown in FIG. As described above, only the jackpot determination calculation counter for counting the jackpot determination calculation random number (random 2-1) is stored in the software random number counter storage area, and other software random number counters are used. May be stored in an area other than the software random number counter storage area in the work area shown in FIG.

  Further, in this embodiment, as will be described later, the game control microcomputer 560 uses a random 2-1 jackpot determination calculation random number, which is a software random number, and a hardware random number generated by the random number circuit 5003. , A random number for jackpot determination is generated. Then, based on the generated big hit determination random number, it is determined whether or not to make a big hit.

  FIG. 47A is an explanatory diagram showing a jackpot determination table. The jackpot determination table is a collection of data stored in the ROM 54, and is a table in which a jackpot determination value to be compared with a jackpot determination random number calculated by the game control microcomputer 560 is set. The jackpot determination table includes a normal-time jackpot determination table used in a normal state (a gaming state that is not a probability change state) and a probability change jackpot determination table used in a probability change state. Each numerical value described in the left column of FIG. 47 (A) is set in the normal jackpot determination table, and each numerical value described in the right column of FIG. 47 (A) is set in the probability variation big hit determination table. Is set.

  The CPU 56 generates a big hit determination random number using a hardware random number extracted from the random number circuit 5003 and a random 2-1 (software random number) at a predetermined time. When it matches one of the big hit judgment values shown in A), it is decided to make a big hit (probability big hit, normal big hit or sudden big hit) for the special symbol. The “probability” shown in FIG. 47A indicates the probability (ratio) of a big hit. Further, deciding whether or not to win a jackpot means deciding whether or not to shift to the jackpot gaming state, but the stop symbol in the first special symbol display 8a or the second special symbol display 8b is determined. It also means deciding whether or not to make a jackpot symbol.

  As shown in FIG. 47A, the minimum value 0 and the maximum value 65535 that can be taken by the jackpot determination random number may overlap the output value of the random number circuit 5003 in the unreadable state. Therefore, it is not a big hit judgment value.

  FIG. 47B is an explanatory diagram showing a jackpot type determination table 131 stored in the ROM 54. When it is determined that the variable display result is a jackpot symbol, the jackpot type determination table 131 determines the jackpot type as “normal jackpot”, “ This table is referred to in order to determine either “probable big hit” or “surprise big hit”. The big hit type determination table 131 is a numerical value to be compared with the random 2-2 value, and is a determination value corresponding to each of “normal big hit”, “probable big hit”, and “crash big hit” (big hit type determination value) Is set. When the random value 2-2 matches any of the jackpot type determination values, the CPU 56 determines the jackpot type as a type corresponding to the matched jackpot type determination value.

  Note that different jackpot type determination tables may be used for the case where the variable display of the first special symbol is performed and the case where the variable display of the second special symbol is performed. In this case, for example, when the variable display of the second special symbol executed based on the start winning winning is made at the second starting winning opening 14 provided with the variable winning ball apparatus 15, the normal big hit and the probable big hit The big hit type may be determined using only the big hit type determination table that does not include sudden change odd big hits. Specifically, the determination value “7” suddenly distributed to the probability variation jackpot in FIG. 47B may be allocated to the probability variation jackpot to configure the jackpot type determination table. With such a configuration, when the probability variation state (short-time state) is established, the winning combination is performed at the second starting winning port 14 provided with the variable winning ball apparatus 15 and the variation display of the second special symbol is executed. Since the frequency of playing is increased, the probability of a big hit of 15 rounds can be increased, the starting rate can be improved, and the interest in games can be improved.

  FIG. 48 is a flowchart showing an example of a special symbol process (step S28) program executed by the game control microcomputer 560 (specifically, the CPU 56) mounted on the main board 31. As described above, in the special symbol process, a process for controlling the first special symbol display 8a or the second special symbol display 8b and the special winning opening is executed. In the special symbol process, the CPU 56 detects that the game ball has won the first start port switch 13a or the second start port 14 for detecting that the game ball has won the first start game port 13. If the second start port switch 14a is turned on, that is, if a start winning is generated, start port switch passing processing is executed (steps S311 and S312). Then, any one of steps S300 to S307 is performed. If the first start winning port switch 13a or the second start port switch 14a is not turned on, any one of steps S300 to S307 is performed according to the internal state.

  The processes in steps S300 to S307 are as follows.

  Special symbol normal processing (step S300): Executed when the value of the special symbol process flag is zero. When the game control microcomputer 560 is in a state where variable display of a special symbol can be started, the game control microcomputer 560 checks the number of numerical data stored in the reserved storage number buffer (total reserved storage number). The number of numerical data stored in the reserved storage number buffer can be confirmed by the count value of the total reserved storage number counter. If the count value of the total reserved memory number counter is not 0, it is determined whether or not the display result of the variable display of the first special symbol or the second special symbol is a big hit. In case of big hit, set big hit flag. Then, the internal state (special symbol process flag) is updated to a value (1 in this example) according to step S301. The jackpot flag is reset when the jackpot game ends.

  Fluctuation pattern setting process (step S301): This process is executed when the value of the special symbol process flag is 1. Also, the variation pattern is determined, and the variation time in the variation pattern (variable display time: the time from the start of variable display until the display result is derived and displayed (stop display)) is defined as the variation display variation time of the special symbol Decide to do. Also, a variable time timer for measuring the special symbol variable time is started. Then, the internal state (special symbol process flag) is updated to a value (2 in this example) corresponding to step S302.

  Display result specifying command transmission process (step S302): executed when the value of the special symbol process flag is 2. Control for transmitting a display result specifying command to the production control microcomputer 100 is performed. Then, the internal state (special symbol process flag) is updated to a value (3 in this example) corresponding to step S303.

  Special symbol changing process (step S303): This process is executed when the value of the special symbol process flag is 3. When the variation time of the variation pattern selected in the variation pattern setting process elapses (the variation time timer set in step S301 times out, that is, the variation time timer value becomes 0), the internal state (special symbol process flag) is stepped. Update to a value corresponding to S304 (4 in this example).

  Special symbol stop process (step S304): executed when the value of the special symbol process flag is 4. The variable display on the first special symbol display 8a or the second special symbol display 8b is stopped, and the stop symbol is derived and displayed. In addition, control for transmitting a symbol confirmation designation command to the effect control microcomputer 100 is performed. If the big hit flag is set, the internal state (special symbol process flag) is updated to a value (5 in this example) corresponding to step S305. If the big hit flag is not set, the internal state (special symbol process flag) is updated to a value corresponding to step S300 (0 in this example). The effect control microcomputer 100 controls the effect display device 9 to stop the effect symbol and the decorative symbol when receiving the symbol confirmation designation command transmitted by the game control microcomputer 560.

  Preliminary winning opening opening process (step S305): This is executed when the value of the special symbol process flag is 5. In the pre-opening process for the big prize opening, control for opening the big prize opening is performed. Specifically, a counter (for example, a counter that counts the number of game balls that have entered the big prize opening) is initialized and the solenoid 21 is driven to open the big prize opening. Also, the execution time of the special prize opening opening process is set by the timer, and the internal state (special symbol process flag) is updated to a value corresponding to step S306 (6 in this example). The pre-opening process for the big winning opening is executed for each round, but when the first round is started, the pre-opening process for the big winning opening is also a process for starting the big hit game.

  Large winning opening opening process (step S306): This process is executed when the value of the special symbol process flag is 6. A control for transmitting an effect control command for round display during the big hit gaming state to the effect control microcomputer 100, a process for confirming the completion of the closing condition of the big prize opening, and the like are performed. If the closing condition for the special prize opening is satisfied and there are still remaining rounds, the internal state (special symbol process flag) is updated to a value (5 in this example) corresponding to step S305. When all the rounds are completed, the internal state (special symbol process flag) is updated to a value corresponding to step S307 (7 in this example).

  Big hit end process (step S307): executed when the value of the special symbol process flag is 7. Control is performed to cause the microcomputer 100 for effect control to perform display control for notifying the player that the big hit gaming state has ended. In addition, a process for setting a flag indicating a gaming state (for example, a probability change flag or a time reduction flag) is performed. Then, the internal state (special symbol process flag) is updated to a value (0 in this example) corresponding to step S300.

  49 and 50 are flowcharts showing the start-port switch passing process in step S312. In the start port switch passing process executed when at least one of the first start port switch 13a and the second start port switch 14a is in the on state, the CPU 56 is turned on by the first start port switch 13a. Whether or not (step S2001). If the first start port switch 13a is on, the CPU 56 sets data indicating “first” (for example, “01 (H)”) in the start port pointer (step S2002). If the first start port switch 13a is not turned on (that is, if the second start port switch 14a is turned on), the CPU 56 indicates data indicating “second” in the start port pointer (for example, “02 (H)”. ”) Is set (step S2003).

  Next, the CPU 56 confirms whether or not the value of the reserved memory number counter (the first reserved memory number counter or the second reserved memory number counter is 4) indicated by the start port pointer (step S2004). The 1 reserved memory number counter is a counter for counting the first reserved memory number that has been won at the first start winning port 13, and the second reserved memory number counter is the first one that has been won at the second start winning port 14. 2. This is a counter for counting the number of reserved memories.If the value of the reserved memory number counter is 4, the process is terminated as it is.

  If the value of the reserved memory number counter is not 4, the CPU 56 increments the value of the reserved memory number counter indicated by the start port pointer by 1 (step S2005). Further, the CPU 56 corresponds to the value of the total reserved storage number counter in the reserved storage specific information storage area (hold specific area) for storing the winning order to the first start winning opening 13 and the second start winning opening 14. Data indicated by the start port pointer (data indicating “first” or “second”) is set in the area (step S2006).

  In this embodiment, when the first start opening switch 13a is turned on (that is, when a game ball starts and wins the first start winning opening 13), data indicating “first” is set, When the second start port switch 14a is turned on (that is, when a game ball starts and wins the second start winning port 14), data indicating “second” is set. For example, the CPU 56 sets 01 (H) as data indicating “first” when the first start port switch 13 a is turned on in the reserved storage specifying information storage area (holding specified area), and the first 2 When the start port switch 14a is turned on, 02 (H) is set as data indicating “second”. In this case, when there is no corresponding reserved storage, 00 (H) is set in the reserved storage specific information storage area (hold specific area).

  FIG. 51A is an explanatory diagram showing a configuration example of a reserved storage specifying information storage area (holding specified area). As shown in FIG. 51A, an area corresponding to the maximum value (8 in this example) of the total reserved memory number counter is secured in the reserved specific area. FIG. 51A shows an example in which the value of the total pending storage number counter is 5. As shown in FIG. 51A, an area corresponding to the maximum value (8 in this example) of the total reserved memory number counter is secured in the reserved specific area, and the first start winning opening 13 or the second start is set. Data indicating “first” or “second” is set in order of winning based on winning in the winning opening 14. Accordingly, in the reserved storage specific information storage area (hold specific area), the winning order to the first start winning opening 13 and the second starting winning opening 14 is stored. Note that the reserved specific area is formed in the RAM 55. “Formed in RAM” means an area in the RAM.

  FIG. 51B is an explanatory diagram showing a configuration example of an area (hold buffer) for storing random numbers and the like corresponding to the hold memory. As shown in FIG. 51 (B), a storage area corresponding to the upper limit value (4 in this example) of the first reserved storage number is secured in the first reserved storage buffer. In addition, a storage area corresponding to the upper limit value of the second reserved storage number (4 in this example) is secured in the second reserved storage buffer. The first reserved storage buffer and the second reserved storage buffer are formed in the RAM 55.

  Next, the CPU 56 determines the value of the random number circuit read value storage area (the first random number circuit read value storage area or the second random number circuit read value storage area) to which the start port pointer points, the previous random number circuit to which the start port pointer points. Save to the read value storage area (first previous random number circuit read value storage area or second previous random number circuit read value storage area) (step S2007). The random number circuit read value storage area is an area for storing a hardware random number value read from the random number storage circuit 531 of the random number circuit 5003, and is secured in the RAM 55, for example. The previous random number circuit read value storage area is an area for storing the hardware random number value read from the random value storage circuit 531 of the random number circuit 5003 in the previous process, and is secured in the RAM 55, for example.

  Next, the CPU 56 reads the hardware random number value from the random number value storage circuit 531 pointed to by the start port pointer, and stores it in the random number circuit read value storage area pointed to by the start port pointer (step S2008). For example, when a game ball wins a start at the first start winning opening 13, a detection signal from the first start opening switch 13a is input as a latch signal SL1, thereby causing a hardware random number to be input to the first random number storage circuit 531a. Is latched. In this case, the CPU 56 starts outputting the output control signal to the first random number value storage circuit 531a, and reads the hardware random number from the first random number value storage circuit 531a. Then, the read hardware random number value is stored in the first random number circuit read value storage area. In addition, for example, when a game ball is won at the second start winning opening 14, a detection signal from the second start opening switch 14a is input as a latch signal SL2, thereby causing the second random value storage circuit 531b to be hardened. Wear random number is latched. In this case, the CPU 56 starts outputting an output control signal to the second random number value storage circuit 531b, and reads a hardware random number from the second random number value storage circuit 531b. Then, the read hardware random number value is stored in the second random number circuit read value storage area.

  In this embodiment, each random number storage circuit 531a, 531b latches a hardware random number by inputting a detection signal from the first start port switch 13a or the second start port switch 14a as a latch signal. However, the latch signal may be output from the CPU 56 to the random value storage circuits 531a and 531b. For example, in the process of step S2008, the CPU 56 outputs a latch signal to the random value storage circuit 531 to which the start port pointer points, and after a delay time of a predetermined time (for example, 0.1 second), the random value storage circuit The value of the hardware random number may be read from 531 and stored in the random number circuit read value storage area indicated by the start port pointer.

  Next, the CPU 56 checks whether or not the value in the random number circuit read value storage area pointed to by the start port pointer matches the value in the previous random number circuit read value storage area pointed to by the start port pointer (step S2009). ). If they do not match, the CPU 56 resets the random number unupdated number counter (the first random number unupdated number counter or the second random number unupdated number counter) that is pointed to by the start port pointer (step S2010). Note that the random number unupdated counter is a counter for counting the number of times the random number generated by the random number circuit 5003 has not been updated. Then, the process proceeds to step S2014.

  If the value in the random number circuit read value storage area pointed to by the start port pointer matches the value in the previous random number circuit read value storage area pointed to by the start port pointer (Y in step S2009), the CPU 56 starts the start port pointer. 1 is added to the value of the random number non-update count counter indicated by (step S2011). Further, it is confirmed whether or not the value of the random number unupdated counter after addition is equal to or greater than a predetermined value (for example, 2 or 3) (step S2012). If the value of the random number unupdated counter after the addition is a predetermined value (Y in step S2012), the CPU 56 performs control to transmit a random number abnormality designation command to the effect control microcomputer 100 (step S2013). That is, since the hardware random number value by the random number circuit 5003 has not been updated for a predetermined number of times or more, it is determined that some sort of fraud has been performed on the random number circuit 5003, and control is performed to transmit a random number abnormality designation command.

  When the value of the random number circuit read value storage area pointed to by the start port pointer matches the value of the previous random number circuit read value storage area pointed to by the start port pointer, it is immediately determined that the random number circuit 5003 is abnormal. A random number abnormality designation command may be transmitted. In this case, for example, when the CPU 56 determines Y in step S2009, the CPU 56 may execute step S2013 as it is without executing steps S2011 and S2012.

  In the processing of steps S2007 to S2013, the CPU 56 determines that a specific bit (a plurality of bits or a single bit) of the value in the random number circuit read value storage area indicated by the start port pointer is Compared with the value stored in the previous random number circuit read value storage area, it may be confirmed whether or not it has changed a plurality of times. If the specific bit has not changed a plurality of times, it may be determined that the random number circuit 5003 is abnormal and a random number abnormality designation command may be transmitted. With such a configuration, a specific bit of the random number circuit 5003 can be crushed (for example, shorted) to effectively prevent an illegal act that narrows the update range of the random number.

  Further, even when the game control microcomputer 560 does not include the random number circuit 5003 and an external random number circuit is used for the game control microcomputer 560, the CPU 56 performs the same processing as steps S2007 to S2013. It is possible to determine whether or not an abnormality has occurred in the external random number circuit. If the CPU 56 determines that an abnormality has occurred in the external random number circuit, it transmits a random number abnormality designation command in accordance with the same processing as in step S2013.

  Next, the CPU 56 extracts a value from a counter for generating each software random number (step S2014). In the process of step S2014, random numbers 2-1 and random 2-2 (see FIG. 46), which are software random numbers, are extracted from the jackpot determination calculation counter and the jackpot type determination counter. In this case, specifically, the CPU 56 stores each counter stored in a software random number counter storage area (see FIG. 30) that is an area of the RAM 55 that is not initialized in the initialization process (see steps S10 to S13) in the main process. Software random numbers such as jackpot determination calculation random numbers (random 2-1) and jackpot type determination random numbers (random 2-2) are read out.

  Next, the CPU 56 determines the jackpot determination random number (random number) used for the jackpot determination based on the random number 2-1 (random hit determination calculation random number) that is the software random number read in step S2014 and the hardware random number read in step S2008. MR1) is calculated (step S2015).

  FIG. 52 is an explanatory diagram showing how to create a random MR1 to be compared with the big hit determination value. As shown in FIG. 52A, when a game ball wins the first start winning opening 13, that is, when the first start win occurs, the CPU 56 uses a first random value storage circuit (first latch circuit). ) Read the count value latched by 531a. Also, random numbers 2-1 (random numbers for jackpot determination calculation) that are software random numbers are extracted. That is, the count value is read from a counter for generating random 2-1 (a jackpot determination calculation counter which is a software counter having the same bit width (for example, 16 bits) as the bit width of the counter 521 of the random number circuit 5003). Then, the count value read from the counter 521 and the extracted random 2-1 are added, and the added value is further divided by 65536 (corresponding to the total number of values from 0 to 65535, in other words, equivalent to 65535 + 1) (integer). And the remainder (remainder) is set as a jackpot determination random number (random MR1: a random number that is actually compared with the jackpot determination value).

  As shown in FIG. 52 (B), when a game ball wins the second start winning opening 14, that is, when a second start win occurs, the CPU 56 uses the second random value storage circuit (second (Latch circuit) Reads the count value latched by 531b. Also, random numbers 2-1 (random numbers for jackpot determination calculation) that are software random numbers are extracted. That is, the count value is read from a counter for generating random 2-1 (a big hit determination calculation counter which is a software counter). Then, the count value read from the counter 521 and the extracted random 2-1 are added, and the added value is further divided by 65536 (corresponding to the total number of values from 0 to 65535, in other words, equivalent to 65535 + 1) (integer). And the remainder (remainder) is set as a big hit determination random number (random MR1).

  If the game control microcomputer 560 does not include the random number circuit 5003 and an external random number circuit is used for the game control microcomputer 560, the CPU 56 causes the external random number circuit to be corrupted in step S2008. Reads a hardware random number from the numerical storage circuit. Then, in step S2015, the CPU 56 performs processing similar to FIG. 52 based on the random 2-1 (random number for jackpot determination calculation) read in step S2014 and the hardware random number read in step S2008. Thus, a big hit determination random number (random MR1) used for the big hit determination is calculated.

  In this embodiment, the jackpot determination random number (random MR1) using two random numbers, that is, the random number 2-1 (random number for jackpot determination calculation) that is a software random number and the hardware random number read from the random number circuit 5003. However, the jackpot determination random number (random MR1) may be calculated using only one of them. For example, the game control microcomputer 560 may calculate the jackpot determination random number (random MR1) using only the random number 2-1 (the jackpot determination calculation random number) that is a software random number in step S2015. In this case, the game control microcomputer 560 may use the jackpot determination random number (random 2-1) as it is without changing the jackpot determination random number (random MR1). Further, for example, the game control microcomputer 560 uses only the hardware random number read from the random number circuit 5003 (or a random number circuit external to the game control microcomputer 560) in step S2015 to determine the big hit determination random number. (Random MR1) may be calculated. In this case, the game control microcomputer 560 may use the read hardware random number (random R) as it is as the big hit determination random number (random MR1) without calculation.

  Next, the CPU 56 stores the software random number other than the random 2-1 read in step S2014 or the random MR1 calculated in step S2015 to the holding storage buffer (the first holding storage buffer or the second holding storage buffer that is pointed to by the start port pointer. ) Is stored in the storage area (step S2016). In this case, the CPU 56 initializes the random number values including the calculated jackpot determination random number (MR1) in the initialization process in the main process (see steps S10 to S13) in the RAM 55 area. Area (see FIG. 30. That is, among the areas of the RAM 55 shown in FIG. 30, the software random number counter storage area is not initialized in the initialization process, while other areas other than the software random number counter storage area are initialized. Stored in the process). Further, the CPU 56 stops sending the output control signal to the random value storage circuit 531 started in step S2008.

  Next, the CPU 56 performs control to transmit the start winning designation command (the first starting winning designation command or the second start winning designation command) indicated by the start opening pointer (step S2018). Further, the CPU 56 increases the value of the total pending memory number counter indicating the total pending memory number that is the sum of the first reserved memory number and the second reserved memory number by 1 (step S2019). Then, the CPU 56 performs control to transmit a total pending storage number designation command indicating the total pending storage number based on the value of the total pending storage number counter (step S2020). The total pending storage number designation command may be transmitted before the start winning designation command.

  When transmitting an effect control command to the effect control microcomputer 100, the CPU 56 sets an address of a command transmission table (preliminarily set for each command in the ROM) corresponding to the effect control command as a pointer. . Then, the address of the command transmission table corresponding to the effect control command is set in the pointer, and the effect control command is transmitted in the effect control command control process (step S30).

  Note that when the number of reserved memories pointed to by the start port pointer has reached the upper limit value (4 in this example) in step S2002, the processing is not terminated as it is, but whether or not the second start port switch 14a is turned on. If it is turned on, the process proceeds to step S2003, and data indicating "second" may be set in the start port pointer. With such a configuration, when the first start port switch 13a and the second start port switch 14a are turned on at the same timing, a random number value can be extracted at an accurate timing and stored in the reserved storage number buffer. .

  53 and 54 are flowcharts showing the special symbol normal process (step S300) in the special symbol process. In the special symbol normal process, the CPU 56 confirms the value of the total pending storage number (step S51). Specifically, the count value of the total pending storage number counter is confirmed. If the total pending storage number is 0, the process is terminated.

  If the total pending storage number is not 0, the CPU 56 checks whether or not the first data among the data set in the pending specific area (see FIG. 51A) is data indicating “first”. (Step S52). If it is data indicating “first”, a special symbol pointer (a flag indicating whether special symbol process processing is being performed for the first special symbol or special symbol process processing is being performed for the second special symbol) is set to “first 1 "is set (step S53). If it is not data indicating “first”, that is, if it is data indicating “second”, data indicating “second” is set in the special symbol pointer (step S54).

  In this embodiment, hereinafter, the first special symbol on the first special symbol display 8a depends on whether the data indicating "first" or the data indicating "second" is set in the special symbol pointer. And the variable display of the second special symbol on the second special symbol display 8b are executed using a common processing routine. Here, the “common processing routine” is a program for realizing a specific series of processes, and in this embodiment, a series for performing variable display of the first special symbol and the second special symbol. It points to the program for realizing the process. In this embodiment, the “common processing routine” includes steps S55 to S76 in a special symbol normal process described later, a variation pattern setting process in step S301, a display result specifying command transmission process in step S302, and a process in step S303. The special symbol changing process and the special symbol stop process of step S304 are included.

  In the RAM 55, the CPU 56 reads out each random number value stored in the storage area corresponding to the reserved storage number = 1 indicated by the special symbol pointer, and stores it in the random number buffer area of the RAM 55 (step S55). Specifically, when the special symbol pointer indicates “first”, the CPU 56 determines each disturbance stored in the storage area corresponding to the first reserved memory number = 1 in the first reserved memory number buffer. The numerical value is read and stored in the random number buffer area of the RAM 55. In addition, when the special symbol pointer indicates “second”, the CPU 56 reads each random number value stored in the storage area corresponding to the second reserved memory number = 1 in the second reserved memory number buffer. And stored in the random number buffer area of the RAM 55.

  Then, the CPU 56 decrements the count value of the reserved storage number counter indicated by the special symbol pointer, and shifts the contents of each storage area (step S56). Specifically, when the special symbol pointer indicates “first”, the CPU 56 decrements the count value of the first reserved memory number counter by 1 and saves each storage area in the first reserved memory number buffer. Shift the contents of. When the special symbol pointer indicates “second”, the count value of the second reserved memory number counter is decremented by 1, and the contents of each storage area in the second reserved memory number buffer are shifted.

  That is, when the special symbol pointer indicates “first”, the CPU 56 saves the first reserved memory number = n (n = 2, 3, 4) in the first reserved memory number buffer of the RAM 55. Are stored in a storage area corresponding to the first reserved memory number = n−1. Further, when the special symbol pointer indicates “second”, it is stored in the storage area corresponding to the second reserved memory number = n (n = 2, 3, 4) in the second reserved memory number buffer of the RAM 55. Each random number value is stored in a storage area corresponding to the second reserved memory number = n−1.

  Therefore, the order in which each random value stored in each storage area corresponding to each first reserved memory number (or each second reserved memory number) is extracted is always the first reserved memory number (or (Second reserved storage number) = 1, 2, 3, 4 in order.

  Then, the CPU 56 stores the count value of the total pending storage number counter in a predetermined area of the RAM 55 (step S57), and then decreases the value of the total pending storage number by one. That is, 1 is subtracted from the count value of the total pending storage number counter (step S58). The CPU 56 stores the value of the total pending storage number counter before the count value is decremented by 1 in a predetermined area of the RAM 55.

  In the special symbol normal process, first, data indicating “first” indicating that the process is executed for the first start winning opening 13, that is, “first” indicating that the process is executed for the first special symbol. ”Or“ second ”indicating that the process is performed on the second special symbol, that is,“ second ”indicating that the process is performed on the second start winning opening 14. Data is set in the special symbol pointer. In the subsequent processing in the special symbol process, processing corresponding to the data set in the special symbol pointer is executed. Therefore, the process of steps S300 to S307 can be shared between the case where the first special symbol is the target and the case where the second special symbol is the target.

  Next, the CPU 56 reads the jackpot determination random number MR1 from the random number buffer area (step S61), and executes the jackpot determination module (step S62). The jackpot determination module is a program that compares a jackpot determination value (see FIG. 47) determined in advance with a jackpot determination random number, and executes a process of determining a jackpot if they match. In other words, this is a program for executing the big hit determination process.

  The jackpot determination process is configured such that when the gaming state is a probable change state (high probability state), the probability of a big hit is higher than when the gaming state is a non-probability change state (normal game state and short-time state). ing. Specifically, a jackpot determination table at the time of probability change in which a large number of jackpot determination values are set in advance (a table in which the value on the right side of FIG. 47A in the ROM 54 is set) and the number of jackpot determination values are variable. There is provided a normal big hit determination table (a table in which the numerical value on the left side of FIG. 47A in the ROM 54 is set) set to be smaller than the big hit determination table. Then, the CPU 56 checks whether or not the gaming state is a probability variation state. If the gaming state is a probability variation state, the jackpot determination process is performed using the probability variation jackpot determination table, and the gaming state is normal. When in the gaming state, the big hit determination process is performed using the normal big hit determination table. That is, when the value of the big hit determination random number (random R) matches any of the big hit determination values shown in FIG. 47A, the CPU 56 determines that the special symbol is a big hit (probability big hit or normal big hit). . If it is determined to be a big hit (Y in step S63), the process proceeds to step S71. Note that deciding whether to win or not is to decide whether or not to shift to the big hit gaming state, but to decide whether or not to stop the special symbol display as a big hit symbol. But there is.

  Note that whether or not the current gaming state is the probability variation state is determined by whether or not the probability variation flag is set. The probability variation flag is set when the gaming state is shifted to the probability variation state, and is reset when the probability variation state is terminated. Specifically, it is determined to be a probable big hit or suddenly probable big hit, set in the process of ending the big hit game, determined to be a normal big hit, and reset in the process of ending the big hit game.

  If the value of the random R does not match any of the big hit determination values, the process proceeds to step S75 as it is.

  In step S71, the CPU 56 sets a big hit flag. Then, the big hit type determination table 131 shown in FIG. 47B is selected as a table used to determine the big hit type as one of a plurality of types (step S72). The type corresponding to the value of the jackpot type determination random number (random 2-2) stored in the random number buffer area (“normal”, “probability” or “surprise”) is determined as the jackpot type ( Step S73). Further, the data indicating the determined jackpot type is set in the jackpot type buffer in the RAM 55 (step S74). For example, when the jackpot type is “normal”, “01” is set as data indicating the jackpot type, and when the jackpot type is “probability”, “02” is set as data indicating the jackpot type. Is “03”, “03” is set as data indicating the big hit type.

  Next, the CPU 56 determines a special symbol stop symbol (step S75). Specifically, when the big hit flag is not set, “−” as a special symbol is determined as a stop symbol of the special symbol. When the big hit flag is set, one of “1”, “3”, and “7”, which is a big hit symbol, is determined as a special symbol stop symbol according to the determination result of the big hit type. That is, when the big hit type is determined to be “surprise”, “1”, which is the two round big hit symbol, is determined as a special symbol stop symbol. When the big hit type is determined as “normal” or “probability change”, “3” or “7” is determined as a special symbol stop symbol.

  Then, the value of the special symbol process flag is updated to a value corresponding to the variation pattern setting process (step S301) (step S76).

  FIG. 55 is a flowchart showing the variation pattern setting process (step S301) in the special symbol process. In the variation pattern setting process, the CPU 56 checks whether or not the big hit flag is set (step S91).

  When the big hit flag is set, one of the big hit variation pattern type determination tables prepared in advance is selected as a table used for determining one of a plurality of types of variation pattern types. (Step S92). Then, the process proceeds to step S101. The CPU 56 can determine the gaming state based on the state of the probability change flag and the time reduction flag.

  If the big hit flag is not set, whether or not the variable display state of the effect symbol is set to the reach state based on whether the gaming state in the pachinko gaming machine 1 is the normal state, the probability changing state, or the short-time state One of the reach determination tables prepared in advance is selected as a table used to determine whether or not (step S95). Further, the random 2-3 is extracted by extracting the count value of the counter for generating the random 2-3 (step S96). Then, the CPU 56 indicates the presence or absence of a reach state corresponding to a value that coincides with the random 2-3 value in an area corresponding to the reserved storage number (the value of the reserved storage number counter) in any of the selected reach determination tables. Based on the data, it is determined whether or not to reach and the type of effect when not reaching or the type of reach when reaching (step S97). Note that the value before being decremented by -1 in the process of step S53 may be used as the reserved storage number used in the process of step S97.

  If it is decided to reach (Y in step S98), the table used to determine the variation pattern type as one of a plurality of types according to the type of reach determined in the process of step S97. As described above, one of the reach variation pattern type determination tables prepared in advance is selected (step S99). If it is decided not to reach (N in step S98), the table used to determine the variation pattern type as one of a plurality of types according to the type of effect determined in the process of step S97. Then, one of the non-reach variation pattern type determination tables prepared in advance is selected (step S100). Then, the process proceeds to step S101.

  In step S <b> 101, the CPU 56 extracts the value of random 4 by extracting the count value of the counter for generating random 4. Then, based on the extracted random 4 value, the variation pattern type is determined as one of a plurality of types by referring to the table selected in the process of step S92, S99 or S100 (step S102). In step S102, for example, when it is a loss and not a reach, the CPU 56 sets the variation pattern type as a loss with a specific effect (slide effect or pseudo-ream) or as a loss without a specific effect. Decide on either type. For example, in the case of a big hit or loss with reach, the variation pattern type is any one of normal reach, super reach 1 or super reach 2 (characters that appear different from super reach 1). To decide. Then, based on the determined variation pattern type, the CPU 56 determines a variation pattern in step S105 described later. For example, the CPU 56, based on the variation pattern type determined in step S102, in step S105, which will be described later, among the variation patterns included in the variation pattern type, a variation pattern that does not involve a sliding effect or pseudo-continuity, or a variation that involves a sliding effect. The variation pattern to be executed is determined from the pattern or the variation pattern accompanied by the pseudo-ream.

  Next, based on the determination result of the variation pattern type in step S102, the CPU 56 determines any hit variation pattern prepared in advance as a table used to determine one of a plurality of variation patterns. A table or one of the prepared deviation variation pattern determination tables is selected (step S103). Further, the value of random 5 is extracted by extracting the count value of the counter for generating random 5 (step S104). Based on the extracted random value 5, the variation pattern is determined as one of a plurality of types by referring to the variation pattern determination table selected in step S103 (step S105).

  Next, an effect control command (variation pattern command) corresponding to the determined variation pattern is controlled to be transmitted to the effect control microcomputer 100 (step S106).

  Also, the special symbol change is started (step S107). For example, a start flag corresponding to the special symbol referred to in the special symbol display control process in step S35 is set. Further, a value corresponding to the variation time corresponding to the selected variation pattern is set in the variation time timer formed in the RAM 55 (step S108). Then, the value of the special symbol process flag is updated to a value corresponding to the display result specifying command transmission process (step S302) (step S109).

  FIG. 56 is a flowchart showing the display result specifying command transmission process (step S302). In the display result specifying command transmission process, the CPU 56 performs control to transmit any effect control command (refer to FIG. 39) of display result 1 designation to display result 4 designation in accordance with the determined jackpot type and deviation. Do. Specifically, the CPU 56 first checks whether or not the big hit flag is set (step S110). If not set, the process proceeds to step S118. When the big hit flag is set, when the big hit type is a probable big hit, control is performed to transmit a display result 3 designation command (steps S111 and S112). When the type of jackpot is a sudden probability change jackpot, control is performed to transmit a display result 4 designation command (steps S113 and S114). If neither the probability variation big hit nor sudden probability variation big hit is found, control is performed to transmit a display result 2 designation command (step S115).

  When the big hit flag is not set (N in step S110), the CPU 56 performs control to transmit a display result 1 designation command (step S118).

  Then, a total pending storage number subtraction designation command designating that 1 is subtracted from the total pending storage number is transmitted (step S119). Instead of transmitting the total pending storage number subtraction designation command, a total pending storage number designation command for designating the total pending storage number after subtraction may be transmitted. Further, the CPU 56 stores the transmitted display result specifying command in the effect symbol type storage area in the RAM 55.

  Thereafter, the CPU 56 updates the value of the special symbol process flag to a value corresponding to the special symbol changing process (step S303) (step S120).

  FIG. 57 is a flowchart showing the special symbol changing process (step S303) in the special symbol process. In the special symbol changing process, the CPU 56 decrements the variable time timer by 1 (step S125), and when the variable time timer times out (step S126), the value of the special symbol process flag corresponds to the special symbol stop process (step S304). The updated value is updated (step S127). If the variable time timer has not timed out, the process ends.

  FIG. 58 is a flowchart showing the special symbol stop process (step S304) in the special symbol process. In the special symbol stop process, the CPU 56 sets an end flag referred to in the special symbol display control process in step S34 to end the variation of the special symbol, and the first special symbol display 8a or the second special symbol display 8b. Then, a control for deriving and displaying the stop symbol is performed (step S131). If data indicating “first” is set in the special symbol pointer, the variation of the first special symbol on the first special symbol display 8a is terminated, and “second” is indicated in the special symbol pointer. When data is set, the variation of the second special symbol on the second special symbol display 8b is terminated. Moreover, control which transmits the symbol determination designation | designated command to the microcomputer 100 for production control is performed (step S132). If the big hit flag is not set, the process proceeds to step S139 (step S133).

  When the big hit flag is set, the CPU 56 resets the probability variation flag and the time reduction flag (step S134), and performs control to send a big hit start designation command to the effect control microcomputer 100 (step S135). Specifically, when the type of jackpot is a probabilistic jackpot, a jackpot start 2 designation command is transmitted. When the type of jackpot is a sudden probability big hit, a sudden start designation command is transmitted. Otherwise, a jackpot start 1 designation command is transmitted. Whether or not the big hit type is a probable big hit or a sudden probable big hit is determined based on data indicating the big hit type stored in the RAM 55 (data stored in the big hit type buffer).

  Also, a value corresponding to the big hit display time (for example, the time for notifying that the big hit has occurred in the effect display device 9) is set in the big hit display time timer (step S136). In addition, the number of times of opening (for example, 15 times in the case of a normal big hit and a probable big hit (15 round big hit) and 2 times in the case of a sudden hit (2 round big hit)) is set in the big prize opening number counter (step). S137). Then, the value of the special symbol process flag is updated to a value corresponding to the pre-winner opening pre-processing (step S305) (step S138).

  In step S139, the CPU 56 checks whether or not a time reduction flag indicating that the time reduction state is set. If the time reduction flag is set, the value of the time reduction counter indicating the number of times the special symbol can be changed in the time reduction state is decremented by 1 (step S140). Then, when the value of the time reduction counter becomes 0, the time reduction flag is reset (step S142). Then, the CPU 56 updates the value of the special symbol process flag to a value corresponding to the special symbol normal process (step S300) (step S148).

  FIG. 59 is a flowchart showing the pre-opening process for the special winning opening in the special symbol process (step S305). In the big prize opening pre-processing, the CPU 56 decrements the value of the big prize opening control timer by 1 (step S401). Then, it is confirmed whether or not the value of the big prize opening control timer is 0 (step S402). If the value of the big prize opening control timer is not 0, the process is terminated.

  When the value of the big prize opening control timer is 0, the CPU 56 designates the big prize opening opening designation command (A1XX) for designating the display state according to the number of rounds during the opening of the big prize opening (during round). (H)) is transmitted to the production control microcomputer 100 (step S403). Note that the CPU 56 recognizes the number of rounds by checking the value of the number-of-releases counter for counting the number of rounds in the big hit game. Then, the CPU 56 controls to open the special winning opening (special variable winning ball apparatus 20) by driving the solenoid 21 (step S404) and decrements the value of the number-of-opening counter (step S405).

  Further, a value corresponding to the maximum time that the big prize opening can be opened in each round is set in the big prize opening control timer (step S406). For example, in the case of 15 rounds of big hit, the maximum time is 29 seconds, and in the case of sudden probability big hit, the maximum time is 0.5 seconds. Then, the value of the special symbol process flag is updated to a value corresponding to the step large winning opening opening process (step S306) (step S415).

  FIG. 60 and FIG. 61 are flowcharts showing the special winning opening opening process (step S306) in the special symbol process. In the special prize opening opening process, the CPU 56 decrements the value of the special prize opening control timer by -1 (step S420).

  Then, the CPU 56 confirms whether or not the value of the special winning opening control timer has become 0 (step S421). When the value of the big prize opening control timer is not 0, it is confirmed whether or not the count switch 23 is turned on (step S432). If the count switch 23 is not turned on, the process is terminated. When the count switch 23 is turned on, the value of the winning number counter for counting the number of winning game balls to the big winning opening is incremented by 1 (step S433). Then, the CPU 56 checks whether or not the value of the winning number counter is a predetermined number (for example, 10) (step S434). If the value of the winning number counter is not a predetermined number, the process is terminated. Note that the determination order of S421 and S432 may be reversed.

  When the value of the big prize opening control timer is 0, or when the value of the winning number counter is a predetermined number, the CPU 56 performs control to drive the solenoid 21 and close the big prize opening (step). S435). Then, the value of the winning number counter is cleared (set to 0) (step S436).

  Next, the CPU 56 confirms the value of the opening number counter (step S438). When the value of the number-of-opening counter is not 0, the CPU 56 designates the post-big prize opening after-opening designation command (A2XX (H)) for designating the display state according to the number of rounds after the big prize opening is opened (after the end of the round). ) Is transmitted to the production control microcomputer 100 (step S439). Then, a value corresponding to the time (interval period) from the end of the round to the start of the next round (interval period) is set in the big prize opening control timer (step S440), and the value of the special symbol process flag is set to the big prize opening. The value is updated according to the pre-opening process (step S305) (step S441). The interval period is, for example, 5 seconds. In the case of a sudden probability big hit, it may be shorter than the 15R big hit.

  When the value of the number-of-opens counter is 0, the CPU 56 performs control to transmit a big hit end 2 designation command to the effect control microcomputer 100 when the data showing the big hit type is data showing the probability variation big hit. (Steps S442 and S447). Whether or not it is a probable big hit in step S442 is specifically a value ("02" in this example) in which the data indicating the big hit type set in the big hit type buffer in the RAM 55 in step S74 indicates a probable big hit. It can be determined by checking whether or not there is. Then, the CPU 56 sets a value corresponding to the jackpot end time (for example, the time for notifying the effect display device 9 that the jackpot game has ended) in the jackpot control timer (step S449), and the special symbol process flag is set. The value is updated to a value corresponding to the big hit end process (step S307) (step S450).

  When the data indicating the big hit type is not the data indicating the probability variation big hit but the data indicating the sudden probability variation big hit, the CPU 56 performs control to transmit a sudden end specification command to the effect control microcomputer 100 (step S443). S444). It is to be noted that, in step S443, whether or not there is a sudden probability variation big hit is, specifically, the value indicating the big hit type set in the big hit type buffer in the RAM 55 in step S74 is a value (in this example, “03”). This can be determined by checking whether or not. When the data indicating the big hit type is not suddenly the data indicating the probable change big hit, control for transmitting the big hit end 1 designation command to the microcomputer 100 for effect control is performed (step S445). Then, control goes to a step S449.

  FIG. 62 is a flowchart showing the jackpot end process (step S307) in the special symbol process. In the jackpot end process, the CPU 56 checks whether or not the jackpot end display timer is set (step S150). If the jackpot end display timer is set, the process proceeds to step S154. If the jackpot end display timer is not set, the jackpot flag is reset (step S151), and control for transmitting a jackpot end designation command is performed (step S152). Here, if it is a probable big hit, a jackpot end 2 designation command is transmitted, if it is suddenly a probable big hit, an abrupt end designation command is transmitted, and if it is none, a jackpot end 1 designation command is transmitted. To do. Then, a value corresponding to the display time corresponding to the time during which the big hit end display is being performed in the image display device 9 (the big hit end display time) is set in the big hit end display timer (step S153), and the processing is ended.

  In step S154, 1 is subtracted from the value of the big hit end display timer. Then, the CPU 56 checks whether or not the value of the jackpot end display timer is 0, that is, whether or not the jackpot end display time has elapsed (step S155). If not, the process ends. If it has elapsed, it is confirmed whether or not the type of jackpot is a probability variation jackpot or a sudden probability variation jackpot (step S158).

  If the big hit type is a probability change big hit or a sudden probability change big hit, the probability change flag is set and the gaming state is shifted to the probability change state (step S161). Then, the process proceeds to step S162. If neither the probability variation big hit nor the sudden probability variation big hit is found, the time reduction flag is set (step S162), and for example, 100 is set to the time reduction number counter (step S163). Then, the value of the special symbol process flag is updated to a value corresponding to the special symbol normal process (step S300) (step S164).

  In this embodiment, whether it is a probable big hit (including a sudden probable big hit) or a normal big hit, the time reduction state is continued until the end of the fluctuation display 100 times after the big hit ends, and the fluctuation display is performed 100 times. In the case where the time saving state is ended when the time is finished, the time saving state may be continued until the next big hit, without being limited by the variable display count when the probability variation big hit is reached.

  Next, the operation of the effect control means will be described. FIG. 63 is a flowchart showing main processing executed by the effect control microcomputer 100 (specifically, the effect control CPU 101) as effect control means mounted on the effect control board 80. The effect control CPU 101 starts executing the main process when the power is turned on. In the main processing, first, initialization processing is performed for clearing the RAM area, setting various initial values, and initializing a timer for determining the activation control activation interval (for example, 2 ms) (step S701). . Thereafter, the effect control CPU 101 proceeds to a loop process for monitoring a timer interrupt flag (step S702). When a timer interrupt occurs, the effect control CPU 101 sets a timer interrupt flag in the timer interrupt process. If the timer interrupt flag is set in the main process, the effect control CPU 101 clears the flag (step S703) and executes the effect control process of steps S704 to S709.

  In the effect control process, the effect control CPU 101 first analyzes the received effect control command and performs a process of setting a flag according to the received effect control command (command analysis process: step S704). Next, the effect control CPU 101 performs effect control process processing (step S705). In the effect control process, the process corresponding to the current control state (effect control process flag) is selected from the processes corresponding to the control state, and display control of the effect display device 9 is executed.

  Next, a first decorative symbol display control process is performed (step S706). In the first decorative symbol display control process, display control of the first decorative symbol display 9a is executed. Further, a second decorative symbol display control process is performed (step S707). In the second decorative symbol display control process, display control of the second decorative symbol display 9b is executed. Further, a hold storage display control process for controlling the display state of the combined hold storage display unit 18c is executed (step S708). Furthermore, a random number update process for updating a count value of a counter for generating a random number used for determining a production mode or the like is executed (step S709). Thereafter, the process proceeds to step S702. As in the special symbol process executed by the game control microcomputer 560, the first ornament symbol display control process and the second ornament symbol display control process are made common, that is, realized by one program module. Thus, the capacity of the program executed by the production control microcomputer 100 may be reduced.

  64 and 65 are flowcharts showing a specific example of the command analysis process (step S704). The effect control command received from the main board 31 is stored in the reception command buffer, but in the command analysis process, the effect control CPU 101 confirms the content of the command stored in the command reception buffer.

  In the command analysis process, the effect control CPU 101 first checks whether or not a reception command is stored in a command reception buffer formed in the RAM (step S611). Whether it is stored or not is determined by comparing the value of the command reception number counter with the read pointer. The case where both match is the case where the received command is not stored. When the reception command is stored in the command reception buffer, the effect control CPU 101 reads the reception command from the command reception buffer (step S612). When read, the value of the read pointer is incremented by +2 (step S613). The reason for +2 is that 2 bytes (1 command) are read at a time.

  As the command reception buffer, for example, a command reception buffer in a ring buffer format capable of storing six 2-byte effect control commands is used. Therefore, the command reception buffer is configured by a 12-byte area of reception command buffers 1 to 12. A command reception number counter indicating in which area the received command is stored is used. The command reception number counter takes a value from 0 to 11. The ring buffer format is not necessarily required.

  The effect control command transmitted from the game control microcomputer 560 is received by an interrupt process based on the effect control INT signal and stored in the command reception buffer. In the command analysis process, it is analyzed which command (see FIG. 32) the effect control command stored in the buffer area is.

  If the received effect control command is a variation pattern command (step S614), the effect control CPU 101 stores the variation pattern command in a variation pattern command storage area formed in the RAM (step S615). Then, a variation pattern command reception flag is set (step S616).

  If the received effect control command is a display result specifying command (step S617), the effect control CPU 101 forms the display result specifying command (one of display result 1 specifying command to display result 4 specifying command) in the RAM. The displayed display result specifying command storage area is stored (step S618).

  If the received effect control command is a symbol confirmation designation command (step S621), the effect control CPU 101 sets a confirmed command reception flag (step S622).

  If the received effect control command is a jackpot start 1 designation command or a jackpot start 2 designation command (step S623), the effect control CPU 101 sets a jackpot start 1 designation command reception flag or a jackpot start 2 designation command reception flag ( Step S624). If the received effect control command is a surprise start designation command (step S625), the effect control CPU 101 sets a surprise start designation command reception flag (step S626).

  If the received effect control command is the first symbol variation designation command (step S627), the first symbol variation designation command reception flag is set (step S628). If the received effect control command is the second symbol variation designation command (step S629), the second symbol variation designation command reception flag is set (step S630).

  If the received effect control command is a power-on specification command (initialization specification command) (step S631), the effect control CPU 101 displays an initial screen on the effect display device 9 indicating that the initialization process has been executed. Control is performed (step S632). The initial screen includes an initial display of predetermined production symbols.

  If the received effect control command is a power failure recovery designation command (step S633), a predetermined power failure recovery screen (screen for displaying information notifying the player that the gaming state is continuing) is displayed. Display control is performed (step S634).

  If the received effect control command is a jackpot end 1 designation command or a jackpot end 2 designation command (step S641), the effect control CPU 101 sets a jackpot end 1 designation command reception flag or a jackpot end 2 designation command reception flag ( Step S642). If the received effect control command is a surprise end designation command (step S643), the effect control CPU 101 sets a sudden end specification command reception flag (step S644).

  If the received effect control command is a special winning opening open designation command (step S645), the effect control CPU 101 sets a special winning opening open flag (step S646). Further, if the received effect control command is a designation command after opening the big prize opening (step S647), the production control CPU 101 sets a flag after opening the big prize opening (step S648).

  If the received effect control command is a random number abnormality designation command (step S649), the effect control CPU 101 determines a predetermined random number circuit abnormality notification screen (information notifying that an abnormality has occurred in the random number circuit 5003). Is displayed (step S650). For example, the effect control CPU 101 controls the effect display device 9 to display a character string such as “Random number circuit is abnormal”.

  If the received effect control command is another command, the effect control CPU 101 sets a flag corresponding to the received effect control command (step S651). Then, control goes to a step S611.

  FIG. 66 is an explanatory diagram showing random numbers used by the effect control microcomputer 100. As shown in FIG. 66, in this embodiment, the production control microcomputer 100 uses random numbers SR1-1 to SR1-3 for determining the first to third final stop symbols. In addition, in order to enhance the effect, a random number other than these (for example, a random number for determining a temporary stop symbol when performing a sliding effect or a pseudo-ream) may be used.

  In step S709 of the effect control main process shown in FIG. 63, the effect control microcomputer 100 counts a counter for generating random numbers SR1-1 to SR1-3 for determining the first to third final stop symbols. Up (add 1). For example, a final stop symbol determination counter for counting each final stop symbol determination random number (specifically, a first final stop symbol determination counter, a second final stop symbol determination counter, and a third final stop symbol determination) A process of counting up (adding the obtained random number addition value) is performed.

  FIG. 67 is a flowchart showing the effect control process (step S705) in the main process shown in FIG. In the effect control process, the effect control CPU 101 performs one of steps S800 to S807 according to the value of the effect control process flag. In each process, the following process is executed.

  Fluctuation pattern command reception waiting process (step S800): It is confirmed whether or not a variation pattern command has been received from the game control microcomputer 560. Specifically, it is confirmed whether or not the variation pattern command reception flag set in the command analysis process is set. If the change pattern command has been received, the value of the effect control process flag is changed to a value corresponding to the effect symbol change start process (step S801).

  Effect design variation start processing (step S801): Using the random SR1-1 to SR1-3, an effect mode such as determining the final stop symbol to be displayed on the effect display device 9 is determined, and the effect design and the decoration design change Control to be started. Then, the value of the effect control process flag is updated to a value corresponding to the effect symbol changing process (step S802).

  Production symbol variation processing (step S802): Controls the switching timing of each variation state (variation speed) constituting the variation pattern and monitors the end of the variation time. When the variation time ends, the value of the effect control process flag is updated to a value corresponding to the effect symbol variation stop process (step S803).

  Production symbol variation stop processing (step S803): Based on the reception of the production control command (design confirmation designation command) for instructing all symbols to stop, the variation of the production symbol (and decoration symbols) is stopped and the display result (stop symbol) ) Is derived and displayed. Then, the value of the effect control process flag is updated to a value corresponding to the jackpot display process (step S804) or the variation pattern command reception waiting process (step S800).

  Big hit display process (step S804): After the end of the variation time, control is performed to display a screen for notifying the effect display device 9 of the occurrence of the big hit. Then, the value of the effect control process flag is updated to a value corresponding to the in-round processing (step S805).

  In-round processing (step S805): Display control during round is performed. In addition, in a gaming machine that executes a so-called probability change promotion effect, a probability change promotion effect is executed when the flag of the probability change promotion effect execution flag indicating execution of the probability change promotion effect is set. If the round end condition is satisfied, if the final round has not ended, the value of the effect control process flag is updated to a value corresponding to the post-round processing (step S806). If the final round has ended, the value of the effect control process flag is updated to a value corresponding to the jackpot end process (step S807).

  Post-round processing (step S806): Display control between rounds is performed. When the round start condition is satisfied, the value of the effect control process flag is updated to a value corresponding to the in-round process (step S805).

  Big hit end process (step S807): In the effect display device 9, display control is performed to notify the player that the big hit gaming state has ended. Then, the value of the effect control process flag is updated to a value corresponding to the variation pattern command reception waiting process (step S800).

  FIG. 68 is a flowchart showing the random number update process (step S709) in the main process shown in FIG. In the random number update process, the effect control CPU 101 reads a hardware random number (random R) from the random number circuit 107 installed in the effect control microcomputer 100 (step S900). Next, the effect control CPU 101 determines a random number addition value used for updating each effect determination random number (specifically, SR1-1 to SR1-3 shown in FIG. 66) based on the read random number value ( Step S901). In this embodiment, as shown in FIG. 69, one of values 1 to 7 is determined as the random number addition value in accordance with the read hardware random number value. Then, the effect control CPU 101 updates each effect determination random number (specifically, SR1-1 to SR1-3 shown in FIG. 66) by adding the determined random number addition value (step S902). In this case, the production control CPU 101, for example, each final stop symbol determination counter (specifically, a first final stop symbol determination counter, a second final stop symbol determination counter, and a third final stop symbol determination counter). The calculated random number addition value is added to the counter). As described above, in this embodiment, the added value determined based on the random value generated by the random number circuit 107 is used as each effect determining random number (specifically, SR1-1 to SR1-3 shown in FIG. 66). Each effect determination random number is updated. Therefore, the value of each effect determination random number can be updated at random, and the situation in which the determined effect content is biased can be prevented.

  In this embodiment, the case where a common random number addition value is added to each effect determination random number (specifically, SR1-1 to SR1-3 shown in FIG. 66) is shown. The random number addition value is calculated separately for each random number for use, and the random number addition value calculated separately is used for each effect determination random number (specifically, SR1-1 to SR1-3 shown in FIG. 66). You may make it add to. In this case, for example, a random number addition value determination table (see FIG. 69) is provided for each effect determination random number, and the distribution of random number values to the random number addition value differs for each random number addition value determination table. You may make it comprise. Then, a random number addition value may be calculated using a random number addition value determination table for each effect determination random number.

  In addition, the addition value added to each production determination random number (specifically SR1-1 to SR1-3 shown in FIG. 66) can be determined using various methods. For example, when the random number circuit 107 is a hardware random number circuit that generates a 16-bit random number value and it is desired to randomly determine an addition value of 3 bits, a 16-bit random number value generated by the random number circuit 107 It is also possible to obtain an added value of 3 bits by masking the upper 13 bits. For example, when the addition value is determined in the range of 1 (001) to 7 (111) and the 16-bit random value generated by the random number circuit 107 is not within this range, 1 (001) The value of the added value maximum value 7 (111) may be repeatedly added (or subtracted) to the random number value generated by the random number circuit 107 until it falls within a range of ˜7 (111). Then, a value that finally falls within the range of 1 (001) to 7 (111) is obtained as an added value, and each effect determination random number (specifically, SR1-1 to SR1-3 shown in FIG. 66). You may make it add to.

  In this embodiment, the effect control microcomputer 100 side obtains a random number addition value based on the hardware random number, and determines a random number (in this example, SR1-1 to SR1-1 shown in FIG. 66). Although the case of updating SR1-3) has been shown, similar processing may be executed on the game control microcomputer 560 side. In this case, for example, the game control microcomputer 560 obtains a random number addition value according to the same processing as step S901 based on the hardware random number read from the random number circuit 5003. Then, the game control microcomputer 560 adds a random number addition value according to the same process as in step S902, thereby determining a variation pattern type determination random number (random 4 shown in FIG. 46) as a random number for determining the effect mode. Alternatively, the random number for determining the variation pattern (random 5 shown in FIG. 46) may be updated. For example, the game control microcomputer 560 obtains a random number addition value by executing the same process as in step S901 in the display random number update process in steps S17 and S26, and executes the same process as in step S902. Thus, the random number addition value is added to the random number for variation pattern type determination (random 4 shown in FIG. 46) and the random number for variation pattern determination (random 5 shown in FIG. 46).

  Further, as described above, the game control microcomputer 560 is configured to update the variation pattern type determination random number (random 4 shown in FIG. 46) and the variation pattern determination random number (random 5 shown in FIG. 46). In this case, different random number addition values are separately calculated for the variation pattern type determination random number and the variation pattern determination random number, and the random number addition values calculated separately are respectively used for the variation pattern type determination random number and the variation pattern determination. You may make it add to a random number. In this case, for example, a random number addition value determination table (see FIG. 69) is provided separately for the variation pattern type determination random number and the variation pattern determination random number, and the random number addition value is determined for each random number addition value determination table. You may make it comprise so that distribution of the random value with respect to may differ. The random number addition values may be calculated using different random number addition value determination tables for the variation pattern type determination random number and the variation pattern determination random number.

  As described above, according to this embodiment, the counter (the counter included in the random number circuit 5003) for generating the big hit determination random number (MR1) used for determining whether or not to shift to the big hit gaming state. 521. Update the value of the big hit determination calculation counter, which is a software counter. Further, the game control microcomputer 560 determines whether or not to shift to the jackpot gaming state based on the jackpot determination random number (MR1) generated using the updated counter value. The gaming machine also includes a game start switch 90 that outputs a game start instruction signal in response to an instruction operation for starting game control. Then, after the stored contents of the RAM 55 are initialized by the initialization process, the update of the counter value is started on condition that a game start instruction signal is output from the game start switch 90. Therefore, the update start timing of the counter value for generating the big hit determination random number (MR1) can be made different according to the operation timing of the game start switch 90, and the timing for determining to shift to the big hit gaming state is predicted. Can be difficult. Therefore, by forcibly initializing the backup RAM using an external connection board, etc., a signal is input from the external connection board (hanging board) at the timing when it is determined that the initialization RAM is to be shifted to the big hit gaming state. By doing so, it is possible to prevent the big hit from being aimed.

  Further, according to this embodiment, the game control board (main board) 31 is stored in the storage case 200 fixed irreversibly (fixed by the one-wearing screw 280). Further, the clear switch 921 is mounted on the power supply board 910, and the game start switch 90 is mounted on the game control board (main board) 31. Therefore, if the storage case 200 fixed irreversibly is not opened, it is possible to prevent the game start switch 90 from being crafted and to prevent an illegal act on the game start switch 90.

  The clear switch 921 is mounted on the game control board (main board) 31 without providing the game start switch 90, and the clear switch 921 mounted on the game control board 31 is also used as a game start switch. May be.

  FIG. 70 is a block diagram showing an example of a circuit configuration of the main board (game control board) 31 when both the clear switch and the game start switch are used. As shown in FIG. 70, a clear switch 921 may be mounted on the main board 31 instead of the game start switch 90.

  FIG. 71 is a flowchart showing a main process when the clear switch and the game start switch are used together. 71, the processes in steps S1 to S13 and S14 to S19 are the same as those shown in FIGS. 37 and 38.

  When the initialization designation command is transmitted (see step S13), the CPU 56 checks whether or not the clear switch 921 is on (step S44A). If it is in the off state (N in step S44A), the CPU 56 confirms again whether or not the clear switch 921 is in the on state after a delay time of a predetermined time (for example, 0.1 second) (step S45A). (Step S46A). If it is in the on state (Y in step S46A), the process returns to step S44A, and the processes in steps S44A to S46A are repeated.

  As described above, by executing the processing of steps S44A to S46A, after executing the initialization processing of steps S10 to S13, the clear switch 921 is once in an OFF state for a predetermined time (for example, 0.1 second) or longer. After confirming that, the process proceeds to the next step S47A and subsequent steps.

  In step S45A, a process of adding or subtracting the value of a predetermined counter is performed, and the process proceeds to step S47A and subsequent steps on condition that the value of the counter becomes a predetermined value in step S46A. Good.

  If the clear switch 921 is off in step S46A (N in step S46A), the CPU 56 thereafter detects the on state of the clear switch 921 (Y in step S47A), for a predetermined time (for example, 0.1 second). (Step S48A), it is checked again whether or not the clear switch 921 is in the ON state (step S49A). If it is an off state (N of step S49A), it will return to step S47A and will repeat the process of step S47A-S49A. If the clear switch 921 is on (Y in step S49A), the process proceeds to the next step S14.

  As described above, by executing the processing of steps S47A to S49A, after executing the initialization processing of steps S10 to S13, the clear switch 921 that is also used as a game start switch is turned on. The process proceeds to step S14 and subsequent steps. Specifically, on condition that the clear switch 921 is turned on, the random number circuit 5003 is activated in the random number circuit setting process in step S14, and the update of the hardware random number is started. In addition, the determination random number update process in step S24 of the timer interrupt process is started, and the update of the software random number is started.

  In step S48A, a process of adding or subtracting a value of a predetermined counter is performed, and the process proceeds to step S14 and subsequent steps on condition that the value of the counter becomes a predetermined value in step S49A. Good.

  As described above, in the modification shown in FIGS. 70 and 71, the characteristic configuration of the gaming machine shown below is shown.

  The gaming machine includes a game control board (for example, the game control board 31) equipped with a microcomputer (for example, a game control microcomputer 560) that controls the progress of the game, and the game control board is fixed irreversibly. The initialization operation means is mounted on the game control board (for example, as shown in FIG. 70, for example, as shown in FIG. 70). Is mounted on the game control board 31), and the counter updating means is provided that the game start instruction signal is output from the initialization operation means after the initialization processing means initializes the storage contents of the data storage means. (E.g., the game control microcomputer 560 implements steps S44A to S49A). After determining “Y” in step S49A, the random number circuit 5003 is activated in the random number circuit setting process in step S14 to start updating the hardware random number, and the determination random number update process in step S24 of the timer interrupt process is started. Then, update of the software random number may be started). With such a configuration, it is possible to eliminate the need to provide a game start operation means separately from the initialization operation means by using both the initialization operation means and the game start operation means. It is possible to reduce the cost for configuring to prevent the act of shifting to.

  In the modification shown in FIGS. 70 and 71, the switch (clear switch 921 in FIG. 70) that serves both as the clear switch and the game start switch is provided on the main board (game control board) 31; It may be provided on the substrate 910. In steps S44A, S46A, S47A, and S49A of the main process shown in FIG. 71, the CPU 56 receives an ON signal from a clear switch 921 (a switch that serves both as a clear switch and a game start switch) provided on the power supply board 910. You may make it determine whether it input.

  Further, according to this embodiment, a counter (for example, a jackpot determination calculation counter) for counting each software random number is stored in the software random number counter storage area (see FIG. 30) in the RAM area. Then, based on the fact that the clear signal is output from the clear switch 921, the game control microcomputer 560 has a work area (work area) out of the contents stored in the RAM area other than the software random number counter storage area. The stored contents stored in other areas are initialized. In this case, the game control microcomputer 560 performs control so as not to initialize the storage contents stored in the software random number counter storage area. For this reason, even if the stored contents of the RAM area are initialized in the initialization process, it is difficult to predict the timing for determining the transition to the big hit gaming state by preventing the software random number counter value from being initialized. can do. Therefore, it is possible to further improve the effect of preventing a big hit from being targeted by inputting a signal from the external connection board (hanging board) at a timing at which it is determined to shift to the big hit gaming state after initialization. Can do.

  Further, according to this embodiment, the game control microcomputer 560 generates the jackpot determination random number MR1 when the start condition is satisfied. Then, it is determined whether or not to shift to the jackpot gaming state by comparing the generated jackpot determination random number MR1 with a predetermined determination value. In this case, the game control microcomputer 560, when the determination numerical value generation condition is satisfied, the random R output from the counter 521 of the random number circuit 5003 and the big hit determination calculation random number (random) updated by the big hit determination calculation counter. 2-1) is added. Next, the added value is divided by the number of numerical values within a predetermined numerical range (65536 (corresponding to the total number of numerical values of 0 to 65535, in other words, equivalent to 65535 + 1)), and the remainder resulting from the division is a big hit The determination random number MR1 is used. Therefore, even if the counter 521 that outputs the random R is fraudulent, the jackpot determination random number MR1 is also updated according to at least the update of the jackpot determination calculation random number (random 2-1) updated by the jackpot determination calculation counter. Can be updated. Therefore, it is possible to further improve the effect of preventing a big hit from being targeted by inputting a signal from the external connection board (hanging board) at a timing at which it is determined to shift to the big hit gaming state after initialization. Can do.

  In addition, according to this embodiment, a plurality of random value storage circuits (latch circuits) 531 corresponding to each of a plurality of start conditions and a corresponding random number value storage circuit (latch) based on the establishment of the start conditions. Circuit) 531 and a plurality of start port switches 13a and 14a as latch signal output means for outputting a latch signal. Further, based on the big hit determination random number MR1 generated using the count value input from the counter 521 via the random value storage circuit (latch circuit) 531, it is determined whether or not to shift to the big hit gaming state. Therefore, even if the gaming machine includes a plurality of start winning ports 13 and 14, an accurate count value can be acquired using only one counter 521. Therefore, even if the gaming machine is provided with a plurality of start winning openings 13, 14, predetermined game control can be executed without increasing the cost. Further, even when the game ball wins with a slight time difference between the start winning opening 13 and the starting winning opening 14, the count value is latched in separate latch circuits, so that the random number value can be reliably extracted. it can.

  Further, according to this embodiment, the game control microcomputer 560 stores the numerical value output from the counter 521 as a stored numerical value in the previous random number circuit read value storage area. Further, when the determination numerical value generation condition is satisfied, the numerical value output from the counter 521 is compared with the stored numerical value stored in the previous random number circuit read value storage area to determine whether or not they match. Then, an abnormality notification is performed when it is determined that they coincide with each other a predetermined number of times. In this case, the game control microcomputer 560 stores the count value output last time by the counter 521 as the stored value when the determination numerical value generation condition is satisfied. Therefore, it can be determined that an abnormality has occurred when the counter 521 is fraudulent, and the external connection board (hanging board) is determined at the timing when it is determined that the counter 521 is shifted to the big hit gaming state after initialization. The effect of preventing the big hit from being targeted can be further improved by inputting a signal from.

  Further, according to this embodiment, the frequency of the pulse signal output from the clock circuit 5001 and the operating frequency of the game control microcomputer 560 are configured to be different. Therefore, the update cycle of the count value can be prevented from being recognized from the outside of the game control microcomputer 560, and the external connection board is determined at the timing when it is determined to shift to the big hit gaming state after initialization. By inputting a signal from the (hanging board), it is possible to further improve the effect of preventing the big hit from being targeted.

  In addition, according to this embodiment, the production control microcomputer 100 stores each final stop symbol for storing each production determination random number (specifically, SR1-1 to SR1-3 shown in FIG. 66). A determination counter (specifically, a first final stop symbol determination counter, a second final stop symbol determination counter, and a third final stop symbol determination counter) is provided. Further, the production control microcomputer 100 reads a random number value from the random number circuit 107 and determines a random number addition value based on the read random number value. Further, the determined random number addition value is added to the effect determination random number stored in each final stop symbol determination counter. And when a predetermined effect mode determination condition is established, by reading the effect determination random number stored in each final stop symbol determination counter, by comparing the read effect determination random number with a predetermined determination value, An effect mode (for example, a final stop symbol) in the gaming machine is determined. Therefore, the random number for effect determination can be updated at random, and a situation in which the determined effect aspect is biased can be prevented.

  Further, according to this embodiment, the game control microcomputer 560 extracts a count value from each random value storage circuit (latch circuit) 531 by outputting a latch signal to the random number circuit 5003. Further, based on the extracted count value, it is determined whether or not an abnormality has occurred in the random number circuit 5003 by determining whether or not the count value is updated normally by the counter 521. Therefore, it can be easily found that the random number circuit 5003 has been cheated. For example, it is possible to easily find a fraudulent act in which some of the bit terminals are short-circuited in the random number circuit 5003 or the random number circuit 5003 is illegally exchanged. For example, considering the cycle of reading the count value from the random value storage circuit (latch circuit) 531 and the cycle of updating the count value of the random number circuit 5003, based on the count value read last time from the random value storage circuit 531, It is possible to obtain the predicted value of the updated count value read this time from the random value storage circuit 531. In this case, the predicted value of the updated value predicted from the previously read count value from the random value storage circuit (latch circuit) 531 is compared with the updated value actually read from the random value storage circuit (latch circuit) 531. It is also possible to determine whether or not an abnormality has occurred in the random number circuit 5003, but whether or not an abnormality has occurred in the random number circuit 5003 more accurately than in the case of using such a method. Can be determined.

  Further, according to this embodiment, the game control microcomputer 560 determines the variation pattern type of the effect symbol as one of a plurality of types using the random number for variation pattern type determination. Further, the game control microcomputer 560 determines a variation pattern of the effect symbol using a variation pattern determination random number from among the variation patterns included in the determined variation pattern type. Therefore, the variation pattern type can be determined using a common random number for determining the variation pattern type, the design change of the variation pattern determination can be facilitated, and the data capacity for determining the variation pattern (determining the variation pattern) The data capacity of the work area) can be reduced.

  Further, according to this embodiment, the game control microcomputer 560 displays the first special symbol on the first special symbol display unit 8a and the second special symbol on the second special symbol display unit 8b. Are executed using a common processing routine. Therefore, it is possible to reduce the data capacity for executing variable display of two special symbols (data capacity of a work area for executing variable display of two special symbols).

  In this embodiment, a game machine provided with two special symbol displays (first special symbol display 8a and second special symbol display 8b) as a variable display unit is taken as an example, but one special symbol is displayed. The present invention can also be applied to a gaming machine provided with a display.

  In this embodiment, the production control board 80, the audio output board 70, and the lamp driver board 35 are provided as the boards on which the circuit for controlling the production apparatus is mounted. It may be mounted on one substrate. Further, a first effect control board (display control board) on which a circuit for controlling the effect display device 9 and the like is mounted and a circuit for controlling other effect devices (lamps, LEDs, speakers 27, etc.) are mounted. You may make it provide two board | substrates with two production | presentation control boards.

  In this embodiment, the game control microcomputer 560 directly transmits a command to the effect control microcomputer 100. However, the game control microcomputer 560 is not connected to another board (for example, FIG. 4). The audio output board 70, the lamp driver board 35, or the like, or the sound / lamp board having the function of the circuit mounted on the audio output board 70 and the function of the circuit mounted on the lamp driver board 35). The command may be transmitted and transmitted to the effect control microcomputer 100 on the effect control board 80 via another board. In that case, the command may simply pass through another board, or the sound output board 70, the lamp driver board 35, and the sound / lamp board are equipped with control means such as a microcomputer, and the control means receives the command. In response to this, control related to voice control and lamp control is executed, and the received command is changed as it is or, for example, to a simplified command to control the effect display device 9. You may make it transmit to 100. Even in that case, the effect control microcomputer 100 performs the display control in accordance with the effect control command directly received from the game control microcomputer 560 in the above-described embodiment. Display control can be performed in accordance with commands received from the board 35 or the sound / lamp board.

  Next, the overall configuration of a slot machine (slot machine), which is another example of the gaming machine in each of the embodiments described above, will be described. FIG. 72 is a front view of the slot machine as seen from the front.

  As shown in FIG. 72, in the slot machine 600, a game panel 601 is detachably attached near the center. Further, a variable display device 602 for variably displaying a plurality of types of symbols is provided near the center of the front surface of the game panel 601. In this embodiment, the variable display device 602 has three symbol display areas of “left”, “middle”, and “right”, and the symbol display reels 602a, 602b, and 602c correspond to the symbol display areas, respectively. Is provided.

  Below the game panel 601, an operation table 620 is provided in which various input switches and the like for the player to perform various operations are arranged. On the back side of the operation table 620, a BET switch 621 for betting (putting) coins one by one, and a MAXBET switch 622 for betting coins by the maximum number (three in this example) that can be placed in one game. A settlement switch 623 and a coin insertion slot 624 are provided. Coins inserted into the coin insertion slot 624 are detected by an inserted coin sensor (not shown).

  On the front side of the operation table 620, a start switch 625, a left reel stop switch 626a, a middle reel stop switch 626b, a right reel stop switch 626c, and a coin jam elimination switch 627 are provided. Lamps 628a and 628b are provided on the right and left sides of the operation table 620, respectively. Below the operation table 620, a speaker 630 for outputting sound effects and the like is provided.

  On the upper part of the game panel 601, an image display device (LCD: liquid crystal display device) 640 for notifying a player of a game method, a game state, and the like is provided. For example, when a winning occurs, an image in which a character performs a predetermined action is displayed on the image display device 640 to notify the player that a winning flag described later is set. Two speakers 641L and 641R that emit sound effects are provided on the left and right of the image display device 640.

  The winning combinations generated in the slot machine 600 include a small winning combination, a replay winning, a big bonus winning, and a regular bonus winning. In the slot machine 600, random numbers are extracted at the timing when the start switch 625 is operated, and it is determined whether or not the winning of any winning combination is allowed. The fact that winnings are allowed is said to be “winning internally”. When an internal winning is made, a winning flag indicating that is set in the slot machine 600. In the game with the winning flag set, the reels 602a to 602c are controlled so that the winning combination corresponding to the winning flag can be drawn. On the other hand, in a game in which the winning flag is not set, the reels 602a to 602c are controlled so that no winning is generated. The slot machine 600 may include a start lever instead of the start switch 625, for example. Then, a random number may be extracted at the timing when the start lever is operated, and it may be determined whether or not to allow any of the above winning combinations to be awarded.

  Note that a game start switch is mounted on the game control board (main board) of the slot machine 600, and after executing the initialization process similar to steps S10 to S13 according to the process similar to FIG. 37 and FIG. On the condition that the game start switch 90 is turned on, the process proceeds to the same process as the process after step S14. Specifically, on condition that the game start switch is turned on, the random number circuit is activated by the same process as the random number circuit setting process in step S14, and the update of the hardware random number is started. Further, the same process as the determination random number update process in step S24 of the timer interrupt process is started, and the update of the software random number is started.

Next, an outline of the game provided by the slot machine will be described.
For example, when a multiplier is set by inserting a coin from the coin insertion slot 624 and pressing the BET switch 621 or the MAXBET switch 622, the operation of the start switch 625 becomes effective. When the player operates the start switch 625, the symbol display reels 602a to 602c provided in the variable display device 602 start rotating. In addition, when a regular bonus prize or a big bonus prize is won internally at the timing when the start switch 625 is operated, for example, a screen on which a predetermined character performs a predetermined action is displayed on the image display device 640. Thus, the player or the like is notified that the internal winning is made.

  When a predetermined time elapses after the symbol display reels 602a to 602c start rotating, the operations of the reel stop switches 626a to 626c become effective. In this state, if the player presses one of the reel stop switches 626a to 626c, the rotation of the reel corresponding to the operated stop switch is stopped. Further, when the symbol display reels 602a to 602c are left for a predetermined period or more without being stopped, the symbol display reels 602a to 602c are automatically stopped. Note that the symbol display reels 602a to 602c may not be automatically stopped even when the symbol display reels 602a to 602c are left for a predetermined period or longer without being stopped.

  When all the symbol display reels 602a to 602c are stopped, the symbol display reels 602a to 602c displayed on the variable display device 602 are determined according to the number of symbols in the upper, middle and lower three symbols. Whether or not a prize is won is determined by a combination of symbols positioned on a valid winning line. When the multiplying number is 1, only the middle one horizontal winning line in the variable display device 602 is valid. When the multiplying number is 2, the top three, the middle, and the bottom three pay lines in the variable display device 602 are valid. When the number of multiplications is 3, a total of five pay lines of three horizontal rows and two diagonal diagonal lines in the variable display device 602 are effective lines.

  When a combination of symbols on the active line becomes a specific display mode determined in advance and a winning occurs, a predetermined game effect is made by sound, light, display on the image display device 640, etc., and the winning is generated The game according to is started.

  In the slot machine 600, the effect control means mounted on the slot machine 600 performs display control of the image display device 640 provided in the slot machine 600. The image display device 640 displays various types of information such as a variation display of the effect symbol and a display for notifying the game state and the game method under the control of the effect control means. A variety of information such as a variation display of effect symbols, a display for notifying a game state and a game method, and the like are displayed by a movie image, and display control of the movie image is performed by the image processing device 640. do it.

  Moreover, in embodiment shown above, the characteristic structure of the gaming machine as shown to the following (1)-(9) is also shown.

(1) A specific game that is advantageous to the player based on the fact that the player can play a predetermined game and the result of the game is in a predetermined mode (for example, a jackpot symbol is displayed) A data storage means (for example, RAM 55) that is capable of transitioning to a state (for example, a big hit gaming state), and retains data even when power supply to the gaming machine is stopped by a backup power supply; and the data storage means Initialization operation means (for example, a clear switch 921) that outputs an initialization instruction signal (for example, a detection signal of the clear switch 921) in response to an instruction operation for initializing the stored contents of the On the basis of the output of the initialization instruction signal, initialization processing means for initializing the recording contents of the data storage means (for example, the game control microcomputer 5) And a counter (for example, a random number) for generating a determination random number (for example, jackpot determination random number MR1) used for determining whether or not to shift to a specific gaming state. Counter 521 of circuit 5003. Counter updating means (for example, clock signal output circuit 524 of random number circuit 5003) for updating the value of the big hit determination calculation random number (random 2-1) for counting up. The counter 521 of the random number circuit 5003 updates the count value based on the fact that the random number generation clock signal SI1 has been output, and the count value of the jackpot determination calculation counter is executed by executing step S24 in the game control microcomputer 560. For executing the process of updating the counter)) and counter updating means Based on a random number for determination generated using the updated counter value, gaming state determination means for determining whether or not to shift to a specific gaming state (for example, execute steps S62 and S63 in the gaming control microcomputer 560) And a game start operation means (for example, a game start switch 90) for outputting a game start instruction signal (for example, a detection signal of the game start switch 90) in response to an instruction operation for starting game control. The counter updating means starts updating the counter value on condition that the game start instruction signal is output from the game start operating means after the initialization processing means initializes the stored contents of the data storage means. (For example, the game control microcomputer 560 performs steps S10 to S13 after executing the initialization process. On condition that the game start switch 90 is turned on in S49, the process proceeds to step S14 and subsequent steps. Specifically, on condition that the game start switch 90 is turned on, the random number circuit 5003 is activated in the random number circuit setting process in step S14, and the update of the hardware random number is started. In addition, the determination random number update process in step S24 of the timer interrupt process is started, and the update of the software random number is started. A gaming machine characterized by that.
According to such a configuration, the counter updating means for updating the counter value for generating the determination random number used for determining whether or not to shift to the specific gaming state, and the counter updated by the counter updating means Based on a random number for determination generated using the value, a game state determination means for determining whether or not to shift to a specific game state, and a game start instruction signal according to an instruction operation for starting game control And a counter update means, on condition that a game start instruction signal is output from the game start operation means after the stored contents of the data storage means are initialized by the initialization processing means. Since updating of the counter value is started, updating of the counter value for generating a random number for determination is performed according to the operation timing of the game start operating means. Can be made different timings can be difficult to predict the determined timing to shift to the specific game state. Accordingly, by forcibly initializing the backup RAM using an external connection board or the like, the external connection board (hanging board) is determined at a timing when it is determined to shift to the specific gaming state (big hit gaming state) after the initialization. ) Can be prevented from being targeted by hitting a signal.

(2) The gaming machine includes a power supply board (for example, a power board 910) on which a power supply circuit (for example, a DC-DC converter 913) for supplying power to the gaming machine, and a microcomputer for controlling the progress of the game ( For example, a game control board (for example, main board 31) on which a game control microcomputer 560 is mounted, and the game control board is fixed irreversibly (fixed with a one-way screw 280) ( For example, the initialization operation means is mounted on the power supply board (for example, the clear switch 921 is mounted on the power supply board 910 as shown in FIG. 4), and the game start operation is stored in the storage case 200). The means is mounted on the game control board (for example, the game start switch 90 is mounted on the main board 31 as shown in FIG. 3). It may be.
According to such a configuration, the game control board is stored in the storage case fixed irreversibly, the initialization operation means is mounted on the power supply board, and the game start operation means is mounted on the game control board. Therefore, if the storage case fixed irreversibly is not opened, it is possible to prevent the game start operation means from being crafted, and the illegal action against the game start operation means can be prevented. Can be prevented.

(3) The counter updating means updates the numerical value within a predetermined numerical value range by software to generate software random numbers (for example, the step S24 in the game control microcomputer 560 executes the jackpot determination calculation counter) Whether or not the game state determination means shifts to a specific game state based on a determination random number (for example, a big hit determination random number MR1) generated using a software random number. (For example, the game control microcomputer 560 executes steps S62 and S63 using the jackpot determination random number MR1 generated in step S2015), and the data storage means stores the software random number in the software random number storage area. (For example, the RAM 55 stores the software shown in FIG. The jackpot determination calculation counter for counting the jackpot determination calculation random number (random 2-1) is stored in the random number counter storage area), and the initialization processing means outputs an initialization instruction signal from the initialization operation means The storage contents stored in the storage area other than the software random number storage area among the storage contents of the data storage means are initialized and the storage contents stored in the software random number storage area are not initialized. (For example, the game control microcomputer 560, in step S10, in the work area (working area) of the RAM 55 area, other than the software random number counter storage area, the start address (address 7F00h. FIG. 30). Set the pointer to clear data (eg “0”). Set in the work area in the next RAM 55. By processing in this way, only the data stored in the area from address 7F00h to address 7FFFh (the area other than the software random number counter storage area in the work area) is cleared. The data stored in the area from 7E00h to 7EFFh (software random number counter storage area) is not cleared.
According to such a configuration, the data storage means stores the software random number in the software random number storage area, and the initialization processing means outputs the initialization instruction signal from the initialization operation means. Among the storage contents of the storage means, the storage contents stored in the storage area other than the software random number storage area are initialized, and the storage contents stored in the software random number storage area are controlled not to be initialized. Therefore, even if the stored contents of the data storage means are initialized, it is possible to make it difficult to predict the timing for determining the transition to the specific gaming state by not initializing the software random number value. . Therefore, it is possible to prevent a big hit from being targeted by inputting a signal from the external connection board (hanging board) at a timing when it is determined that the game state is to be shifted to the specific gaming state (big hit gaming state) after initialization. Can be further improved.

(4) The counter updating means increments the count value within a predetermined numerical range (for example, 0 to 65535), and outputs the count value as the first numerical value (for example, random R) (for example, the counter 521). ) And a numerical value creating means (for example, a game) that updates the numerical value within a predetermined numerical range (for example, 0 to 65535) by software to generate a second numerical value (for example, a random number for random determination (random 2-1)) The control microcomputer 560 executes step S24 and counts up the value of the jackpot determination calculation counter), and the start condition is satisfied (for example, the first start winning opening 13 or the second starting winning opening 14). Determination numerical value generating means (for example, a big hit determination random number MR1) when a game ball is won) The game control microcomputer 560 executes step S2015), and the game state determination unit is configured to enter the specific game state by comparing the determination numerical value generated by the determination numerical value generation unit with a predetermined determination value. (For example, the game control microcomputer 560 executes steps S62 and S63 using the jackpot determination random number MR1 generated in step S2015) and the determination numerical value generation means The first numerical value generated by the counter circuit and the numerical value generating means generated when the numerical value generation condition is satisfied (for example, when a game ball has won the first starting winning hole 13 or the second starting winning hole 14). 2 is added, and the added value is divided by the number of numerical values within a predetermined numerical range (for example, 65536). The remainder is used as a numerical value for determination (for example, the game control microcomputer 560 adds random R and random 2-1 as shown in FIG. 52 in step S2015, and further adds 65536 (0 to It is equivalent to the total number of numerical values of 65535, in other words, equivalent to 65535 + 1, and is divided (dividing as an integer), and the remainder (remainder) is a big hit determination random number (random MR1: a random number that is actually compared with the big hit determination value) And may be configured as follows.
According to such a configuration, the data storage means stores the software random number in the software random number storage area, and the initialization processing means outputs the initialization instruction signal from the initialization operation means. Among the storage contents of the storage means, the storage contents stored in the storage area other than the software random number storage area are initialized, and the storage contents stored in the software random number storage area are controlled not to be initialized. Therefore, even if the stored contents of the data storage means are initialized, it is possible to make it difficult to predict the timing for determining the transition to the specific gaming state by not initializing the software random number value. . Therefore, it is possible to prevent a big hit from being targeted by inputting a signal from the external connection board (hanging board) at a timing when it is determined that the game state is to be shifted to the specific gaming state (big hit gaming state) after initialization. Can be further improved.

(5) The counter update means includes a counter circuit (for example, a counter 521) that increments the count value within a predetermined numerical range and outputs the count value, and includes a plurality of start conditions (for example, the first start winning opening 13). Alternatively, a plurality of latch circuits (for example, a first random value storage circuit 531a and a second random value storage circuit 531b) corresponding to each of the start winning prizes in the second start winning opening 14 and the start condition is satisfied. And a plurality of latch signal output means (for example, a first start port switch 13a and a second start port switch 14a) for outputting a latch signal to the corresponding latch circuit. It is determined whether or not to shift to the specific gaming state based on a determination random number generated using the count value input from the counter circuit via the latch circuit (for example, , Game control microcomputer 560 uses the jackpot determining random number MR1 was determined using the random R in step S2015, step S62, S63 to run) it may be configured so.
According to such a configuration, a plurality of latch circuits corresponding to each of a plurality of starting conditions, and a plurality of latch signal outputs for outputting a latch signal to the corresponding latch circuit based on the establishment of the starting conditions And a gaming state determination unit determines whether or not to shift to a specific gaming state based on a determination random number generated using a count value input from a counter circuit via a latch circuit. Since it is comprised, even if it is a case where a game machine is provided with a some starting area | region, an exact count value can be acquired using only one counter circuit. Therefore, even when the gaming machine includes a plurality of start areas, predetermined game control can be executed without increasing the cost.

(6) The counter update means includes a counter circuit (for example, a counter 521) that increments the count value within a predetermined numerical value range and outputs the count value, and stores a numerical value output from the counter circuit as a stored numerical value. The storage means (for example, the part for executing step S2007 in the game control microcomputer 560) and the determination numerical value generation condition are satisfied (for example, the game ball is won in the first start winning opening 13 or the second starting winning opening 14). Numerical value comparison means (for example, in the game control microcomputer 560) that compares the numerical value output from the counter circuit with the stored numerical value stored in the numerical value storage means to determine whether they match. When it is determined that the part that executes step S2009) and the numerical value comparing means match continuously a predetermined number of times, an abnormality notification is made. Anomaly notification means to be performed (for example, a part that executes step S650 in the effect control microcomputer 100 based on the random number abnormality designation command transmitted in step S2013 when the game control microcomputer 560 determines Y in step S2012) The numerical value storage means stores the first numerical value output from the counter circuit as a stored numerical value when the determination numerical value generation condition is satisfied (for example, the game control microcomputer 560 executes step S2007). Then, the value previously read from the random value storage circuit 531 may be saved in the previous random number circuit read value storage area).
According to such a configuration, the numerical value storage unit that stores the numerical value output from the counter circuit as a stored numerical value, the numerical value output from the counter circuit when the determination numerical value generation condition is satisfied, and the numerical value storage unit A numerical value comparing means for comparing the stored numerical values to determine whether or not they match, and an abnormality notifying means for notifying the abnormality when it is determined that the numerical value comparing means has matched continuously a predetermined number of times, Since the numerical value storage means is configured to store the first numerical value output from the counter circuit as a stored numerical value when the determination numerical value generation condition is satisfied, when the counter circuit is illegally operated It can be determined that an abnormality has occurred, and a signal is input from the external connection board (hanging board) at the timing when it is determined that the game will be shifted to the specific gaming state (big hit gaming state) after initialization. It is possible to further improve the effect of preventing the jackpot will be targeted by.

(7) The gaming machine includes a game control microcomputer (for example, a game control microcomputer 560) that performs a game control process for controlling the progress of the game, and a pulse signal supply circuit (for example, a clock circuit 5001) outputs the game machine. The frequency of the pulse signal and the operating frequency of the game control microcomputer are made different (for example, the clock circuit 5001 generates a reference clock signal CLK having a predetermined cycle generated by dividing the system clock signal by 2 ⁷ (= 128). Output to the random number circuit 5003).
According to such a configuration, since the frequency of the pulse signal output from the pulse signal supply circuit and the operation frequency of the game control microcomputer are different, the count value is externally provided from the game control microcomputer. Can be prevented from being recognized, and a signal is input from the external connection board (hanging board) at the timing when it is determined to shift to the specific gaming state (big hit gaming state) after initialization. By doing so, it is possible to further improve the effect of preventing the big hit from being targeted.

(8) The gaming machine is a numerical value (for example, each effect determination random number (specifically, SR1-1 to SR1-3 shown in FIG. 66), or, for example, a variation pattern type determination random number (random 4) or Numerical value storage means (for example, each final stop symbol determination counter (specifically, a first final stop symbol determination counter, a second final stop symbol determination) for storing a random number for determining a variation pattern (random 5). Counter and a third final stop symbol determination counter) or, for example, a variation pattern type determination counter or a variation pattern determination counter), and a random number value is read out from the random number circuit, and based on the read random number value. Adding means for adding the determined added value to the numerical value stored in the numerical value storing means (for example, the step in the microcomputer 100 for effect control). A part that executes S901 and S902, or a part that executes the same processing as steps S901 and S902 in steps S17 and S26 in the game control microcomputer 560, for example, and a predetermined effect mode determination condition is satisfied. Sometimes, the performance mode determining means (for example, the performance control microcomputer 100) determines the performance mode in the gaming machine by reading the numerical value stored in the numerical value storage means and comparing the read numerical value with a predetermined determination value. A portion for determining the final stop symbol to be displayed on the effect display device 9 by using the random SR1-1 to SR1-3 by executing the effect symbol variation start process in step S801 in FIG. (Step for executing steps S102 and S105) It may be configured to include.
According to such a configuration, a numerical value storage means for storing numerical values, a random number value is read from the random number circuit, an addition value is determined based on the read random number value, and the determined addition value is a numerical value storage means An adding means for adding to the numerical value stored in the memory, and when a predetermined effect mode determination condition is satisfied, the numerical value stored in the numerical value storing means is read and the read numerical value is compared with a predetermined determination value Since it is configured to include an effect mode determining means for determining the effect mode in the gaming machine, the numerical value for determining the effect can be randomly updated, and the determined effect mode is biased Can be prevented.

(9) The gaming machine has a game control microcomputer (for example, a game control microcomputer 560) that controls the progress of the game, a random number circuit (for example, a random number circuit 5003) that generates random numbers, and a start condition is established. Based on the detection (for example, the first start port switch 13a or the second start port switch 14a has detected a game ball), a start detection switch (for example, the first start port) outputs a predetermined latch signal to the random number circuit. The random number circuit increments the count value within a predetermined numerical range and outputs the count value, for example, a counter circuit (for example, a counter 521). ) And the latch signal is input, the count value input from the counter circuit is latched to control the game control. Including a latch circuit (for example, a first random value storage circuit 531a and a second random value storage circuit 531b) that outputs to the microcomputer, and the game control microcomputer is configured to have a predetermined Including an initial setting means for executing an initial setting process (for example, a part for executing step S14 in the game control microcomputer 560), and the initial setting means outputs a latch signal to the random number circuit to thereby output a count value from the latch circuit. The count value is extracted by the counter circuit based on the count value extracted by the count value extracting means (for example, the part executing steps S1508 to S1511 in the game control microcomputer 560) and the count value extracting means. To determine whether it is working correctly Ri, abnormality determination means for abnormalities in the random number circuit to determine whether occurring (e.g., portions for performing the steps S1512~S1515 in the gaming control microcomputer 560) and may be configured to include.
According to such a configuration, the initial setting unit outputs the latch signal to the random number circuit, thereby extracting the count value from the latch circuit, and the count value extracted by the count value extracting unit. And an abnormality determining means for determining whether or not an abnormality has occurred in the random number circuit by determining whether or not the count value is normally updated by the counter circuit. Therefore, it is possible to easily find out that the random number circuit has been cheated.

  The present invention is suitable for a gaming machine in which a player can play a predetermined game and can shift to a specific game state that is advantageous to the player based on the result of the game being in a predetermined mode. Applied.

DESCRIPTION OF SYMBOLS 1 Pachinko machine 8a 1st special symbol display 8b 2nd special symbol display 9 Production display device 9a 1st decorative symbol display 9b 2nd decorative symbol display 13 1st start winning port 14 2nd starting winning port 15 Variable Winning ball device 18c Total hold memory display 31 Game control board (main board)
56 CPU
78 Movable member 80 Production control board 85a Upper production LED
85b Medium production LED
85c Lower production LED
90 game start switch 100 effect control microcomputer 101 effect control CPU
107 random number circuit 511 counter circuit 531a first random value storage circuit (first latch circuit)
531b Second random value storage circuit (second latch circuit)
560 Microcomputer for game control 921 Clear switch 5003 Random number circuit

Claims (1)

A gaming machine that allows a player to play a predetermined game, and that can shift to a specific gaming state that is advantageous to the player based on the result of the game being in a predetermined mode,
Data storage means for retaining data even if power supply to the gaming machine is stopped by a backup power supply; and
Initialization operation means for outputting an initialization instruction signal in response to an instruction operation for initializing the storage contents of the data storage means;
Initialization processing means for initializing the recording contents of the data storage means based on the output of the initialization instruction signal from the initialization operation means;
Counter updating means for updating a counter value for generating a random number for determination used for determining whether or not to shift to the specific gaming state;
Gaming state determination means for determining whether to shift to the specific gaming state based on the determination random number generated using the counter value updated by the counter updating means,
The game machine characterized in that the initialization operation means is also used as a game start operation means for outputting a game start instruction signal in response to an instruction operation for starting game control.

Images