JP2013131557A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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JP2013131557A
JP2013131557A JP2011278709A JP2011278709A JP2013131557A JP 2013131557 A JP2013131557 A JP 2013131557A JP 2011278709 A JP2011278709 A JP 2011278709A JP 2011278709 A JP2011278709 A JP 2011278709A JP 2013131557 A JP2013131557 A JP 2013131557A
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substrate
controller
spacer
side electrode
electrode pad
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JP5840479B2 (en
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Takashi Imoto
孝志 井本
Yoshiyasu Ando
善康 安藤
Akira Tanimoto
亮 谷本
Masatsugu Iwamoto
正次 岩本
Masashi Noda
真史 野田
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of equalizing or shortening lengths of a wire connecting between a controller and an external connection terminal and a wire connecting between the controller and a memory chip, and of suppressing warpage of products.SOLUTION: A semiconductor device 50 has: a substrate to which an external connection terminal 12 is formed; a controller 4 mounted on a first surface 2a of the substrate 2; a first spacer 6a arranged on one side of the controller 4 and made of a resin; a second spacer 6b mounted on an opposite side to the first spacer 6a across the controller 4 and made of a resin; a memory chip 8 mounted on the first spacer 6a and the second spacer 6b stretching over the first spacer 6a and the second spacer 6b; and a resin mold part 10 encapsulating a space 18 surrounded by the memory chip 8, the first spacer 6a, the second spacer 6b, and the substrate 2, and the circumference of the memory chip 8.

Description

本発明は、半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

従来、配線層が形成された基板上にコントローラおよびメモリチップを載置した半導体装置が知られている。このような半導体装置では、基板上に載置されたコントローラやメモリチップを覆うように合成樹脂でモールドすることで、半導体装置の外郭を構成する樹脂モールド部が形成される。   Conventionally, a semiconductor device in which a controller and a memory chip are mounted on a substrate on which a wiring layer is formed is known. In such a semiconductor device, a resin mold part that forms the outline of the semiconductor device is formed by molding with a synthetic resin so as to cover the controller and the memory chip mounted on the substrate.

基板に設けられたコントローラと外部接続端子とは、基板に形成された配線層や金属ワイヤを介して電気的に接続される。また、コントローラとメモリチップとは、基板に形成された配線層や金属ワイヤを介して電気的に接続される。   The controller provided on the substrate and the external connection terminal are electrically connected via a wiring layer or a metal wire formed on the substrate. The controller and the memory chip are electrically connected via a wiring layer or a metal wire formed on the substrate.

基板上の中央部であって、基板とメモリチップとの間の空間にコントローラを配置して、配線層や金属ワイヤを含んだ配線の等長化や短縮化を図り、外部接続端子、コントローラ、メモリチップ間で送受信される信号の品質向上が図られる。例えば、基板とメモリチップとの間の空間、すなわちコントローラの周囲には、接着材が充填されて、コントローラの周囲には接着剤層が形成される。このような、半導体装置では、製品の反りを抑えることが望まれている。   In the central part of the board, the controller is arranged in the space between the board and the memory chip, and the wiring including the wiring layer and the metal wire is made equal in length and shortened. The quality of signals transmitted and received between memory chips can be improved. For example, an adhesive is filled in the space between the substrate and the memory chip, that is, around the controller, and an adhesive layer is formed around the controller. In such a semiconductor device, it is desired to suppress product warpage.

米国特許７６２９６９５号US Pat. No. 7,629,695

本発明は、コントローラと外部接続端子を結ぶ配線や、コントローラとメモリチップとを結ぶ配線の等長化や短縮化を図るとともに、製品の反りの抑制を図ることができる半導体装置を提供することを目的とする。   It is an object of the present invention to provide a semiconductor device in which wiring for connecting a controller and external connection terminals, wiring for connecting a controller and a memory chip, and the like can be shortened and warping of a product can be suppressed. Objective.

本願発明の一態様によれば、外部接続端子が形成された基板と、基板の第一面上に載置されたコントローラと、第一面上に載置されて、コントローラの一方側に配置された第１スペーサと、第一面上に載置されて、コントローラを挟んで第１スペーサの反対側に載置された第２スペーサと、第１スペーサと第２スペーサとに跨らせて、第１スペーサと第２スペーサとの上に載置されたメモリチップと、メモリチップ、第１スペーサ、第２スペーサ、および基板に囲まれた空間およびメモリチップの周囲を封止する樹脂モールド部と、を備える半導体装置が提供される。基板の第一面には複数の基板側電極パッドが形成される。コントローラには複数のコントローラ側電極パッドが形成される。メモリチップには複数のチップ側電極パッドが形成される。基板には、基板側電極パッド同士を電気的に接続するパッド間配線層と、基板側電極パッドと外部接続端子とを電気的に接続する端子用配線層とが形成される。第２スペーサは第１スペーサより小さい。コントローラ側電極パッドと基板側電極パッドとが金属ワイヤで接続されることで、コントローラと外部接続端子とが端子用配線層を介して電気的に接続される。コントローラ側電極パッドと基板側電極パッドとが金属ワイヤで接続され、チップ側電極パッドと基板側電極パッドとが金属ワイヤで接続される。これにより、コントローラとメモリチップとがパッド間配線層を介して電気的に接続される。第１スペーサおよび第２スペーサのうちメモリチップが載置される載置面の高さは、コントローラの高さおよびコントローラ側電極パッドに接続される金属ワイヤが通過する高さよりも高い。基板側電極パッドのうち、端子用配線層につながる基板側電極パッドは、基板の第１面における略中央の領域に形成される。コントローラは、平面視において略方形形状を呈しており、コントローラの平面視における一辺に沿って、外部接続端子と電気的に接続されるコントローラ側電極パッドが形成され、平面視において基板の第１面における略中央の領域に一辺が位置するようにコントローラが配置される。空間の開放側から見た空間の断面積のほうが、空間の開放側から見たメモリチップ上に設けられる樹脂モールド部の断面積よりも大きい半導体装置が提供される。   According to one aspect of the present invention, the substrate on which the external connection terminals are formed, the controller placed on the first surface of the substrate, placed on the first surface, and disposed on one side of the controller. The first spacer, the second spacer placed on the first surface, placed on the opposite side of the first spacer across the controller, and straddling the first spacer and the second spacer, A memory chip mounted on the first spacer and the second spacer, a memory chip, the first spacer, the second spacer, and a resin mold part for sealing the space surrounded by the substrate and the periphery of the memory chip; Are provided. A plurality of substrate-side electrode pads are formed on the first surface of the substrate. A plurality of controller-side electrode pads are formed on the controller. A plurality of chip-side electrode pads are formed on the memory chip. An inter-pad wiring layer that electrically connects the substrate-side electrode pads and a terminal wiring layer that electrically connects the substrate-side electrode pads and the external connection terminals are formed on the substrate. The second spacer is smaller than the first spacer. By connecting the controller-side electrode pad and the substrate-side electrode pad with a metal wire, the controller and the external connection terminal are electrically connected via the terminal wiring layer. The controller side electrode pad and the substrate side electrode pad are connected by a metal wire, and the chip side electrode pad and the substrate side electrode pad are connected by a metal wire. As a result, the controller and the memory chip are electrically connected via the inter-pad wiring layer. Of the first spacer and the second spacer, the height of the placement surface on which the memory chip is placed is higher than the height of the controller and the height through which the metal wire connected to the controller-side electrode pad passes. Of the substrate-side electrode pads, the substrate-side electrode pad connected to the terminal wiring layer is formed in a substantially central region on the first surface of the substrate. The controller has a substantially square shape in plan view, and a controller-side electrode pad that is electrically connected to the external connection terminal is formed along one side of the controller in plan view. The first surface of the substrate in plan view The controller is arranged so that one side is located in a substantially central region. A semiconductor device is provided in which the cross-sectional area of the space viewed from the open side of the space is larger than the cross-sectional area of the resin mold portion provided on the memory chip viewed from the open side of the space.

図１は、第１の実施の形態にかかる半導体装置の概略構成を示す正面断面図である。FIG. 1 is a front sectional view showing a schematic configuration of the semiconductor device according to the first embodiment. 図２は、図１に示すＡ−Ａ線に沿った矢視断面図であって、半導体装置の横断面図である。FIG. 2 is a cross-sectional view taken along line AA shown in FIG. 1 and is a cross-sectional view of the semiconductor device. 図３は、図１に示すＢ−Ｂ線に沿った矢視図であって、半導体装置の底面図である。FIG. 3 is a bottom view of the semiconductor device, taken along the line B-B shown in FIG. 1. 図４は、図１に示すＣ−Ｃ線に沿った矢視図であって、樹脂モールド部とメモリチップを省略した半導体装置の平面図である。FIG. 4 is a plan view of the semiconductor device in which the resin mold part and the memory chip are omitted, taken along the line CC in FIG. 図５は、基板、コントローラ、メモリチップを電気的に接続させる配線の概略構成を示すための模式図である。FIG. 5 is a schematic diagram for illustrating a schematic configuration of wiring for electrically connecting the substrate, the controller, and the memory chip. 図６は、第１の実施の形態にかかる半導体装置の製造手順を示すフローチャートである。FIG. 6 is a flowchart showing a manufacturing procedure of the semiconductor device according to the first embodiment.

以下に添付図面を参照して、本発明の実施の形態にかかる半導体装置およびその製造方法を詳細に説明する。なお、この実施の形態により本発明が限定されるものではない。   Exemplary embodiments of a semiconductor device and a method for manufacturing the same will be described below in detail with reference to the accompanying drawings. In addition, this invention is not limited by this embodiment.

（第１の実施の形態）
図１は、第１の実施の形態にかかる半導体装置の概略構成を示す正面断面図である。図２は、図１に示すＡ−Ａ線に沿った矢視断面図であって、半導体装置の横断面図である。図３は、図１に示すＢ−Ｂ線に沿った矢視図であって、半導体装置の底面図である。図４は、図１に示すＣ−Ｃ線に沿った矢視図であって、樹脂モールド部とメモリチップを省略した半導体装置の平面図である。なお、図面の簡単化のために、ハッチングを省略している。 (First embodiment)
FIG. 1 is a front sectional view showing a schematic configuration of the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view taken along line AA shown in FIG. 1 and is a cross-sectional view of the semiconductor device. FIG. 3 is a bottom view of the semiconductor device, taken along the line B-B shown in FIG. 1. FIG. 4 is a plan view of the semiconductor device in which the resin mold part and the memory chip are omitted, taken along the line CC in FIG. Note that hatching is omitted for simplification of the drawing.

半導体装置５０は、基板２、コントローラ４、スペーサ６、メモリチップ８、樹脂モールド部１０を備える。基板２は、例えば絶縁性樹脂基板の内部や表面に配線層を設けたものであり、素子搭載基板と端子形成基板とを兼ねる。このような基板２として、ガラス−エポキシ樹脂やガラス−ＢＴ樹脂（ビスマレイミド・トリアジン樹脂）などを用いたプリント配線板が使用される。基板２は、例えば５０μｍから３００μｍの厚さで形成される。   The semiconductor device 50 includes a substrate 2, a controller 4, a spacer 6, a memory chip 8, and a resin mold part 10. The substrate 2 is, for example, provided with a wiring layer inside or on the surface of an insulating resin substrate, and serves as both an element mounting substrate and a terminal forming substrate. As such a substrate 2, a printed wiring board using glass-epoxy resin, glass-BT resin (bismaleimide / triazine resin) or the like is used. The substrate 2 is formed with a thickness of 50 μm to 300 μm, for example.

図３に示すように、基板２の裏面（第二面）２ｂは、ソルダレジスト（図示せず）で覆われており、ソルダレジストがエッチングされた部分には、導電性のパターンとして、例えば銅箔パターンが形成されている。基板２の裏面２ｂに形成された複数の導電性のパターンが、外部システムとの信号の送受信を可能とする外部接続端子１２となる。本実施の形態では、外部接続端子１２は、基板２の裏面２ｂの略全域にわたって形成されている。   As shown in FIG. 3, the back surface (second surface) 2b of the substrate 2 is covered with a solder resist (not shown), and a conductive pattern is formed on the etched portion of the solder resist, for example, copper. A foil pattern is formed. A plurality of conductive patterns formed on the back surface 2b of the substrate 2 serve as external connection terminals 12 that enable transmission and reception of signals with an external system. In the present embodiment, the external connection terminal 12 is formed over substantially the entire back surface 2 b of the substrate 2.

図４に示すように、基板２の表面（第一面）２ａは、ソルダレジスト（図示せず）で覆われており、ソルダレジストが開口された部分には、導電性のパターンとして、例えば銅箔パターンが形成されている。基板２の表面２ａに形成された複数の導電性のパターンの一部が、基板側電極パッド１４となる。   As shown in FIG. 4, the surface (first surface) 2 a of the substrate 2 is covered with a solder resist (not shown), and a conductive pattern is formed in a portion where the solder resist is opened, for example, copper. A foil pattern is formed. Part of the plurality of conductive patterns formed on the surface 2 a of the substrate 2 becomes the substrate-side electrode pad 14.

コントローラ４は、複数のメモリチップ８から、データの書き込みや読み出しを行うメモリチップ８を選択する。コントローラ４は、選択したメモリチップ８へのデータの書き込みや、選択したメモリチップ８に記憶されたデータの読み出しなどを制御する。コントローラ４は、基板２の表面２ａ上に載置され、熱硬化性樹脂を用いた接着剤９によって基板２に接着される。   The controller 4 selects a memory chip 8 for writing and reading data from the plurality of memory chips 8. The controller 4 controls the writing of data to the selected memory chip 8 and the reading of data stored in the selected memory chip 8. The controller 4 is placed on the surface 2a of the substrate 2 and adhered to the substrate 2 with an adhesive 9 using a thermosetting resin.

コントローラ４の上面には、複数の電極パッド（コントローラ側電極パッド１６）が形成されている。コントローラ４の上面は、平面視において略方形形状を呈している。コントローラ側電極パッド１６は、コントローラ４の上面の４辺に沿って並べて配置されている。コントローラ４の上面の平面視における４辺のうちの１辺（第一辺４ａ）に沿って配置されるコントローラ側電極パッド１６は、後述する端子用配線層を介して外部接続端子１２と接続される電極パッドとなる。コントローラ４は、平面視において第一辺４ａが基板２の表面２ａの略中央と近接する（理想的には略中央となる領域に位置する）ように配置される。   A plurality of electrode pads (controller-side electrode pad 16) are formed on the upper surface of the controller 4. The upper surface of the controller 4 has a substantially square shape in plan view. The controller side electrode pads 16 are arranged side by side along the four sides of the upper surface of the controller 4. The controller-side electrode pad 16 arranged along one side (first side 4a) of the four sides in the plan view of the upper surface of the controller 4 is connected to the external connection terminal 12 via a terminal wiring layer to be described later. Electrode pad. The controller 4 is arranged so that the first side 4a is close to the approximate center of the surface 2a of the substrate 2 in a plan view (ideally located in a region that is approximately the center).

スペーサ６は、基板２と同様に、絶縁性の樹脂材料、例えばガラス−エポキシ樹脂やガラス−ＢＴ樹脂などを用いることができる。スペーサ６は、第１スペーサ６ａと第２スペーサ６ｂとを有する。第１スペーサ６ａと第２スペーサ６ｂとは、基板２の表面２ａ上に載置され、熱硬化性樹脂を用いた接着剤９によって基板２に接着される。なお、接着剤９に絶縁性樹脂を用いる場合には、スペーサ６は絶縁性の樹脂材料の他、導電性の材料や半導体、例えばシリコンウェーハから切り出されたシリコンチップを用いることができる。   As with the substrate 2, an insulating resin material such as glass-epoxy resin or glass-BT resin can be used for the spacer 6. The spacer 6 includes a first spacer 6a and a second spacer 6b. The first spacer 6a and the second spacer 6b are placed on the surface 2a of the substrate 2 and bonded to the substrate 2 with an adhesive 9 using a thermosetting resin. When an insulating resin is used for the adhesive 9, the spacer 6 can be an insulating resin material, a conductive material, or a semiconductor, for example, a silicon chip cut out from a silicon wafer.

第１スペーサ６ａは、コントローラ４の一方側に配置される。第２スペーサ６ｂは、コントローラ４を挟んで第１スペーサ６ａの反対側に配置される。第１スペーサ６ａおよび第２スペーサ６ｂの上面は、メモリチップ８が載置される載置面６ｃとなっている。また、第１スペーサ６ａおよび第２スペーサ６ｂは、基板２の表面２ａ上のうち、コントローラ４の一方側およびその反対側となる領域の全域より少し小さい領域を覆うような大きさで形成されている。第２スペーサ６ｂは、第１スペーサ６ａよりも小さく形成されている。   The first spacer 6 a is disposed on one side of the controller 4. The second spacer 6b is disposed on the opposite side of the first spacer 6a with the controller 4 in between. The upper surfaces of the first spacer 6a and the second spacer 6b serve as a mounting surface 6c on which the memory chip 8 is mounted. Further, the first spacer 6a and the second spacer 6b are formed to have a size so as to cover a region slightly smaller than the entire region of one side of the controller 4 and the opposite side of the surface 2a of the substrate 2. Yes. The second spacer 6b is formed smaller than the first spacer 6a.

メモリチップ８は、ＮＡＮＤ型フラッシュメモリなどの記憶素子である。メモリチップ８は、第１スペーサ６ａと第２スペーサ６ｂとに跨らせて、第１スペーサ６ａと第２スペーサ６ｂの載置面６ｃ上に載置される。メモリチップ８は、複数枚設けられて、第１スペーサ６ａと第２スペーサ６ｂの載置面６ｃ上に積層されている。スペーサ６側の最下層に配置されたメモリチップと、スペーサ６とは、熱硬化性樹脂を用いた接着剤９によって接着される。また、積層されたメモリチップ８同士も、熱硬化性樹脂を用いた接着剤９によって接着される。   The memory chip 8 is a storage element such as a NAND flash memory. The memory chip 8 is placed on the placement surface 6c of the first spacer 6a and the second spacer 6b across the first spacer 6a and the second spacer 6b. A plurality of memory chips 8 are provided and stacked on the mounting surface 6c of the first spacer 6a and the second spacer 6b. The memory chip arranged in the lowermost layer on the spacer 6 side and the spacer 6 are bonded by an adhesive 9 using a thermosetting resin. The stacked memory chips 8 are also bonded to each other with an adhesive 9 using a thermosetting resin.

本実施の形態では、８枚のメモリチップ８が積層された例を示している。図２に示すように、最下層から３枚目までのメモリチップ８は、平面視において一方向にわずかにずらしながら積層される。そして、４〜５枚目までのメモリチップ８は、それまでとは反対の方向にわずかにずらしながら積層さる。また、６〜７枚目までのメモリチップ８は、最下層から３枚目までのメモリチップ８と同じ方向にずらして積層される。また、８枚目のメモリチップ８は、４〜５枚目までのメモリチップ８と同じ方向にずらして積層される。メモリチップ８の上面のうち、メモリチップ８をずらして積層することで露出する部分には、複数の電極パッド（チップ側電極パッド２０）が設けられている。   In the present embodiment, an example in which eight memory chips 8 are stacked is shown. As shown in FIG. 2, the memory chips 8 from the bottom layer to the third are stacked while being slightly shifted in one direction in plan view. Then, the fourth to fifth memory chips 8 are stacked while being slightly shifted in the opposite direction. Further, the sixth to seventh memory chips 8 are stacked while being shifted in the same direction as the third to third memory chips 8. Further, the eighth memory chip 8 is stacked while being shifted in the same direction as the fourth to fifth memory chips 8. A plurality of electrode pads (chip-side electrode pads 20) are provided on a portion of the upper surface of the memory chip 8 that is exposed by shifting and stacking the memory chips 8.

このような構成により、基板２、スペーサ６およびメモリチップ８に囲まれるともに、コントローラ４が配置された空間１８が形成される。この空間１８は、平面視においてコントローラ４から見て第１スペーサ６ａと第２スペーサ６ｂとが配置された方向と略９０度異なる方向に対しては、スペーサ６に塞がれていない開放された状態となっている。   With such a configuration, a space 18 is formed that is surrounded by the substrate 2, the spacer 6, and the memory chip 8 and in which the controller 4 is disposed. This space 18 is opened not covered by the spacer 6 in a direction that is approximately 90 degrees different from the direction in which the first spacer 6a and the second spacer 6b are disposed when viewed from the controller 4 in plan view. It is in a state.

樹脂モールド部１０は、合成樹脂を用いて構成されており、積層されたメモリチップ８の周囲や空間１８を含めて、基板２の表面２ａ側を封止する。樹脂モールド部１０は、半導体装置５０の外郭を構成して、封止されたメモリチップ８やコントローラ４を保護する。   The resin mold portion 10 is configured using a synthetic resin, and seals the surface 2 a side of the substrate 2 including the periphery of the stacked memory chips 8 and the space 18. The resin mold part 10 constitutes an outline of the semiconductor device 50 and protects the sealed memory chip 8 and the controller 4.

図５は、基板２、コントローラ４、メモリチップ８を電気的に接続させる配線の概略構成を示すための模式図である。図５に示すように、基板２には配線層の一部として、外部接続端子１２と基板側電極パッド１４とを電気的に接続する端子用配線層２２と、基板側電極パッド１４同士を電気的に接続するパッド間配線層２４とを有している。   FIG. 5 is a schematic diagram for illustrating a schematic configuration of wiring for electrically connecting the substrate 2, the controller 4, and the memory chip 8. As shown in FIG. 5, as a part of the wiring layer, the substrate 2 is electrically connected to the terminal wiring layer 22 that electrically connects the external connection terminal 12 and the substrate-side electrode pad 14 and the substrate-side electrode pad 14. And an inter-pad wiring layer 24 to be connected to each other.

コントローラ４に設けられたコントローラ側電極パッド１６の一部は、ワイヤボンディングされた金属ワイヤ２６によって、端子用配線層２２の端部に設けられた基板側電極パッド１４と電気的に接続される。これにより、外部接続端子１２とコントローラ４とが電気的に接続される。   A part of the controller-side electrode pad 16 provided in the controller 4 is electrically connected to the substrate-side electrode pad 14 provided at the end of the terminal wiring layer 22 by a wire-bonded metal wire 26. Thereby, the external connection terminal 12 and the controller 4 are electrically connected.

コントローラ４に設けられたコントローラ側電極パッド１６の一部は、ワイヤボンディングされた金属ワイヤ２７によって、パッド間配線層２４の端部に設けられた基板側電極パッド１４と電気的に接続される。また、メモリチップ８に設けられたチップ側電極パッド２０の一部は、ワイヤボンディングされた金属ワイヤ２８によって、パッド間配線層２４の端部に設けられた基板側電極パッド１４のうち、金属ワイヤ２７が接続された基板側電極パッド１４の他端側に設けられた基板側電極パッド１４に電気的に接続される。これにより、コントローラ４とメモリチップ８とが電気的に接続される。   A part of the controller-side electrode pad 16 provided in the controller 4 is electrically connected to the substrate-side electrode pad 14 provided at the end portion of the inter-pad wiring layer 24 by a wire wire-bonded metal wire 27. In addition, a part of the chip side electrode pad 20 provided in the memory chip 8 is a metal wire among the substrate side electrode pads 14 provided at the end of the inter-pad wiring layer 24 by the metal wire 28 bonded by wire bonding. 27 is electrically connected to the substrate-side electrode pad 14 provided on the other end side of the substrate-side electrode pad 14 to which 27 is connected. Thereby, the controller 4 and the memory chip 8 are electrically connected.

なお、図１や図２に示すように、空間１８の高さは、コントローラ４の高さおよびコントローラ４に接続される金属ワイヤ２６，２７が通過する高さよりも高くなっている。すなわち、基板２に載置された際の、第１スペーサ６ａおよび第２スペーサ６ｂの載置面６ｃの高さが、コントローラ４の高さおよびコントローラ４に接続される金属ワイヤ２６，２７が通過する高さよりも高くなるように、第１スペーサ６ａおよび第２スペーサ６ｂの高さが定められている。   As shown in FIGS. 1 and 2, the height of the space 18 is higher than the height of the controller 4 and the height through which the metal wires 26 and 27 connected to the controller 4 pass. That is, the height of the placement surface 6c of the first spacer 6a and the second spacer 6b when placed on the substrate 2 passes through the height of the controller 4 and the metal wires 26 and 27 connected to the controller 4. The height of the first spacer 6a and the second spacer 6b is determined so as to be higher than the height to be performed.

また、空間１８のスペーサ６によって塞がれていない開放側から見た空間１８の断面積が、同様の方向から見たメモリチップ８上に設けられる樹脂モールド部１０の断面積（領域Ｓの断面積）よりも大きくなっている。一般的に、半導体装置５０は、規格などによってその高さＨが定められているため、樹脂モールド部１０の高さを変更するのが難しい場合がある。このような場合には、空間１８の断面積のほうが領域Ｓの断面積よりも大きくなるように、スペーサ６やメモリチップ８の高さが設定される。   In addition, the cross-sectional area of the space 18 viewed from the open side that is not blocked by the spacer 6 of the space 18 is equal to the cross-sectional area of the resin mold portion 10 provided on the memory chip 8 viewed from the same direction (the area S is cut). Area). In general, since the height H of the semiconductor device 50 is determined by standards or the like, it may be difficult to change the height of the resin mold portion 10. In such a case, the height of the spacer 6 and the memory chip 8 is set so that the cross-sectional area of the space 18 is larger than the cross-sectional area of the region S.

次に、半導体装置５０の製造手順について説明する。図６は、第１の実施の形態にかかる半導体装置の製造手順を示すフローチャートである。まず、基板２の表面２ａ上にコントローラ４を載置する（ステップＳ１）。次に、コントローラ４のコントローラ側電極パッド１６と、基板２の基板側電極パッド１４とを金属ワイヤ２６，２７で電気的に接続する（ステップＳ２）。   Next, a manufacturing procedure of the semiconductor device 50 will be described. FIG. 6 is a flowchart showing a manufacturing procedure of the semiconductor device according to the first embodiment. First, the controller 4 is placed on the surface 2a of the substrate 2 (step S1). Next, the controller-side electrode pad 16 of the controller 4 and the substrate-side electrode pad 14 of the substrate 2 are electrically connected by the metal wires 26 and 27 (step S2).

次に、コントローラ４の両側に第１スペーサ６ａと第２スペーサ６ｂとを載置する（ステップＳ３）。次に、第１スペーサ６ａおよび第２スペーサ６ｂの載置面６ｃ上にメモリチップ８を積層し、メモリチップ８のチップ側電極パッド２０と基板２の基板側電極パッド１４とを金属ワイヤ２７で電気的に接続する（ステップＳ４）。   Next, the first spacer 6a and the second spacer 6b are placed on both sides of the controller 4 (step S3). Next, the memory chip 8 is stacked on the mounting surface 6c of the first spacer 6a and the second spacer 6b, and the chip-side electrode pad 20 of the memory chip 8 and the substrate-side electrode pad 14 of the substrate 2 are connected by the metal wire 27. Electrical connection is made (step S4).

そして、基板２の表面２ａ上を金型で覆い、軟化した合成樹脂を金型の中に注入して、注入された合成樹脂を硬化させて樹脂モールド部１０を形成する（ステップＳ５）ことで、半導体装置５０が製造される。   Then, the surface 2a of the substrate 2 is covered with a mold, the softened synthetic resin is injected into the mold, and the injected synthetic resin is cured to form the resin mold portion 10 (step S5). The semiconductor device 50 is manufactured.

以上説明したように、本実施の形態１にかかる半導体装置５０によれば、コントローラ４が基板２の表面２ａの略中央と近接して配置されるので、コントローラ４と外部接続端子１２を結ぶ配線や、コントローラ４とメモリチップ８とを結ぶ配線の等長化や短縮化を図ることができる。   As described above, according to the semiconductor device 50 according to the first embodiment, since the controller 4 is disposed in the vicinity of the approximate center of the surface 2a of the substrate 2, the wiring that connects the controller 4 and the external connection terminal 12 In addition, the wiring connecting the controller 4 and the memory chip 8 can be made equal in length or shortened.

特に、外部接続端子１２に電気的に接続されるコントローラ側電極パッド１６の多くが形成された第一辺４ａが、基板２の表面２ａの略中央となる領域に位置するようにコントローラ４が配置されているので、基板２の裏面２ｂの略全域にわたって形成された外部接続端子１２とコントローラ４との間の配線の等長化が図りやすくなる。この時、コントローラ４が外部接続端子１２を通じて、外部とデータを送受信するための電極パッド１６を、第一辺４ａに配置することが好ましい。コントローラ４に設けられた電極パッド１６のうち、これらが最も等長化や短縮化の効果が高いためである。   In particular, the controller 4 is arranged so that the first side 4a on which many of the controller-side electrode pads 16 that are electrically connected to the external connection terminals 12 are formed is located in a region that is approximately the center of the surface 2a of the substrate 2. Therefore, it is easy to achieve the equal length of the wiring between the external connection terminal 12 and the controller 4 formed over substantially the entire back surface 2b of the substrate 2. At this time, it is preferable that the electrode pad 16 for the controller 4 to transmit / receive data to / from the outside through the external connection terminal 12 is arranged on the first side 4a. This is because, among the electrode pads 16 provided in the controller 4, these are the most effective in lengthening and shortening.

また、スペーサ６にシリコンチップを用いた場合、基板２とメモリチップ８との間となるほとんどの部分は、スペーサ６とコントローラ４で構成される。すると、メモリチップ８の上側となる部分は、樹脂製の樹脂モールド部１０、コントローラ４の下側となる部分は、樹脂製の基板２となる。すなわち、メモリチップ８およびコントローラ４とを上下に挟む領域が、どちらも樹脂材料で構成されるため、半導体装置５０の反りの抑制を図ることができる。   When a silicon chip is used for the spacer 6, most of the portion between the substrate 2 and the memory chip 8 is composed of the spacer 6 and the controller 4. Then, the upper part of the memory chip 8 is the resin mold part 10 made of resin, and the lower part of the controller 4 is the resin substrate 2. That is, since the regions sandwiching the memory chip 8 and the controller 4 in the upper and lower directions are both made of a resin material, warpage of the semiconductor device 50 can be suppressed.

また、第１スペーサ６ａおよび第２スペーサ６ｂが、基板２の表面２ａ上のうち、コントローラ４の一方側およびその反対側となる領域の全域より少し小さい領域を覆うような大きさで形成されているので、メモリチップ８のうち、載置面６ｃによって支持されていない領域をより小さい面積に留めることができる。したがって、上述したステップＳ５での樹脂材料の注入時に、注入圧力などによってメモリチップ８が変形したり割れたりしてしまうのを抑えることができる。   Further, the first spacer 6a and the second spacer 6b are formed to have a size so as to cover a region slightly smaller than the entire region of the one side of the controller 4 and the opposite side of the surface 2a of the substrate 2. Therefore, the area of the memory chip 8 that is not supported by the mounting surface 6c can be kept to a smaller area. Therefore, it is possible to suppress the memory chip 8 from being deformed or cracked due to the injection pressure or the like when the resin material is injected in step S5 described above.

また、空間１８のスペーサ６によって塞がれていない開放側から見た空間１８の断面積が、同様の方向から見たメモリチップ８上に設けられる樹脂モールド部１０の断面積（領域Ｓの断面積）よりも大きくなっているので、上述したステップＳ５での樹脂材料の注入時に、メモリチップ８の上側よりも先に、空間１８に樹脂材料が充填されやすくなる。メモリチップ８の上側よりも先に空間１８に充填された樹脂材料によって、メモリチップ８が支持されることで、メモリチップ８の上側へ注入された樹脂材料からの圧力などによってメモリチップ８が変形したり割れたりしてしまうのを抑えることができる。さらに、メモリチップ８の上側よりも先に空間１８に充填されるので、空気等の巻き込みによるボイド不良を抑制することができる。   In addition, the cross-sectional area of the space 18 viewed from the open side that is not blocked by the spacer 6 of the space 18 is equal to the cross-sectional area of the resin mold portion 10 provided on the memory chip 8 viewed from the same direction (the area S is cut). Therefore, the space 18 is easily filled with the resin material before the upper side of the memory chip 8 when the resin material is injected in step S5 described above. Since the memory chip 8 is supported by the resin material filled in the space 18 before the upper side of the memory chip 8, the memory chip 8 is deformed by the pressure from the resin material injected to the upper side of the memory chip 8. Can be prevented from cracking or cracking. Furthermore, since the space 18 is filled before the upper side of the memory chip 8, void defects due to entrainment of air or the like can be suppressed.

また、空間１８は、平面視においてコントローラ４から見て第１スペーサ６ａと第２スペーサ６ｂとが配置された方向と略９０度異なる方向に対しては、スペーサ６に塞がれていない開放された状態となっているので、この開放部分から空間１８に対して樹脂材料が円滑に注入されやすくなる。なお、本実施の形態では、平面視において方形形状を呈する基板２の長辺側が開放されているが、短辺側が開放されるようにスペーサ６を設けても構わない。ただし、長辺側を開放したほうが、空間１８における合成樹脂の注入流路が短くなるため、より円滑に樹脂が注入されやすくなる。   In addition, the space 18 is not opened by the spacer 6 in a direction that is approximately 90 degrees different from the direction in which the first spacer 6 a and the second spacer 6 b are disposed when viewed from the controller 4 in plan view. Therefore, the resin material can be smoothly injected into the space 18 from the open portion. In the present embodiment, the long side of the substrate 2 having a square shape in plan view is opened, but the spacer 6 may be provided so that the short side is opened. However, since the synthetic resin injection flow path in the space 18 becomes shorter when the long side is opened, the resin can be injected more smoothly.

２ 基板、２ａ 表面（第一面）、２ｂ 裏面（第二面）、４ コントローラ、４ａ 第一辺、６ スペーサ、６ａ 第１スペーサ、６ｂ 第２スペーサ、６ｃ 載置面、８ メモリチップ、９ 接着剤、１０ 樹脂モールド部、１２ 外部接続端子、１４ 基板側電極パッド、１６ コントローラ側電極パッド、１８ 空間、２０ チップ側電極パッド、２２ 端子用配線層、２４ パッド間配線層、２６，２７，２８ 金属ワイヤ、５０ 半導体装置、Ｓ 領域   2 substrate, 2a front surface (first surface), 2b back surface (second surface), 4 controller, 4a first side, 6 spacer, 6a first spacer, 6b second spacer, 6c mounting surface, 8 memory chip, 9 Adhesive, 10 Resin mold part, 12 External connection terminal, 14 Substrate side electrode pad, 16 Controller side electrode pad, 18 space, 20 Chip side electrode pad, 22 Terminal wiring layer, 24 Inter-pad wiring layer, 26, 27, 28 metal wires, 50 semiconductor devices, S region

Claims (6)

外部接続端子が形成された基板と、
前記基板の第一面上に載置されたコントローラと、
前記第一面上に載置されて、前記コントローラの一方側に配置された第１スペーサと、
前記第一面上に載置されて、前記コントローラを挟んで前記第１スペーサの反対側に載置された第２スペーサと、
前記第１スペーサと前記第２スペーサとに跨らせて、前記第１スペーサと前記第２スペーサとの上に載置されたメモリチップと、
前記メモリチップ、前記第１スペーサ、前記第２スペーサ、および前記基板に囲まれた空間および前記メモリチップの周囲を封止する樹脂モールド部と、
前記基板の第一面に形成された複数の基板側電極パッドと、
前記コントローラに形成された複数のコントローラ側電極パッドと、
前記メモリチップに形成された複数のチップ側電極パッドと、
前記基板に形成された前記基板側電極パッド同士を電気的に接続するパッド間配線層と、
前記基板に形成された前記基板側電極パッドと前記外部接続端子とを電気的に接続する端子用配線層と、を備え、
前記第２スペーサは前記第１スペーサより小さく、
前記コントローラ側電極パッドと前記基板側電極パッドとが金属ワイヤで接続されることで、前記コントローラと前記外部接続端子とが前記端子用配線層を介して電気的に接続され、
前記コントローラ側電極パッドと前記基板側電極パッドとが金属ワイヤで接続され、前記チップ側電極パッドと前記基板側電極パッドとが金属ワイヤで接続されることで、前記コントローラと前記メモリチップとが前記パッド間配線層を介して電気的に接続され、
前記第１スペーサおよび前記第２スペーサのうち前記メモリチップが載置される載置面の高さは、前記コントローラの高さおよび前記コントローラ側電極パッドに接続される金属ワイヤが通過する高さよりも高く、
前記基板側電極パッドのうち、前記端子用配線層につながる基板側電極パッドは、前記基板の第１面における略中央の領域に形成され、
前記コントローラは、平面視において略方形形状を呈しており、
前記コントローラの平面視における一辺に沿って、前記外部接続端子と電気的に接続される前記コントローラ側電極パッドが形成され、
平面視において前記基板の第１面における略中央の領域に形成された前記基板側電極パッドと、前記一辺に沿って形成された前記コントローラ側電極パッドとが、前記金属ワイヤを介して電気的に接続され、
前記空間の開放側から見た前記空間の断面積のほうが、前記空間の開放側から見た前記メモリチップ上に設けられる樹脂モールド部の断面積よりも大きい半導体装置。 A substrate on which external connection terminals are formed;
A controller mounted on the first surface of the substrate;
A first spacer placed on the first surface and disposed on one side of the controller;
A second spacer placed on the first surface and placed on the opposite side of the first spacer across the controller;
A memory chip mounted on the first spacer and the second spacer across the first spacer and the second spacer;
A resin mold part for sealing the memory chip, the first spacer, the second spacer, the space surrounded by the substrate and the periphery of the memory chip;
A plurality of substrate-side electrode pads formed on the first surface of the substrate;
A plurality of controller-side electrode pads formed on the controller;
A plurality of chip-side electrode pads formed on the memory chip;
An inter-pad wiring layer that electrically connects the substrate-side electrode pads formed on the substrate;
A terminal wiring layer for electrically connecting the substrate-side electrode pad formed on the substrate and the external connection terminal;
The second spacer is smaller than the first spacer;
By connecting the controller-side electrode pad and the substrate-side electrode pad with a metal wire, the controller and the external connection terminal are electrically connected via the terminal wiring layer,
The controller side electrode pad and the substrate side electrode pad are connected by a metal wire, and the chip side electrode pad and the substrate side electrode pad are connected by a metal wire, so that the controller and the memory chip are Electrically connected via the inter-pad wiring layer,
Of the first spacer and the second spacer, the height of the placement surface on which the memory chip is placed is higher than the height of the controller and the height through which the metal wire connected to the controller-side electrode pad passes. high,
Of the substrate-side electrode pads, the substrate-side electrode pad connected to the terminal wiring layer is formed in a substantially central region on the first surface of the substrate,
The controller has a substantially square shape in plan view,
The controller-side electrode pad that is electrically connected to the external connection terminal is formed along one side in a plan view of the controller,
The substrate-side electrode pad formed in a substantially central region of the first surface of the substrate in plan view and the controller-side electrode pad formed along the one side are electrically connected via the metal wire. Connected,
A semiconductor device in which a cross-sectional area of the space viewed from the open side of the space is larger than a cross-sectional area of a resin mold portion provided on the memory chip viewed from the open side of the space. 外部接続端子が形成された基板と、
前記基板の第一面上に載置されたコントローラと、
前記第一面上に載置されて、前記コントローラの一方側に配置された第１スペーサと、
前記第一面上に載置されて、前記コントローラを挟んで前記第１スペーサの反対側に載置された第２スペーサと、
前記第１スペーサと前記第２スペーサとに跨らせて、前記第１スペーサと前記第２スペーサとの上に載置されたメモリチップと、
前記メモリチップ、前記第１スペーサ、前記第２スペーサ、および前記基板に囲まれた空間および前記メモリチップの周囲を封止する樹脂モールド部と、
前記基板の第一面に形成された複数の基板側電極パッドと、
前記コントローラに形成された複数のコントローラ側電極パッドと、
前記メモリチップに形成された複数のチップ側電極パッドと、
前記基板に形成された前記基板側電極パッド同士を電気的に接続するパッド間配線層と、
前記基板に形成された前記基板側電極パッドと前記外部接続端子とを電気的に接続する端子用配線層と、を備え、
前記コントローラ側電極パッドと前記基板側電極パッドとが金属ワイヤで接続されることで、前記コントローラと前記外部接続端子とが前記端子用配線層を介して電気的に接続され、
前記コントローラ側電極パッドと前記基板側電極パッドとが金属ワイヤで接続され、前記チップ側電極パッドと前記基板側電極パッドとが金属ワイヤで接続されることで、前記コントローラと前記メモリチップとが前記パッド間配線層を介して電気的に接続される半導体装置。 A substrate on which external connection terminals are formed;
A controller mounted on the first surface of the substrate;
A first spacer placed on the first surface and disposed on one side of the controller;
A second spacer placed on the first surface and placed on the opposite side of the first spacer across the controller;
A memory chip mounted on the first spacer and the second spacer across the first spacer and the second spacer;
A resin mold part for sealing the memory chip, the first spacer, the second spacer, the space surrounded by the substrate and the periphery of the memory chip;
A plurality of substrate-side electrode pads formed on the first surface of the substrate;
A plurality of controller-side electrode pads formed on the controller;
A plurality of chip-side electrode pads formed on the memory chip;
An inter-pad wiring layer that electrically connects the substrate-side electrode pads formed on the substrate;
A terminal wiring layer for electrically connecting the substrate-side electrode pad formed on the substrate and the external connection terminal;
By connecting the controller-side electrode pad and the substrate-side electrode pad with a metal wire, the controller and the external connection terminal are electrically connected via the terminal wiring layer,
The controller side electrode pad and the substrate side electrode pad are connected by a metal wire, and the chip side electrode pad and the substrate side electrode pad are connected by a metal wire, so that the controller and the memory chip are A semiconductor device electrically connected through an inter-pad wiring layer. 前記第１スペーサおよび前記第２スペーサのうち前記メモリチップが載置される載置面の高さは、前記コントローラの高さおよび前記コントローラ側電極パッドに接続される金属ワイヤが通過する高さよりも高い請求項２に記載の半導体装置。   Of the first spacer and the second spacer, the height of the placement surface on which the memory chip is placed is higher than the height of the controller and the height through which the metal wire connected to the controller-side electrode pad passes. The semiconductor device according to claim 2, which is high. 前記基板側電極パッドのうち、前記端子用配線層につながる基板側電極パッドは、前記基板の第１面における略中央の領域に形成され、
前記コントローラは、平面視において略方形形状を呈しており、
前記コントローラの平面視における一辺に沿って、前記外部接続端子と電気的に接続される前記コントローラ側電極パッドが形成され、
平面視において前記基板の第１面における略中央の領域に形成された前記基板側電極パッドと、前記一辺に沿って形成された前記コントローラ側電極パッドとが、前記金属ワイヤを介して電気的に接続される請求項２または３に記載の半導体装置。 Of the substrate-side electrode pads, the substrate-side electrode pad connected to the terminal wiring layer is formed in a substantially central region on the first surface of the substrate,
The controller has a substantially square shape in plan view,
The controller-side electrode pad that is electrically connected to the external connection terminal is formed along one side in a plan view of the controller,
The substrate-side electrode pad formed in a substantially central region of the first surface of the substrate in plan view and the controller-side electrode pad formed along the one side are electrically connected via the metal wire. The semiconductor device according to claim 2, which is connected. 前記空間の開放側から見た前記空間の断面積のほうが、前記空間の開放側から見た前記メモリチップ上に設けられる樹脂モールド部の断面積よりも大きい請求項２〜４のいずれか１つに記載の半導体装置。   5. The cross-sectional area of the space viewed from the open side of the space is larger than the cross-sectional area of the resin mold portion provided on the memory chip viewed from the open side of the space. A semiconductor device according to 1. 外部接続端子が形成された基板の第一面上にコントローラを載置し、
前記第一面上の、前記コントローラの一方側に第１スペーサを載置し、
前記第一面上の、前記コントローラを挟んで前記第１スペーサの反対側に第２スペーサを載置し、
前記第１スペーサと前記第２スペーサとに跨らせて、前記第１スペーサと前記第２スペーサとの上にメモリチップを載置し、
前記コントローラに形成されたコントローラ側電極パッドと、前記基板の第一面に形成された基板側電極パッドとを金属ワイヤで接続して、前記コントローラと前記外部接続端子とを前記基板側電極パッドと前記外部接続端子とを電気的に接続する端子用配線層を介して電気的に接続し、
前記コントローラ側電極パッドと前記基板側電極パッドとを金属ワイヤで接続するとともに、前記メモリチップに形成されたチップ側電極パッドと前記基板側電極パッドとを金属ワイヤで接続して、前記コントローラと前記メモリチップとを前記基板側電極パッド同士を電気的に接続するパッド間配線層を介して電気的に接続し、
前記メモリチップ、前記第１スペーサ、前記第２スペーサ、および前記基板に囲まれた空間および前記メモリチップの周囲を樹脂モールド部で一括封止する、
半導体装置の製造方法。 The controller is placed on the first surface of the substrate on which the external connection terminals are formed,
Placing a first spacer on one side of the controller on the first surface;
On the first surface, a second spacer is placed on the opposite side of the first spacer across the controller,
A memory chip is placed on the first spacer and the second spacer across the first spacer and the second spacer,
A controller-side electrode pad formed on the controller and a substrate-side electrode pad formed on the first surface of the substrate are connected by a metal wire, and the controller and the external connection terminal are connected to the substrate-side electrode pad. Electrically connected through a terminal wiring layer that electrically connects the external connection terminal,
The controller-side electrode pad and the substrate-side electrode pad are connected with a metal wire, and the chip-side electrode pad formed on the memory chip and the substrate-side electrode pad are connected with a metal wire, and the controller and the Electrically connecting the memory chip via the inter-pad wiring layer that electrically connects the substrate-side electrode pads;
The memory chip, the first spacer, the second spacer, and the space surrounded by the substrate and the periphery of the memory chip are collectively sealed with a resin mold part,
A method for manufacturing a semiconductor device.
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