JP2013120937A - Method and structure for protection against via failure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for forming a decoy via and a functional via.SOLUTION: Provided is a semiconductor device comprising: a first interconnect layer having a plurality of metal portions including a first metal portion; a second interconnect layer having plurality of metal portions including a second metal portion; a third interconnect layer having a plurality of metal portions including a third metal portion; a functional via coupled to the first metal portion and the second metal portion; and a decoy via in a protection region around the functional via, the decoy via coupled to the first metal portion and the third metal portion.

Description

  The present invention relates to vias, and more particularly to vias used to avoid failures.

  In semiconductor devices, tabs often extend laterally from the sides of the conductor. These conductors are often considered buses because they are relatively wide to reduce resistance so that they can propagate relatively high currents without causing problematic voltage drops. For a given technique, the depth of the line at a given metal level is the same, so that the width becomes a variable in determining the resistance per unit length.

  Note that Patent Document 1, which is a prior art document, describes a semiconductor chip interconnection structure.

US Pat. No. 5,439,731

  Increasing bus width reduces resistance, but requires more area and inevitably increases the risk of voids due to stress in the vias. This stress can lead to various failures, including via failures. Although via failures can be unlikely to occur, there are often millions of vias on a given semiconductor device. As a result, the likelihood of at least one via failure occurring is relatively high. Therefore, it is common to provide redundant vias in view of the low likelihood that two vias will fail at the same location. In situations where vias are on the tab, the options for redundant vias are limited. On the other hand, placing the via on the tab provides inherent protection by keeping the via away from a bus that is wider and creates more holes.

  In order to solve the above problem, the invention according to claim 1 is a method of forming a decoy via and a functional via, comprising: a metal portion of a first interconnect layer; and a portion of a second interconnect layer. And a step of forming a functional via in between, and a step of forming a decoy via in a protective region between the metal portion of the first interconnect layer and the metal portion of the third interconnect layer. To do.

The invention according to claim 2 is characterized in that, in the method according to claim 1, the first interconnect layer is on the second interconnect layer.
The invention according to claim 3 is characterized in that, in the method according to claim 1, the first interconnect layer is on the third interconnect layer.

  The invention according to claim 4 is the method according to claim 1, wherein the first interconnect layer is formed by forming a plurality of metal portions in the first dielectric layer, and the second interconnect layer is formed. The connection layer is formed by a step of forming a plurality of metal portions in the second dielectric layer, and the third interconnect layer is formed by a step of forming a plurality of metal portions in the third dielectric layer. This is the gist.

The invention according to claim 5 is characterized in that, in the method according to claim 4, the functional via is formed after the second interconnection layer is formed.
The invention according to claim 6 is the method according to claim 5, wherein the portion of the first interconnect layer is a bus having a tab and the functional via contacts the tab. To do.

A seventh aspect of the invention is characterized in that, in the method of the sixth aspect, the decoy via is aligned adjacent to the functional via.
The invention according to claim 8 is characterized in that, in the method according to claim 7, the plurality of metal portions in the first dielectric layer contains copper.

The invention according to claim 9 is characterized in that, in the method according to claim 7, there is no space available for the redundant via immediately adjacent to the functional via.
The invention according to claim 10 is characterized in that, in the method according to claim 7, there is no space available for the via in the first interconnect layer in the protection region.

  The invention according to claim 11 is a semiconductor device comprising: a first interconnect layer having a plurality of metal portions including a first metal portion; and a plurality of metal portions including a second metal portion. Two interconnect layers; a third interconnect layer having a plurality of metal portions including a third metal portion; a functional via coupled to the first metal portion and the second metal portion; And a decoy via in a protection area around the functional via, the decoy via being coupled to the first metal part and the third metal part.

The invention according to claim 12 is characterized in that, in the semiconductor device according to claim 11, the first interconnect layer is on the second interconnect layer.
The invention according to claim 13 is the semiconductor device according to claim 11, characterized in that the first interconnect layer is on the third interconnect layer.

  The invention according to claim 14 is the semiconductor device according to claim 13, wherein the first metal portion includes a bus having a tab, and the functional via is coupled to the tab.

The gist of the invention described in claim 15 is the semiconductor device according to claim 14, wherein the decoy via is coupled to the tab.
The invention according to claim 16 is the semiconductor device according to claim 15, characterized in that the functional via extends from a bottom surface of the tab, and the decoy via contacts the top surface of the tab.

The invention according to claim 17 is the semiconductor device according to claim 16, wherein the decoy via is aligned adjacent to the functional via.
The invention according to claim 18 is the semiconductor device according to claim 17, wherein there is no space available for a via immediately adjacent to the functional via.

  The invention of claim 19 includes the step of forming a first interconnect layer having a plurality of metal portions including a first metal portion, and a first interlayer dielectric on the first interconnect layer. And forming a second interconnect layer having a plurality of metal portions comprising a second metal portion on the first interlayer dielectric, the second interconnect layer Forming a functional via penetrating the first interlayer dielectric from the second metal portion to the first metal portion during the formation of the first and second interconnect layers on the second interconnect layer; Forming a second interlayer dielectric layer, and forming a third interconnect layer having a plurality of metal portions including a third metal portion on the second interlayer dielectric layer. , During the formation of the third interconnect layer, from the third metal portion to the second metal portion. Comprising forming a decoy via penetrating the interlayer dielectric layer, wherein the decoy via is summarized in that located in the protection area of the functional via.

  According to a twentieth aspect, in the method according to the nineteenth aspect, there is no space available for the via in the second interconnect layer in the protection region in addition to the functional via. The gist.

1 is a top view of a semiconductor device according to one embodiment. FIG. 2 is a cross-sectional view of the semiconductor device of FIG. 1.

  The present invention is illustrated by way of example and is not limited by the accompanying drawings. In the drawings, like reference numbers indicate like elements. Elements in the drawings are shown for simplicity and clarity and have not necessarily been drawn to scale.

  The semiconductor device includes a bus having a tab and has a via that is prone to failure on the tab. The semiconductor device is constructed using a first metal interconnect layer, a second metal interconnect layer, and a third interconnect layer. A failure-prone via is connected between the metal portion that is part of the second interconnect layer and the metal portion that is part of the first interconnect layer. Within the protection region, decoy vias are aligned in close proximity to the fragile via and between the metal portion that is part of the first interconnect layer and the metal portion that is part of the third interconnect layer. Connected. The decoy via is connected at one end to an interconnect layer different from the one to which the faulty via is connected, but these two vias have a common connection with the first interconnect layer portion. Thus, the decoy via provides a hole gettering effect and thus protects a via that is prone to failure when holes are generated from the first interconnect layer. This can be better understood with reference to the drawings and the following description.

  FIG. 1 shows a semiconductor device having a bus 12 with tabs 14 extending laterally from the sides thereof. The width of the bus 12 may be twice or more that of the tab 14. A bus 16 adjacent to the tab 14 is also shown. In effect, the bus 16 prevents the tab 14 from extending further laterally from the side of the bus 12. Both the decoy via 18 extending upward and the functional via 20 extending downward are connected to the tab 14. As an alternative, the functional via 20 may extend upward while the decoy via 18 extends downward.

  FIG. 2 shows a cross-section of the semiconductor device 10 through the bus 12 including the tabs 14 and thus through the decoy via 18, the decoy via 20, and the bus 16. Also shown are metal portions 22, 24, 26, 28, and via fill 30 vias, 32. Buses 12 and 16 are formed in the interconnect layer 34. Metal portions 22 and 24 are formed in the interconnect layer 36. Metal portions 26 and 28 are formed in the interconnect layer 38. A substrate 40, an active circuit layer 42 on the substrate 40, an interlayer dielectric (ILD) 44 on the active circuit layer 42, a dielectric layer 50 in which an interconnect layer 36 is formed, interconnect layers 34 and 36, Also shown is the ILD 46 between, the dielectric layer 52 in which the interconnect layer 34 is formed, the ILD 48 between the interconnect layers 34 and 38, and the dielectric layer 54 in which the interconnect layer 38 is formed. Has been. Via 18 is formed by forming a via opening in ILD 48 and filling it with via fill 32. A metal portion 26 is formed on and in contact with the via fill 32. Similarly, the via 20 is formed by forming a via opening in the ILD 46 and filling it with the via filling 30. The bus 12 that is part of the interconnect layer 34 is formed on and in contact with the via fill 30. The bus 12 performs a circuit function that carries the signal as the metal portion 24 does, which is why the functional via 20 is named. On the other hand, the metal portion 26 is not further connected to additional circuitry, which is the reason for the name of the decoy via 18. Via fill 30 and via fill 32 may be formed simultaneously with interconnect layers 34 and 38, for example, in dual damascene patterning, respectively.

As shown in FIGS. 1 and 2, the decoy via 18 is aligned at a position adjacent to the via 20. This position is an effective position because it is in the path of holes that originate from the main part of the bus 12. Although gettering of these holes by the decoy via 18 may cause an opening between the via 18 and the bus 12, the decoy via 18 is not a functional via and the circuit does not rely on the via 18 to provide a current path. So that is not a problem. Holes on the path to the interface between the via 20 and the metal portion 24 gather in the decoy via 18 instead of the functional via 20. Due to the presence of the metal portion 22, a redundant or decoy via under the bus 12 that is directly adjacent to the functional via 20 is not possible. This shows the value of being able to provide decoy vias between interconnect layers different from the interconnect layer to which the functional via 20 is connected. As also shown in FIG. 2, there is no space available for decoy or redundant vias on the opposite side of via 20. While it may be beneficial to have a decoy via connected between the metal portion 24 and the active circuit layer 42, in this example where voids occur from the wide bus 12 to the tab 14, the need for the decoy via 18 is taken. It will not replace it.
Assuming that holes do not occur from the metal portion 24 toward the bottom of the via 20, it may be beneficial to add a decoy via directly above the via 20, but this decoy via is provided in place of the decoy via 18. It may be provided in addition to the decoy beer 18.

  On the other hand, vacancies arising from the metal portion 24 can damage the interface between the via 20 and the metal portion 24 and are therefore close to the functional via 20 on the metal portion 24 but not aligned. Decoy beer would be beneficial. In this situation, it is not desirable to stack the functional via 20 on top of the additional decoy via. This additional decoy via should be offset from the functional via. The intent is to prevent excessive holes from reaching the functional via and thus protect the decoy via sufficiently to preserve the functional via. This location, which is sufficient to provide protection, may be referred to as a protected area. Accordingly, the decoy via is placed in a protected area to maintain the integrity of the functional via (and may be further aligned with the functional via).

  It should be understood that, thus far, methods have been provided for forming decoy and functional vias. The method includes forming a functional via between a metal portion of the first interconnect layer and a portion of the second interconnect layer. The method further comprises forming a decoy via in a protective region between the metal portion of the first interconnect layer and the metal portion of the third interconnect layer. The method is further characterized in that the first interconnect layer is over the second interconnect layer. The method can be further characterized in that the first interconnect layer is over the third interconnect layer. The method includes forming a first interconnect layer by forming a plurality of metal portions in a first dielectric layer, and a second interconnect layer forming a plurality of metal portions in the second dielectric layer. And the third interconnect layer may be further formed by forming a plurality of metal portions in the third dielectric layer. The method can be further characterized in that the functional via is formed after the second interconnect layer is formed. The method can be further characterized in that the portion of the first interconnect layer is a bus having a tab and the functional via contacts the tab. The method can be further characterized in that the decoy via is aligned adjacent to the functional via. The method can be further characterized in that the plurality of metal portions in the first dielectric layer comprises copper. The method can be further characterized in that there is no space available for redundant vias immediately adjacent to functional vias. The method can be further characterized in that there is no space in the protected area in the first interconnect layer that can utilize vias.

  A semiconductor device is also disclosed. The semiconductor device comprises a first interconnect layer having a plurality of metal portions having a first metal portion. The semiconductor device further includes a second interconnect layer comprising a plurality of metal portions having a second metal portion. The semiconductor device further includes a third interconnect layer having a plurality of metal portions including a third metal portion. The semiconductor device further includes a functional via coupled to the first metal portion and the second metal portion. The semiconductor device further includes a decoy via in a protective region around the functional via that is coupled to the first metal portion and the third metal portion. The semiconductor device can be further characterized in that the first interconnect layer is over the second interconnect layer. The semiconductor device can be further characterized in that the first interconnect layer is over the third interconnect layer. The semiconductor device can be further characterized in that the first metal portion includes a bus having a tab and the functional via is coupled to the tab. The semiconductor device can be further characterized in that the decoy via is coupled to the tab. The semiconductor device can be further characterized in that the functional via extends from the bottom surface of the tab and the decoy via contacts the top surface of the tab. The semiconductor device can be further characterized in that the decoy via is aligned adjacent to the functional via. The semiconductor device can be further characterized in that there is no space available for vias immediately adjacent to the functional via.

  A method is also disclosed. The method includes forming a first interconnect layer having a plurality of metal portions including a first metal portion. The method further includes forming a first interlayer dielectric over the first interconnect layer. The method further includes forming a second interconnect layer having a plurality of metal portions including a second metal portion on the first interlayer dielectric, during the formation of the second interconnect layer. Forming a functional via penetrating the first interlayer dielectric from the second metal portion to the first metal portion; The method further includes forming a second interlayer dielectric layer over the second interconnect layer. The method further includes forming a third interconnect layer having a plurality of metal portions including a third metal portion on the second interlayer dielectric layer, wherein the third interconnect layer is formed. Inside, forming a decoy via that penetrates the second interlayer dielectric layer from the third metal part to the second metal part, a decoy via in the protective region of the functional via. The method can be further characterized in that there is no space in the protection region available for vias that join the functional via in the second interconnect layer.

  Although the invention has been described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the invention as set forth in the appended claims. be able to. For example, functional vias on a large plate may have similar obstructions to decoy vias or redundant vias as shown in FIG. It may be beneficial to provide decoy vias between different interconnect levels. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefit, advantage, or solution to a problem described herein with respect to a particular embodiment is considered as an important, required, or basic feature or element of any or all claims. It is not intended to be interpreted.

  Further, as used herein, the term “one” (“a” or “an”) is defined as one or more. Further, the use of the introductory phrases such as “at least one” and “one or more” in the claims is subject to another claim by the indefinite article “a” or “an”. The introduction of an element includes any particular claim that includes the claim element thus introduced, even if the same claim is preceded by the words “one or more” or “at least one” and “one ( The inclusion of indefinite articles such as “a” or “an”) should not be construed to imply limiting to inventions that include only one such element. The same is true for the use of definite articles.

  Unless stated otherwise, terms such as “first” and “second” are used to appropriately distinguish between the elements such terms describe. Accordingly, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

Claims (20)

A method of forming decoy vias and functional vias,
Forming a functional via between a metal portion of the first interconnect layer and a portion of the second interconnect layer;
Forming a decoy via in a protective region between the metal portion of the first interconnect layer and the metal portion of the third interconnect layer.   The method of claim 1, wherein the first interconnect layer is over the second interconnect layer.   The method of claim 1, wherein the first interconnect layer is over the third interconnect layer.   The first interconnect layer is formed by forming a plurality of metal portions in a first dielectric layer, and the second interconnect layer is forming a plurality of metal portions in a second dielectric layer. The method of claim 1, wherein the third interconnect layer is formed by forming a plurality of metal portions in a third dielectric layer.   The method of claim 4, wherein the functional via is formed after the second interconnect layer is formed.   The method of claim 5, wherein the portion of the first interconnect layer is a bus having a tab and the functional via contacts the tab.   The method of claim 6, wherein the decoy via is aligned adjacent to the functional via.   The method of claim 7, wherein the plurality of metal portions in the first dielectric layer comprises copper.   The method of claim 7, wherein there is no space available for redundant vias immediately adjacent to the functional via.   The method of claim 7, wherein no space is available in the protection region for vias in the first interconnect layer. A semiconductor device,
A first interconnect layer having a plurality of metal portions including a first metal portion;
A second interconnect layer having a plurality of metal portions including a second metal portion;
A third interconnect layer having a plurality of metal portions including a third metal portion;
A functional via coupled to the first metal portion and the second metal portion;
And a decoy via in a protective region around the functional via, wherein the decoy via is coupled to the first metal portion and the third metal portion.   The semiconductor device of claim 11, wherein the first interconnect layer is over the second interconnect layer.   The semiconductor device of claim 11, wherein the first interconnect layer is over the third interconnect layer.   The semiconductor device of claim 13, wherein the first metal portion comprises a bus having a tab and the functional via is coupled to the tab.   The semiconductor device of claim 14, wherein the decoy via is coupled to the tab.   The semiconductor device according to claim 15, wherein the functional via extends from a bottom surface of the tab, and the decoy via contacts an upper surface of the tab.   The semiconductor device of claim 16, wherein the decoy via is aligned adjacent to the functional via.   The semiconductor device of claim 17, wherein there is no space available for a via immediately adjacent to the functional via. Forming a first interconnect layer having a plurality of metal portions including a first metal portion;
Forming a first interlayer dielectric on the first interconnect layer;
Forming a second interconnect layer having a plurality of metal portions comprising a second metal portion on the first interlayer dielectric, wherein during the formation of the second interconnect layer, Forming a functional via penetrating the first interlayer dielectric from a second metal portion to the first metal portion; and
Forming a second interlayer dielectric layer on the second interconnect layer;
Forming a third interconnect layer having a plurality of metal portions including a third metal portion on the second interlayer dielectric layer, during the formation of the third interconnect layer; Forming a decoy via that penetrates the second interlayer dielectric layer from the third metal portion to the second metal portion, and
The method wherein the decoy via is located within a protected area of the functional via.   20. The method of claim 19, wherein in addition to the functional via, no space is available in the protection area for vias in the second interconnect layer.

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