JP2009099833A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having sufficient reliability by suppressing an electric field concentration to an insulating film formed between wiring and suppressing dielectric breakdown even if the device is miniaturized. <P>SOLUTION: The semiconductor device includes: a first insulating film (second inter-layer insulating film) 504 which is formed on a substrate and has a via hole 506c and a wiring groove (upper layer wiring groove) 505c connected to the upper portion of the via hole 506c; a via 506 buried in the via hole 506c; metal wiring (upper layer wiring) 505 which is electrically connected to the via 506 while buried in the wiring groove (upper layer wiring groove) 505c; and a second insulating film (insulating film) 508 which is formed on the side surface of the via hole 506c and formed while being sandwiched between the side surface of the metal wiring (upper layer wiring) 505 and the first insulating film (second inter-layer insulating film) 504. In a planar view, the via 506 is formed in a region between the adjoining metal wiring (upper wiring) 505 without causing stick-out. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a multilayer wiring structure and a method for manufacturing the same.

  In recent years, miniaturization and multilayering of wiring structures have progressed along with higher integration, higher functionality, and higher speed of semiconductor integrated circuit devices. Here, in order to meet the demand for higher speed of the semiconductor integrated circuit device, a low resistance material mainly made of Cu is used as a material of the wiring. A material having a low dielectric constant is used as a material for the interlayer insulating film on which the wiring layer is formed. For example, the wiring is formed by a buried wiring technique in which a wiring groove is formed in an interlayer insulating film and Cu is embedded in the wiring groove.

  However, Cu is easily diffused into the insulating film by heat or an electric field. This diffusion of Cu causes TDDB (Time Dependence on Dielectric Breakdown), which reduces the reliability of the semiconductor device. Therefore, the bottom and side surfaces of the wiring trench are coated with a metal prevention film made of a metal having a high melting point such as Ta, and the upper surface of the wiring is covered with a SiN-based film so that Cu diffuses into the insulating film. Is preventing.

  On the other hand, when a low dielectric constant film is used as an interlayer insulating film between wirings, there is a risk that the insulation resistance is lowered. Here, when the wiring structure is further miniaturized and further multilayered, the distance between adjacent wirings becomes small. As a result, when an insulating film having a low dielectric constant is used as an interlayer insulating film between miniaturized wirings, deterioration of insulation resistance becomes a problem.

Therefore, as a technique for improving the insulation resistance when using the embedded wiring technique, a method of forming a wiring so that the portion of the wiring where the electric field concentrates is separated from the polished surface of the insulating film has been proposed (for example, Patent Documents). 1). In addition, in order to reduce the insulation resistance of the low dielectric constant film and to deteriorate the insulation resistance during the processing of the low dielectric constant film, an insulating property different from the material of the interlayer insulation film provided between the wirings There has been proposed a technique for increasing insulation resistance by inserting an insulating barrier layer made of a high material between wirings (see, for example, Patent Document 2).
JP 2006-179948 A International Publication No. 04/107434 Pamphlet

  However, according to the above two methods, since it is necessary to improve the insulation resistance between adjacent wirings for all wiring regions, there is a problem that the resistance of the wiring increases. Therefore, it is necessary to examine which part of the region between adjacent wirings has low insulation resistance.

  FIG. 5 is a diagram illustrating a result of measuring a leakage current generated between wirings when a voltage is applied between the wirings. In addition, in the area | region where the via | veer (via hole) which connects upper layer wiring and lower layer wiring is not provided, the result of having changed the separation distance between mutually adjacent wiring is shown, respectively. As shown in FIG. 5, the larger the separation distance between wirings, the smaller the leakage current generated between the wirings. From this result, it can be seen that the insulation resistance of the insulating film provided between the wirings is improved as the separation distance between the wirings is increased.

  FIG. 6 is a diagram showing a measurement result of the TDDB life of the insulating film provided between the wirings. Here, the TDDB life is a measure for objectively measuring the time dependency of dielectric breakdown, and for example, the time from voltage application to dielectric breakdown when a high voltage is applied between wirings under high temperature measurement conditions. Say. Note that the horizontal axis and the vertical axis in FIG. 6 represent the failure time and the Weibull plot, respectively, and show the results obtained by changing the distance between adjacent wirings in the region where no via hole is provided. . As shown in FIG. 6, the TDDB life is extended as the separation distance between the wirings is increased. From this result, it can be seen that the reliability of the insulating film provided between the wirings is improved as the separation distance between the wirings is increased.

  From the above results, it was confirmed that the insulation and reliability of the insulating film provided between the wirings increased as the separation distance between the wirings increased. However, the results shown in FIGS. It is a result when not provided. Therefore, the insulation resistance between the wirings in the region where the via hole was provided was examined. The result will be described with reference to FIG.

  FIG. 7 shows the measurement of leakage current generated between wirings when a voltage is applied between the wirings when via holes are provided (with connection holes) and when via holes (without connection holes) are provided. It is a figure which shows a result. From FIG. 7, it can be seen that when the via hole is provided, the leakage current is large and the insulation resistance is low as compared with the case where the via hole is not provided. The reason for this will be described below with reference to FIGS.

  FIG. 8A is a plan view showing a configuration of a conventional semiconductor device having a multilayer wiring structure in a 65 nm or smaller device using the dual damascene method. Moreover, FIG.8 (b) is sectional drawing in the VIIIb-VIIIb line | wire shown to Fig.8 (a). As shown in FIGS. 8A and 8B, the conventional semiconductor device is embedded in a first interlayer insulating film 101 formed on a substrate (not shown) and the first interlayer insulating film 101. A lower wiring 102 formed of a diffusion barrier film 102a and a Cu film 102b, and a first insulating diffusion barrier film 103 formed on the first interlayer insulating film 101 and the lower wiring 102, A second interlayer insulating film 104 formed on the first insulating diffusion prevention film 103, and is formed to be embedded in the upper part of the second interlayer insulation film 104, and includes a diffusion prevention film 105a and a Cu film 105b. The upper layer wiring 105, the first insulating diffusion prevention film 103 and the second interlayer insulating film 104 are provided in the via hole 106 c reaching the upper surface of the lower layer wiring 102, and the upper layer wiring 105 and the lower layer wiring 102 are connected to each other. Via to connect And 06, and a second insulating diffusion barrier layer 107 formed on the upper wiring 105 and the second interlayer insulating film 104. The via 106 is composed of a diffusion prevention film 105a formed on the inner surface of the via hole 106c and a Cu film 105b embedded in the via hole 106c in the same manner as the upper layer wiring 105.

  In the conventional semiconductor device having the above-described configuration, as shown in FIG. 8A, a part of the via hole 106c (via 106) protrudes into a region between the upper wirings 105 adjacent to each other as viewed in a plan view. . For this reason, in the region where the via 106 is formed, the separation distance between the upper wirings 105 adjacent to each other is locally smaller than in other regions. In this case, as a result of local electric field concentration occurring at the protruding portion of the via 106, there arises a problem that the insulation resistance of the insulating film provided between the wirings deteriorates in the region where the via 106 is formed.

  Here, in order to prevent the via 106 from protruding into the region between the upper layer wirings 105, when forming the upper layer wiring 105, the wiring for the upper layer wiring 105 is set so that the width is larger than the diameter of the via hole 106c. There is no problem if a groove is provided. However, in order to increase the contact area between the lower layer wiring 102 and the via 106, it is required to form the via hole 106 c so that the diameter is larger than the wiring groove for the upper layer wiring 105. As a result, the diameter of the via hole 106 c at the connection portion between the via 106 and the upper layer wiring 105 becomes larger than the wiring width of the upper layer wiring 105. Further, with the progress of miniaturization of the semiconductor device, in particular, when a dual damascene method in which the via hole 106c is formed before the wiring groove of the upper layer wiring is used, for example, in a plan view due to misalignment that occurs when the via hole 106c is formed. Therefore, there is a high possibility that a part of the via 106 protrudes from the upper layer wiring 105.

  Here, a case where a part of the via protrudes from the upper layer wiring when forming the multilayer wiring structure of the semiconductor device will be described in detail with reference to FIGS. 9 (a), 10 (a), and 11 (a) are plan views showing states after via holes are formed in the conventional multilayer wiring structure forming step. FIG. 9B, FIG. 10B, and FIG. 11B are plan views each showing a state after forming a wiring groove for upper layer wiring in the formation process of the multilayer wiring structure.

  First, as shown in FIGS. 9A and 9B, the via hole 900 is formed so that the diameter 301 is smaller than or equal to the width 302 of the wiring groove 310 of the upper layer wiring 905 and there is no misalignment with the wiring. When formed, the separation distance 303 between adjacent upper layer wirings 905 is constant regardless of the presence or absence of vias. In this case, since the electric field strength does not increase locally, there is little possibility that the insulation resistance of the interlayer insulating film 904 provided between the upper wirings 905 is lowered.

  On the other hand, in FIGS. 10A and 10B, the via hole 910 is formed so that the diameter 301 is larger than the width 302 of the wiring groove of the upper layer wiring 905 in order to increase the contact area between the lower layer wiring and the via, for example. Shows when to do. From FIG. 10B, it can be seen that the via hole 910 protrudes from the wiring groove 310 in plan view. Here, when the distance from the side surface of the wiring groove 310 to the side surface of the via hole 910 is defined as the protruding amount E1, the separation distance 304 between the upper wirings 905 adjacent to each other is the upper layer in the other region in the region where the via hole 910 is formed. The protrusion distance E1 is smaller than the separation distance 303 between the wirings 905.

  Further, FIGS. 11A and 11B show a case where misalignment occurs when forming a via hole, for example. From FIG. 11B, it can be seen that the via hole 911 protrudes from the wiring groove 310 when seen in a plan view. Here, assuming that the distance from the side surface of the wiring groove 310 to the side surface of the via hole 911 caused by misalignment is the protrusion amount E2, in the region where the via hole 911 is formed, the upper layers adjacent to each other are formed as shown in FIG. The separation distance 304 between the wirings 905 is smaller than the separation distance 303 between the upper layer wirings 905 in other regions by the protrusion amount E2. When misalignment of the via hole 911 occurs when ensuring a large contact area between the lower layer wiring and the via, the separation distance 304 between the upper layer wiring 905 in the region where the via hole 911 is formed is larger than that in other regions. It gets even smaller.

  As described above, in a conventional semiconductor device having a multilayer wiring structure, when a via hole whose diameter is larger than the wiring groove of the upper layer wiring is formed, or even if the via hole is equal to or smaller than the wiring groove, the side surface of the wiring groove is caused by misalignment. When formed so as to protrude, local electric field concentration occurs in the insulating film provided between the wirings, so that the insulation resistance between the wirings may be deteriorated.

  In view of the above problems, the present invention suppresses electric field concentration on an insulating film provided between wirings, suppresses dielectric breakdown even when miniaturized, and has a sufficiently reliable semiconductor device and a method for manufacturing the same The purpose is to provide.

  In order to solve the above problems, a semiconductor device according to the present invention includes a substrate, a first insulating film formed on the substrate, having a via hole and a wiring trench connected to an upper portion of the via hole, and the via hole. A via buried in the via, a metal wiring electrically connected to the via and buried in the wiring trench, and provided on a side surface of the via hole, between the side surface of the metal wiring and the first insulating film And a second insulating film formed between the two.

  According to this configuration, for example, in order to secure a wide contact area between the lower layer wiring and the via, even when the via hole protrudes into a region between the metal wirings adjacent to each other in plan view, On the side surface, a second insulating film formed between the metal wiring and the interlayer insulating film (first insulating film) is provided. For this reason, it can suppress that the separation distance between the metal wiring adjacent to each other becomes smaller than the region where the via is not formed. As a result, even when a voltage is applied between the wirings, the electric field is not concentrated in the protruding region of the via hole, but is distributed and applied to the interface between the second insulating film and the metal wiring. It can be greatly prevented. Therefore, if the semiconductor device of this embodiment is used, even if the semiconductor device is miniaturized, the dielectric breakdown of the insulating film provided between the wirings is suppressed, and a highly reliable semiconductor device can be realized.

  Further, there are a plurality of the metal wirings, and the distance between the metal wiring adjacent to the via hole and the via hole may be shorter than the distance between the metal wirings.

  Further, the second insulating film is provided between the metal wiring and the first insulating film and between the via and the first insulating film, and an upper second insulating film of the via The horizontal cross-sectional shape may be a kamaboko shape.

  The second insulating film may be formed between the first insulating film and at least one side surface of both sides of the portion of the metal wiring formed on the via. Good.

  The 1 insulating film may be a low dielectric constant film. In this case, it is preferable that the first insulating film is made of SiOC, SiCNH, or SiOCH.

  Furthermore, the second insulating film may have an electrical insulating property equal to or higher than that of the first insulating film.

  The region where the via is formed may be included in the region where the metal wiring is formed in a plan view.

  Further, a part of the side surface of the via may form the same surface as one of the side surfaces of the metal wiring.

  Subsequently, in the method of manufacturing a semiconductor device according to the present invention, after forming a first insulating film on the substrate, a step (a) of forming a via hole in the first insulating film, and a second step on the side surface of the via hole. After the step (b) of depositing an insulating film and the step (b), by selectively removing the upper portion of the first insulating film, at least one side surface is in contact with the second insulating film, Forming a wiring groove connected to the upper portion of the via hole; and after the step (c), a conductive film is embedded in the wiring groove and the via hole and then a part of the conductor film is removed. And a step of forming a via provided in the via hole and a metal wiring electrically connected to the via and having at least one side surface of the portion provided on the via contacting the second insulating film. (D).

  According to this method, in the step (c), the wiring groove is formed so that at least one side surface is in contact with the second insulating film, so that it protrudes into a region between adjacent metal wirings in plan view. A via in which a second insulating film is provided on a side surface of the via hole can be formed. As a result, it is possible to suppress the separation distance between adjacent metal wirings from becoming smaller than a region where no via is formed, and even if a voltage is applied between the wirings, the via hole protrudes locally. Concentration of the electric field can be suppressed. Therefore, when the semiconductor device manufacturing method of the present invention is used, even if the semiconductor device is miniaturized, the dielectric breakdown of the insulating film provided between the wirings is suppressed, and a semiconductor device having high reliability can be manufactured.

  Furthermore, in the method for manufacturing a semiconductor device of the present invention, the width of the wiring groove is changed from a predetermined width in the step (c) in order to interpose the second insulating film between the metal wiring and the first insulating film. There is no need to do. In other words, by forming the wiring trench in the predetermined region, the second insulating film can be left in a self-aligned manner only in the protruding region of the via hole formed so as to protrude from the metal wiring in a plan view. . Therefore, according to the method for manufacturing a semiconductor device of the present invention, in addition to the above-described effects, a semiconductor device having a highly reliable insulating film between the wirings can be relatively easily obtained without increasing the resistance of the metal wiring. Can be manufactured.

  In the step (d), the second insulating film may be formed from the side surface above the via to the side surface of the metal wiring.

  In the step (d), the metal wiring may be formed so that both side surfaces are in contact with the second insulating film.

  Further, after the step (b) and before the step (c), the method further includes a step of embedding a resist in the via hole, and the step (c) includes forming the wiring groove and then removing the resist. You may have the process of removing.

  Further, the step (d) may be a step of simultaneously forming the via and the metal wiring by using a dual damascene method.

  The first insulating film may be a low dielectric constant film. In this case, the first insulating film is preferably made of SiOC, SiCNH, or SiOCH.

  The second insulating film may have an electrical insulating property equal to or higher than that of the first insulating film.

  Further, the step (b) may be a step of depositing the second insulating film made of a silicon oxide film by using a PECVD method.

  According to the semiconductor device and the manufacturing method thereof of the present invention, for example, it is possible to suppress the occurrence of dielectric breakdown of an insulating film provided between adjacent wirings of a multilayer wiring structure. A high-speed semiconductor device that can operate at high speed can be realized.

(Embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings. FIG. 1A is a plan view showing the configuration of the semiconductor device of this embodiment. Moreover, FIG.1 (b) is sectional drawing in the Ib-Ib line | wire shown to Fig.1 (a). In FIG. 1A, the second insulating diffusion barrier film 507 is omitted.

  As shown in FIGS. 1A and 1B, the semiconductor device of this embodiment includes a substrate (not shown) and a first interlayer insulating film formed on the substrate and having a lower wiring trench 502c on the upper portion. 501, a lower layer wiring 502 formed by being embedded in the lower layer wiring trench 502 c and composed of a first diffusion prevention film 502 a made of Ta or the like and a first metal film 502 b made of Cu or the like, and a first interlayer A first insulating diffusion barrier film 503 formed on the insulating film 501 and the lower wiring 502, and formed on the first insulating diffusion barrier film 503, connected to the via hole 506c and the upper portion of the via hole 506c. And a second interlayer insulating film 504 having an upper wiring groove 505c.

  Further, the semiconductor device of this embodiment is electrically connected to the lower layer wiring 502 through the via 506 and the via 506 formed by burying the second metal film 505b made of Cu or the like in the via hole 506c, and the upper layer An upper layer wiring 505 formed by embedding a second metal film 505b made of Cu or the like in the wiring groove 505c and a part of a side surface of the via hole 506c, and the upper layer wiring 505 and the second interlayer insulating film 504 An insulating film 508 formed between them, a second interlayer insulating film 504, an upper wiring 505, and a second insulating diffusion prevention film 507 formed on the insulating film 508 are provided. A second diffusion barrier film 505a made of Ta or the like is formed on the inner surfaces of the via hole 506c and the upper wiring groove 505c. Note that the first diffusion barrier film 502a and the second diffusion barrier film 505a, and the first insulating diffusion barrier film 503 and the second insulating diffusion barrier film 507 are made of Cu, which is a wiring material, with interlayer insulation. In order to prevent diffusion into the film, it is provided so as to surround the wiring.

  Next, the region in which the via and the upper layer wiring in the semiconductor device of this embodiment are formed will be described in detail with reference to FIGS. 2A and 2B are a bird's-eye view and a plan view showing the configuration of the semiconductor device of this embodiment, respectively. FIG. 2C is a cross-sectional view taken along line A-A ′ shown in FIG.

  As shown in FIGS. 2A to 2C, in the semiconductor device of this embodiment, for example, the opening diameter of the via hole 506c is set to the wiring width of the upper layer wiring 505 in order to ensure a sufficient contact area between the lower layer wiring and the via. As a result, the via hole 506c is formed so as to protrude from a region between the upper wirings 505 adjacent to each other. Here, an insulating film 508 is provided on the side surface of the via hole 506 c that protrudes from the upper layer wiring 505 when seen in a plan view. According to this configuration, the via 506 formed by burying the second metal film 505b (see FIG. 1) in the via hole 506c is provided without protruding into a region between the adjacent upper layer wirings 505. Specifically, as shown in FIG. 2B, the horizontal cross-sectional shape of the insulating film 508 has a kamaboko shape.

  A feature of the semiconductor device of this embodiment is that it includes an insulating film 508 formed on the side surface of the via hole 506c and sandwiched between the upper wiring 505 and the second interlayer insulating film 504. According to this configuration, even when the via hole 506c is formed so as to protrude into the region between the upper wirings 505 adjacent to each other when seen in a plan view, the insulating film 508 is provided on the side surface of the protruding via hole 506c. It is possible to suppress the separation distance 510 (see FIG. 1A) between the upper layer wirings 505 adjacent to each other from becoming smaller than a region where the via 506 is not formed. As a result, even when a voltage is applied between the wirings, the electric field is not concentrated on the protruding region of the via hole 506c, but is dispersed at the interface 601 (see FIG. 2A) between the insulating film 508 and the upper wiring 505. In addition, local electric field concentration can be largely prevented. Therefore, if the semiconductor device of this embodiment is used, even if the semiconductor device is miniaturized, the dielectric breakdown of the insulating film provided between the wirings is suppressed, and a highly reliable semiconductor device can be realized.

  Next, a method for manufacturing the semiconductor device of this embodiment will be described. 3A to 3F are cross-sectional views showing a method for manufacturing a semiconductor device of this embodiment.

  First, as shown in FIG. 3A, a first interlayer insulating film 501 is formed on a semiconductor substrate (not shown). Thereafter, a lower wiring groove 502c is formed in the first interlayer insulating film 501, and a first diffusion prevention film 502a made of Ta or the like and a first metal film 502b made of Cu or the like are sequentially formed on the inner surface of the lower wiring groove 502c. accumulate. Thereby, the lower layer wiring 502 composed of the first diffusion preventing film 502a and the first metal film 502b can be formed. Next, a first insulating diffusion prevention film 503 made of, for example, a SiCN-based material is formed on the first interlayer insulating film 501 and the lower layer wiring 502.

  Subsequently, on the first insulating diffusion barrier film 503, the second interlayer insulating film 504 and PETEOS (Plasma-Enhanced Tetraethylorthosilicate) which is a silicon oxide film formed by, for example, PECVD (Plasma Enhanced Chemical Vapor Deposition) method. ) A cap film 511 made of a film or the like is sequentially formed. Thereafter, a part of the cap film 511, the second interlayer insulating film 504, and the first insulating diffusion barrier film 503 is removed, and a via hole 506c is opened. At this time, the first insulating diffusion barrier film 503 is removed until the film thickness becomes about 10 nm.

  Next, as illustrated in FIG. 3B, an insulating film 508 is deposited on the inner surface of the via hole 506 c and the cap film 511. The thickness of the insulating film 508 to be deposited is set such that the opening of the via hole 506c is not blocked. The insulating film 508 is made of, for example, a PET-OS (Plasma-Enhanced Tetraethylorthosilicate) film, which is a silicon oxide film formed by PECVD (Plasma Enhanced Chemical Vapor Deposition), and the second interlayer insulating film 504 is made of a material. When the low dielectric constant SiOC film is used, the film thickness ratio between the portion of the insulating film 508 formed on the upper side surface of the via hole 506c and the portion formed on the cap film 511 is approximately 1. It becomes. This is because the PETEOS film exhibits a relatively good film property. It is also possible to adjust the PECVD film formation conditions (RF-POWER, pressure, etc.) so that the film properties are lowered as the via hole 506c approaches the bottom, and the bottom of the via hole 506c is hardly coated. The film thickness of the insulating film 508 deposited in this step takes into consideration the diameter R1 when the via hole 506c is opened, the wiring width R2 of the upper wiring groove formed in the subsequent process, and the misalignment amount R3 of the upper wiring groove. Can be set. For example, when R1 = 90 nm, R2 = 70 nm, and R3 = 10 nm, it can be estimated that the maximum length of a portion of the via hole 506c that protrudes into the region between the upper layer wirings 505 adjacent to each other in plan view is 20 nm. At this time, it is preferable to deposit the insulating film 508 so as to have a film thickness of 20 nm because a via 506 is formed without protruding in a region between adjacent upper layer wirings 505 in a later step.

  Next, as shown in FIG. 3C, after a resist 509 is buried in the via hole 506c by coating and heat treatment is performed, the resist is left only in the via hole 506c by etching back. As a result, the inside of the via hole 506c is protected by the resist 509. Therefore, when the upper wiring groove is formed by dry etching in a later process, the lower surface of the via hole 506c reaches the lower wiring 502 due to the etching back after the heat treatment. It is possible to suppress damage to the body. In order to facilitate embedding the resist 509 in the via hole 506c in this step, the insulating film 508 is formed with a thickness that does not block the upper portion of the via hole 506c in the step shown in FIG. Good. However, in order to suppress an increase in the specific resistance of the via, it is preferable that the film thickness of the insulating film 508 formed on the lower side surface of the via hole 506c is smaller than the film thickness on the upper side surface of the via hole 506c. This is because the larger the thickness of the insulating film 508 formed on the side surface of the via hole 506c, the smaller the via formation region and the higher the resistance. Therefore, in the step of forming the insulating film 508 shown in FIG. 3B, the PETEOS film may be deposited under the condition that the film property on the lower side surface of the via hole 506c is relatively poor.

  Next, as shown in FIG. 3D, although not shown, a resist pattern is formed on the insulating film 508, and etching is performed using the resist pattern as a mask to remove part of the second interlayer insulating film 504. Thus, an upper wiring trench 505c connected to the upper portion of the via hole 506c is formed. At this time, the portion of the insulating film 508 provided in the formation region of the upper wiring trench 505c is removed together with the second interlayer insulating film 504, while the portion provided on a part of the side surface of the via hole 506c remains. The depth of the upper wiring groove 505c in the via hole 506c is determined by the height of the resist 509 in the via hole 506c before the etching of the upper wiring groove 505c and the etching of the resist 509 in the second interlayer insulating film 504 and the via hole 506c. It is possible to adjust by the selection ratio at the time. Accordingly, the remaining depth (the height from the bottom of the via hole 506c to the upper surface of the remaining insulating film 508) on a part of the side surface of the via hole 506c can also be adjusted. Next, the resist 509 embedded in the via hole 506c is removed.

  Subsequently, as shown in FIG. 3E, by performing a multi-stage dry etching method, the insulating film 508 on the surface of the cap film 511 and the bottom of the via hole 506c, and the first insulating diffusion prevention film 503 are formed. And the upper surface of the lower layer wiring 502 is exposed so that the insulating film 508 provided on the side surface of the via hole 506c other than the formation region of the upper layer wiring groove 505c remains. Specifically, after the insulating film 508 is removed under conditions that enhance selective removability in the depth direction (for example, low pressure, high bias, etc.), the first insulating diffusion prevention film 503 is removed by etching back. . At this time, the cap film 511 may also be removed, or may be left depending on the type of the second interlayer insulating film 504 such as low moisture resistance. FIG. 3E illustrates a case where the cap film 511 is not left. Thus, in this step, the insulating film 508 can be left on a part of the side surface of the via hole 506c, and the via hole 506c can reach the lower layer wiring 502.

  Next, as shown in FIG. 3F, on the inner surface of the via hole 506c and the upper wiring groove 505c and the insulating film 508, a second diffusion prevention film 505a made of a laminated film of Ta and TaN or the like, a Cu seed film ( (Not shown) are sequentially deposited. Thereafter, a second metal film 505b made of Cu is deposited on the Cu seed film by electrolytic plating so as to fill the via hole 506c and the upper wiring groove 505c. Subsequently, the second diffusion barrier film 505a and the second metal film 505b formed outside the via hole 506c and the upper wiring groove 505c are removed by a CMP (Chemical Mechanical Polishing) method. Thereby, the via 506 and the upper layer wiring 505 constituted by the second diffusion prevention film 505a and the second metal film 505b can be formed at the same time. Although not shown in FIG. 3E, the insulating film 508 and the first insulating diffusion prevention film 503 formed on the surface of the cap film 511 and the bottom of the via hole 506c are removed by multi-stage dry etching. When the upper surface of the lower layer wiring 502 is exposed so that the insulating film 508 provided on the side surface outside the formation region of the upper layer wiring groove 505c remains in the via hole 506c, the upper portion of the via hole 506c and the upper layer wiring groove 505c are exposed. The upper portion of the upper portion is tapered (corner drop) during etching, and the distance between the adjacent upper layer wiring grooves 505c and the distance between the upper layer wiring groove 505c and the upper portion of the via hole 506c are shortened. In that case, when the second diffusion barrier film 505a and the second metal film 505b formed outside the via hole 506c and the upper wiring groove 505c are removed by the CMP method, the thickness exceeds the taper depth. By polishing, it is possible to prevent the separation distance from decreasing due to the taper. Subsequently, a second insulating diffusion barrier film 507 is formed on the second interlayer insulating film 504 and the upper wiring 505. The semiconductor device of this embodiment can be manufactured by the above method.

  The semiconductor device manufacturing method of this embodiment is characterized in that, after forming the insulating film 508 on the side surface of the via hole 506c in the step shown in FIG. 3B, at least one side surface is formed in the step shown in FIG. The purpose is to form an upper wiring trench 505c in contact with the insulating film 508. According to this method, for example, in order to ensure a sufficient contact area between the lower layer wiring 502 and the via 506, even when the opening diameter of the via hole 506c is larger than the width of the upper layer wiring groove 505c, A via 506 in which an insulating film 508 is provided on the side surface of the via hole 506 c that protrudes into a region between adjacent upper layer wirings 505 can be formed. As a result, the separation distance between the upper layer wirings 505 adjacent to each other can be suppressed from becoming smaller than a region where the via 506 is not formed, and even if a voltage is applied between the wirings, It is possible to suppress local concentration of the electric field. Therefore, when the semiconductor device manufacturing method of this embodiment is used, even if the semiconductor device is miniaturized, the dielectric breakdown of the insulating film provided between the wirings is suppressed, and a highly reliable semiconductor device can be manufactured.

  Further, in the method of manufacturing the semiconductor device according to the present embodiment, since the insulating film 508 is interposed between the upper layer wiring 505 and the second interlayer insulating film 504, the upper layer wiring groove 505c in the step shown in FIG. There is no need to change the width of a predetermined width. In other words, by forming the upper layer wiring groove 505c in a predetermined region, the insulating film 508 is left in a self-aligned manner only in the protruding region of the via hole 506c formed so as to protrude from the upper layer wiring 505 in plan view. Can do. Therefore, when the method for manufacturing a semiconductor device of this embodiment is used, in addition to the above-described effects, a semiconductor device having a highly reliable insulating film between wirings can be relatively manufactured without increasing the resistance of the upper wiring 505. It can be manufactured easily.

  In the semiconductor device and the manufacturing method thereof according to the present embodiment, it is more preferable that the second interlayer insulating film 504 is composed of a low dielectric constant film because parasitic resistance between wirings can be reduced. In this case, specific materials for the low dielectric constant film include, but are not limited to, SiOC, SiCN, or SiOCH.

  In addition, it is more preferable that the insulating film 508 is made of a film having higher electrical insulation than the second interlayer insulating film 504. Thereby, for example, even when the insulating film 508 is small in thickness and the insulating film 508 is not embedded in the entire protruding region of the via hole 506c, it is possible to sufficiently ensure insulation with the adjacent upper layer wiring 505.

  In the semiconductor device manufacturing method of the present embodiment, the dual damascene method in which the upper layer wiring 505 and the via 506 are formed at the same time is used. However, the present invention is not limited to this.

  Hereinafter, modifications of the semiconductor device of this embodiment will be described. FIGS. 4A and 4B are a bird's-eye view and a plan view showing a region where an upper layer wiring and a via are formed, respectively, according to a modification of the semiconductor device of this embodiment. FIG. 4C is a cross-sectional view taken along line A-A ′ shown in FIG.

  As shown in FIGS. 4A to 4C, in the modification of the semiconductor device of this embodiment, the via hole 506c is not only one side of the region between the upper layer wirings 505 adjacent to each other as viewed in a plan view. It is formed to protrude. Here, an insulating film 508 is formed between both side surfaces of a portion of the upper layer wiring 505 formed on the via 506 and a second interlayer insulating film (not shown). As a result, the protruding region of the via hole 506c is filled with the insulating film 508, so that the separation distance between the upper wirings 505 adjacent to each other can be suppressed to be smaller than the region where the via 506 is not formed. Therefore, even if the modification of the semiconductor device of this embodiment is used, the same effect as that of the above-described semiconductor device of this embodiment can be obtained.

  In addition, the modification of the semiconductor device of this embodiment can be manufactured by changing a part of the manufacturing method of the semiconductor device of this embodiment. Specifically, after the steps shown in FIGS. 3A to 3C are sequentially performed, in the step shown in FIG. 3D, not only one side surface but also both side surfaces are in contact with the insulating film 508. A wiring groove 505c is formed. Thereafter, a modification of the semiconductor device of the present embodiment can be manufactured by performing the same process as the above-described manufacturing method.

  The semiconductor device of the present invention is useful for miniaturization of a semiconductor device having a multilayer wiring structure.

(A) is a top view which shows the structure of the semiconductor device of embodiment of this invention, (b) is sectional drawing in the Ib-Ib line | wire shown to (a). (A)-(c) is a figure which shows the structure of the semiconductor device of embodiment of this invention. (A)-(f) is sectional drawing which shows the manufacturing method of the semiconductor device of embodiment of this invention. (A)-(c) is a figure which shows the modification concerning the semiconductor device of embodiment of this invention. It is a figure which shows the result of having measured the leakage current which generate | occur | produces between the wiring which concerns on the conventional semiconductor device. It is a figure which shows the measurement result of the TDDB lifetime of the insulating film provided between the wiring which concerns on the conventional semiconductor device. It is a figure which shows the result of having measured the leakage current which generate | occur | produces between wiring when a voltage is applied between the wiring which concerns on the conventional semiconductor device. (A) is a top view which shows the structure of the conventional semiconductor device, (b) is sectional drawing in the VIIIb-VIIIb line | wire shown to (a). (A), (b) is a top view which shows the formation process of the conventional multilayer wiring structure. (A), (b) is a top view which shows the formation process of the conventional multilayer wiring structure. (A), (b) is a top view which shows the formation process of the conventional multilayer wiring structure.

Explanation of symbols

501 First interlayer insulating film
502 Lower layer wiring
502a First diffusion prevention film
502b First metal film
502c Lower layer wiring groove
503 First insulating diffusion barrier film
504 Second interlayer insulating film
505 Upper layer wiring
505a Second diffusion barrier film
505b Second metal film
505c Upper layer wiring groove
506 Via
506c Beer hole
507 Second insulating diffusion barrier film
508 Insulating film
509 resist
510 Separation distance
511 Cap membrane
601 interface

Claims (18)

A substrate,
A first insulating film formed on the substrate and having a via hole and a wiring groove connected to the upper portion of the via hole;
Vias embedded in the via holes;
Metal wiring electrically connected to the via and embedded in the wiring trench;
A semiconductor device comprising a second insulating film provided on a side surface of the via hole and formed between the side surface of the metal wiring and the first insulating film. There are a plurality of the metal wirings,
2. The semiconductor device according to claim 1, wherein a distance between the metal wiring adjacent to the via hole and the via hole is shorter than a distance between the metal wirings. The second insulating film is provided between the metal wiring and the first insulating film, and between the via and the first insulating film,
The semiconductor device according to claim 1, wherein a horizontal cross-sectional shape of the second insulating film is a kamaboko type.   3. The second insulating film is formed so as to be sandwiched between the first insulating film on at least one side surface of a portion of the metal wiring formed on the via. A semiconductor device according to 1.   The semiconductor device according to claim 1, wherein the first insulating film is a low dielectric constant film.   The semiconductor device according to claim 5, wherein the first insulating film is made of SiOC, SiCNH, or SiOCH.   The semiconductor device according to claim 1, wherein the second insulating film has an electrical insulating property equal to or higher than that of the first insulating film.   The semiconductor device according to claim 1, wherein the region in which the via is formed is included in a region in which the metal wiring is formed in a plan view.   The semiconductor device according to claim 1, wherein a part of the side surface of the via forms the same surface as one of the side surfaces of the metal wiring. (A) forming a via hole in the first insulating film after forming the first insulating film on the substrate;
After the step (a), a step (b) of depositing a second insulating film on the side surface of the via hole;
After the step (b), by selectively removing the upper portion of the first insulating film, at least one side surface is in contact with the second insulating film, and a wiring groove connected to the upper portion of the via hole is formed. Forming (c);
After the step (c), a conductive film is buried in the wiring groove and the via hole, and then a part of the conductor film is removed, so that the via provided in the via hole is electrically connected to the via. And a step (d) of forming a metal wiring in which at least one side surface of the portion provided on the via is in contact with the second insulating film.   The method of manufacturing a semiconductor device according to claim 10, wherein in the step (d), the second insulating film is formed from the side surface of the upper portion of the via to the side surface of the metal wiring.   12. The method of manufacturing a semiconductor device according to claim 10, wherein in the step (d), the metal wiring is formed so that both side surfaces are in contact with the second insulating film. A step of embedding a resist in the via hole after the step (b) and before the step (c);
The method of manufacturing a semiconductor device according to claim 10, wherein the step (c) includes a step of removing the resist after forming the wiring groove.   The method of manufacturing a semiconductor device according to claim 10, wherein the step (d) is a step of simultaneously forming the via and the metal wiring using a dual damascene method.   The method of manufacturing a semiconductor device according to claim 10, wherein the first insulating film is a low dielectric constant film.   The method of manufacturing a semiconductor device according to claim 10, wherein the first insulating film is made of SiOC, SiCNH, or SiOCH.   17. The method for manufacturing a semiconductor device according to claim 10, wherein the second insulating film has an electrical insulating property equal to or higher than that of the first insulating film.   The method of manufacturing a semiconductor device according to claim 10, wherein the step (b) is a step of depositing the second insulating film made of a silicon oxide film using a PECVD method.

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