JP2013114069A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device that can improve the display quality.SOLUTION: A liquid crystal display device comprises: a first substrate; a second substrate; and a liquid crystal layer. The first substrate includes: a switching element disposed for each of pixels; a common electrode formed across the plural pixels; an insulation film disposed on the common electrode and having a penetration hole penetrating to reach the common electrode; a pixel electrode which is electrically connected to the switching element, the pixel electrode being provided for each pixel to face the common electrode on the insulation film, and having a slit on the penetration hole; and a first alignment film covering the pixel electrode and the common electrode which is exposed from the insulation film at the penetration hole. The second substrate includes a second alignment film facing the first alignment film. The liquid crystal layer is held between the first alignment film of the first substrate and the second alignment film of the second substrate.

Description

  Embodiments described herein relate generally to a liquid crystal display device.

  Liquid crystal display devices are utilized in various fields as display devices for OA equipment such as personal computers and televisions, taking advantage of features such as light weight, thinness, and low power consumption. In recent years, liquid crystal display devices are also used as mobile terminal devices such as mobile phones, display devices such as car navigation devices and game machines.

  In recent years, liquid crystal display panels in a fringe field switching (FFS) mode and an in-plane switching (IPS) mode have been put into practical use. Such an FFS mode or IPS mode liquid crystal display panel has a configuration in which a liquid crystal layer is held between an array substrate including a pixel electrode and a common electrode and a counter substrate.

  In such an FFS mode or IPS mode configuration, the electrode structure of the pixel electrode and the common electrode is asymmetric with respect to the liquid crystal layer. Therefore, when the impurity ions contained in the liquid crystal layer are adsorbed on the surface of the array substrate, or the alignment film covering the pixel electrode (or in contact with the liquid crystal layer) is charged up, the pixel electrode The charge tends to be injected into the alignment film or discharged to the pixel electrode through the alignment film, and the charge tends to decrease on the pixel electrode side. On the other hand, on the common electrode side, since the insulating film interposed between the pixel electrodes does not pass charges, charges accumulate due to adsorption of impurity ions on the surface of the array substrate and charge up of the alignment film. Presents a tendency to be

  As a result, even when a voltage that forms a potential difference between the pixel electrode and the common electrode is not applied, a DC is applied due to the asymmetry of the charge, resulting in a deterioration in display quality such as so-called burn-in. There is a fear.

JP 2008-216858 A

  An object of the present embodiment is to provide a liquid crystal display device capable of improving display quality.

According to this embodiment,
Insulation in which a switching element disposed in each pixel, a common electrode formed over a plurality of pixels, and an insulating film disposed on the common electrode and having a through-hole penetrating to the common electrode A pixel electrode electrically connected to the switching element and formed on each of the pixels on the insulating film and facing the common electrode and having a slit formed on the through hole; A first substrate including a pixel electrode and a first alignment film covering the common electrode exposed from the insulating film by the through-hole, and a second substrate including a second alignment film facing the first alignment film And a liquid crystal layer held between the first alignment film of the first substrate and the second alignment film of the second substrate.

According to this embodiment,
A gate line extending along the first direction, a first source line and a second source line extending along a second direction orthogonal to the first direction, the gate line and the first source line, An electrically connected switching element, a first interlayer insulating film covering the switching element, a common electrode formed on the first interlayer insulating film, and on the first interlayer insulating film and the common electrode A second interlayer insulating film having a through-hole formed between the first source wiring and the second source wiring and penetrating to the common electrode; and penetrating the first interlayer insulating film and the second interlayer insulating film A pixel electrode electrically connected to the switching element through a contact hole and facing the common electrode on the second interlayer insulating film and having a slit formed in the through hole; A first substrate including a pixel electrode and a first alignment film that covers the common electrode exposed from the second interlayer insulating film by the through-hole, and a second alignment film facing the first alignment film. A liquid crystal display device comprising: a second substrate; and a liquid crystal layer held between the first alignment film of the first substrate and the second alignment film of the second substrate. Provided.

FIG. 1 is a diagram schematically showing a configuration and an equivalent circuit of a liquid crystal display panel constituting the liquid crystal display device of the present embodiment. FIG. 2 is a schematic plan view of the pixel structure in the array substrate shown in FIG. 1 as viewed from the counter substrate side. FIG. 3 is a diagram schematically showing a cross-sectional structure of the liquid crystal display panel shown in FIG. 4 is a cross-sectional view in which the path from the common electrode to the pixel electrode in FIG. 3 is developed along line AB in the drawing.

  Hereinafter, the present embodiment will be described in detail with reference to the drawings. In each figure, the same reference numerals are given to components that exhibit the same or similar functions, and duplicate descriptions are omitted.

  FIG. 1 is a diagram schematically showing a configuration and an equivalent circuit of a liquid crystal display panel LPN constituting the liquid crystal display device of the present embodiment.

  That is, the liquid crystal display device includes an active matrix transmissive liquid crystal display panel LPN. The liquid crystal display panel LPN is held between the array substrate AR, which is the first substrate, the counter substrate CT, which is the second substrate disposed to face the array substrate AR, and the array substrate AR and the counter substrate CT. Liquid crystal layer LQ. Such a liquid crystal display panel LPN includes an active area ACT for displaying an image. This active area ACT is composed of a plurality of pixels PX arranged in an m × n matrix (where m and n are positive integers).

  In the active area ACT, the array substrate AR includes n gate wirings G (G1 to Gn) and n capacitance lines C (C1 to Cn) that extend in the first direction X in the first direction X, respectively. M source lines S (S1 to Sm) extending along a second direction Y orthogonal to each other, the switching element SW electrically connected to the gate line G and the source line S in each pixel PX, and each pixel PX , The pixel electrode PE electrically connected to the switching element SW, the common electrode CE facing the pixel electrode PE, and the like are provided.

  The common electrode CE is formed in common across the plurality of pixels PX. The pixel electrode PE is formed in an island shape in each pixel PX.

  Each gate line G is drawn outside the active area ACT and connected to the gate driver GD. Each source line S is drawn outside the active area ACT and connected to the source driver SD. Each capacitance line C is drawn out of the active area ACT and is electrically connected to a voltage application unit VCS to which an auxiliary capacitance voltage is supplied. The common electrode CE is electrically connected to a power supply unit VS to which a common voltage is supplied. For example, at least a part of the gate driver GD and the source driver SD is formed on the array substrate AR, and is connected to the driving IC chip 2. In the illustrated example, the driving IC chip 2 as a signal source necessary for driving the liquid crystal display panel LPN is mounted on the array substrate AR outside the active area ACT of the liquid crystal display panel LPN.

  Further, the liquid crystal display panel LPN of the illustrated example has a configuration applicable to the FFS mode or the IPS mode, and includes a pixel electrode PE and a common electrode CE on the array substrate AR. In the liquid crystal display panel LPN having such a configuration, a horizontal electric field (for example, an electric field substantially parallel to the main surface of the substrate in the fringe electric field) formed between the pixel electrode PE and the common electrode CE is mainly used. The liquid crystal molecules constituting the liquid crystal layer LQ are switched.

  FIG. 2 is a schematic plan view of the structure of the pixel PX in the array substrate AR shown in FIG. 1 as viewed from the counter substrate CT side. Here, only main parts necessary for the description are shown.

  The gate lines G1 and G2 extend along the first direction X, respectively. Such gate lines G1 and G2 are arranged along the second direction Y at the first pitch. The source lines S1 and S2 extend along the second direction Y, respectively. Such source lines S1 and S2 are arranged along the first direction X at a second pitch smaller than the first pitch. The pixel PX defined by the gate lines G1 and G2 and the source lines S1 and S2 has a vertically long rectangular shape whose length along the first direction X is shorter than the length along the second direction Y. That is, the length of the pixel PX along the second direction Y corresponds to the first pitch between the gate lines, and the length of the pixel PX along the first direction X corresponds to the second pitch between the source lines.

  Although illustration of the switching element is omitted in the figure, in the pixel PX on the left side in the figure, for example, the switching element is arranged near the intersection of the gate wiring G2 and the source wiring S1, and the gate The wiring G2 and the source wiring S1 are electrically connected.

  The common electrode CE extends along the first direction X. That is, the common electrode CE is disposed in each pixel PX and is formed in common over a plurality of pixels PX adjacent to each other in the first direction X across the source line S.

  The pixel electrode PE of each pixel PX is disposed above the common electrode CE. Each pixel electrode PE is formed in an island shape corresponding to a rectangular pixel shape in each pixel PX. In the illustrated example, the pixel electrode PE is formed in a substantially rectangular shape having a short side along the first direction X and a long side along the second direction Y. Each pixel electrode PE has a plurality of slits PSL facing the common electrode CE. In the illustrated example, each of the slits PSL extends along the second direction Y and has a long axis parallel to the second direction Y. Focusing on the positional relationship between the pixel electrode PE and the source wirings S1 and S2, the slits PSL of the pixel electrode PE are both located between the source wiring S1 and the source wiring S2. Further, all the slits PSL are located above the common electrode CE.

  FIG. 3 is a diagram schematically showing a cross-sectional structure of the liquid crystal display panel LPN shown in FIG.

  That is, the array substrate AR is formed by using a first insulating substrate 10 having light transparency such as a glass substrate. The array substrate AR includes a switching element SW, a common electrode CE, a pixel electrode PE, and the like on the inner surface 10A of the first insulating substrate 10 (that is, the side facing the counter substrate CT).

  The switching element SW shown here is, for example, a thin film transistor (TFT). The switching element SW includes a semiconductor layer formed of polysilicon or amorphous silicon. The switching element SW may be either a top gate type or a bottom gate type, but the top gate type is adopted in the illustrated example.

  In other words, the switching element SW includes a semiconductor layer SC made of polysilicon disposed on the first insulating substrate 10. An undercoat layer made of an insulating film may be interposed between the first insulating substrate 10 and the semiconductor layer SC. The semiconductor layer SC is covered with the first insulating film 11. The first insulating film 11 is also disposed on the first insulating substrate 10.

  The gate electrode WG of the switching element SW is formed on the first insulating film 11 and is located immediately above the semiconductor layer SC. The gate electrode WG is electrically connected to a gate wiring (not shown) and is covered with the second insulating film 12. The second insulating film 12 is also disposed on the first insulating film 11.

  The source electrode WS and the drain electrode WD of the switching element SW are formed on the second insulating film 12. Similarly, the source lines S1 and S2 are formed on the second insulating film 12. The source electrode WS is electrically connected to the source line S1. The source electrode WS and the drain electrode WD are in contact with the semiconductor layer SC through contact holes that penetrate the first insulating film 11 and the second insulating film 12, respectively. The switching element SW having such a configuration is covered with the third insulating film 13 together with the source lines S1 and S2. The third insulating film 13 is also disposed on the second insulating film 12. In the third insulating film 13, a first contact hole CH1 penetrating to the drain electrode WD is formed. Such a third insulating film 13 functions as a first interlayer insulating film that covers the switching element SW. The third insulating film 13 is made of, for example, a transparent resin material.

  The common electrode CE is formed on the third insulating film 13. The common electrode CE does not extend to the first contact hole CH1 formed in the third insulating film 13. Such a common electrode CE is formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). A fourth insulating film 14 is disposed on the common electrode CE. The fourth insulating film 14 is also disposed on the third insulating film 13.

  In the fourth insulating film 14, a plurality of through holes TH penetrating to the common electrode CE are formed between the source wiring S <b> 1 and the source wiring S <b> 2. The through hole TH is formed corresponding to a slit PSL of the pixel electrode PE described later, and extends linearly along the second direction Y. Such a through hole TH has a diameter or width that decreases from the upper surface 14T of the fourth insulating film 14 downward, that is, toward the common electrode CE, for example. In other words, the fourth insulating film 14 located between the through holes TH is formed in a tapered shape whose width decreases from the surface in contact with the common electrode CE toward the upper surface 14T. Note that the upper surface 14T of the fourth insulating film 14 located between the through holes TH is substantially flat.

  The fourth insulating film 14 covers a part of the first contact hole CH1. In a portion of the fourth insulating film 14 covering the first contact hole CH1, a second contact hole CH2 penetrating to the drain electrode WD is formed. Such a fourth insulating film 14 functions as a second interlayer insulating film. The fourth insulating film 14 is made of, for example, silicon nitride (SiNx).

  The pixel electrode PE is formed on the fourth insulating film 14 and faces the common electrode CE. The pixel electrode PE is electrically connected to the drain electrode WD of the switching element SW through the first contact hole CH1 that penetrates the third insulating film 13 and the second contact hole CH2 that penetrates the fourth insulating film 14. Yes. In the pixel electrode PE, a slit PSL is formed on the through hole TH of the fourth insulating film 14. That is, the pixel electrode PE is located on the upper surface 14T of the fourth insulating film 14, but does not extend to the through hole TH. Therefore, in the through hole TH, the common electrode CE is exposed from the fourth insulating film 14 and the pixel electrode PE. The pixel electrode PE is formed of a transparent conductive material, for example, ITO or IZO.

  Note that the through hole TH of the fourth insulating film 14 and the slit PSL of the pixel electrode PE can be collectively formed by a technique such as etching.

  Such a pixel electrode PE is covered with the first alignment film AL1. The first alignment film AL1 also covers the common electrode CE exposed from the fourth insulating film 14 in the through hole TH. Such a first alignment film AL1 is formed of a material exhibiting horizontal alignment and is disposed on a surface in contact with the liquid crystal layer LQ of the array substrate AR.

  On the other hand, the counter substrate CT is formed using a second insulating substrate 30 having optical transparency such as a glass substrate. The counter substrate CT includes a black matrix 31, a color filter 32, an overcoat layer 33, and the like that partition each pixel PX on the inner surface 30A of the second insulating substrate 30 (that is, the side facing the array substrate AR).

  The black matrix 31 is formed on the inner surface 30 </ b> A of the second insulating substrate 30 so as to face the gate wiring G and the source wiring S provided on the array substrate AR, and further to the wiring section such as the switching element SW.

  The color filter 32 is formed on the inner surface 30 </ b> A of the second insulating substrate 30 and extends also on the black matrix 31. The color filter 32 is formed of a resin material colored in a plurality of different colors, for example, three primary colors such as red, blue, and green. The boundary between the color filters 32 of different colors is located on the black matrix 31.

  The overcoat layer 33 covers the color filter 32. The overcoat layer 33 flattens the surface irregularities of the black matrix 31 and the color filter 32. Such an overcoat layer 33 is formed of a transparent resin material. The overcoat layer 33 is covered with the second alignment film AL2. The second alignment film AL2 is formed of a material exhibiting horizontal alignment, and is disposed on the surface in contact with the liquid crystal layer LQ of the counter substrate CT.

  The array substrate AR and the counter substrate CT as described above are arranged so that the first alignment film AL1 and the second alignment film AL2 face each other. At this time, a predetermined cell gap is formed between the array substrate AR and the counter substrate CT by columnar spacers formed on one substrate. The array substrate AR and the counter substrate CT are bonded together with a sealing material in a state where a cell gap is formed. The liquid crystal layer LQ is composed of a liquid crystal composition including liquid crystal molecules LM sealed in a cell gap formed between the first alignment film AL1 of the array substrate AR and the second alignment film AL2 of the counter substrate CT. ing.

  A backlight BL is arranged on the back side of the liquid crystal display panel LPN having such a configuration. As the backlight BL, various forms are applicable, and any of those using a light emitting diode (LED) or a cold cathode tube (CCFL) as a light source can be applied. The description of the structure is omitted.

  On the outer surface of the array substrate AR, that is, the outer surface 10B of the first insulating substrate 10, the first optical element OD1 including the first polarizing plate PL1 is disposed. The second optical element OD2 including the second polarizing plate PL2 is disposed on the outer surface of the counter substrate CT, that is, the outer surface 30B of the second insulating substrate 30. The first polarizing axis (or first absorption axis) of the first polarizing plate PL1 and the second polarizing axis (or second absorption axis) of the second polarizing plate PL2 are in a crossed Nicols positional relationship, for example.

  As shown in FIG. 2, the first alignment film AL1 and the second alignment film AL2 are aligned in directions parallel to each other in a plane parallel to the main surface of the substrate (or the XY plane) (for example, light Orientation treatment). The first alignment film AL1 is subjected to an alignment process along a direction intersecting an acute angle of 45 ° or less with respect to the major axis of the slit PSL (second direction Y in the example shown in FIG. 2). The alignment treatment direction R1 of the first alignment film AL1 is, for example, a direction that intersects the second direction Y in which the slits PSL extend with an angle of 5 ° to 15 °. Further, the second alignment film AL2 is subjected to an alignment process along a direction parallel to the alignment processing direction R1 of the first alignment film AL1. The alignment treatment direction R1 of the first alignment film AL1 and the alignment treatment direction R2 of the second alignment film AL2 are opposite to each other.

  At this time, the first polarizing axis of the first polarizing plate PL1 is set, for example, in an orientation parallel to the alignment processing direction R1 of the first alignment film AL1, and the second polarizing axis of the second polarizing plate PL2 is The orientation is set to be orthogonal to the alignment treatment direction R1 of the one alignment film AL1.

  The second alignment film AL2 is substantially flat over substantially the entire area of the active area ACT, and a substantially uniform alignment process is possible by a rubbing process. On the other hand, the first alignment film AL1 is stacked on the portion stacked on the pixel electrode PE located on the upper surface 14T of the fourth insulating film 14 and the common electrode CE exposed in the through hole TH of the fourth insulating film 14. Since there is a difference in level between the portions and there is a possibility that the alignment treatment cannot be uniformly performed by the rubbing treatment, it is desirable to apply a photo-alignment treatment as a method of the alignment treatment.

  4 is a cross-sectional view in which the path from the common electrode CE to the pixel electrode PE in FIG. 3 is developed along the line AB in the drawing. (A) in the figure corresponds to this embodiment, and corresponds to a cross-sectional view of a path from the common electrode CE to the pixel electrode PE through the through hole TH and the slit PSL, and (B) in the figure is This corresponds to a comparative example in which a through hole reaching the common electrode CE is not formed in the fourth insulating film 14 positioned immediately below the slit PSL, and reaches the pixel electrode PE from the common electrode CE through the fourth insulating film 14 and the slit PSL. It corresponds to a cross-sectional view of the route up to.

  In the present embodiment shown in (A), only the first alignment film AL1 is interposed between the liquid crystal layer LQ and the pixel electrode PE, and the first alignment film is also interposed between the liquid crystal layer LQ and the common electrode CE. Only AL1 is present. That is, the common electrode CE and the pixel electrode PE have a symmetrical electrode structure with respect to the liquid crystal layer LQ.

  For this reason, even if the impurity ions contained in the liquid crystal layer LQ are adsorbed on the surface of the first alignment film AL1 or the first alignment film AL1 is charged up, both the pixel electrode side and the common electrode side are the same. This causes the injection or discharge of electric charges. Thereby, in a state where no voltage is applied between the pixel electrode and the common electrode, it is possible to suppress the application of DC due to the asymmetry of charges.

  On the other hand, in the comparative example shown in (B), only the first alignment film AL1 is interposed between the liquid crystal layer LQ and the pixel electrode PE, whereas between the liquid crystal layer LQ and the common electrode CE. Is interposed by the fourth insulating film 14 and the first alignment film AL1. That is, the common electrode CE and the pixel electrode PE have an asymmetric electrode structure with respect to the liquid crystal layer LQ.

  For this reason, as described above, the charge tends to decrease on the pixel electrode side, while the charge tends to accumulate on the common electrode side. As a result, even when no voltage is applied between the pixel electrode and the common electrode, a state in which DC is applied due to charge asymmetry is formed.

  That is, in a configuration in which the fourth insulating film is interposed as an interlayer insulating film between the common electrode CE and the pixel electrode PE, and the pixel electrode PE and its slit PSL are located immediately above the common electrode CE, the fourth insulating film 14 In addition, if the through hole TH corresponding to the slit PSL is not provided, the pixel electrode PE and the common electrode CE have an asymmetric electrode structure, which causes a problem inherent to this structure (application of DC). Therefore, the through hole TH corresponding to the slit PSL is formed in the fourth insulating film 14, and the pixel electrode PE and the common electrode have a symmetrical electrode structure, so that the inherent problem can be solved.

  The operation of the liquid crystal display device having the above configuration will be described below.

  When the voltage that forms a potential difference is not applied between the pixel electrode PE and the common electrode CE, the voltage is not applied to the liquid crystal layer LQ when the voltage is not applied, and the pixel electrode PE and the common electrode CE No electric field is formed between the two. Therefore, the liquid crystal molecules LM included in the liquid crystal layer LQ are aligned in the alignment treatment directions (R1 and R2) of the first alignment film AL1 and the second alignment film AL2 in the XY plane as shown by the solid line in FIG. (The direction in which the liquid crystal molecules LM are initially aligned is referred to as the initial alignment direction).

  When OFF, a part of the backlight light from the backlight BL is transmitted through the first polarizing plate PL1 and enters the liquid crystal display panel LPN. The light incident on the liquid crystal display panel LPN is linearly polarized light orthogonal to the first polarization axis of the first polarizing plate PL1. Such a polarization state of linearly polarized light hardly changes when it passes through the liquid crystal display panel LPN in the OFF state. Therefore, the linearly polarized light transmitted through the liquid crystal display panel LPN is absorbed by the second polarizing plate PL2 having a crossed Nicol positional relationship with the first polarizing plate PL1 (black display).

  In addition, during this OFF, the application of DC due to charge asymmetry is suppressed between the pixel electrode and the common electrode, so that it is possible to suppress the occurrence of display defects such as so-called burn-in, and sufficient transmittance or luminance It is possible to realize a black display in which the decrease is caused. In addition, since the luminance during black display can be sufficiently reduced, the contrast ratio can be improved.

  On the other hand, when a voltage that forms a potential difference is applied between the pixel electrode PE and the common electrode CE, the voltage is applied to the liquid crystal layer LQ, and the pixel electrode PE and the common electrode CE A fringe electric field is formed in between. For this reason, the liquid crystal molecules LM are aligned in an azimuth different from the initial alignment direction in the XY plane, as indicated by a broken line in FIG. In the positive type liquid crystal material, the liquid crystal molecules LM are aligned in a direction substantially parallel to the electric field (that is, a direction substantially orthogonal to the major axis of the slit PSL).

  At such ON time, linearly polarized light orthogonal to the first polarization axis of the first polarizing plate PL1 is incident on the liquid crystal display panel LPN, and the polarization state is the alignment state of the liquid crystal molecules LM when passing through the liquid crystal layer LQ. It changes according to. For this reason, at the time of ON, at least a part of light that has passed through the liquid crystal layer LQ is transmitted through the second polarizing plate PL2 (white display).

  As described above, according to this embodiment, a liquid crystal display device capable of improving display quality can be provided.

  In addition, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  For example, in the above embodiment, the slit PSL of the pixel electrode PE is formed to have a long axis parallel to the second direction Y, but may be formed to have a long axis parallel to the first direction X. It may be formed so as to have a long axis parallel to a direction intersecting the first direction X and the second direction Y, or may be formed in a shape bent in a dogleg shape.

LPN ... Liquid crystal display panel AR ... Array substrate CT ... Counter substrate PE ... Pixel electrode PSL ... Slit CE ... Common electrode LQ ... Liquid crystal layer LM ... Liquid crystal molecule 14 ... Fourth insulating film TH ... Through-hole

Claims (5)

Insulation in which a switching element disposed in each pixel, a common electrode formed over a plurality of pixels, and an insulating film disposed on the common electrode and having a through-hole penetrating to the common electrode A pixel electrode electrically connected to the switching element and formed on each of the pixels on the insulating film and facing the common electrode and having a slit formed on the through hole; A first substrate that includes a pixel electrode and a first alignment film that covers the common electrode exposed from the insulating film through the through hole;
A second substrate comprising a second alignment film facing the first alignment film;
A liquid crystal layer held between the first alignment film of the first substrate and the second alignment film of the second substrate;
A liquid crystal display device comprising:   The first alignment film is aligned in a direction intersecting the major axis of the slit, and the second alignment film is aligned in a direction opposite to and parallel to the alignment direction of the first alignment film. The liquid crystal display device according to claim 1. A gate line extending along the first direction, a first source line and a second source line extending along a second direction orthogonal to the first direction, the gate line and the first source line, An electrically connected switching element, a first interlayer insulating film covering the switching element, a common electrode formed on the first interlayer insulating film, and on the first interlayer insulating film and the common electrode A second interlayer insulating film having a through-hole formed between the first source wiring and the second source wiring and penetrating to the common electrode; and penetrating the first interlayer insulating film and the second interlayer insulating film A pixel electrode electrically connected to the switching element through a contact hole and facing the common electrode on the second interlayer insulating film and having a slit formed in the through hole; A first alignment film in serial pixel electrodes and the through-hole covering the common electrode exposed from the second interlayer insulating film, a first substrate having a
A second substrate comprising a second alignment film facing the first alignment film;
A liquid crystal layer held between the first alignment film of the first substrate and the second alignment film of the second substrate;
A liquid crystal display device comprising: The long axis of the slit is parallel to the second direction,
The first alignment film is subjected to an alignment process in a direction crossing a second direction, and the second alignment film is subjected to an alignment process in a direction parallel to and opposite to the alignment process direction of the first alignment film. The liquid crystal display device according to claim 3.   The liquid crystal display device according to claim 1, wherein the first alignment film is subjected to a photo-alignment process.

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