JP2013029784A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device capable of suppressing deterioration of display quality.SOLUTION: A liquid crystal display device comprises: a first base plate which includes first pixel electrodes having linearly extending belt-like first main pixel electrodes and first common electrodes having first main common electrodes extending substantially in parallel with the first main pixel electrode on both sides across the first main pixel electrode; a second base plate which includes second pixel electrodes having second main pixel electrodes facing the first main pixel electrodes and electrically connected to the first pixel electrodes and second common electrodes having second main common electrodes facing the first main common electrodes and electrically connected to the first common electrodes; and a liquid crystal layer which includes liquid crystal molecules held between the first base plate and the second base plate.

Description

  Embodiments described herein relate generally to a liquid crystal display device.

  2. Description of the Related Art In recent years, flat display devices have been actively developed. In particular, liquid crystal display devices have attracted particular attention because of their advantages such as light weight, thinness, and low power consumption. In particular, an active matrix liquid crystal display device in which a switching element is incorporated in each pixel has a structure using a lateral electric field (including a fringe electric field) such as an IPS (In-Plane Switching) mode or an FFS (Fringe Field Switching) mode. Attention has been paid. Such a horizontal electric field mode liquid crystal display device includes a pixel electrode and a counter electrode formed on an array substrate, and switches liquid crystal molecules with a horizontal electric field substantially parallel to the main surface of the array substrate.

  On the other hand, a technique for switching liquid crystal molecules by forming a lateral electric field or an oblique electric field between a pixel electrode formed on an array substrate and a counter electrode formed on the counter substrate has been proposed.

JP 2009-192822 A JP 09-160041 A

  An object of the present embodiment is to provide a liquid crystal display device capable of suppressing deterioration in display quality.

According to this embodiment,
A first pixel electrode provided with a linearly extending strip-shaped first main pixel electrode, and a first main common extending substantially parallel to the first main pixel electrode on both sides of the first main pixel electrode A first substrate having a first common electrode having an electrode; a second pixel electrode having a second main pixel electrode opposed to the first main pixel electrode and electrically connected to the first pixel electrode; A second substrate having a second main common electrode opposed to the first main common electrode and electrically connected to the first common electrode, the first substrate, and the second substrate There is provided a liquid crystal display device comprising: a liquid crystal layer including liquid crystal molecules held between the second substrate.

According to this embodiment,
A first pixel electrode provided with a linearly extending strip-shaped first main pixel electrode, and a first main common extending substantially parallel to the first main pixel electrode on both sides of the first main pixel electrode A first common electrode having an electrode; a conductive member in contact with the first pixel electrode; and a first alignment film that covers the first pixel electrode and the first common electrode and exposes the conductive member. A first substrate, a second pixel electrode having a second main pixel electrode facing the first main pixel electrode, contacting the conductive member, and a second main common electrode facing the first main common electrode. A second substrate comprising: a second common electrode electrically connected to the first common electrode; and a second alignment film covering the second pixel electrode and the second common electrode and exposing the conductive member. And liquid crystal molecules held between the first substrate and the second substrate The liquid crystal display device characterized by comprising a liquid crystal layer comprising is provided.

According to this embodiment,
A columnar spacer, a first pixel electrode having a strip-shaped first main pixel electrode extending linearly and covering the columnar spacer, and substantially parallel to the first main pixel electrode on both sides of the first main pixel electrode A first common electrode including a first main common electrode extending in a first direction, and a first orientation that exposes the first pixel electrode that covers the first pixel electrode and the first common electrode and covers the top surface of the columnar spacer. A first substrate having a film; a second pixel electrode having a second main pixel electrode facing the first main pixel electrode; and contacting the first pixel electrode exposed from the first alignment film; A second common electrode having a second main common electrode facing the first main common electrode and electrically connected to the first common electrode; covering the second pixel electrode and the second common electrode; A contact portion of the pixel electrode with the first pixel electrode; A liquid crystal display, comprising: a second substrate including a second alignment film that exits; and a liquid crystal layer including liquid crystal molecules held between the first substrate and the second substrate. An apparatus is provided.

FIG. 1 is a diagram schematically showing a configuration and an equivalent circuit of a liquid crystal display device according to the present embodiment. FIG. 2 is a plan view schematically showing a structure example of one pixel when the liquid crystal display panel shown in FIG. 1 is viewed from the counter substrate side. FIG. 3 is a cross-sectional view schematically showing a cross-sectional structure when the liquid crystal display panel shown in FIG. 2 is cut along line AA. 4 is a cross-sectional view schematically showing a cross-sectional structure when the liquid crystal display panel shown in FIG. 2 is cut along line BB. FIG. 5 is a cross-sectional view schematically showing a cross-sectional structure when the liquid crystal display panel shown in FIG. 2 is cut along line CC. FIG. 6 is a diagram for explaining the cross-sectional structure of the liquid crystal display panel of the comparative example and the relationship of the electric field formed between the first main pixel electrode and the second main common electrode. FIG. 7 is a cross-sectional view schematically showing a cross-sectional structure along the first direction of the liquid crystal display panel including a connection portion between the first pixel electrode and the second pixel electrode. FIG. 8 is a cross-sectional view schematically showing a cross-sectional structure along the second direction of the liquid crystal display panel including a connection portion between the first pixel electrode and the second pixel electrode. FIG. 9 is a cross-sectional view schematically showing a cross-sectional structure along the first direction of the liquid crystal display panel including a connection portion between the first common electrode and the second common electrode. FIG. 10 is a cross-sectional view schematically showing a cross-sectional structure along the second direction Y of the liquid crystal display panel including a connection portion between the first common electrode and the second common electrode.

  Hereinafter, the present embodiment will be described in detail with reference to the drawings. In each figure, the same reference numerals are given to components that exhibit the same or similar functions, and duplicate descriptions are omitted.

  FIG. 1 is a diagram schematically showing a configuration and an equivalent circuit of a liquid crystal display device according to the present embodiment.

  That is, the liquid crystal display device includes an active matrix type liquid crystal display panel LPN. The liquid crystal display panel LPN is held between the array substrate AR, which is the first substrate, the counter substrate CT, which is the second substrate disposed to face the array substrate AR, and the array substrate AR and the counter substrate CT. Liquid crystal layer LQ. Such a liquid crystal display panel LPN includes an active area ACT for displaying an image. This active area ACT is composed of a plurality of pixels PX arranged in an m × n matrix (where m and n are positive integers).

  In the active area ACT, the liquid crystal display panel LPN includes n gate lines G (G1 to Gn), n auxiliary capacitance lines C (C1 to Cn), m source lines S (S1 to Sm), and the like. ing. For example, the gate line G and the auxiliary capacitance line C extend substantially linearly along the first direction X. These gate lines G and storage capacitor lines C are alternately arranged in parallel along a second direction Y that intersects the first direction X. Here, the first direction X and the second direction Y are substantially orthogonal to each other. The source line S intersects with the gate line G and the auxiliary capacitance line C. The source line S extends substantially linearly along the second direction Y. Note that the gate wiring G, the auxiliary capacitance line C, and the source wiring S do not necessarily extend linearly, and some of them may be bent.

  Each gate line G is drawn outside the active area ACT and connected to the gate driver GD. Each source line S is drawn outside the active area ACT and connected to the source driver SD. At least a part of the gate driver GD and the source driver SD is formed on, for example, the array substrate AR, and is connected to the driving IC chip 2 with a built-in controller.

  Each pixel PX includes a switching element SW, a pixel electrode PE, a common electrode CE, and the like. The storage capacitor Cs is formed, for example, between the storage capacitor line C and the pixel electrode PE. The auxiliary capacitance line C is electrically connected to a voltage application unit VCS to which an auxiliary capacitance voltage is applied.

  In the present embodiment, the liquid crystal display panel LPN has a configuration in which the pixel electrode PE is formed on the array substrate AR while at least a part of the common electrode CE is formed on the counter substrate CT. The liquid crystal molecules in the liquid crystal layer LQ are switched mainly using an electric field formed between the PE and the common electrode CE. The electric field formed between the pixel electrode PE and the common electrode CE is an oblique electric field (or slightly inclined with respect to the XY plane or the substrate main surface defined by the first direction X and the second direction Y) (or , A transverse electric field substantially parallel to the main surface of the substrate).

  The switching element SW is constituted by, for example, an n-channel thin film transistor (TFT). The switching element SW is electrically connected to the gate line G and the source line S. Such a switching element SW may be either a top gate type or a bottom gate type. In addition, the semiconductor layer of the switching element SW is formed of, for example, polysilicon, but may be formed of amorphous silicon.

  The pixel electrode PE is disposed in each pixel PX and is electrically connected to the switching element SW. The common electrode CE is disposed in common to the pixel electrodes PE of the plurality of pixels PX via the liquid crystal layer LQ. The pixel electrode PE and the common electrode CE are formed of a light-transmitting conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). You may form with another metal material.

  The array substrate AR includes a power feeding unit VS for applying a voltage to the common electrode CE. For example, the power supply unit VS is formed outside the active area ACT. The common electrode CE is drawn out of the active area ACT and is electrically connected to the power supply unit VS via a conductive member (not shown).

  FIG. 2 is a plan view schematically showing a structural example of one pixel PX when the liquid crystal display panel LPN shown in FIG. 1 is viewed from the counter substrate side. Here, a plan view in the XY plane is shown. Note that, here, the configuration of the array substrate AR and the configuration of the counter substrate CT are intentionally shifted, but originally the first pixel electrode PE1 of the array substrate AR is the second pixel electrode of the counter substrate CT. Almost overlaps with PE2 (or the second pixel electrode PE2 is located immediately above the first pixel electrode PE1), and the first common electrode CE1 of the array substrate AR substantially overlaps the second common electrode CE2 of the counter substrate CT (or The second common electrode CE2 is located immediately above the first common electrode CE1).

  The array substrate AR includes a gate line G1, a gate line G2, an auxiliary capacitance line C1, a source line S1, a source line S2, a switching element (not shown), and the like. The array substrate AR includes a first pixel electrode PE1 having a linearly extending strip-shaped first main pixel electrode PA1, and a first main pixel electrode PA1 on both sides of the first main pixel electrode PA1. A first common electrode CE1 including a first main common electrode CA1 extending substantially in parallel.

  The counter substrate CT includes a second main pixel electrode PA2 that opposes the first main pixel electrode PA1, and a second pixel electrode PE2 that is electrically connected to the first pixel electrode PE1, and the first main common electrode CA1. A second common electrode CE2 including a second main common electrode CA2 and electrically connected to the first common electrode CE1;

  The illustrated pixel PX has a rectangular shape whose length along the first direction X is shorter than the length along the second direction Y, as indicated by a broken line. The gate line G1 and the gate line G2 are adjacent to each other along the second direction Y and extend along the first direction X. The auxiliary capacitance line C1 is disposed between the adjacent gate line G1 and gate line G2, and extends along the first direction X. The source line S1 and the source line S2 are adjacent to each other along the first direction X and extend along the second direction Y.

  In the pixel PX, the source line S1 is disposed at the left end, and the source line S2 is disposed at the right end. Strictly speaking, the source line S1 is disposed across the boundary between the pixel PX and the pixel adjacent to the left side, and the source line S2 is disposed over the boundary between the pixel PX and the pixel adjacent to the right side. Yes. In the pixel PX, the gate line G1 is disposed at the upper end, and the gate line G2 is disposed at the lower end. Strictly speaking, the gate line G1 is disposed over the boundary between the pixel PX and the adjacent pixel on the upper side, and the gate line G2 is disposed over the boundary between the pixel PX and the adjacent pixel on the lower side. ing. The auxiliary capacitance line C1 is disposed at a substantially central portion of the pixel PX.

  The pixel electrode PE includes a first pixel electrode PE1 provided on the array substrate AR and a second pixel electrode PE2 provided on the counter substrate CT. The first pixel electrode PE1 includes a first main pixel electrode PA1 and a first subpixel electrode PB1. The second pixel electrode PE2 includes a second main pixel electrode PA2 and a second subpixel electrode PB2.

  The common electrode CE includes a first common electrode CE1 provided on the array substrate AR and a second common electrode CE2 provided on the counter substrate CT. The first common electrode CE1 includes a first main common electrode CA1. The second common electrode CE2 includes a second main common electrode CA2.

  First, attention is focused on the configuration on the array substrate AR side. The first main pixel electrode PA1 and the first subpixel electrode PB1 are formed integrally or continuously and are electrically connected to each other. The first main pixel electrode PA1 is linear along the second direction Y from the first subpixel electrode PB1 to the vicinity of the upper end and the vicinity of the lower end of the pixel PX between the source line S1 and the source line S2. It extends to. Further, the first main pixel electrode PA1 is disposed at a substantially middle position between the source line S1 and the source line S2, that is, at the center of the pixel PX. Such a first main pixel electrode PA1 is formed in a strip shape having substantially the same width along the first direction X. The distance along the first direction X between the source line S1 and the first main pixel electrode PA1 is substantially the same as the distance along the first direction X between the source line S2 and the first main pixel electrode PA1. The first subpixel electrode PB1 extends linearly along the first direction X. In the illustrated example, an auxiliary capacitance line C1 is disposed immediately below the first subpixel electrode PB1.

  The first main common electrode CA1 extends linearly along a second direction Y substantially parallel to the first main pixel electrode PA1 on both sides of the first main pixel electrode PA1 in the XY plane. . Alternatively, the first main common electrode CA1 faces the source line S and extends substantially parallel to the first main pixel electrode PA1. The first main common electrode CA1 is formed in a strip shape having substantially the same width along the first direction X.

  In the illustrated example, two first main common electrodes CA1 are arranged in parallel and are disposed at both left and right ends of the pixel PX, respectively. Hereinafter, in order to distinguish these first main common electrodes CA1, the first main common electrode on the left side in the figure is referred to as CAL1, and the first main common electrode on the right side in the figure is referred to as CAR1. The first main common electrode CAL1 is opposed to the source line S1, and the first main common electrode CAR1 is opposed to the source line S2. The first main common electrode CAL1 and the first main common electrode CAR1 are electrically connected to each other inside or outside the active area.

  Paying attention to the positional relationship between the first main pixel electrode PA1 and the first main common electrode CA1, a transmissive region is formed between the first main pixel electrode PA1 and the first main pixel electrode PA1 without overlapping each other. The main common electrodes CA1 are alternately arranged along the first direction X. That is, the first main common electrode CAL1, the first main pixel electrode PA1, and the first main common electrode CAR1 are arranged in this order along the first direction X. The distance along the first direction X between the first main common electrode CAL1 and the first main pixel electrode PA1 is substantially the same as the distance along the first direction X between the first main common electrode CAR1 and the first main pixel electrode PA1. It is equivalent.

  On the other hand, paying attention to the configuration on the counter substrate CT side, the second main pixel electrode PA2 and the second subpixel electrode PB2 are formed integrally or continuously and are electrically connected to each other. The second main pixel electrode PA2 is located immediately above the first main pixel electrode PA1, and is linear along the second direction Y from the second subpixel electrode PB2 to the vicinity of the upper end and the vicinity of the lower end of the pixel PX. It extends to. The second main pixel electrode PA2 is formed in a strip shape having substantially the same width along the first direction X.

  The second main common electrode CA2 extends linearly along a second direction Y substantially parallel to the second main pixel electrode PA2 on both sides of the second main pixel electrode PA1 in the XY plane. . The second main common electrode CA2 is formed in a strip shape having substantially the same width along the first direction X.

  In the illustrated example, the two second main common electrodes CA2 are arranged in parallel and are disposed at the left and right ends of the pixel PX, respectively. Hereinafter, in order to distinguish these second main common electrodes CA2, the second main common electrode on the left side in the drawing is referred to as CAL2, and the second main common electrode on the right side in the drawing is referred to as CAR2. The second main common electrode CAL2 faces the first main common electrode CAL1, and the second main common electrode CAR2 faces the first main common electrode CAR1. The second main common electrode CAL2 and the second main common electrode CAR2 are electrically connected to each other inside or outside the active area.

  In the pixel PX, the first main common electrode CAL1 and the second main common electrode CAL2 are arranged at the left end, and the first main common electrode CAR1 and the second main common electrode CAR2 are arranged at the right end. Strictly speaking, the first main common electrode CAL1 and the second main common electrode CAL2 are disposed across the boundary between the pixel PX and the pixel adjacent to the left side, and the first main common electrode CAR1 and the second main common electrode CAR2 are arranged. Are arranged across the boundary between the pixel PX and a pixel adjacent to the right side thereof.

  Paying attention to the positional relationship between the second main pixel electrode PA2 and the second main common electrode CA2, a transmissive region that does not overlap each other and allows light to pass therethrough is formed. The main common electrodes CA2 are alternately arranged along the first direction X. That is, the second main common electrode CAL2, the second main pixel electrode PA2, and the second main common electrode CAR2 are arranged in this order along the first direction X. The distance along the first direction X between the second main common electrode CAL2 and the second main pixel electrode PA2 is substantially the same as the distance along the first direction X between the second main common electrode CAR2 and the second main pixel electrode PA2. It is equivalent.

  In the example shown in FIG. 2, the first conductive member CM1 and the second conductive member CM2 are arranged.

  The first conductive member CM1 is in contact with the first pixel electrode PE1 and the second pixel electrode PE2, and electrically connects the first pixel electrode PE1 and the second pixel electrode PE2. For example, the first conductive member CM1 is disposed between the first subpixel electrode PB1 and the second subpixel electrode PB2 located immediately above the auxiliary capacitance line C1, and the first subpixel electrode PB1 and the second subpixel electrode PB2 are disposed. Each pixel electrode PB2 is contacted. That is, the storage capacitor line C1 passes immediately below the position where the first pixel electrode PE1 and the second pixel electrode PE2 are electrically connected. When both the first pixel electrode PE1 and the second pixel electrode PE2 are formed in a cross shape by the main pixel electrode and the sub-pixel electrode, the first conductive member CM1 is arranged at the center portion of the cross, that is, the first main pixel electrode. And the second subpixel electrode are arranged at the intersection. When the first conductive member CM1 is arranged in this way, even if a deviation occurs between the substrates in the manufacturing process of bonding the array substrate AR and the counter substrate CT, the first main pixel electrode or the second subpixel electrode is not affected. Since the conductive member CM1 is disposed, the upper and lower electrodes can be reliably electrically connected.

Note that the gate wiring may be configured to pass directly under the position where the first pixel electrode PE1 and the second pixel electrode PE2 are electrically connected.

  The second conductive member CM2 is in contact with the first common electrode CE1 and the second common electrode CE2, and electrically connects the first common electrode CE1 and the second common electrode CE2. For example, the second conductive member CM2 is disposed immediately above the intersection between the gate line G1 and the source line S1.

  The first conductive member CM1 and the second conductive member CM2 are formed of, for example, a paste-like conductive material. The first conductive member CM1 and the second conductive member CM2 may also have a function as a spacer for forming a cell gap between the array substrate AR and the counter substrate CT.

  Alignment films AL1 and AL2 are not disposed on the electrode portions in contact with the first conductive member CM1 and the second conductive member CM2 in order to conduct. Thus, a portion without an alignment film is generated for each pixel, but patterning is possible by applying the alignment film by inkjet. In the case of patterning, the portion without the alignment film may be made larger than the portion where the conductive member is in contact with the pixel electrode or the common electrode in consideration of the accuracy of bonding between the substrates.

  FIG. 3 is a cross-sectional view schematically showing a cross-sectional structure when the liquid crystal display panel LPN shown in FIG. 2 is cut along line AA. Here, only parts necessary for the description are shown.

  A backlight 4 is disposed on the back side of the array substrate AR constituting the liquid crystal display panel LPN. As the backlight 4, various forms are applicable, and any of those using a light emitting diode (LED) or a cold cathode tube (CCFL) as a light source can be applied. The description of the structure is omitted.

  The array substrate AR is formed using a first insulating substrate 10 having light transparency. The source wiring S1 and the source wiring S2 are formed on the first interlayer insulating film 11 and covered with the second interlayer insulating film 12. Note that gate wirings and auxiliary capacitance lines (not shown) are disposed between the first insulating substrate 10 and the first interlayer insulating film 11, for example.

  The first main pixel electrode PA1, the first main common electrode CAL1, and the first main common electrode CAR1 are formed on the second interlayer insulating film 12. The first main common electrode CAL1 is located immediately above the source line S1, and the first main common electrode CAR1 is located immediately above the source line S2. In other words, the source line S1 is disposed immediately below the first main common electrode CAL1, and the source line S2 is disposed immediately below the first main common electrode CAR1. The first main pixel electrode PA1 is spaced apart from the first main common electrode CAL1 and the first main common electrode CAR1, and is located on the inner side of the source line S1 and the source line S2 above the respective positions.

  The first alignment film AL1 is disposed on the surface of the array substrate AR that faces the counter substrate CT, and extends over substantially the entire active area ACT. The first alignment film AL1 covers the first main pixel electrode PA1, the first main common electrode CAL1, the first main common electrode CAR1, and the like, and is also disposed on the second interlayer insulating film 12. Such a first alignment film AL1 is formed of a material exhibiting horizontal alignment.

  The counter substrate CT is formed by using a second insulating substrate 20 having optical transparency. The black matrix BM partitions each pixel PX and forms an opening AP. That is, the black matrix BM is disposed so as to face the wiring portions such as the source wiring, the gate wiring, the auxiliary capacitance line, and the switching element. Here, only the portion extending along the second direction Y is illustrated, but the black matrix BM may include a portion extending along the first direction X. The black matrix BM is disposed on the inner surface 20A of the second insulating substrate 20 facing the array substrate AR.

  The color filter CF is arranged corresponding to each pixel PX. That is, the color filter CF is disposed in the opening AP in the inner surface 20A of the second insulating substrate 20, and a part of the color filter CF runs on the black matrix BM. The color filters CF arranged in the pixels PX adjacent to each other in the first direction X have different colors. For example, the color filter CF is formed of resin materials colored in three primary colors such as red, blue, and green. A red color filter made of a resin material colored in red is arranged corresponding to the red pixel. A blue color filter made of a resin material colored in blue is arranged corresponding to a blue pixel. A green color filter made of a resin material colored in green is arranged corresponding to the green pixel. The boundary between these color filters CF is at a position overlapping the black matrix BM.

  The overcoat layer OC covers the color filter CF. This overcoat layer OC alleviates the influence of irregularities on the surface of the color filter CF.

  The second main pixel electrode PA2, the second main common electrode CAL2, and the second main common electrode CAR2 are formed on the side of the overcoat layer OC that faces the array substrate AR. The second main pixel electrode PA2 is located immediately above the first main pixel electrode PA1. The second main common electrode CAL2 is located immediately above the first main common electrode CAL1, and is located directly below the black matrix BM. The second main common electrode CAR2 is located immediately above the first main common electrode CAR1, and is located directly below the black matrix BM.

  The width along the first direction X of the first main common electrode CAL1 and the second main common electrode CAL2 is substantially equal to the width of the black matrix BM located immediately above them. The widths of the first main common electrode CAR1 and the second main common electrode CAR2 along the first direction X are substantially equal to the width of the black matrix BM located immediately above them.

  In the opening AP, between the first main common electrode CAL1 and the first main common electrode CAR1 and the first main pixel electrode PA1, and the second main common electrode CAL2, the second main common electrode CAR2, and the second main pixel electrode. The area between PA1 corresponds to a transmission area through which light can be transmitted.

  The second alignment film AL2 is disposed on the surface of the counter substrate CT facing the array substrate AR, and extends over substantially the entire active area ACT. The second alignment film AL2 covers the second main pixel electrode PA2, the second main common electrode CAL2, the second main common electrode CAR2, the overcoat layer OC, and the like. Such a second alignment film AL2 is formed of a material exhibiting horizontal alignment.

  The first alignment film AL1 and the second alignment film AL2 are subjected to alignment treatment (for example, rubbing treatment or photo-alignment treatment) for initial alignment of the liquid crystal molecules of the liquid crystal layer LQ. The first alignment treatment direction PD1 in which the first alignment film AL1 initially aligns liquid crystal molecules and the second alignment treatment direction PD2 in which the second alignment film AL2 initially aligns liquid crystal molecules are parallel to each other and opposite to each other. Or the same direction. For example, the first alignment processing direction PD1 and the second alignment processing direction PD2 are substantially parallel to and in the same direction as the second direction Y in the XY plane, as shown in FIG.

  The array substrate AR and the counter substrate CT as described above are arranged so that the first alignment film AL1 and the second alignment film AL2 face each other. At this time, between the first alignment film AL1 of the array substrate AR and the second alignment film AL2 of the counter substrate CT, for example, a columnar spacer integrally formed on one substrate by a resin material is disposed. As a result, a predetermined cell gap, for example, a cell gap of 2 to 7 μm is formed. As described above, the first conductive member CM1 and the second conductive member CM2 may be columnar spacers. The array substrate AR and the counter substrate CT are bonded to each other with a sealing material outside the active area ACT in a state where a predetermined cell gap is formed.

  The liquid crystal layer LQ is held in a cell gap formed between the array substrate AR and the counter substrate CT, and is disposed between the first alignment film AL1 and the second alignment film AL2. Such a liquid crystal layer LQ is made of, for example, a liquid crystal material having a positive dielectric anisotropy (positive type).

  The first optical element OD1 is attached to the outer surface of the array substrate AR, that is, the outer surface 10B of the first insulating substrate 10 constituting the array substrate AR with an adhesive or the like. The first optical element OD1 is located on the side facing the backlight 4 of the liquid crystal display panel LPN, and controls the polarization state of incident light incident on the liquid crystal display panel LPN from the backlight 4. The first optical element OD1 includes a first polarizing plate PL1 having a first polarization axis (or first absorption axis) AX1.

  The second optical element OD2 is attached to the outer surface of the counter substrate CT, that is, the outer surface 20B of the second insulating substrate 20 constituting the counter substrate CT with an adhesive or the like. The second optical element OD2 is located on the display surface side of the liquid crystal display panel LPN, and controls the polarization state of the outgoing light emitted from the liquid crystal display panel LPN. The second optical element OD2 includes a second polarizing plate PL2 having a second polarization axis (or second absorption axis) AX2.

  The first polarizing axis AX1 of the first polarizing plate PL1 and the second polarizing axis AX2 of the second polarizing plate PL2 are, for example, in an orthogonal positional relationship (crossed Nicols). At this time, for example, one polarizing plate is arranged so that the polarization axis thereof is parallel or orthogonal to the initial alignment direction of the liquid crystal molecules, that is, the first alignment processing direction PD1 or the second alignment processing direction PD2. When the initial alignment direction is parallel to the second direction Y, the polarization axis of one polarizing plate is parallel to the second direction X or parallel to the first direction X.

  In the example shown in FIG. 2A, the first polarizing plate PL1 has the first polarizing axis AX1 orthogonal to the initial alignment direction (second direction Y) of the liquid crystal molecules LM (that is, the first polarizing plate PL1). The second polarizing plate PL2 has a second polarizing axis AX2 that is parallel to the initial alignment direction of the liquid crystal molecules LM (that is, parallel to the second direction Y). Is arranged).

  In the example shown in FIG. 2B, the second polarizing plate PL2 has the second polarizing axis AX2 orthogonal to the initial alignment direction (second direction Y) of the liquid crystal molecules LM (that is, The first polarizing plate PL1 has a first polarizing axis AX1 that is parallel to the initial alignment direction of the liquid crystal molecules LM (that is, the second direction Y). In parallel).

  4 is a cross-sectional view schematically showing a cross-sectional structure when the liquid crystal display panel LPN shown in FIG. 2 is cut along the line BB. Here, the illustration of the configuration below the second interlayer insulating film 12 in the array substrate AR and the configuration above the overcoat layer OC in the counter substrate CT are omitted.

  In the array substrate AR, the first conductive member CM1 is in contact with the first subpixel electrode PB1. The first main common electrode CAL1, the first main common electrode CAR1, and the second interlayer insulating film 12 are covered with the first alignment film AL1. The first subpixel electrode PB1 is covered with the first alignment film AL1 except for the contact portion in contact with the first conductive member CM1. That is, the first alignment film AL1 exposes the contact portion of the first subpixel electrode PB1 with the first conductive member CM1.

  In the counter substrate CT, the first conductive member CM1 is in contact with the second subpixel electrode PB2. The second main common electrode CAL2, the second main common electrode CAR2, and the overcoat layer OC are covered with the second alignment film AL2. The second subpixel electrode PB2 is covered with the second alignment film AL2 except for the contact portion in contact with the first conductive member CM1. That is, the second alignment film AL2 exposes the contact portion of the second subpixel electrode PB2 with the first conductive member CM1.

  Note that the first alignment film AL1 and the second alignment film AL2 may expose the entire first conductive member CM1, but the contact portion with the first subpixel electrode PB1 of the first conductive member CM1 and the second conductive film CM1. The side surface of the first conductive member CM1 may be covered except for the contact portion with the sub-pixel electrode PB2.

  FIG. 5 is a cross-sectional view schematically showing a cross-sectional structure when the liquid crystal display panel LPN shown in FIG. 2 is cut along the line CC. Here, the illustration of the configuration below the second interlayer insulating film 12 in the array substrate AR and the configuration above the overcoat layer OC in the counter substrate CT are omitted.

  In the array substrate AR, the second conductive member CM2 is in contact with the first main common electrode CAL1. The first main common electrode CAL1 is covered with the first alignment film AL1 except for the contact portion in contact with the second conductive member CM2. That is, the first alignment film AL1 exposes the contact portion of the first main common electrode CAL1 with the second conductive member CM2.

  In the counter substrate CT, the second conductive member CM2 is in contact with the second main common electrode CAL2. The second main common electrode CAL2 is covered with the second alignment film AL2 except for the contact portion in contact with the second conductive member CM2. That is, the second alignment film AL2 exposes a contact portion of the second main common electrode CAL2 with the second conductive member CM2.

  The first alignment film AL1 and the second alignment film AL2 may expose the entire second conductive member CM2, but the contact portion of the second conductive member CM2 with the first main common electrode CAL1 and the second conductive member CM2. Except for the contact portion with the main common electrode CAL2, the side surface of the second conductive member CM2 and the like may be covered.

  Next, the operation of the liquid crystal display panel LPN configured as described above will be described with reference to FIGS.

  That is, in a state where no voltage is applied to the liquid crystal layer LQ, that is, in a state where no potential difference (or electric field) is formed between the pixel electrode PE and the common electrode CE (when OFF), the liquid crystal of the liquid crystal layer LQ The molecules LM are aligned such that their major axes are directed to the first alignment processing direction PD1 of the first alignment film AL1 and the second alignment processing direction PD2 of the second alignment film AL2. Such OFF time corresponds to the initial alignment state, and the alignment direction of the liquid crystal molecules LM at the OFF time corresponds to the initial alignment direction.

  Strictly speaking, the liquid crystal molecules LM are not always aligned parallel to the XY plane, and are often pretilted. For this reason, the initial alignment direction of the liquid crystal molecules LM here is a direction obtained by orthogonally projecting the major axis of the liquid crystal molecules LM at the time of OFF to the XY plane. Hereinafter, in order to simplify the description, it is assumed that the liquid crystal molecules LM are aligned in parallel to the XY plane and rotate in a plane parallel to the XY plane.

  Here, the first alignment treatment direction PD1 and the second alignment treatment direction PD2 are both substantially parallel to the second direction Y. At the OFF time, the liquid crystal molecules LM are initially aligned in the direction in which the major axis is substantially parallel to the second direction Y, as indicated by a broken line in FIG. That is, the initial alignment direction of the liquid crystal molecules LM is parallel to the second direction Y (or 0 ° with respect to the second direction Y).

  As in the illustrated example, when the first alignment processing direction PD1 and the second alignment processing direction PD2 are parallel and in the same direction, in the cross section of the liquid crystal layer LQ, the liquid crystal molecules LM are substantially near the middle portion of the liquid crystal layer LQ. Alignment is performed horizontally (pretilt angle is substantially zero), and is aligned with a pretilt angle that is symmetrical in the vicinity of the first alignment film AL1 and in the vicinity of the second alignment film AL2 (spray alignment). As described above, with the intermediate portion of the liquid crystal layer LQ as a boundary, the alignment of the liquid crystal molecules LM in the vicinity of the first alignment film AL1 on the array substrate AR and the liquid crystal molecules in the vicinity of the second alignment film AL2 on the counter substrate CT. Since the LM orientation is symmetrical in the vertical direction, it is optically compensated even in the direction inclined from the normal direction of the substrate. Therefore, when the splay alignment is used as the initial alignment, there is little light leakage in the case of black display, a high contrast ratio can be realized, and display quality can be improved.

  When the first alignment treatment direction PD1 and the second alignment treatment direction PD2 are parallel and opposite to each other, the liquid crystal molecules LM are in the vicinity of the first alignment film AL1, in the second alignment film AL2 in the cross section of the liquid crystal layer LQ. And in the middle part of the liquid crystal layer LQ with a substantially uniform pretilt angle (homogeneous alignment).

  Part of the backlight light from the backlight 4 passes through the first polarizing plate PL1 and enters the liquid crystal display panel LPN. The polarization state of light incident on the liquid crystal display panel LPN varies depending on the alignment state of the liquid crystal molecules LM when passing through the liquid crystal layer LQ. At the OFF time, the light that has passed through the liquid crystal layer LQ is absorbed by the second polarizing plate PL2 (black display).

  On the other hand, in a state where a voltage is applied to the liquid crystal layer LQ, that is, in a state where a potential difference (or an electric field) is formed between the pixel electrode PE and the common electrode CE (when ON), the pixel electrode PE and the common electrode CE A lateral electric field (or oblique electric field) substantially parallel to the substrate is formed between the two. At this time, as shown in FIG. 3, the first main pixel electrode PA1 and the second main pixel electrode PA2 having the pixel potential, the first main common electrode CAL1, the first main common electrode CAR1, and the second main common having the common potential. An electric field is formed between the electrode CAL2 and the second main common electrode CAR2. The liquid crystal molecules LM are affected by the electric field and rotate in a plane whose major axis is substantially parallel to the XY plane as indicated by the solid line in the figure.

  In the example shown in FIG. 2, in the lower left region of the pixel PX, the liquid crystal molecules LM are aligned so as to rotate clockwise with respect to the second direction Y and to face the lower left in the drawing. In the upper left region of the pixel PX, the liquid crystal molecules LM are rotated counterclockwise with respect to the second direction Y and are oriented so as to face the upper left in the drawing. In the lower right region of the pixel PX, the liquid crystal molecules LM are aligned so as to rotate counterclockwise with respect to the second direction Y and to face the lower right in the drawing. In the upper right region of the pixel PX, the liquid crystal molecules LM are aligned so as to rotate clockwise in the second direction Y and to face the upper right in the drawing.

  Thus, in each pixel PX, in a state where an electric field is formed between the pixel electrode PE and the common electrode CE, the alignment direction of the liquid crystal molecules LM is divided into a plurality of directions with the position overlapping the pixel electrode PE as a boundary. The domains are formed in the respective orientation directions. That is, a plurality of domains are formed in one pixel PX.

  At such an ON time, part of the backlight light incident on the liquid crystal display panel LPN from the backlight 4 is transmitted through the first polarizing plate PL1 and incident on the liquid crystal display panel LPN. The backlight light incident on the liquid crystal layer LQ changes its polarization state. At such ON time, at least part of the light that has passed through the liquid crystal layer LQ is transmitted through the second polarizing plate PL2 (white display).

  According to this embodiment, the first main pixel electrode PA1 and the second main pixel electrode PA2, the first main common electrode CAL1, the first main common electrode CAR1, the second main common electrode CAL2, and the second A transverse electric field (or oblique electric field) is formed between the main common electrode CAR2. For this reason, not only in the intermediate portion of the liquid crystal layer LQ but also in the vicinity of the interface with the array substrate AR, that is, in the vicinity of the first alignment film AL1, and in the vicinity of the interface with the counter substrate CT, that is, in the vicinity of the second alignment film AL2, As a result, the alignment state of the liquid crystal molecules LM can be easily changed, and a high-speed response is possible.

  Therefore, in the liquid crystal layer LQ in almost the entire region between the pixel electrode and the common electrode, a desired retardation Δn · d (Δn is refractive index anisotropy necessary for white display without applying a high driving voltage, d is the thickness of the liquid crystal layer LQ), and the transmittance at the opening AP can be improved. In addition, the electric field formed between the pixel electrode and the common electrode is strengthened, so that the action of an undesired electric field from the outside can be suppressed, and the decrease in transmittance can be suppressed.

  FIG. 6 is a diagram for explaining the cross-sectional structure of the liquid crystal display panel LPN of the comparative example and the relationship of the electric field formed between the first main pixel electrode and the second main common electrode.

  When ON, an electric field is formed between the first main pixel electrode PA1, the second main common electrode CAL2, and the second main common electrode CAR2. In such an ON state, the electric field is unlikely to act in the region A surrounded by the dotted line in the figure, so that the liquid crystal molecules LM are unlikely to change to a desired alignment state. For this reason, desired retardation cannot be imparted to the light transmitted through the region A, and the transmittance at the opening AP is reduced.

  In order to confirm the above phenomenon, the inventor prepared a liquid crystal display device corresponding to the present embodiment shown in FIG. 3 and the like and a liquid crystal display device corresponding to the comparative example shown in FIG. The transmittance was measured in the ON state. The liquid crystal display device corresponding to the present embodiment includes a first main pixel electrode PA1, a second main pixel electrode PA2, a first main common electrode CAL1, a first main common electrode CAR1, a second main common electrode CAL2, and a second main common. An electrode CAR2 is provided. The liquid crystal display device corresponding to the comparative example includes a first main pixel electrode PA1, a second main common electrode CAL2, and a second main common electrode CAR2.

  All other conditions are the same. That is, the width along the first direction X of the main pixel electrode PA is set to 7 μm, the width along the first direction X of the main common electrode CA is set to 7 μm, and the first direction between the main pixel electrode PA and the main common electrode CA is set. The distance between horizontal electrodes along X was 10 μm, the pixel pitch was 50 μm, and the cell gap was 4 μm.

  When the transmittance of the liquid crystal display device corresponding to the comparative example was 1, the transmittance of 1.03 could be obtained in the liquid crystal display device corresponding to the present embodiment.

  Next, the inventor examined the effect of installing a shield electrode inside the liquid crystal display panel LPN. The shield electrode shields an external electric field that enters from the outside of the liquid crystal display panel LPN toward the counter substrate CT, and is formed of a transparent conductive material such as ITO. Such a shield electrode may be provided on the inner surface 20A of the second insulating substrate 20 in some cases. The reason why the shield electrode is installed on the inner surface 20A instead of the outer surface 20B is that the array substrate AR and the counter substrate CT are bonded together, and then the outer surface of the counter substrate CT is polished to thin the liquid crystal display panel LPN. This is because it is easy to be electrically connected to a wiring (for example, a wiring having a common potential) provided on the substrate AR.

  By installing the shield electrode, the influence of the electric field entering from the outside on the liquid crystal layer LQ can be reduced, while the shield electrode itself functions as an electrode for applying an electric field to the liquid crystal layer LQ, and the array substrate AR There is a possibility that an undesired vertical electric field may be formed between the first main pixel electrode PA1 and the like. For this reason, the electric field between the main pixel electrode and the main common electrode that should be originally formed is disturbed, and there is a possibility that the transmittance is reduced as compared with the case where the shield electrode is not provided.

  In the liquid crystal display device corresponding to the comparative example shown in FIG. 6, when the shield electrode was installed, the transmittance was reduced by 10% compared to the case where the shield electrode was not installed. On the other hand, in the liquid crystal display device corresponding to the present embodiment shown in FIG. 3 and the like, when the shield electrode is installed, the transmittance is reduced by about 6% compared to the case where the shield electrode is not installed.

  As described above, the liquid crystal display device according to the present embodiment can suppress the decrease in the transmittance as compared with the liquid crystal display device of the comparative example, so that the configuration of the comparative example (the first main pixel electrode PA1 and the second main common electrode CA2 are included). According to the configuration of the present embodiment in which the second main pixel electrode PA2 and the first main common electrode CA1 are arranged in addition to the arranged configuration), the electric field formed between the main pixel electrode and the main common electrode is enhanced. It was confirmed that it was possible.

  Thus, according to the present embodiment, it is possible to suppress a decrease in transmittance. Thereby, it becomes possible to suppress degradation of display quality.

  Further, since the first common electrode CE1 and the second common electrode CE2 are electrically connected in the active area ACT, a voltage drop due to the wiring resistance of the common electrode CE can be suppressed. Thereby, it is possible to suppress the occurrence of display quality problems such as flicker and crosstalk. In the active area ACT, the electrical connection between the first common electrode CE1 and the second common electrode CE2 can be made redundant, and even if a disconnection occurs in a part of the common electrode, each pixel A desired voltage can be applied to the common electrode CE of PX. In the above example, the first main common electrode CA1 and the second main common electrode CA2 are electrically connected in one pixel PX. However, in the active area ACT, the first main common electrode CA1 is provided for each of the plurality of pixels. And the second main common electrode CA2 may be electrically connected.

  In addition, the first pixel electrode PE1 and the second pixel electrode PE2 are electrically connected via a first conductive member CM1 located on the storage capacitor line or the gate wiring, and the first common electrode CE1 and the second common electrode CE1 are shared by the second common electrode CE1. The electrode CE2 is electrically connected via a second conductive member CM2 located at the intersection of the source wiring and the gate wiring or auxiliary capacitance line. For this reason, even if the alignment of the liquid crystal molecules LM is disturbed around the first conductive member CM1 and the second conductive member CM2, the periphery does not contribute to the display, and therefore generation of dark lines due to undesired alignment of the liquid crystal molecules LM or Generation of bright lines can be suppressed.

  In addition, according to the present embodiment, since a high transmittance is obtained in the electrode gap between the main pixel electrode and the main common electrode, in order to sufficiently increase the transmittance per pixel, This can be dealt with by enlarging the inter-electrode distance to the main common electrode. For product specifications with different pixel pitches, the inter-electrode distance is changed (that is, the arrangement position of the main common electrode is changed with respect to the main pixel electrode arranged in the approximate center of the pixel PX). It is possible to use the peak condition of the transmittance distribution. That is, in the display mode of the present embodiment, fine electrode processing is not always required from a low-resolution product specification with a relatively large pixel pitch to a high-resolution product specification with a relatively small pixel pitch, and the distance between the electrodes is not required. Products with various pixel pitches can be provided by setting. Therefore, it is possible to easily realize the demand for high transmittance and high resolution.

  Further, according to the present embodiment, the transmittance is sufficiently lowered in the region overlapping with the black matrix BM. This is because the electric field does not leak outside the pixel from the position of the common electrode CE, and an undesired lateral electric field does not occur between adjacent pixels across the black matrix BM. This is because the liquid crystal molecules in the overlapping region maintain the initial alignment state as in the OFF state (or during black display). Therefore, even when the colors of the color filters are different between adjacent pixels, it is possible to suppress the occurrence of color mixing, and it is possible to suppress a decrease in color reproducibility and a decrease in contrast ratio.

  Further, when misalignment between the array substrate AR and the counter substrate CT occurs, there may be a difference in the distance between the horizontal electrodes with the main common electrode on both sides across the main pixel electrode. However, since such misalignment occurs in common for all the pixels PX, there is no difference in the electric field distribution among the pixels PX, and the influence on the display of the image is extremely small. In addition, even if a misalignment occurs between the array substrate AR and the counter substrate CT, it is possible to suppress undesired electric field leakage to adjacent pixels. For this reason, even when the colors of the color filters are different between adjacent pixels, it is possible to suppress the occurrence of color mixing, and it is possible to suppress a decrease in color reproducibility and a decrease in contrast ratio.

  Further, according to the present embodiment, the main common electrode is opposed to the source wiring. In particular, when the main common electrode CAL and the main common electrode CAR are disposed immediately above the source line S1 and the source line S2, respectively, the main common electrode CAL and the main common electrode CAR are more than the source line S1 and the source line S2. Compared with the case where it is arranged on the pixel electrode PE side, the opening AP can be enlarged, and the transmittance of the pixel PX can be improved.

  Further, by disposing the main common electrode CAL and the main common electrode CAR directly above the source line S1 and the source line S2, respectively, the interelectrode distance between the pixel electrode PE and the main common electrode CAL and the main common electrode CAR is increased. It becomes possible to form a lateral electric field that is closer to the horizontal. For this reason, it is possible to maintain the wide viewing angle, which is an advantage of the IPS mode, which is a conventional configuration.

  Further, since the first main common electrode CAL1 provided in the array substrate AR is located immediately above the source line S1, and the first main common electrode CAR1 is located immediately above the source line S2, an undesired electric field from the source line is formed. It is possible to shield. For this reason, it is possible to form a desired electric field formed between the main pixel electrode and the main common electrode, and it is possible to suppress deterioration in display quality.

  Further, according to the present embodiment, a plurality of domains can be formed in one pixel. Therefore, the viewing angle can be optically compensated in a plurality of directions, and a wide viewing angle can be achieved.

  In the above example, the case where the initial alignment direction of the liquid crystal molecules LM is parallel to the second direction Y has been described. However, the initial alignment direction of the liquid crystal molecules LM is the second direction Y as shown in FIG. May be in a diagonal direction D that crosses diagonally. Here, the angle θ1 formed by the initial alignment direction D with respect to the second direction Y is an angle greater than 0 ° and less than 45 °. Note that it is extremely effective from the viewpoint of controlling the alignment of the liquid crystal molecules LM that the angle θ1 formed is about 5 ° to 30 °, more preferably 20 ° or less. That is, it is desirable that the initial alignment direction of the liquid crystal molecules LM is substantially parallel to the direction in the range of 0 ° to 20 ° with respect to the second direction Y.

  In the above example, the case where the liquid crystal layer LQ is made of a liquid crystal material having positive (positive type) dielectric anisotropy has been described. However, the liquid crystal layer LQ has a negative dielectric anisotropy (negative). Type) liquid crystal material. However, although detailed explanation is omitted, in the case of a negative type liquid crystal material, the above-mentioned angle θ1 is set to 45 ° to 90 °, preferably 70 ° or more, because the dielectric anisotropy becomes positive and negative. preferable.

  Even when ON, the horizontal electric field is hardly formed on the pixel electrode PE or the common electrode CE (or an electric field sufficient to drive the liquid crystal molecule LM is not formed), so that the liquid crystal molecule LM is OFF. As with time, it hardly moves from the initial orientation direction. For this reason, even if the pixel electrode PE and the common electrode CE are formed of a light-transmitting conductive material such as ITO, the backlight hardly transmits in these regions, and hardly contributes to the display when ON. Therefore, the pixel electrode PE and the common electrode CE are not necessarily formed of a transparent conductive material, and may be formed using a conductive material such as aluminum, silver, or copper.

  In the above example, the configuration in which the auxiliary capacitance line is disposed immediately below the first subpixel electrode PB1 has been described. However, a gate wiring may be disposed immediately below the first subpixel electrode PB1.

  Next, another structural example for electrically connecting the first pixel electrode PE1 and the second pixel electrode PE2 will be described.

  FIG. 7 is a cross-sectional view schematically showing a cross-sectional structure along the first direction X of the liquid crystal display panel including a connection portion between the first pixel electrode PE1 and the second pixel electrode PE2. FIG. 8 is a cross-sectional view schematically showing a cross-sectional structure along the second direction Y of the liquid crystal display panel including a connection portion between the first pixel electrode PE1 and the second pixel electrode PE2. Here, the illustration of the configuration below the second interlayer insulating film 12 in the array substrate AR and the configuration above the overcoat layer OC in the counter substrate CT are omitted.

  In the array substrate AR, the first columnar spacer SP1 is formed on the second interlayer insulating film 12. Such a first columnar spacer SP1 has a first upper surface T1 facing the counter substrate CT. The first subpixel electrode PB1 covers the first columnar spacer SP1. The first main common electrode CAL1, the first main common electrode CAR1, and the second interlayer insulating film 12 are covered with the first alignment film AL1. The first subpixel electrode PB1 is covered with the first alignment film AL1 except for the portion (contact portion PC) that covers the first upper surface T1 of the first columnar spacer SP1. That is, the first alignment film AL1 exposes the contact portion PC that is closest to the counter substrate CT in the first subpixel electrode PB1.

  In the counter substrate CT, the contact portion PC of the first subpixel electrode PB1 exposed from the first alignment film AL1 is in contact with the second subpixel electrode PB2. The second main common electrode CAL2, the second main common electrode CAR2, and the overcoat layer OC are covered with the second alignment film AL2. The second subpixel electrode PB2 is covered with the second alignment film AL2 except for the contact portion in contact with the contact portion PC. That is, the second alignment film AL2 exposes a contact portion with the contact portion PC in the second subpixel electrode PB2. In other words, a contact hole PCH that exposes the second subpixel electrode PB2 is formed in the second alignment film AL2, and the first pixel electrode PE1 contacts the second pixel electrode PE2 through the contact hole PCH. The first pixel electrode PE1 and the second pixel electrode PE2 are electrically connected.

  In the example shown here, the configuration in which the first sub-pixel electrode PB1 covers the first columnar spacer SP1 has been described. However, the first pixel electrode PE1 only needs to cover the first columnar spacer SP1. The pixel electrode PA1 may cover the first columnar spacer SP1. Further, a part of the first columnar spacer SP1 may be exposed from the first pixel electrode PE1, and the first pixel electrode PE1 may not completely cover the entire first columnar spacer SP1.

  The first columnar spacer SP1 may be provided on the counter substrate CT. In this case, the first columnar spacer SP1 is formed on the side of the overcoat layer OC that faces the array substrate AR, and is covered with the second pixel electrode PE2. That is, the second pixel electrode PE2 includes a contact portion PC that contacts the first pixel electrode PE1.

  In such a structural example, even when the first pixel electrode PE1 and the second pixel electrode PE2 are electrically connected, the same effect as described above can be obtained.

  Next, another structural example for electrically connecting the first common electrode CE1 and the second common electrode CE2 will be described.

  FIG. 9 is a cross-sectional view schematically showing a cross-sectional structure along the first direction X of the liquid crystal display panel including a connection portion between the first common electrode CE1 and the second common electrode CE2. FIG. 10 is a cross-sectional view schematically showing a cross-sectional structure along the second direction Y of the liquid crystal display panel including a connection portion between the first common electrode CE1 and the second common electrode CE2. Here, the illustration of the configuration below the second interlayer insulating film 12 in the array substrate AR and the configuration above the overcoat layer OC in the counter substrate CT are omitted.

  In the array substrate AR, the second columnar spacer SP2 is formed on the second interlayer insulating film 12. Such a second columnar spacer SP2 has a second upper surface T2 facing the counter substrate CT. The first main common electrode CAL1 is disposed on the second upper surface T2 of the second columnar spacer SP2. The first main common electrode CAL1, the first main common electrode CAR1, and the second interlayer insulating film 12 are covered with the first alignment film AL1. However, the first main common electrode CAL1 is covered with the first alignment film AL1 except for a portion (contact portion CC) that covers the second upper surface T2 of the second columnar spacer SP2. In other words, the first alignment film AL1 exposes the contact portion CC closest to the counter substrate CT in the first main common electrode CAL1.

  In the counter substrate CT, the contact portion CC of the first main common electrode CAL1 exposed from the first alignment film AL1 is in contact with the second main common electrode CAL2. The second main common electrode CAL2, the second main common electrode CAR2, and the overcoat layer OC are covered with the second alignment film AL2. However, the second main common electrode CAL2 is covered with the second alignment film AL2 except for the contact portion in contact with the contact portion CC. That is, the second alignment film AL2 exposes a contact portion with the contact portion CC in the second main common electrode CAL2. In other words, a contact hole CCH exposing the second main common electrode CAL2 is formed in the second alignment film AL2, and the first common electrode CE1 contacts the second common electrode CE2 through the contact hole CCH. The first common electrode CE1 and the second common electrode CE2 are electrically connected.

  In the example shown here, the configuration in which the first main common electrode CAL1 covers the second columnar spacer SP2 has been described. However, the first common electrode CE1 only needs to cover the second columnar spacer SP2. Further, a part of the second columnar spacer SP2 may be exposed from the first common electrode CE1, and the first common electrode CE1 may not completely cover the entire second columnar spacer SP2.

  Further, the second columnar spacer SP2 may be provided on the counter substrate CT. In this case, the second columnar spacer SP2 is formed on the side of the overcoat layer OC facing the array substrate AR, and is covered with the second common electrode CE2. That is, the second common electrode CE2 includes a contact portion CC that contacts the first common electrode CE1.

  In such a structural example, even when the first common electrode CE1 and the second common electrode CE2 are electrically connected, the same effect as described above can be obtained.

  In the present embodiment, the common electrode CE is provided in the array substrate AR in addition to the first main common electrode CA1 and the second main common electrode CA2 and is opposed to the gate line G and the auxiliary capacitance line C. One sub-common electrode may be provided. The first sub-common electrode extends along the first direction X, and is formed integrally or continuously with the first main common electrode CA1. By providing such a first sub-common electrode, it is possible to shield an undesired electric field from the gate line G and the auxiliary capacitance line C.

  In addition to the first main common electrode CA1 and the second main common electrode CA2, the common electrode CE includes a second sub-common electrode provided in the counter substrate CT and facing the gate line G and the auxiliary capacitance line C. May be. The second sub-common electrode extends along the first direction X, and is formed integrally or continuously with the second main common electrode CA2.

  As described above, according to the present embodiment, it is possible to provide a liquid crystal display device capable of suppressing deterioration in display quality.

  In addition, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

LPN ... Liquid crystal display panel AR ... Array substrate CT ... Counter substrate LQ ... Liquid crystal layer PE ... Pixel electrode PA ... Main pixel electrode PB ... Sub-pixel electrode CE ... Common electrode CA ... Main common electrode CB ... Sub-common electrode CM1 ... First conductive Member CM2 ... 2nd conductive member SP1 ... 1st columnar spacer SP2 ... 2nd columnar spacer

Claims (11)

A first pixel electrode provided with a linearly extending strip-shaped first main pixel electrode, and a first main common extending substantially parallel to the first main pixel electrode on both sides of the first main pixel electrode A first substrate provided with a first common electrode provided with an electrode;
A second pixel electrode provided with a second main pixel electrode opposed to the first main pixel electrode and electrically connected to the first pixel electrode; and a second main common electrode opposed to the first main common electrode. A second substrate comprising: a second common electrode electrically connected to the first common electrode;
A liquid crystal layer comprising liquid crystal molecules held between the first substrate and the second substrate;
A liquid crystal display device comprising:   The conductive member according to claim 1, further comprising a conductive member that is in contact with the first pixel electrode and the second pixel electrode and electrically connects the first pixel electrode and the second pixel electrode. Liquid crystal display device.   Further, the columnar spacer is covered with the first pixel electrode and forms a cell gap for holding a liquid crystal layer between the first substrate and the second substrate, and the first pixel electrode is the columnar spacer. The liquid crystal display device according to claim 1, wherein the liquid crystal display device covers and covers the second pixel electrode. A first pixel electrode provided with a linearly extending strip-shaped first main pixel electrode, and a first main common extending substantially parallel to the first main pixel electrode on both sides of the first main pixel electrode A first common electrode having an electrode; a conductive member in contact with the first pixel electrode; and a first alignment film that covers the first pixel electrode and the first common electrode and exposes the conductive member. A first substrate,
A second pixel electrode having a second main pixel electrode facing the first main pixel electrode and contacting the conductive member; a second main common electrode facing the first main common electrode; and the first common electrode A second substrate comprising: a second common electrode electrically connected; and a second alignment film covering the second pixel electrode and the second common electrode and exposing the conductive member;
A liquid crystal layer comprising liquid crystal molecules held between the first substrate and the second substrate;
A liquid crystal display device comprising: A columnar spacer, a first pixel electrode having a strip-shaped first main pixel electrode extending linearly and covering the columnar spacer, and substantially parallel to the first main pixel electrode on both sides of the first main pixel electrode A first common electrode including a first main common electrode extending in a first direction, and a first orientation that exposes the first pixel electrode that covers the first pixel electrode and the first common electrode and covers the top surface of the columnar spacer. A first substrate comprising a film;
A second main pixel electrode facing the first main pixel electrode; a second pixel electrode contacting the first pixel electrode exposed from the first alignment film; and a second main pixel facing the first main common electrode. A second common electrode provided with a common electrode and electrically connected to the first common electrode; and a contact with the first pixel electrode of the second pixel electrode while covering the second pixel electrode and the second common electrode A second alignment film including a second alignment film exposing a portion;
A liquid crystal layer comprising liquid crystal molecules held between the first substrate and the second substrate;
A liquid crystal display device comprising:   6. The liquid crystal display device according to claim 1, wherein the first substrate further includes a source wiring disposed immediately below the first main common electrode. 7.   The first substrate further includes a gate wiring or an auxiliary capacitance line that passes immediately below a position where the first pixel electrode and the second pixel electrode are electrically connected to each other. The liquid crystal display device according to any one of the above.   2. The method according to claim 1, further comprising a second conductive member that contacts the first common electrode and the second common electrode and electrically connects the first common electrode and the second common electrode. 8. The liquid crystal display device according to any one of 7 above.   And a second columnar spacer that is covered by the first common electrode and forms a cell gap for holding a liquid crystal layer between the first substrate and the second substrate, wherein the first common electrode is The liquid crystal display device according to claim 1, wherein the liquid crystal display device covers the second columnar spacer and is in contact with the second common electrode.   With no electric field formed between the first pixel electrode and the second pixel electrode and the first common electrode and the second common electrode, the initial alignment direction of the liquid crystal molecules in the liquid crystal layer is 10. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is substantially parallel to a direction within a range of 0 ° to 20 ° with respect to an extending direction of one main pixel electrode.   The liquid crystal molecules are formed on the first substrate and the second substrate in a state where no electric field is formed between the first pixel electrode and the second pixel electrode, and the first common electrode and the second common electrode. The liquid crystal display device according to claim 10, wherein the liquid crystal display device is splayed or homogeneously oriented.

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