JP5824301B2 - Liquid crystal display - Google Patents

Description

  Embodiments described herein relate generally to a liquid crystal display device.

  2. Description of the Related Art In recent years, flat display devices have been actively developed. In particular, liquid crystal display devices have attracted particular attention because of their advantages such as light weight, thinness, and low power consumption. In particular, an active matrix liquid crystal display device in which a switching element is incorporated in each pixel has a structure using a lateral electric field (including a fringe electric field) such as an IPS (In-Plane Switching) mode or an FFS (Fringe Field Switching) mode. Attention has been paid. Such a horizontal electric field mode liquid crystal display device includes a pixel electrode and a counter electrode formed on an array substrate, and switches liquid crystal molecules with a horizontal electric field substantially parallel to the main surface of the array substrate.

  On the other hand, a technique for switching liquid crystal molecules by forming a lateral electric field or an oblique electric field between a pixel electrode formed on an array substrate and a counter electrode formed on the counter substrate has been proposed.

JP 2009-42630 A JP 2009-192822 A

  An object of the present embodiment is to provide a liquid crystal display device capable of reducing cost and suppressing deterioration in display quality.

According to this embodiment,
The gate wiring extending along the first direction, the source wiring extending along the second direction intersecting the first direction, and the length along the first direction is longer than the length along the second direction A first substrate having a main pixel electrode disposed in a long pixel and extending along a first direction; and extending along the first direction on both sides of the main pixel electrode. A liquid crystal, comprising: a second substrate having a common electrode having a main common electrode; and a liquid crystal layer including liquid crystal molecules held between the first substrate and the second substrate. A display device is provided.

According to this embodiment,
A first gate line and a second gate line respectively extending along a first direction; an auxiliary capacitance line extending along a first direction between the first gate line and the second gate line; A source line extending along a second direction intersecting the first direction, and two or more main pixels extending along the first direction between the first gate line and the second gate line And a first substrate having at least one main pixel electrode located above the storage capacitor line, and extending along the first direction on both sides of the main pixel electrode. A second substrate having a common electrode having a main common electrode and a liquid crystal layer including liquid crystal molecules held between the first substrate and the second substrate are provided. A liquid crystal display device is provided.

According to this embodiment,
A first gate wiring and a second gate wiring extending along a first direction and arranged at a first pitch along a second direction intersecting the first direction; the first gate wiring and the second gate wiring; Auxiliary capacitance lines extending along the first direction with the gate wiring, and extending along the second direction and arranged at a second pitch larger than the first pitch along the first direction. The first source line, the second source line, the first gate line, the second gate line, the first source line, and the second source line are located on the inner side and are each along the first direction. A first substrate including two or more main pixel electrodes extending in a row, and at least one main pixel electrode positioned above the auxiliary capacitance line; and above the first gate wiring , The second gate wiring And a main common electrode positioned between the main pixel electrodes and extending along the first direction, and a second direction positioned above the first source line and above the second source line, respectively. A second substrate having a common electrode including a sub-common electrode extending along each of the first and second liquid crystal layers, and a liquid crystal layer including liquid crystal molecules held between the first substrate and the second substrate. A liquid crystal display device characterized by the above is provided.

FIG. 1 is a diagram schematically showing a configuration and an equivalent circuit of a liquid crystal display device according to the present embodiment. FIG. 2 is a plan view schematically showing a structural example of one pixel when the array substrate shown in FIG. 1 is viewed from the counter substrate side. FIG. 3 is a plan view schematically showing an example of the structure of one pixel in the counter substrate shown in FIG. FIG. 4 is a cross-sectional view schematically showing a cross-sectional structure of the array substrate taken along line AB in FIG. FIG. 5 is a cross-sectional view schematically showing a cross-sectional structure of the liquid crystal display panel taken along line CD in FIG. FIG. 6 is a plan view schematically showing another structural example of one pixel when the array substrate shown in FIG. 1 is viewed from the counter substrate side. FIG. 7 is a plan view schematically showing another structural example of one pixel when the array substrate shown in FIG. 1 is viewed from the counter substrate side. FIG. 8 is a plan view schematically showing another structural example of one pixel when the array substrate shown in FIG. 1 is viewed from the counter substrate side.

  Hereinafter, the present embodiment will be described in detail with reference to the drawings. In each figure, the same reference numerals are given to components that exhibit the same or similar functions, and duplicate descriptions are omitted.

  FIG. 1 is a diagram schematically showing a configuration and an equivalent circuit of a liquid crystal display device according to the present embodiment.

  That is, the liquid crystal display device includes an active matrix type liquid crystal display panel LPN. The liquid crystal display panel LPN is held between the array substrate AR, which is the first substrate, the counter substrate CT, which is the second substrate disposed to face the array substrate AR, and the array substrate AR and the counter substrate CT. Liquid crystal layer LQ. Such a liquid crystal display panel LPN includes an active area ACT for displaying an image. This active area ACT is composed of a plurality of pixels PX arranged in an m × n matrix (where m and n are positive integers).

  In the active area ACT, the liquid crystal display panel LPN includes n gate lines G (G1 to Gn), n auxiliary capacitance lines C (C1 to Cn), m source lines S (S1 to Sm), and the like. ing. The gate line G and the auxiliary capacitance line C correspond to, for example, a signal line extending substantially linearly along the first direction X. The gate lines G and the auxiliary capacitance lines C are adjacent to each other at intervals along the second direction Y intersecting the first direction X, and are alternately arranged in parallel. Here, the first direction X and the second direction Y are substantially orthogonal to each other. The source line S intersects with the gate line G and the auxiliary capacitance line C. The source line S corresponds to a signal line extending substantially linearly along the second direction Y. Note that the gate wiring G, the auxiliary capacitance line C, and the source wiring S do not necessarily extend linearly, and some of them may be bent.

  Each gate line G is drawn outside the active area ACT and connected to the gate driver GD. Each source line S is drawn outside the active area ACT and connected to the source driver SD. At least a part of the gate driver GD and the source driver SD is formed on, for example, the array substrate AR, and is connected to the driving IC chip 2 with a built-in controller.

  Each pixel PX includes a switching element SW, a pixel electrode PE, a common electrode CE, and the like. The storage capacitor Cs is formed, for example, between the storage capacitor line C and the pixel electrode PE. The auxiliary capacitance line C is electrically connected to a voltage application unit VCS to which an auxiliary capacitance voltage is applied.

  In the present embodiment, the liquid crystal display panel LPN has a configuration in which the pixel electrode PE is formed on the array substrate AR while at least a part of the common electrode CE is formed on the counter substrate CT. The liquid crystal molecules in the liquid crystal layer LQ are switched mainly using an electric field formed between the PE and the common electrode CE. The electric field formed between the pixel electrode PE and the common electrode CE is an oblique electric field (or slightly inclined with respect to the XY plane or the substrate main surface defined by the first direction X and the second direction Y) (or , A transverse electric field substantially parallel to the main surface of the substrate).

  The switching element SW is constituted by, for example, an n-channel thin film transistor (TFT). The switching element SW is electrically connected to the gate line G and the source line S. Such a switching element SW may be either a top gate type or a bottom gate type. In addition, the semiconductor layer of the switching element SW is formed of, for example, amorphous silicon, but may be formed of polysilicon.

  The pixel electrode PE is disposed in each pixel PX and is electrically connected to the switching element SW. The common electrode CE is disposed in common to the pixel electrodes PE of the plurality of pixels PX via the liquid crystal layer LQ. The pixel electrode PE and the common electrode CE are formed of a light-transmitting conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). You may form with another metal material.

  The array substrate AR includes a power feeding unit VS for applying a voltage to the common electrode CE. For example, the power supply unit VS is formed outside the active area ACT. The common electrode CE of the counter substrate CT is drawn out of the active area ACT and is electrically connected to the power supply unit VS via a conductive member (not shown).

  FIG. 2 is a plan view schematically showing a structure example of one pixel PX when the array substrate AR shown in FIG. 1 is viewed from the counter substrate side. Here, a plan view in the XY plane is shown.

  The array substrate AR includes a gate line G1, a gate line G2, an auxiliary capacitance line C1, a source line S1, a source line S2, a switching element SW, a pixel electrode PE, a first alignment film AL1, and the like.

  In the illustrated example, the pixel PX has a horizontally long rectangular shape whose length along the first direction X is longer than the length along the second direction Y, as indicated by a broken line. The gate wiring G1 and the gate wiring G2 are arranged at a first pitch along the second direction Y, and extend along the first direction X, respectively. The auxiliary capacitance line C1 is located between the gate line G1 and the gate line G2, and extends along the first direction X. The source wiring S1 and the source wiring S2 are arranged at the second pitch along the first direction X and extend along the second direction Y, respectively.

  In the illustrated pixel PX, the source line S1 is disposed at the left end, and the source line S2 is disposed at the right end. Strictly speaking, the source line S1 is disposed across the boundary between the pixel PX and the pixel adjacent to the left side, and the source line S2 is disposed over the boundary between the pixel PX and the pixel adjacent to the right side. Yes. That is, the length along the first direction X of the pixel PX corresponds to the second pitch between the source lines.

  In the pixel PX, the gate line G1 is disposed at the upper end, and the gate line G2 is disposed at the lower end. Strictly speaking, the gate line G1 is disposed over the boundary between the pixel PX and the adjacent pixel on the upper side, and the gate line G2 is disposed over the boundary between the pixel PX and the adjacent pixel on the lower side. ing. That is, the length along the second direction Y of the pixel PX corresponds to the first pitch between the gate lines. The first pitch is smaller than the second pitch.

  In the illustrated pixel PX, the auxiliary capacitance line C1 is unevenly distributed on the gate line G1 side rather than the gate line G2 side. That is, the interval along the second direction Y between the auxiliary capacitance line C1 and the gate line G1 is smaller than the interval along the second direction Y between the auxiliary capacitance line C1 and the gate line G2.

  In the illustrated example, the switching element SW is electrically connected to the gate line G2 and the source line S1. The switching element SW is provided near the intersection of the gate line G2 and the source line S1, particularly in a region between the auxiliary capacitance line C1 and the gate line G2. Such a switching element SW includes a gate electrode WG formed integrally with the gate line G2, a semiconductor layer SC made of amorphous silicon formed immediately above the gate electrode WG, and a semiconductor layer formed integrally with the source line S1. A source electrode WS in contact with the SC and a drain electrode WD in contact with the semiconductor layer SC are provided.

  The pixel electrode PE is located between the adjacent source line S1 and source line S2, and is located between the gate line G1 and the gate line G2. That is, the pixel electrode PE is located on the inner side surrounded by the source wiring S1 and the source wiring S2, and the gate wiring G1 and the gate wiring G2. Such a pixel electrode PE is electrically connected to the drain electrode WD of the switching element SW via the contact hole CH1 and the contact hole CH2.

  The pixel electrode PE includes two or more main pixel electrodes PA that are electrically connected to each other. In the illustrated example, the pixel electrode PE includes two main pixel electrodes PA1 and PA2 while being electrically connected to the switching element SW near the left end of the pixel PX. Each of the main pixel electrode PA1 and the main pixel electrode PA2 extends linearly along the first direction X toward the right end portion of the pixel PX (that is, toward the source line S2). Each of the main pixel electrode PA1 and the main pixel electrode PA2 is formed in a strip shape having substantially the same width along the second direction Y.

  Among the main pixel electrodes PA of the pixel electrode PE, at least one main pixel electrode PA is located above the auxiliary capacitance line C1. In the illustrated example, the main pixel electrode PA1 is located above the auxiliary capacitance line C1. That is, in such a pixel electrode PE, in the vicinity of the contact hole CH1 and the contact hole CH2 connected to the drain electrode WD and in the main pixel electrode PA1, the storage capacitor line C1 is opposed to display an image on the pixel PX. The necessary capacity is formed.

  The array substrate AR may further include a part of the common electrode CE.

  In such an array substrate AR, the pixel electrode PE is covered with the first alignment film AL1. The first alignment film AL1 is subjected to alignment treatment (for example, rubbing treatment or photo-alignment treatment) along the first alignment treatment direction PD1 in order to initially align the liquid crystal molecules of the liquid crystal layer LQ. The first alignment treatment direction PD1 in which the first alignment film AL1 initially aligns the liquid crystal molecules is substantially parallel to the first direction X that is the extending direction of the main pixel electrode PA.

  Here, an example of the dimensions will be described. The pitch of the gate wiring G, that is, the distance between the gate wiring G1 and the gate wiring G2 in the second direction Y is 50 μm to 60 μm. The distance along the first direction X with the source line S2 is 150 μm to 180 μm, the width along the second direction Y of the gate line G and the auxiliary capacitance line C is 5 μm, and the second direction of the main pixel electrode PA. The width along Y is 5 μm, and the width along the first direction X of the source wiring S is 3 μm. Note that the gate line G and the auxiliary capacitance line C are formed in the same layer and need to be electrically insulated, so a margin of, for example, 10 μm is secured between them.

  FIG. 3 is a plan view schematically showing a structural example of one pixel PX in the counter substrate CT shown in FIG. Here, a plan view in the XY plane is shown. Here, only the configuration necessary for the description is illustrated, and the pixel electrode PE, the source wiring S, the gate wiring G, and the like provided in the array substrate are indicated by broken lines.

  The common electrode CE includes a main common electrode CA on the counter substrate CT. In the illustrated example, the common electrode CE further includes a sub-common electrode CB on the counter substrate CT. The main common electrode CA and the sub-common electrode CB are electrically connected to each other. However, the sub-common electrode CB may be omitted.

  The main common electrode CA is linear along a first direction X substantially parallel to the extending direction of the main pixel electrode PA on both sides of the main pixel electrode PA1 and the main pixel electrode PA2 in the XY plane. It extends to. Alternatively, one main common electrode CA is disposed above the gate line G and between the main pixel electrodes PA, and extends along a first direction X substantially parallel to the extending direction of the main pixel electrode PA. I'm out. Such a main common electrode CA is formed in a strip shape having substantially the same width along the second direction Y.

  In the illustrated example, three main common electrodes CA are arranged in parallel in the second direction Y at intervals. That is, three main common electrodes CA are arranged at equal pitches along the second direction Y per pixel. In the pixel PX, the main common electrode CAU is disposed at the upper end, the main common electrode CAB is disposed at the lower end, and the main common electrode CAC is disposed at the center of the pixel. Strictly speaking, the main common electrode CAU is disposed over the boundary between the pixel PX and the adjacent pixel on the upper side, and the main common electrode CAB is disposed over the boundary between the pixel PX and the adjacent pixel on the lower side. Has been placed. The main common electrode CAU is located above the gate line G1, and the main common electrode CAB is located above the gate line G2.

  The main common electrode CAU and the main common electrode CAC are located on both sides of the main pixel electrode PA1. Similarly, the main common electrode CAC and the main common electrode CAB are located on both sides of the main pixel electrode PA2. In other words, the main common electrode CAC disposed in the center of the pixel is located between the main pixel electrode PA1 and the main pixel electrode PA2. That is, in the XY plane, the main common electrode CA and the main pixel electrode PA are alternately arranged along the second direction Y. In the illustrated example, the main common electrode CAU, the main pixel electrode PA1, and the main common electrode are arranged. The CAC, the main pixel electrode PA2, and the main common electrode CAB are arranged in this order. In addition, the electrode interval along the second direction Y between the main common electrode CAU and the main pixel electrode PA1, the electrode interval along the second direction Y between the main pixel electrode PA1 and the main common electrode CAC, the main common The electrode interval along the second direction Y between the electrode CAC and the main pixel electrode PA2 and the electrode interval along the second direction Y between the main pixel electrode PA2 and the main common electrode CAB are substantially equal. It is desirable.

  The sub-common electrode CB extends linearly along the second direction Y on both sides of the pixel electrode PE in the XY plane. Alternatively, the sub-common electrode CB is disposed above the source line S and extends linearly along the second direction Y. Such a sub-common electrode CB is formed in a strip shape having substantially the same width along the first direction X. Further, such a sub-common electrode CB is formed integrally or continuously with the main common electrode CA and is electrically connected to the main common electrode CA. That is, in the counter substrate CT, the common electrode CE is formed in a lattice shape.

  In the illustrated example, two sub-common electrodes CB are arranged in parallel in the first direction X with an interval between them, and are arranged at both left and right ends of the pixel PX, respectively. That is, two sub-common electrodes CB are arranged per pixel. In the illustrated pixel PX, the sub-common electrode CBL is disposed at the left end, and the sub-common electrode CBR is disposed at the right end. Strictly speaking, the sub-common electrode CBL is disposed over the boundary between the pixel PX and the pixel adjacent to the left side, and the sub-common electrode CBR is disposed over the boundary between the pixel PX and the pixel adjacent to the right side. Has been. The sub-common electrode CBL is located above the source line S1, and the sub-common electrode CBR is located above the source line S2.

  In such a counter substrate CT, the common electrode CE is covered with the second alignment film AL2. The second alignment film AL2 is subjected to alignment treatment (for example, rubbing treatment or photo-alignment treatment) along the second alignment treatment direction PD2 in order to initially align the liquid crystal molecules of the liquid crystal layer LQ. The second alignment treatment direction PD2 in which the second alignment film AL2 initially aligns the liquid crystal molecules is parallel to the first alignment treatment direction PD1 and is in the same direction or in the opposite direction. In the illustrated example, the second alignment processing direction PD2 is parallel to the first direction X, and in the XY plane, the first alignment processing direction PD1 is parallel to each other and is in the same direction.

  As shown in FIG. 3, the opening AP has a rectangular shape whose length along the first direction X is longer than the length along the second direction Y.

  FIG. 4 is a cross-sectional view schematically showing a cross-sectional structure of the array substrate AR cut along the line AB in FIG.

  The array substrate AR is formed using a first insulating substrate 10 having light transparency. The array substrate AR includes the switching element SW, the auxiliary capacitance line C1, the pixel electrode PE, the first insulating film 11, the second insulating film 12, the third insulating film 13, the first alignment film AL1, and the like in the first insulating substrate 10. I have.

  The gate electrode WG of the switching element SW is a part of the gate wiring G2, and is formed on the inner surface 10A of the first insulating substrate 10. The auxiliary capacitance line C <b> 1 is formed on the inner surface 10 </ b> A of the first insulating substrate 10. The gate electrode WG and the auxiliary capacitance line C1 are covered with the first insulating film 11.

  The semiconductor layer SC of the switching element SW is formed on the first insulating film 11 and is located immediately above the gate electrode WG. The source electrode WS of the switching element SW is a part of the source line S1, is formed on the first insulating film 11, and is in contact with the semiconductor layer SC. The drain electrode WD of the switching element SW is formed on the first insulating film 11 and is in contact with the semiconductor layer SC. The semiconductor layer SC, the source electrode WS, and the drain electrode WD are covered with the second insulating film 12. In the second insulating film 12, a contact hole CH1 penetrating to the drain electrode WD is formed.

  The third insulating film 13 is formed on the second insulating film 12. A contact hole CH2 is formed in the third insulating film 13. The contact hole CH2 is larger in size than the contact hole CH1, and penetrates to the drain electrode WD through the contact hole CH1 and to the second insulating film 12 around the contact hole CH1.

  The pixel electrode PE is formed on the third insulating film 13 and is in contact with the drain electrode WD via the contact hole CH1 and the contact hole CH2. A part of the pixel electrode PE (for example, the main pixel electrode PA1) is opposed to the auxiliary capacitance line C1 through the first insulating film 11, the second insulating film 12, and the third insulating film 13. .

  The first alignment film AL1 covers the pixel electrode PE and the like, and is also disposed on the third insulating film 13. Such a first alignment film AL1 is formed of a material exhibiting horizontal alignment.

  FIG. 5 is a cross-sectional view schematically showing a cross-sectional structure of the liquid crystal display panel LPN cut along line CD in FIG.

  A backlight 4 is disposed on the back side of the array substrate AR constituting the liquid crystal display panel LPN. As the backlight 4, various forms are applicable, and any of those using a light emitting diode (LED) or a cold cathode tube (CCFL) as a light source can be applied. The description of the structure is omitted.

  In the array substrate AR, the gate wiring G1, the auxiliary capacitance line C1, and the gate wiring G2 are formed on the inner surface 10A of the first insulating substrate 10, that is, on the side facing the counter substrate CT, and covered with the first insulating film 11. It has been broken. The main pixel electrode PA1 and the main pixel electrode PA2 of the pixel electrode PE are formed on the third insulating film 13 and covered with the first alignment film AL1. The main pixel electrode PA1 and the main pixel electrode PA2 are located on the inner side of the gate wiring G1 and the gate wiring G2, respectively. The main pixel electrode PA1 is located immediately above the auxiliary capacitance line C1. A first insulating film 11, a second insulating film 12, and a third insulating film 13 are interposed between the main pixel electrode PA1 and the auxiliary capacitance line C1. The first alignment film AL1 is disposed on the surface of the array substrate AR that faces the counter substrate CT, and extends over substantially the entire active area ACT.

  The counter substrate CT is formed by using a second insulating substrate 20 having optical transparency. The counter substrate CT includes a black matrix BM, a color filter CF, an overcoat layer OC, a common electrode CE, a second alignment film AL2, and the like on the inner side of the second insulating substrate 20, that is, on the side facing the array substrate AR. Yes.

  The black matrix BM partitions each pixel PX and forms an opening AP. That is, the black matrix BM is disposed so as to face wiring portions such as the source wiring S, the gate wiring G, the auxiliary capacitance line C, and the switching element SW. In the example shown here, the black matrix BM includes a portion positioned above the gate wiring G1 and the gate wiring G2, and a portion positioned above the switching element SW, the source wiring S1, the source wiring S2, and the like (not shown). It is formed in a lattice shape. The black matrix BM is disposed on the inner surface 20A of the second insulating substrate 20 facing the array substrate AR.

  The color filter CF is arranged corresponding to each pixel PX. That is, the color filter CF is disposed on the inner surface 20A of the second insulating substrate 20 on the inner side partitioned by the black matrix BM, and a part of the color filter CF rides on the black matrix BM. The color filters CF arranged in the pixels PX adjacent to each other in the second direction Y have different colors. For example, the color filter CF is formed of resin materials colored in three primary colors such as red, blue, and green. A red color filter made of a resin material colored in red is arranged corresponding to the red pixel. A blue color filter made of a resin material colored in blue is arranged corresponding to a blue pixel. A green color filter made of a resin material colored in green is arranged corresponding to the green pixel. The boundary between these color filters CF is at a position overlapping the black matrix BM.

  The overcoat layer OC covers the color filter CF. This overcoat layer OC alleviates the influence of irregularities on the surface of the color filter CF.

  The main common electrode CAU, the main common electrode CAC, the main common electrode CAB, the sub-common electrode CB (not shown), and the like are formed on the side of the overcoat layer OC facing the array substrate AR. In particular, the main common electrode CAU, the main common electrode CAB, and the sub-common electrode CB (not shown) are located immediately below the black matrix BM. The main common electrode CAU is located immediately above the gate line G1. The main common electrode CAB is located immediately above the gate line G2. The main common electrode CAC is located between the main common electrode CAU and the main common electrode CAB, and no main pixel electrode is located immediately below, and no gate wiring is located.

  In the opening AP, a region between the pixel electrode PE and the common electrode CE, that is, a region between the main common electrode CAU and the main pixel electrode PA1, and a region between the main common electrode CAC and the main pixel electrode PA1. The region, the region between the main common electrode CAC and the main pixel electrode PA2, and the region between the main common electrode CAB and the main pixel electrode PA2 correspond to a transmission region through which the backlight can be transmitted.

  The second alignment film AL2 is disposed on the surface of the counter substrate CT facing the array substrate AR, and extends over substantially the entire active area ACT. The second alignment film AL2 covers the common electrode CE, the overcoat layer OC, and the like. Such a second alignment film AL2 is formed of a material exhibiting horizontal alignment.

  The array substrate AR and the counter substrate CT as described above are arranged so that the first alignment film AL1 and the second alignment film AL2 face each other. At this time, a predetermined cell is formed between the first alignment film AL1 of the array substrate AR and the second alignment film AL2 of the counter substrate CT by, for example, a columnar spacer integrally formed on one substrate with a resin material. A gap, for example a cell gap of 2-7 μm, is formed. The array substrate AR and the counter substrate CT are bonded to each other with a sealing material outside the active area ACT in a state where a predetermined cell gap is formed.

  The liquid crystal layer LQ is held in a cell gap formed between the array substrate AR and the counter substrate CT, and is disposed between the first alignment film AL1 and the second alignment film AL2. Such a liquid crystal layer LQ is made of, for example, a liquid crystal material having a positive dielectric anisotropy (positive type).

  The interval between the main pixel electrode PA and the main common electrode CA in the second direction Y is larger than the thickness of the liquid crystal layer LQ, and the interval between the main pixel electrode PA and the main common electrode CA is the same as that of the liquid crystal layer LQ. It has a size more than twice the thickness.

  The first optical element OD1 is attached to the outer surface of the array substrate AR, that is, the outer surface 10B of the first insulating substrate 10 constituting the array substrate AR with an adhesive or the like. The first optical element OD1 is located on the side facing the backlight 4 of the liquid crystal display panel LPN, and controls the polarization state of incident light incident on the liquid crystal display panel LPN from the backlight 4. The first optical element OD1 includes a first polarizing plate PL1 having a first polarization axis (or first absorption axis) AX1. Note that another optical element such as a retardation plate may be disposed between the first polarizing plate PL1 and the first insulating substrate 10.

  The second optical element OD2 is attached to the outer surface of the counter substrate CT, that is, the outer surface 20B of the second insulating substrate 20 constituting the counter substrate CT with an adhesive or the like. The second optical element OD2 is located on the display surface side of the liquid crystal display panel LPN, and controls the polarization state of the outgoing light emitted from the liquid crystal display panel LPN. The second optical element OD2 includes a second polarizing plate PL2 having a second polarization axis (or second absorption axis) AX2. Note that another optical element such as a retardation plate may be disposed between the second polarizing plate PL2 and the second insulating substrate 20.

  The first polarizing axis AX1 of the first polarizing plate PL1 and the second polarizing axis AX2 of the second polarizing plate PL2 are in a substantially orthogonal positional relationship (crossed Nicols). At this time, one polarizing plate is disposed, for example, so that the polarization axis thereof is substantially parallel or substantially orthogonal to the extending direction of the main pixel electrode PA or the main common electrode CA. That is, when the extending direction of the main pixel electrode PA or the main common electrode CA is the first direction X, the absorption axis of one polarizing plate is substantially parallel to the first direction X (that is, the second direction Y and Or substantially perpendicular to the first direction X (that is, substantially parallel to the second direction Y).

  Alternatively, one polarizing plate is disposed, for example, so that the polarization axis thereof is parallel or orthogonal to the initial alignment direction of the liquid crystal molecules, that is, the first alignment processing direction PD1 or the second alignment processing direction PD2. When the initial alignment direction is parallel to the first direction X, the polarization axis of one polarizing plate is parallel to the first direction X or parallel to the second direction Y.

  In the example shown in FIG. 3A, the first polarizing plate PL1 has the first polarizing axis AX1 in the extending direction of the main pixel electrode PA or the initial alignment direction (first direction X) of the liquid crystal molecules LM. The second polarizing plate PL2 is disposed so as to be parallel to the first direction X (that is, parallel to the first direction X). The second polarizing axis AX2 of the second polarizing plate PL2 is the extension direction of the main pixel electrode PA or the liquid crystal molecule LM. Are arranged so as to be orthogonal to the initial alignment direction (that is, parallel to the second direction Y).

  In the example shown in FIG. 3B, the second polarizing plate PL2 has a second polarizing axis AX2 whose extension direction of the main pixel electrode PA or initial alignment direction of the liquid crystal molecules LM (first direction X). ) In parallel (that is, parallel to the first direction X), and the first polarizing plate PL1 has a first polarization axis AX1 extending in the main pixel electrode PA or a liquid crystal. The molecules LM are arranged so as to be orthogonal to the initial alignment direction (that is, parallel to the second direction Y).

  Next, the operation of the liquid crystal display panel LPN configured as described above will be described with reference to FIGS.

  That is, in a state where no voltage is applied to the liquid crystal layer LQ, that is, in a state where no electric field is formed between the pixel electrode PE and the common electrode CE (when OFF), the liquid crystal molecules LM of the liquid crystal layer LQ The major axis is oriented so as to face the first orientation treatment direction PD1 of the first orientation film AL1 and the second orientation treatment direction PD2 of the second orientation film AL2. Such OFF time corresponds to the initial alignment state, and the alignment direction of the liquid crystal molecules LM at the OFF time corresponds to the initial alignment direction.

  Strictly speaking, the liquid crystal molecules LM are not always aligned parallel to the XY plane, and are often pretilted. For this reason, the initial alignment direction of the liquid crystal molecules LM here is a direction obtained by orthogonally projecting the major axis of the liquid crystal molecules LM at the time of OFF to the XY plane. Hereinafter, in order to simplify the description, it is assumed that the liquid crystal molecules LM are aligned in parallel to the XY plane and rotate in a plane parallel to the XY plane.

  Here, both the first alignment treatment direction PD1 and the second alignment treatment direction PD2 are substantially parallel to the first direction X. At the OFF time, the liquid crystal molecules LM are initially aligned in the direction in which the major axis is substantially parallel to the first direction X, as indicated by a broken line in FIG.

  As in the illustrated example, when the first alignment processing direction PD1 and the second alignment processing direction PD2 are parallel and in the same direction, in the cross section of the liquid crystal layer LQ, the liquid crystal molecules LM are substantially near the middle portion of the liquid crystal layer LQ. Alignment is performed horizontally (pretilt angle is substantially zero), and is aligned with a pretilt angle that is symmetrical in the vicinity of the first alignment film AL1 and in the vicinity of the second alignment film AL2 (spray alignment).

  Here, as a result of the alignment processing of the first alignment film AL1 in the first alignment processing direction PD1, the liquid crystal molecules LM in the vicinity of the first alignment film AL1 are initially aligned in the first alignment processing direction PD1, and the second alignment film AL2 is formed. As a result of the alignment processing in the second alignment processing direction PD2, the liquid crystal molecules LM in the vicinity of the second alignment film AL2 are initially aligned in the second alignment processing direction PD1. When the first alignment treatment direction PD1 and the second alignment treatment direction PD2 are parallel to each other and in the same direction, the liquid crystal molecules LM are in the splay alignment as described above, and as described above, the intermediate between the liquid crystal layers LQ. The alignment of the liquid crystal molecules LM in the vicinity of the first alignment film AL1 on the array substrate AR and the alignment of the liquid crystal molecules LM in the vicinity of the second alignment film AL2 on the counter substrate CT are symmetrical in the vertical direction with the portion as a boundary. Become. For this reason, optical compensation is also made in a direction inclined from the normal direction of the substrate. Therefore, when the first alignment processing direction PD1 and the second alignment processing direction PD2 are parallel to each other and in the same direction, light leakage is small in the case of black display, and a high contrast ratio can be realized. It becomes possible to improve the quality.

  When the first alignment treatment direction PD1 and the second alignment treatment direction PD2 are parallel and opposite to each other, the liquid crystal molecules LM are in the vicinity of the first alignment film AL1, in the second alignment film AL2 in the cross section of the liquid crystal layer LQ. And in the middle part of the liquid crystal layer LQ with a substantially uniform pretilt angle (homogeneous alignment).

  Part of the backlight light from the backlight 4 passes through the first polarizing plate PL1 and enters the liquid crystal display panel LPN. The light incident on the liquid crystal display panel LPN is linearly polarized light orthogonal to the first absorption axis AX1 of the first polarizing plate PL1. The polarization state of such linearly polarized light changes depending on the alignment state of the liquid crystal molecules LM when passing through the liquid crystal layer LQ, but the polarization state of the linearly polarized light that has passed through the liquid crystal layer LQ hardly changes at the OFF time. Therefore, the linearly polarized light transmitted through the liquid crystal display panel LPN is absorbed by the second polarizing plate PL2 having a crossed Nicol positional relationship with the first polarizing plate PL1 (black display).

  On the other hand, in a state where a voltage is applied to the liquid crystal layer LQ, that is, a state where an electric field is formed between the pixel electrode PE and the common electrode CE (when ON), the substrate is interposed between the pixel electrode PE and the common electrode CE. A horizontal electric field (or an oblique electric field) substantially parallel to the line is formed. The liquid crystal molecules LM are affected by the electric field and rotate in a plane whose major axis is substantially parallel to the XY plane as indicated by the solid line in the figure.

  In the example shown in FIG. 3, in the pixel PX, for example, in the region between the main pixel electrode PA1 and the main common electrode CAC, the liquid crystal molecules LM rotate counterclockwise with respect to the first direction X. Oriented to face the lower left in the figure. Further, in the region between the main pixel electrode PA2 and the main common electrode CAC, the liquid crystal molecules LM are rotated clockwise with respect to the first direction X and oriented so as to face the upper left in the drawing.

  As described above, in each pixel PX, in a state where an electric field is formed between the pixel electrode PE and the common electrode CE, the alignment direction of the liquid crystal molecules LM overlaps with the main pixel electrode PA or the main common electrode CA. Dividing into a plurality of directions with the position as a boundary, a domain is formed in each orientation direction. That is, a plurality of domains are formed in one pixel PX.

  At such an ON time, part of the backlight light incident on the liquid crystal display panel LPN from the backlight 4 is transmitted through the first polarizing plate PL1 and incident on the liquid crystal display panel LPN. The light incident on the liquid crystal display panel LPN is linearly polarized light orthogonal to the first absorption axis AX1 of the first polarizing plate PL1. The polarization state of such linearly polarized light changes according to the alignment state of the liquid crystal molecules LM when passing through the liquid crystal layer LQ. For example, when linearly polarized light parallel to the first direction X is incident on the liquid crystal display panel LPN, it is oriented in the 45 ° -225 ° azimuth or 135 ° -315 ° azimuth with respect to the first direction X when passing through the liquid crystal layer LQ. The liquid crystal molecules LM are affected by the phase difference of λ / 2 (where λ is the wavelength of light transmitted through the liquid crystal layer LQ). Thereby, the polarization state of the light that has passed through the liquid crystal layer LQ becomes linearly polarized light parallel to the second direction Y. For this reason, at the time of ON, at least a part of the light that has passed through the liquid crystal layer LQ is transmitted through the second polarizing plate PL2 (white display). However, at the position overlapping with the pixel electrode or the common electrode, since the liquid crystal molecules maintain the initial alignment state, black display is performed as in the OFF state.

  According to the present embodiment, the length along the first direction X, which is the extending direction of the gate wiring or the auxiliary capacitance line, is longer than the length along the second direction Y, which is the extending direction of the source wiring. Due to the pixel configuration, the total number of pixels in the active area is the same as in the case of a vertically long pixel configuration in which the length along the second direction Y is longer than the length along the first direction X. However, the total number of signal wirings such as gate wirings, auxiliary capacitance lines, and source wirings can be reduced.

  In the active area ACT shown in FIG. 1, when a vertically long pixel configuration is adopted, for example, the total number of source lines S is 2400 (m = 2400), and the total number of gate lines G is 480 (n = 480). On the other hand, when a horizontally long pixel configuration is adopted, the total number of source lines S is 800 (m = 800), the total number of gate lines G is 1440 (n = 1440), and 640 lines. Signal wiring can be reduced.

  As described above, since the total number of signal lines can be reduced, the number of terminals of the signal lines can be reduced, and the scale of drivers for supplying signals to these signal lines can be reduced and the liquid crystal display panel LPN can be reduced. It is possible to reduce the number of drive IC chips to be mounted on the board. Therefore, cost can be reduced.

  Further, according to the present embodiment, high transmittance can be obtained in the electrode gap between the pixel electrode PE and the common electrode CE. In addition, in order to sufficiently increase the transmittance per pixel, it is possible to cope with the problem by increasing the inter-electrode distance between the main pixel electrode PA and the main common electrode CA. For product specifications with different pixel pitches, the peak condition of the transmittance distribution can be used by changing the inter-electrode distance between the main pixel electrode PA and the main common electrode CA. That is, in the display mode of the present embodiment, fine electrode processing is not always required from a low-resolution product specification with a relatively large pixel pitch to a high-resolution product specification with a relatively small pixel pitch, and the distance between the electrodes is not required. Products with various pixel pitches can be provided by setting.

  Further, according to the present embodiment, the transmittance is sufficiently lowered in the region overlapping with the black matrix BM. This is because an electric field does not leak outside the pixel from the position of the common electrode CE located immediately above the gate line G and the source line S, and it is not desired between adjacent pixels across the black matrix BM. This is because no horizontal electric field is generated, and the liquid crystal molecules LM in the region overlapping with the black matrix BM maintain the initial alignment state as in the OFF state (or during black display). Therefore, even when the color of the color filter CF is different between adjacent pixels, it is possible to suppress the occurrence of color mixing, and it is possible to suppress a decrease in color reproducibility and a decrease in contrast ratio.

  Further, when misalignment between the array substrate AR and the counter substrate CT occurs, there may be a difference in the inter-electrode distance between the common electrode CE on both sides of the pixel electrode PE. However, since such misalignment occurs in common for all the pixels PX, there is no difference in the electric field distribution among the pixels PX, and the influence on the display of the image is extremely small. In addition, even if a misalignment occurs between the array substrate AR and the counter substrate CT, it is possible to suppress undesired electric field leakage to adjacent pixels. For this reason, even when the color of the color filter CF is different between adjacent pixels, it is possible to suppress the occurrence of color mixing, and it is possible to suppress a decrease in color reproducibility and a decrease in contrast ratio. .

  Further, according to the present embodiment, a plurality of domains can be formed in one pixel. Therefore, the viewing angle can be optically compensated in a plurality of directions, and a wide viewing angle can be achieved.

  In the above example, the case where the initial alignment direction of the liquid crystal molecules LM is parallel to the first direction X has been described. However, the initial alignment direction of the liquid crystal molecules LM is oblique to the first direction X and the second direction Y. It may be an oblique direction that intersects.

  In the above example, the case where the liquid crystal layer LQ is made of a liquid crystal material having positive (positive type) dielectric anisotropy has been described. However, the liquid crystal layer LQ has a negative dielectric anisotropy (negative). Type) liquid crystal material.

  Even when ON, the horizontal electric field is hardly formed on the pixel electrode PE or the common electrode CE (or an electric field sufficient to drive the liquid crystal molecule LM is not formed), so that the liquid crystal molecule LM is OFF. As with time, it hardly moves from the initial orientation direction. For this reason, even if the pixel electrode PE and the common electrode CE are formed of a light-transmitting conductive material such as ITO, the backlight hardly transmits in these regions, and hardly contributes to the display when ON. Therefore, the pixel electrode PE and the common electrode CE do not necessarily need to be formed of a transparent conductive material, such as aluminum (Al), titanium (Ti), silver (Ag), molybdenum (Mo), and tungsten (W). An opaque conductive material may be used.

  When at least one of the pixel electrode PE and the common electrode CE is formed of the above-described opaque conductive material, the linearly polarized light incident on the liquid crystal display panel LPN is substantially parallel to the extending direction of the edge of the pixel electrode PE or the common electrode CE. Or substantially orthogonal. In addition, the extending direction of the gate line G, the auxiliary capacitance line C, and the source line S formed of the opaque conductive material as described above is substantially parallel to the linearly polarized light incident on the liquid crystal display panel LPN. It is almost orthogonal. For this reason, the linearly polarized light reflected at the edges of the pixel electrode PE, the common electrode CE, the gate wiring G, the auxiliary capacitance line C, and the source wiring S is not easily disturbed, and the first polarizing plate is a polarizer. The polarization plane when passing through PL1 can be maintained. Accordingly, at the time of OFF, the linearly polarized light transmitted through the liquid crystal display panel LPN is sufficiently absorbed by the second polarizing plate PL2, which is an analyzer, and thus light leakage can be suppressed. That is, the transmittance can be sufficiently reduced during black display, and the reduction in contrast ratio can be suppressed. Further, it is not necessary to expand the width of the black matrix BM in order to prevent light leakage around the pixel electrode PE and the common electrode CE, and it is possible to suppress the reduction of the area of the opening AP and the reduction of the transmittance at the time of ON. Is possible.

  In addition, since the backlight hardly transmits on the pixel electrode PE or the common electrode CE even when it is ON, the main pixel electrode PA and the auxiliary capacitance line C of the pixel electrode PE overlap each other in the opening AP to increase the capacitance. Even if it is the structure to form, the area of the substantial transmissive area | region in the opening part AP is not reduced. That is, according to the present embodiment in which a capacitance is formed by the main pixel electrode PA and the auxiliary capacitance line C, it is possible to secure a capacitance necessary for display in the pixel PX without reducing the area of the transmission region. .

  In addition, since some of the main common electrodes CA are located above the gate lines G that do not contribute to display, the substantial area of the transmission region in the opening AP is not reduced.

  In the above example, the configuration in which one pixel electrode PE includes two main pixel electrodes PA has been described. However, the present invention is not limited to this example. When the number of main pixel electrodes PA included in one pixel electrode PE is a, the number of main common electrodes CA arranged per pixel is (a + 1), and one is provided between adjacent main common electrodes CA. Main pixel electrodes PA are disposed (where a is a positive number).

  In the present embodiment, the structure of the pixel PX is not limited to the above example.

  FIG. 6 is a plan view schematically showing another structural example of one pixel PX when the array substrate AR shown in FIG. 1 is viewed from the counter substrate side.

  Compared with the structural example shown in FIG. 2, the structural example shown here is not only between the auxiliary capacitive line C1 and the main pixel electrode PA1, but also between the auxiliary capacitive line C1 and the main pixel electrode PA2. Is different in that it forms. That is, the auxiliary capacitance line C1 is located immediately below the main pixel electrode PA1, and a part of the auxiliary capacitance line C1 branches off and extends along the first direction X and is located immediately below the main pixel electrode PA2. According to such a structure example, it is possible to form a larger capacity than the structure example shown in FIG. 2 without reducing the area of the transmission region in the opening AP.

  FIG. 7 is a plan view schematically showing another structural example of one pixel PX when the array substrate AR shown in FIG. 1 is viewed from the counter substrate side.

  The structural example shown here is different from the structural example shown in FIG. 2 in that the array substrate AR includes a gate shield electrode GS and a source shield electrode SS.

  That is, the gate shield electrode GS is opposed to the gate line G1 and the gate line G2. Such a gate shield electrode GS extends linearly along the first direction X and is formed in a strip shape. Note that the width of the gate shield electrode GS along the second direction Y is not necessarily constant. The gate shield electrode GS is electrically connected to the common electrode CE and has the same potential as the common electrode CE.

  The source shield electrode SS is opposed to the source line S1 and the source line S2. Such a source shield electrode SS extends linearly along the second direction Y and is formed in a strip shape. Note that the width along the first direction X of the source shield electrode SS is not necessarily constant. The source shield electrode SS is electrically connected to the common electrode CE and has the same potential as the common electrode CE. In the illustrated example, the gate shield electrode GS and the source shield electrode SS are integrally or continuously formed.

  Since the gate shield electrode GS and the source shield electrode SS are formed on the upper surface of the third insulating film 13 which is the same layer as the pixel electrode PE, they are formed using the same material (for example, ITO) as the pixel electrode PE. Is possible.

  In the array substrate AR having such a structure example, when combined with the counter substrate CT shown in FIG. 3, the gate shield electrode GS faces the main common electrode CA, and the source shield electrode SS faces the sub-common electrode CB. .

  According to such a structural example, since the gate shield electrode GS faces the gate line G, an undesired electric field from the gate line G can be shielded. For this reason, it is possible to suppress an undesired bias from being applied to the liquid crystal layer LQ from the gate wiring G, and it is possible to prevent display defects such as burn-in and the liquid crystal molecule alignment defects. It becomes possible to suppress the occurrence of leakage.

  Further, since the source shield wiring SS is opposed to the source wiring S, an undesired electric field from the source wiring S can be shielded. For this reason, it is possible to suppress an undesired bias from being applied to the liquid crystal layer LQ from the source wiring S, and crosstalk (for example, a state in which the pixel PX is set to a pixel potential for displaying black). Thus, when a pixel potential for displaying white is supplied to the source wiring connected to the pixel PX, a display defect such as a phenomenon in which light leaks from a part of the pixel PX and increases in luminance) occurs. Can be suppressed.

  Further, since the gate shield electrode GS and the source shield electrode SS provided in the array substrate AR are electrically connected to each other and are formed in a lattice shape in the array substrate AR, the redundancy can be improved. . Further, since the main common electrode CA and the sub-common electrode CB provided in the counter substrate CT are electrically connected to each other and formed in a lattice shape, the redundancy can be improved. Since the gate shield electrode GS and source shield electrode SS on the array substrate AR side and the main common electrode CA and sub-common electrode CB on the counter substrate CT side are electrically connected to each other, disconnection occurs in part. Even if it does, it becomes possible to supply a common electric potential stably to each pixel PX, and it becomes possible to suppress generation | occurrence | production of a display defect.

  Note that the gate shield electrode GS and the source shield electrode SS may also be applied to the structural example shown in FIG.

  FIG. 8 is a plan view schematically showing another structure example of one pixel PX when the array substrate AR shown in FIG. 1 is viewed from the counter substrate side.

  The structural example shown here is different from the structural example shown in FIG. 2 in that the gate wiring G is arranged at substantially the center of the pixel PX.

  That is, in the pixel PX, the storage capacitor line C1 is disposed at the upper end, and the storage capacitor line C2 is disposed at the lower end. Strictly speaking, the storage capacitor line C1 is disposed over the boundary between the pixel PX and the adjacent pixel on the upper side, and the storage capacitor line C2 is formed over the boundary between the pixel PX and the adjacent pixel on the lower side. Has been placed. The gate line G1 is located between the auxiliary capacitance line C1 and the auxiliary capacitance line C2. The switching element SW is electrically connected to the gate line G1 and the source line S1. The pixel electrode PE is electrically connected to the switching element SW, and between the main pixel electrode PA1 located between the gate line G1 and the auxiliary capacitance line C1, and between the gate line G2 and the auxiliary capacitance line C1. A main pixel electrode PA2 is provided.

  The array substrate AR having such a structure example can be combined with the counter substrate CT shown in FIG. In this case, the main common electrode CAU is located above the auxiliary capacitance line C1, the main common electrode CAC is located above the gate line G1, and the main common electrode CAB is located above the auxiliary capacitance line C2.

  The array substrate having such a structure example is applicable to a specification in which the capacitance formed between the pixel electrode PE and the auxiliary capacitance line C1 is relatively small as compared with the structure example shown in FIG. .

  As described above, according to the present embodiment, it is possible to provide a liquid crystal display device capable of reducing cost and suppressing deterioration in display quality.

  In addition, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

LPN ... Liquid crystal display panel AR ... Array substrate CT ... Counter substrate LQ ... Liquid crystal layer PE ... Pixel electrode PA ... Main pixel electrode
CE ... Common electrode CA ... Main common electrode CB ... Sub-common electrode G ... Gate wiring C ... Auxiliary capacitance line S ... Source wiring

Claims (11)

A first gate wiring and a second gate wiring extending along a first direction and arranged at a first pitch along a second direction intersecting the first direction; the first gate wiring and the second gate wiring; Auxiliary capacitance lines extending along the first direction with the gate wiring, and extending along the second direction and arranged at a second pitch larger than the first pitch along the first direction. A first source line and a second source line; a first switching element electrically connected to the first gate line and the first source line; and the second gate line and the first source line. a second switching element connected, the second direction in located inside surrounded by the first gate wiring and said second gate wiring and the first source line and the second source line and the second switching element At least one said main pixel electrode comprises two or more main pixel electrode extending along the first direction respectively a drain electrode electrically connected to a pixel electrode extending in the auxiliary capacitance line A first substrate comprising a pixel electrode located above;
A second substrate having at least a common electrode located above the first gate line, above the second gate line, and between the main pixel electrodes;
A liquid crystal layer comprising liquid crystal molecules held between the first substrate and the second substrate;
Equipped with a,
The auxiliary capacitance line has an extension portion extended in a second direction between the first switching element and the second switching element,
The liquid crystal display device , wherein the pixel electrode is opposed to the extension portion between the first switching element and the drain electrode . The liquid crystal display device according to claim 1 , wherein the first substrate further includes a gate shield electrode facing the first and second gate lines and having the same potential as the common electrode. 3. The liquid crystal display device according to claim 1, wherein the first substrate further includes a source shield electrode facing the first and second source lines and having the same potential as the common electrode. The initial alignment direction of the liquid crystal molecules of the liquid crystal layer is substantially parallel to the extending direction of the main pixel electrode in a state where no electric field is formed between the pixel electrode and the common electrode. the liquid crystal display device according to any one of claims 1 to 3. The liquid crystal molecules are splay aligned or homogeneously aligned between the first substrate and the second substrate in a state where no electric field is formed between the pixel electrode and the common electrode. The liquid crystal display device according to claim 4 . And a first polarizing plate disposed on the outer surface of the first substrate and a second polarizing plate disposed on the outer surface of the second substrate, wherein the first polarizing axis of the first polarizing plate and the second polarizing plate a second polarization axis is perpendicular, any one of claims 1 to 5 first polarization axis of the first polarizing plate, wherein the parallel or perpendicular to the initial alignment direction of liquid crystal molecules of the liquid crystal layer 2. A liquid crystal display device according to item 1. The common electrode is located above the first gate line, above the second gate line, and between the main pixel electrodes and extends along the first direction, and the first common line, 7. The liquid crystal display device according to claim 1, further comprising: a sub-common electrode positioned above the source line and above the second source line and extending along the second direction. . 8. The liquid crystal display device according to claim 1, wherein the main pixel electrode positioned above the auxiliary capacitance line is formed wider than the auxiliary capacitance line. 9. 9. The first switching element, the second switching element, and the extended portion of the storage capacitor line are unevenly distributed on the first source line side rather than the second source line side. The liquid crystal display device according to any one of the above. 10. The liquid crystal display device according to claim 1, wherein the storage capacitor line is unevenly distributed on the first gate line side rather than on the second gate line side. 11. The first substrate further includes:
A gate electrode which is a part of the second gate wiring;
A first insulating film covering the gate electrode and the auxiliary capacitance line;
A semiconductor layer formed on the first insulating film;
A source electrode formed on the first insulating film and in contact with the semiconductor layer, the source electrode being a part of the first source wiring;
The drain electrode formed on the first insulating film and in contact with the semiconductor layer;
A second insulating film interposed between the semiconductor layer, the source electrode, the drain electrode, and the pixel electrode;
11. The liquid crystal display device according to claim 1, wherein the pixel electrode is electrically connected to the drain electrode through a contact hole formed in the second insulating film.

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