JP5699068B2 - Liquid crystal display - Google Patents

Description

  Embodiments described herein relate generally to a liquid crystal display device.

  2. Description of the Related Art In recent years, flat display devices have been actively developed. In particular, liquid crystal display devices have attracted particular attention because of their advantages such as light weight, thinness, and low power consumption. In particular, an active matrix liquid crystal display device in which a switching element is incorporated in each pixel has a structure using a lateral electric field (including a fringe electric field) such as an IPS (In-Plane Switching) mode or an FFS (Fringe Field Switching) mode. Attention has been paid. Such a horizontal electric field mode liquid crystal display device includes a pixel electrode and a counter electrode formed on an array substrate, and switches liquid crystal molecules with a horizontal electric field substantially parallel to the main surface of the array substrate.

  On the other hand, a technique for switching liquid crystal molecules by forming a lateral electric field or an oblique electric field between a pixel electrode formed on an array substrate and a counter electrode formed on the counter substrate has been proposed.

JP 2009-42630 A JP 2009-192822 A

  An object of the present embodiment is to provide a liquid crystal display device capable of reducing cost and suppressing deterioration in display quality.

According to this embodiment,
The first storage capacitor line and the second storage capacitor line that extend along the first direction, and the first storage capacitor line and the second storage capacitor line that are located between the first storage capacitor line and the second storage capacitor line and extend along the first direction. A gate line, a source line extending along a second direction intersecting the first direction, a semiconductor layer, a gate electrode electrically connected to the gate line, a contact with the semiconductor layer and the source A source electrode electrically connected to the wiring, a first electrode part in contact with the semiconductor layer, a second electrode connected to the first electrode part and facing the first auxiliary capacitance line and extending along a first direction A first substrate comprising: an electrode part; and a drain electrode comprising a third electrode part connected to the first electrode part and facing the second auxiliary capacitance line and extending along a first direction; On both sides of the second electrode part and on both sides of the third electrode part A second substrate having a common electrode with a main common electrode that is positioned and extends along the first direction, and liquid crystal molecules held between the first substrate and the second substrate. And a liquid crystal layer including the liquid crystal display device.

According to this embodiment,
The first storage capacitor line and the second storage capacitor line that extend along the first direction, and the first storage capacitor line and the second storage capacitor line that are located between the first storage capacitor line and the second storage capacitor line and extend along the first direction. A gate line, a source line extending along a second direction intersecting the first direction, a semiconductor layer, a gate electrode electrically connected to the gate line, a contact with the semiconductor layer and the source A source electrode electrically connected to the wiring; a drain electrode in contact with the semiconductor layer; a first electrode electrically connected to the drain electrode and facing the first auxiliary capacitance line and extending along a first direction; A first substrate having a second main pixel electrode electrically connected to the first main pixel electrode and the drain electrode and facing the second auxiliary capacitance line and extending along a first direction; And both sides sandwiching the first main pixel electrode, and A second substrate including a common electrode having a main common electrode located on both sides of the second main pixel electrode and extending along a first direction, and the first substrate and the second substrate And a liquid crystal layer including liquid crystal molecules held between the liquid crystal display device and the liquid crystal display device.

According to this embodiment,
The first storage capacitor line and the second storage capacitor line that extend along the first direction, and the first storage capacitor line and the second storage capacitor line that are located between the first storage capacitor line and the second storage capacitor line and extend along the first direction. A gate electrode electrically connected to the gate wiring, the first auxiliary capacitance line, the second auxiliary capacitance line, the gate wiring, an insulating film covering the gate electrode, and the insulation A semiconductor layer formed on the film and positioned above the gate electrode; a source wiring formed on the insulating film and extending in a second direction intersecting the first direction; and the source on the insulating film A source electrode electrically connected to the wiring and in contact with the semiconductor layer; and a drain electrode formed on the insulating film, the first electrode portion being in contact with the semiconductor layer, connected to the first electrode portion, and Through the insulating film. A second electrode portion extending along the first direction so as to overlap with the auxiliary capacitance line, and connected to the first electrode portion in the first direction so as to overlap with the second auxiliary capacitance line via the insulating film A drain electrode provided with a third electrode portion extending along the first substrate, and both sides sandwiching the second electrode portion, and both sides sandwiching the third electrode portion. A second substrate having a common electrode including a main common electrode extending in one direction, and a liquid crystal layer including liquid crystal molecules held between the first substrate and the second substrate. There is provided a liquid crystal display device comprising the above.

According to this embodiment,
The first storage capacitor line and the second storage capacitor line that extend along the first direction, and the first storage capacitor line and the second storage capacitor line that are located between the first storage capacitor line and the second storage capacitor line and extend along the first direction. A gate electrode electrically connected to the gate wiring, the first auxiliary capacitance line, the second auxiliary capacitance line, the gate wiring, and a first insulating film covering the gate electrode, A semiconductor layer formed on the first insulating film and positioned above the gate electrode; a source wiring formed on the first insulating film and extending in a second direction intersecting the first direction; A source electrode electrically connected to the source wiring on the first insulating film and in contact with the semiconductor layer, a drain electrode formed on the first insulating film and in contact with the semiconductor layer, the semiconductor layer, and the source Wiring, the source electrode, And a second insulating film covering the drain electrode, and a pixel electrode formed on the second insulating film, wherein the first insulating film and the second insulating film are electrically connected to the drain electrode. Through the first insulating film and the second insulating film, which are electrically connected to the first main pixel electrode and the drain electrode extending in the first direction so as to overlap the first auxiliary capacitance line through the first insulating film and the second insulating film A first substrate having a second main pixel electrode extending along a first direction so as to overlap the second auxiliary capacitance line, both sides sandwiching the second electrode portion, and A second substrate including a common electrode having a main common electrode located on both sides of the third electrode portion and extending along a first direction; and the first substrate and the second substrate; And a liquid crystal layer containing liquid crystal molecules held between Crystal display device is provided.

FIG. 1 is a diagram schematically showing a configuration and an equivalent circuit of a liquid crystal display device according to the present embodiment. FIG. 2 is a plan view schematically showing a structural example of one pixel when the array substrate shown in FIG. 1 is viewed from the counter substrate side. FIG. 3 is a plan view schematically showing an example of the structure of one pixel in the counter substrate shown in FIG. FIG. 4 is a cross-sectional view schematically showing a cross-sectional structure of the array substrate taken along line AB in FIG. FIG. 5 is a cross-sectional view schematically showing a cross-sectional structure of the liquid crystal display panel taken along line CD in FIG. FIG. 6 is a plan view schematically showing another structural example of one pixel when the array substrate shown in FIG. 1 is viewed from the counter substrate side. FIG. 7 is a plan view schematically showing another structural example of one pixel when the array substrate shown in FIG. 1 is viewed from the counter substrate side. FIG. 8 is a plan view schematically showing another structural example of one pixel when the array substrate shown in FIG. 1 is viewed from the counter substrate side. FIG. 9 is a cross-sectional view schematically showing a cross-sectional structure of the array substrate taken along line EF in FIG. FIG. 10 is a plan view schematically showing another structural example of one pixel when the array substrate shown in FIG. 1 is viewed from the counter substrate side. FIG. 11 is a plan view schematically showing another structural example of one pixel when the array substrate shown in FIG. 1 is viewed from the counter substrate side. 12 is a plan view schematically showing another structure example of one pixel when the array substrate shown in FIG. 1 is viewed from the counter substrate side.

  Hereinafter, the present embodiment will be described in detail with reference to the drawings. In each figure, the same reference numerals are given to components that exhibit the same or similar functions, and duplicate descriptions are omitted.

  FIG. 1 is a diagram schematically showing a configuration and an equivalent circuit of a liquid crystal display device according to the present embodiment.

  That is, the liquid crystal display device includes an active matrix type liquid crystal display panel LPN. The liquid crystal display panel LPN is held between the array substrate AR, which is the first substrate, the counter substrate CT, which is the second substrate disposed to face the array substrate AR, and the array substrate AR and the counter substrate CT. Liquid crystal layer LQ. Such a liquid crystal display panel LPN includes an active area ACT for displaying an image. This active area ACT is composed of a plurality of pixels PX arranged in an m × n matrix (where m and n are positive integers).

  In the active area ACT, the liquid crystal display panel LPN includes n gate lines G (G1 to Gn), n auxiliary capacitance lines C (C1 to Cn), m source lines S (S1 to Sm), and the like. ing. The gate line G and the auxiliary capacitance line C correspond to, for example, signal lines extending along the first direction X. The gate line G and the auxiliary capacitance line C are adjacent to each other with an interval along the second direction Y intersecting the first direction X. Here, the first direction X and the second direction Y are substantially orthogonal to each other. The source line S intersects with the gate line G and the auxiliary capacitance line C. The source wiring S corresponds to a signal wiring extending along the second direction Y. Note that the gate wiring G, the auxiliary capacitance line C, and the source wiring S do not necessarily extend linearly, and some of them may be bent.

  Each gate line G is drawn outside the active area ACT and connected to the gate driver GD. Each source line S is drawn outside the active area ACT and connected to the source driver SD. At least a part of the gate driver GD and the source driver SD is formed on, for example, the array substrate AR, and is connected to the driving IC chip 2 with a built-in controller.

  Each pixel PX includes a switching element SW, a pixel electrode PE, a common electrode CE, and the like. The storage capacitor Cs is formed, for example, between the storage capacitor line C and the pixel electrode PE. The auxiliary capacitance line C is electrically connected to a voltage application unit VCS to which an auxiliary capacitance voltage is applied. Note that a plurality of auxiliary capacitance lines C for forming a capacitance with the pixel electrode PE may be arranged per pixel.

  In the present embodiment, the liquid crystal display panel LPN has a configuration in which the pixel electrode PE is formed on the array substrate AR while at least a part of the common electrode CE is formed on the counter substrate CT. The liquid crystal molecules in the liquid crystal layer LQ are switched mainly using an electric field formed between the PE and the common electrode CE. The electric field formed between the pixel electrode PE and the common electrode CE is an oblique electric field (or slightly inclined with respect to the XY plane or the substrate main surface defined by the first direction X and the second direction Y) (or , A transverse electric field substantially parallel to the main surface of the substrate).

  The switching element SW is constituted by, for example, an n-channel thin film transistor (TFT). The switching element SW is electrically connected to the gate line G and the source line S. Such a switching element SW may be either a top gate type or a bottom gate type. In addition, the semiconductor layer of the switching element SW is formed of, for example, amorphous silicon, but may be formed of polysilicon.

  The pixel electrode PE is disposed in each pixel PX and is electrically connected to the switching element SW. In this embodiment, as will be described in detail later, the drain electrode of the switching element SW may function as the pixel electrode PE, or a pixel electrode PE electrically connected to the drain electrode may be provided separately. In the case where the drain electrode functions as the pixel electrode PE, the pixel electrode PE is formed of a wiring material, an opaque conductive material, or a light-shielding or reflective conductive material. For example, aluminum (Al), titanium It is formed of at least one metal material of (Ti), silver (Ag), molybdenum (Mo), tungsten (W), copper (Cu), or chromium (Cr) or an alloy containing any one thereof. Further, when the pixel electrode PE is provided separately from the drain electrode, the pixel electrode PE is formed of a light-transmitting conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). It may be formed by the above wiring material.

  The common electrode CE is disposed in common to the pixel electrodes PE of the plurality of pixels PX via the liquid crystal layer LQ. Such a common electrode CE may be formed of, for example, a light-transmitting conductive material such as ITO or IZO, or may be formed of the above wiring material.

  The array substrate AR includes a power feeding unit VS for applying a voltage to the common electrode CE. For example, the power supply unit VS is formed outside the active area ACT. The common electrode CE of the counter substrate CT is drawn out of the active area ACT and is electrically connected to the power supply unit VS via a conductive member (not shown).

  FIG. 2 is a plan view schematically showing a structure example of one pixel PX when the array substrate AR shown in FIG. 1 is viewed from the counter substrate side. Here, a plan view in the XY plane is shown.

  The array substrate AR includes a gate line G1, an auxiliary capacity line C1, an auxiliary capacity line C2, a source line S1, a source line S2, a switching element SW, a first alignment film AL1, and the like.

  In the illustrated example, the pixel PX has a horizontally long rectangular shape whose length along the first direction X is longer than the length along the second direction Y, as indicated by a broken line. The auxiliary capacitance line C1 and the auxiliary capacitance line C2 are arranged at the first pitch along the second direction Y, and each extend along the first direction X. The gate line G1 is located between the auxiliary capacitance line C1 and the auxiliary capacitance line C2, and extends along the first direction X. The source wiring S1 and the source wiring S2 are arranged at the second pitch along the first direction X and extend along the second direction Y, respectively.

  In the illustrated pixel PX, the source line S1 is disposed at the left end, and the source line S2 is disposed at the right end. Strictly speaking, the source line S1 is disposed across the boundary between the pixel PX and the pixel adjacent to the left side, and the source line S2 is disposed over the boundary between the pixel PX and the pixel adjacent to the right side. Yes. That is, the length along the first direction X of the pixel PX corresponds to the second pitch between the source lines.

  The auxiliary capacitance line C1 is disposed in a region above the pixel PX with respect to the gate line G1, and the auxiliary capacitance line C2 is disposed in a region below the pixel PX with respect to the gate line G1. The length of the pixel PX along the second direction Y is larger than the first pitch between the storage capacitor lines. The first pitch is smaller than the second pitch.

  In the illustrated pixel PX, the gate line G1 is located approximately in the middle between the auxiliary capacitance line C1 and the auxiliary capacitance line C2, or in the center of the pixel. That is, the interval along the second direction Y between the auxiliary capacitance line C1 and the gate line G1 is substantially the same as the interval along the second direction Y between the auxiliary capacitance line C2 and the gate line G1.

  In the illustrated example, the switching element SW is located near the source line S1, that is, near the left end of the pixel PX, and is electrically connected to the gate line G1 and the source line S1. The switching element SW includes a gate electrode WG electrically connected to the gate wiring G1, a semiconductor layer SC made of amorphous silicon formed above the gate electrode WG, and a semiconductor wiring SC electrically connected to the source wiring S1. A contact source electrode WS and a drain electrode WD in contact with the semiconductor layer SC are provided. In the illustrated example, the gate electrode WG is formed integrally with the gate line G1, and the source electrode WS is formed integrally with the source line S1. Further, the portion of the source electrode WS that is in contact with the semiconductor layer SC extends along the second direction Y. The drain electrode WD is located between the adjacent source line S1 and source line S2. Such a drain electrode WD also has a function as the pixel electrode PE.

  The drain electrode WD is connected to the first electrode portion D1 that is in contact with the semiconductor layer SC, the second electrode portion D2 that is connected to the first electrode portion D1 and extends in the first direction X, and the first electrode portion D1 is connected to the first electrode portion D1. A third electrode portion D3 extending along the one direction X is provided. The first electrode part D1, the second electrode part D2, and the third electrode part D3 are integrally or continuously formed and are electrically connected to each other.

  The first electrode portion D1 is located near the left end portion of the pixel PX and extends linearly along the second direction Y. The semiconductor layer SC is in contact with a part (contact position) of this first electrode part D1, in particular, a part (contact position) located at a substantially equal distance from the second electrode part D2 and the third electrode part D3. In the first electrode portion D1, the portion that contacts the semiconductor layer SC is substantially parallel to the portion that contacts the semiconductor layer SC of the source electrode WS and extends along the second direction Y. Such a first electrode portion D1 is formed in a strip shape having substantially the same width along the first direction X.

  The second electrode portion D2 and the third electrode portion D3 extend linearly from the first electrode portion D1 along the first direction X, respectively. In other words, each of the second electrode portion D2 and the third electrode portion D3 is provided in the direction from the vicinity of the left end portion (that is, the source line S1 side) of the pixel PX toward the vicinity of the right end portion (that is, the source line S2 side). It extends along one direction X. The second electrode portion D2 and the third electrode portion D3 are formed in a strip shape having substantially the same width along the second direction Y. In the illustrated example, on the source line S1 side of the pixel PX, the first electrode part D1 is connected to one end of each of the second electrode part D2 and the third electrode part D3.

  In such a drain electrode WD, the second electrode portion D2 faces the storage capacitor line C1. That is, the auxiliary capacitance line C1 extends linearly along the first direction X, passing directly under the second electrode portion D2. Further, the third electrode portion D3 is opposed to the storage capacitor line C2. That is, the auxiliary capacitance line C2 extends linearly along the first direction X, passing directly below the third electrode portion D3. Such a drain electrode WD is opposed to the auxiliary capacitance line C1 in the second electrode portion D2, and is opposed to the auxiliary capacitance line C2 in the third electrode portion D3 to form a capacitance necessary for image display in the pixel PX. Yes. However, in order not to reduce the area of the transmission region in the pixel PX, it is desirable that the storage capacitor line C1 extends directly below the drain electrode WD without protruding from the drain electrode WD.

  The array substrate AR may further include a part of the common electrode CE.

  In such an array substrate AR, the drain electrode WD is covered with the first alignment film AL1. The first alignment film AL1 is subjected to alignment treatment (for example, rubbing treatment or photo-alignment treatment) along the first alignment treatment direction PD1 in order to initially align the liquid crystal molecules of the liquid crystal layer LQ. The first alignment treatment direction PD1 in which the first alignment film AL1 initially aligns the liquid crystal molecules is substantially parallel to the first direction X.

  Here, as an example of dimensions, the length of the pixel PX along the second direction Y is 50 μm to 60 μm, and the length along the first direction of the pixel PX (second pitch of the source wiring S, that is, the source) The distance between the wiring S1 and the source wiring S2 along the first direction X) is 150 μm to 180 μm, the width along the second direction Y of the gate wiring G and the auxiliary capacitance line C is 5 μm, and the source wiring S The width along the first direction X is 3 μm. The gate line G and the auxiliary capacitance line C are formed in the same layer and need to be electrically insulated, so a margin of about 10 μm is secured between them. Further, since the source wiring S and the source electrode WS and the drain electrode WD are formed in the same layer and need to be electrically insulated, a margin of about 10 μm is secured between them.

  FIG. 3 is a plan view schematically showing a structural example of one pixel PX in the counter substrate CT shown in FIG. Here, a plan view in the XY plane is shown. Here, only the configuration necessary for the description is illustrated, and the gate wiring G, the auxiliary capacitance line C, the source wiring S, the switching element SW, and the like provided in the array substrate are indicated by broken lines.

  The common electrode CE includes a main common electrode CA on the counter substrate CT. In the illustrated example, the common electrode CE further includes a sub-common electrode CB on the counter substrate CT. However, the sub-common electrode CB may be omitted.

  The main common electrode CA is located on both sides of the drain electrode WD across the second electrode portion D2 and on both sides of the third electrode portion D3 in the XY plane, along the first direction X. It extends linearly. Alternatively, the main common electrode CA is located between the second electrode portion D2 and the third electrode portion D3, at the upper end portion of the pixel PX, and at the lower end portion of the pixel PX, and extends along the first direction X. Is extended. Such a main common electrode CA is formed in a strip shape having substantially the same width along the second direction Y.

  In the illustrated example, three main common electrodes CA are arranged in parallel in the second direction Y at intervals. That is, three main common electrodes CA are arranged at equal pitches along the second direction Y per pixel. In the pixel PX, the main common electrode CAU is disposed at the upper end, the main common electrode CAB is disposed at the lower end, and the main common electrode CAC is disposed at the center of the pixel. Strictly speaking, the main common electrode CAU is disposed over the boundary between the pixel PX and the adjacent pixel on the upper side, and the main common electrode CAB is disposed over the boundary between the pixel PX and the adjacent pixel on the lower side. Has been placed. That is, the length along the second direction Y of the pixel PX corresponds to the pitch along the second direction Y between the main common electrode CAU and the main common electrode CAB. The main common electrode CAC is located and overlaps between the second electrode part D2 and the third electrode part D3 or in the upper layer of the gate wiring G1.

  The main common electrode CAU and the main common electrode CAC are located on both sides of the second electrode portion D2 and the auxiliary capacitance line C1. Similarly, the main common electrode CAC and the main common electrode CAB are located on both sides of the third electrode portion D3 and the auxiliary capacitance line C2. In other words, one main common electrode CAC disposed in the center of the pixel is located approximately in the middle between the second electrode portion D2 and the third electrode portion D3. That is, in the illustrated example, the main common electrode CAB, the third electrode portion D3, the main common electrode CAC, the second electrode portion D2, and the main common electrode CAU are arranged in this order along the second direction Y in the XY plane. It is out. In addition, the inter-electrode distance along the second direction Y between the second electrode part D2 and the main common electrode CAC, and the second direction Y between the main common electrode CAC and the third electrode part D3. The distance between the electrodes is substantially the same. Further, the inter-electrode distance along the second direction Y between the main common electrode CAU and the second electrode portion D2, and the second direction Y between the third electrode portion D3 and the main common electrode CAB. The distance between the electrodes is substantially the same.

  The sub-common electrode CB extends linearly along the second direction Y on both sides of the drain electrode WD in the XY plane. Alternatively, the sub-common electrode CB is located above the source line S and is connected to the main common electrode CA and extends linearly along the second direction Y. Such a sub-common electrode CB is formed in a strip shape having substantially the same width along the first direction X. Further, such a sub-common electrode CB is formed integrally or continuously with the main common electrode CA and is electrically connected to the main common electrode CA. That is, in the counter substrate CT, the common electrode CE is formed in a lattice shape.

  In the illustrated example, two sub-common electrodes CB are arranged in parallel in the first direction X with an interval between them, and are arranged at both left and right ends of the pixel PX, respectively. That is, two sub-common electrodes CB are arranged per pixel. In the illustrated pixel PX, the sub-common electrode CBL is disposed at the left end, and the sub-common electrode CBR is disposed at the right end. Strictly speaking, the sub-common electrode CBL is disposed over the boundary between the pixel PX and the pixel adjacent to the left side, and the sub-common electrode CBR is disposed over the boundary between the pixel PX and the pixel adjacent to the right side. Has been. The sub-common electrode CBL is located above the source line S1, and the sub-common electrode CBR is located above the source line S2.

  In such a counter substrate CT, the common electrode CE is covered with the second alignment film AL2. The second alignment film AL2 is subjected to alignment treatment (for example, rubbing treatment or photo-alignment treatment) along the second alignment treatment direction PD2 in order to initially align the liquid crystal molecules of the liquid crystal layer LQ. The second alignment treatment direction PD2 in which the second alignment film AL2 initially aligns the liquid crystal molecules is parallel to the first alignment treatment direction PD1 and is in the same direction or in the opposite direction. In the illustrated example, the second alignment processing direction PD2 is parallel to the first direction X, and in the XY plane, the first alignment processing direction PD1 is parallel to each other and is in the same direction.

  FIG. 4 is a cross-sectional view schematically showing a cross-sectional structure of the array substrate AR cut along the line AB in FIG.

  The array substrate AR is formed using a first insulating substrate 10 having light transparency. The array substrate AR includes a switching element SW, a storage capacitor line C1, a first insulating film 11, a first alignment film AL1, and the like in the first insulating substrate 10.

  The gate electrode WG of the switching element SW is a part of the gate wiring G1 and is formed on the inner surface 10A of the first insulating substrate 10. The auxiliary capacitance line C <b> 1 is formed on the inner surface 10 </ b> A of the first insulating substrate 10 so as to be separated from the gate electrode WG. The gate electrode WG, the gate line G, and the auxiliary capacitance line C are formed of the same material, and these can be collectively formed using the same material. The gate electrode WG and the auxiliary capacitance line C1 integrated with the gate wiring G1 are covered with the first insulating film 11.

  The semiconductor layer SC of the switching element SW is formed on the first insulating film 11 and is located above the gate electrode WG. The source electrode WS of the switching element SW is a part of the source line S1, is formed on the first insulating film 11, and is in contact with the semiconductor layer SC. The drain electrode WD is separated from the source electrode WS and the source wiring S and is formed on the first insulating film 11. The first electrode portion D1, which is a part of the drain electrode WD, is in contact with the semiconductor layer SC. In addition, the second electrode portion D2, which is a part of the drain electrode WD, is located above the storage capacitor line C1. That is, the second electrode portion D2 faces the storage capacitor line C1 with the first insulating film 11 interposed therebetween. The source electrode WS and the drain electrode WD are formed of the same material as the source wiring (specifically, the wiring material described above), and these can be collectively formed using the same material.

  The first alignment film AL1 covers the semiconductor layer SC, the source electrode WS, the drain electrode WD, and the like constituting the switching element SW, and is also disposed on the first insulating film 11. Such a first alignment film AL1 is formed of a material exhibiting horizontal alignment.

  Note that these switching elements SW may be covered with another insulating film such as a passivation film.

  FIG. 5 is a cross-sectional view schematically showing a cross-sectional structure of the liquid crystal display panel LPN cut along line CD in FIG.

  A backlight 4 is disposed on the back side of the array substrate AR constituting the liquid crystal display panel LPN. As the backlight 4, various forms are applicable, and any of those using a light emitting diode (LED) or a cold cathode tube (CCFL) as a light source can be applied. The description of the structure is omitted.

  In the array substrate AR, the gate wiring G1, the auxiliary capacitance line C1, and the auxiliary capacitance line C2 are formed on the inner surface 10A of the first insulating substrate 10, that is, on the side facing the counter substrate CT, and are covered with the first insulating film 11. ing. The second electrode portion D2 and the third electrode portion D3 of the drain electrode WD are formed on the first insulating film 11 and covered with the first alignment film AL1. The second electrode portion D2 and the third electrode portion D3 are located on both sides of the gate wiring G1. The second electrode portion D2 is located above the auxiliary capacitance line C1, and is disposed so as to overlap the auxiliary capacitance line C1 with the first insulating film 11 interposed therebetween. The third electrode portion D3 is located above the auxiliary capacitance line C2 and is disposed so as to overlap the auxiliary capacitance line C2 with the first insulating film 11 interposed therebetween. The first alignment film AL1 is disposed on the surface of the array substrate AR that faces the counter substrate CT, and extends over substantially the entire active area ACT.

  The counter substrate CT is formed by using a second insulating substrate 20 having optical transparency. The counter substrate CT includes a color filter CF, an overcoat layer OC, a common electrode CE, a second alignment film AL2, and the like on the inner side of the second insulating substrate 20, that is, the side facing the array substrate AR. A black matrix that partitions each pixel PX may be disposed on the inner surface 20A of the second insulating substrate 20 facing the array substrate AR.

  The color filter CF is arranged corresponding to each pixel PX. That is, the color filter CF is disposed on the inner surface 20 </ b> A of the second insulating substrate 20. The color filters CF arranged in the pixels PX adjacent to each other in the second direction Y have different colors. For example, the color filter CF is formed of resin materials colored in three primary colors such as red, blue, and green. The red color filter is arranged corresponding to the red pixel. The blue color filter is arranged corresponding to the blue pixel. The green color filter is arranged corresponding to the green pixel.

  The overcoat layer OC covers the color filter CF. This overcoat layer OC alleviates the influence of irregularities on the surface of the color filter CF.

  The main common electrode CAU, the main common electrode CAC, the main common electrode CAB, the sub-common electrode CB (not shown), and the like of the common electrode CE are formed on the side of the overcoat layer OC that faces the array substrate AR. Each of the main common electrode CAU and the main common electrode CAB is located immediately below the boundary between adjacent color filters. The main common electrode CAC is located between the main common electrode CAU and the main common electrode CAB, between the second electrode part D2 and the third electrode part D3, or above the gate line G1.

  A region between the drain electrode WD functioning as a pixel electrode and the common electrode CE, that is, a region between the main common electrode CAU and the second electrode portion D2, and between the main common electrode CAC and the second electrode portion D2. The region, the region between the main common electrode CAC and the third electrode portion D3, and the region between the main common electrode CAB and the third electrode portion D3 correspond to a transmissive region that can transmit backlight light.

  The second alignment film AL2 is disposed on the surface of the counter substrate CT facing the array substrate AR, and extends over substantially the entire active area ACT. The second alignment film AL2 covers the common electrode CE, the overcoat layer OC, and the like. Such a second alignment film AL2 is formed of a material exhibiting horizontal alignment.

  The array substrate AR and the counter substrate CT as described above are arranged so that the first alignment film AL1 and the second alignment film AL2 face each other. At this time, a predetermined cell is formed between the first alignment film AL1 of the array substrate AR and the second alignment film AL2 of the counter substrate CT by, for example, a columnar spacer integrally formed on one substrate with a resin material. A gap, for example a cell gap of 2-7 μm, is formed. The array substrate AR and the counter substrate CT are bonded to each other with a sealing material outside the active area ACT in a state where a predetermined cell gap is formed.

  The liquid crystal layer LQ is held in a cell gap formed between the array substrate AR and the counter substrate CT, and is disposed between the first alignment film AL1 and the second alignment film AL2. Such a liquid crystal layer LQ is made of, for example, a liquid crystal material having a positive dielectric anisotropy (positive type).

  Note that the distance along the second direction Y between the second electrode part D2, the main common electrode CAU and the main common electrode CAC, and the second direction between the third electrode part D3, the main common electrode CAC and the main common electrode CAB. The interval along Y is larger than the thickness of the liquid crystal layer LQ, and is twice or more as large as the thickness of the liquid crystal layer LQ.

  The first optical element OD1 is attached to the outer surface of the array substrate AR, that is, the outer surface 10B of the first insulating substrate 10 constituting the array substrate AR with an adhesive or the like. The first optical element OD1 is located on the side facing the backlight 4 of the liquid crystal display panel LPN, and controls the polarization state of incident light incident on the liquid crystal display panel LPN from the backlight 4. The first optical element OD1 includes a first polarizing plate PL1 having a first polarization axis (or first absorption axis) AX1. Note that another optical element such as a retardation plate may be disposed between the first polarizing plate PL1 and the first insulating substrate 10.

  The second optical element OD2 is attached to the outer surface of the counter substrate CT, that is, the outer surface 20B of the second insulating substrate 20 constituting the counter substrate CT with an adhesive or the like. The second optical element OD2 is located on the display surface side of the liquid crystal display panel LPN, and controls the polarization state of the outgoing light emitted from the liquid crystal display panel LPN. The second optical element OD2 includes a second polarizing plate PL2 having a second polarization axis (or second absorption axis) AX2. Note that another optical element such as a retardation plate may be disposed between the second polarizing plate PL2 and the second insulating substrate 20.

  The first polarizing axis AX1 of the first polarizing plate PL1 and the second polarizing axis AX2 of the second polarizing plate PL2 are in a substantially orthogonal positional relationship (crossed Nicols). At this time, for example, one polarizing plate is disposed so that the polarization axis thereof is substantially parallel or substantially orthogonal to the extending direction of the second electrode portion D2, the third electrode portion D3, the main common electrode CA, and the like. That is, when the extending direction of the second electrode portion D2, the third electrode portion D3, and the main common electrode CA is the first direction X, the polarization axis of one polarizing plate is substantially parallel to the first direction X. Alternatively, it is substantially parallel to the second direction Y.

  Alternatively, one polarizing plate is disposed, for example, so that the polarization axis thereof is substantially parallel or substantially orthogonal to the initial alignment direction of the liquid crystal molecules, that is, the first alignment processing direction PD1 or the second alignment processing direction PD2. When the initial alignment direction is parallel to the first direction X, the polarization axis of one polarizing plate is substantially parallel to the first direction X or substantially parallel to the second direction Y.

  In the example shown in FIG. 3A, the second polarizing plate PL2 is arranged so that the second polarizing axis AX2 is orthogonal to the first direction X, and the first polarizing plate PL1 is The first polarization axis AX1 is arranged so as to be parallel to the first direction X. In the example shown in FIG. 3B, the first polarizing plate PL1 is arranged so that the first polarizing axis AX1 is orthogonal to the first direction X, and the second polarizing plate PL2 Are arranged such that their second polarization axis AX2 is parallel to the first direction X.

  Next, the operation of the liquid crystal display panel LPN configured as described above will be described with reference to FIGS.

  That is, in a state where no voltage is applied to the liquid crystal layer LQ, that is, in a state where no electric field is formed between the drain electrode WD and the common electrode CE (when OFF), the liquid crystal molecules LM of the liquid crystal layer LQ The major axis is oriented so as to face the first orientation treatment direction PD1 of the first orientation film AL1 and the second orientation treatment direction PD2 of the second orientation film AL2. Such OFF time corresponds to the initial alignment state, and the alignment direction of the liquid crystal molecules LM at the OFF time corresponds to the initial alignment direction.

  Strictly speaking, the liquid crystal molecules LM are not always aligned parallel to the XY plane, and are often pretilted. For this reason, the initial alignment direction of the liquid crystal molecules LM here is a direction obtained by orthogonally projecting the major axis of the liquid crystal molecules LM at the time of OFF to the XY plane. Hereinafter, in order to simplify the description, it is assumed that the liquid crystal molecules LM are aligned in parallel to the XY plane and rotate in a plane parallel to the XY plane. Here, both the first alignment treatment direction PD1 and the second alignment treatment direction PD2 are substantially parallel to the first direction X. At the OFF time, the liquid crystal molecules LM are initially aligned in the direction in which the major axis is substantially parallel to the first direction X, as indicated by a broken line in FIG.

  As in the illustrated example, when the first alignment processing direction PD1 and the second alignment processing direction PD2 are parallel and in the same direction, in the cross section of the liquid crystal layer LQ, the liquid crystal molecules LM are substantially near the middle portion of the liquid crystal layer LQ. Alignment is performed horizontally (pretilt angle is substantially zero), and is aligned with a pretilt angle that is symmetrical in the vicinity of the first alignment film AL1 and in the vicinity of the second alignment film AL2 (spray alignment). Thus, in the state in which the liquid crystal molecules LM are splay aligned, the liquid crystal molecules LM in the vicinity of the first alignment film AL1 and the liquid crystal molecules LM in the vicinity of the second alignment film AL2 in the direction inclined from the normal direction of the substrate Is optically compensated. Therefore, when the first alignment processing direction PD1 and the second alignment processing direction PD2 are parallel to each other and in the same direction, light leakage is small in the case of black display, and a high contrast ratio can be realized. It becomes possible to improve the quality.

  When the first alignment treatment direction PD1 and the second alignment treatment direction PD2 are parallel and opposite to each other, the liquid crystal molecules LM are in the vicinity of the first alignment film AL1, in the second alignment film AL2 in the cross section of the liquid crystal layer LQ. And in the middle part of the liquid crystal layer LQ with a substantially uniform pretilt angle (homogeneous alignment).

  Part of the backlight light from the backlight 4 passes through the first polarizing plate PL1 and enters the liquid crystal display panel LPN. The light incident on the liquid crystal display panel LPN is linearly polarized light orthogonal to the first absorption axis AX1 of the first polarizing plate PL1. The polarization state of such linearly polarized light hardly changes when OFF. Therefore, the linearly polarized light transmitted through the liquid crystal display panel LPN is absorbed by the second polarizing plate PL2 having a crossed Nicol positional relationship with the first polarizing plate PL1 (black display).

  On the other hand, in a state where a voltage is applied to the liquid crystal layer LQ, that is, a state where an electric field is formed between the drain electrode WD and the common electrode CE (when ON), the substrate is interposed between the drain electrode WD and the common electrode CE. A horizontal electric field (or an oblique electric field) substantially parallel to the line is formed. The liquid crystal molecules LM are affected by the electric field and rotate in a plane whose major axis is substantially parallel to the XY plane as indicated by the solid line in the figure.

  In the example shown in FIG. 3, for example, in the pixel PX, in the region between the second electrode portion D2 and the main common electrode CAC, the liquid crystal molecule LM rotates counterclockwise with respect to the first direction X. The orientation is directed to the lower left in the figure. Further, in the region between the third electrode portion D3 and the main common electrode CAC, the liquid crystal molecules LM are oriented so as to rotate clockwise with respect to the first direction X and to face the upper left in the drawing.

  Thus, in each pixel PX, in a state where an electric field is formed between the drain electrode WD and the common electrode CE, the alignment direction of the liquid crystal molecules LM has a position overlapping the drain electrode WD or a position overlapping the common electrode CE. Dividing into a plurality of directions as boundaries, a domain is formed in each orientation direction. That is, a plurality of domains are formed in one pixel PX.

  At such ON time, linearly polarized light orthogonal to the first absorption axis AX1 of the first polarizing plate PL1 is incident on the liquid crystal display panel LPN, and the polarization state is the alignment of the liquid crystal molecules LM when passing through the liquid crystal layer LQ. It changes according to the state. For example, when linearly polarized light parallel to the first direction X is incident on the liquid crystal display panel LPN, it is oriented in the 45 ° -225 ° azimuth or 135 ° -315 ° azimuth with respect to the first direction X when passing through the liquid crystal layer LQ. The liquid crystal molecules LM are affected by the phase difference of λ / 2 (where λ is the wavelength of light transmitted through the liquid crystal layer LQ). Thereby, the polarization state of the light that has passed through the liquid crystal layer LQ becomes linearly polarized light parallel to the second direction Y. For this reason, at the time of ON, at least a part of the light that has passed through the liquid crystal layer LQ is transmitted through the second polarizing plate PL2 (white display). However, at the position overlapping with the drain electrode or the common electrode, since the liquid crystal molecules maintain the initial alignment state, black display is performed as in the OFF state.

  According to the present embodiment, the length along the first direction X that is the extending direction of the gate wiring and the auxiliary capacitance line is longer than the length along the second direction Y that is the extending direction of the source wiring and the like. By adopting a horizontally long pixel configuration, the total number of pixels in the active area is the same as in the case of a vertically long pixel configuration in which the length along the second direction Y is longer than the length along the first direction X. However, the total number of signal wirings such as gate wirings, auxiliary capacitance lines, and source wirings can be reduced. For this reason, the number of terminals of the signal wiring can be reduced, the scale of drivers for supplying signals to these signal wirings can be reduced, and the number of driving IC chips to be mounted on the liquid crystal display panel LPN can be reduced. It becomes possible to reduce. Therefore, cost can be reduced.

  In addition, according to the present embodiment, one gate line G is located in the center of the pixel PX, and two auxiliary capacitance lines C per pixel PX are located on both sides of the gate line G, and the drain electrode WD. A capacity necessary for image display is formed in each pixel PX. For this reason, it is not necessary to route the auxiliary capacitance line C in the pixel PX, and it is possible to secure a space necessary for forming the capacitance. In addition, since the gate line G is located immediately below the main common electrode CAC that is a non-transmissive region in the pixel PX, the area of the transmissive region is not reduced even if it is located at the center of the pixel.

  Further, according to the present embodiment, the drain electrode WD of the switching element SW functions as the pixel electrode PE. In such a drain electrode WD, the distance from the contact position PP in contact with the semiconductor layer SC to each of the second electrode part D2 and the third electrode part D3 can be made equal, and the second electrode part D2 and the third electrode part Deterioration of display quality due to a resistance difference with the electrode part D3 can be suppressed. Since the contact position PP is equidistant from both the gate wiring G1 and the gate wiring G2, even if the first pitch between the gate wirings G is changed for each specification, the contact position PP is changed from the contact position PP to the second electrode. There is no deviation in the distance to each of the part D2 and the third electrode part D3, and products with various pixel pitches can be provided.

  Further, a capacitance is formed between the auxiliary capacitance line C1 and the drain electrode WD that are opposed to each other with the first insulating film 11 interposed therebetween. That is, the gap between the storage capacitor line C1 and the drain electrode WD corresponds to the film thickness of the first insulating film 11. For this reason, the configuration of the present embodiment is more efficient than a case where a capacitance is formed in a state where a plurality of insulating films are interposed between the auxiliary capacitance line C1 and the pixel electrode PE, and a larger capacitance can be efficiently obtained in a small area. It becomes possible to form.

  Further, in the drain electrode WD, the first electrode portion D1 including the region in contact with the semiconductor layer SC extends linearly along the second direction Y, and most of the first electrode portion D1 is located above the gate electrode WG. Therefore, the region protruding from the gate electrode WG is very small. For this reason, it becomes possible to ensure a sufficiently large area of the transmission region.

  Further, according to the present embodiment, the drain electrode WD that functions as the pixel electrode PE is formed of a wiring material that does not use indium (In). For this reason, it is possible to reduce the amount of indium used as compared with the case where both the pixel electrode PE and the common electrode CE are formed of ITO or IZO. Further, not only the drain electrode WD but also the common electrode CE can be made indium-free when formed of a conductive material that does not use indium (In).

  In addition, on the drain electrode WD or the common electrode CE, a horizontal electric field is hardly formed even when it is turned on (or an electric field sufficient to drive the liquid crystal molecules LM is not formed). The liquid crystal molecules LM hardly move from the initial alignment direction as in the OFF state. For this reason, even when the drain electrode WD and the common electrode CE are formed of a light-transmitting conductive material such as ITO at the time of ON, the backlight light hardly transmits in these regions, and display is performed at the time of ON. Hardly contributes. That is, as in the present embodiment, even when the drain electrode WD and the common electrode CE are formed of the above-described opaque wiring material, compared with the case where the drain electrode WD and the common electrode CE are formed of a transparent conductive material. Thus, it is possible to suppress the reduction of the transmittance at the time of ON or the reduction of the area of the transmissive region that substantially contributes to display.

  In the present embodiment in which the drain electrode WD is formed of the above-described opaque wiring material, the linearly polarized light incident on the liquid crystal display panel LPN is substantially parallel or substantially orthogonal to the extending direction of the edge of the drain electrode WD. . Further, the extending direction of the gate wiring G, the auxiliary capacitance line C, and the source wiring S formed of the opaque wiring material as described above is substantially parallel to the linearly polarized light incident on the liquid crystal display panel LPN. It is almost orthogonal. In addition, the common electrode CE may be formed of the above-described opaque conductive material, and the extending direction of the common electrode CE is substantially parallel or substantially orthogonal to the linearly polarized light incident on the liquid crystal display panel LPN. For this reason, the linearly polarized light reflected at the edges of the drain electrode WD, the common electrode CE, the gate wiring G, the auxiliary capacitance line C, and the source wiring S is not easily disturbed, and the first polarizing plate is a polarizer. The polarization plane when passing through PL1 can be maintained. Accordingly, at the time of OFF, the linearly polarized light transmitted through the liquid crystal display panel LPN is sufficiently absorbed by the second polarizing plate PL2, which is an analyzer, and thus light leakage can be suppressed. That is, the transmittance can be sufficiently reduced during black display, and the reduction in contrast ratio can be suppressed. In addition, it is not necessary to expand the width of the black matrix in order to prevent light leakage around the drain electrode WD and the common electrode CE, and it is possible to reduce the area of the transmissive region and reduce the transmittance at the time of ON. It becomes. Therefore, it is possible to suppress deterioration of display quality.

  Further, according to the present embodiment, the drain electrode WD functioning as the pixel electrode PE can be formed of the same material as the source wiring S and the source electrode WS formed in the same layer. Therefore, the drain electrode WD can be formed at the same time in the process of forming the source wiring S and the like. That is, the process of forming the pixel electrode PE separately from the drain electrode WD of the switching element SW can be omitted. Therefore, the manufacturing cost can be reduced.

  In addition, according to the present embodiment, the drain electrode WD directly contacts the semiconductor layer SC without passing through the contact hole of the insulating film, and functions as the pixel electrode PE. For this reason, it is possible to suppress the occurrence of alignment disorder of the liquid crystal molecules LM due to the unevenness of the contact holes. This makes it possible to suppress light leakage at the time of OFF and improve the contrast ratio.

  Further, according to the present embodiment, high transmittance can be obtained in the electrode gap between the drain electrode WD and the common electrode CE. Further, in order to sufficiently increase the transmittance per pixel, it is possible to cope with the problem by increasing the inter-electrode distance between the drain electrode WD and the common electrode CE. For product specifications with different pixel pitches, the peak condition of the transmittance distribution can be used by changing the interelectrode distance between the drain electrode WD and the common electrode CE. That is, in the display mode of the present embodiment, fine electrode processing is not always required from a low-resolution product specification with a relatively large pixel pitch to a high-resolution product specification with a relatively small pixel pitch, and the distance between the electrodes is not required. Products with various pixel pitches can be provided by setting.

  Further, according to the present embodiment, the transmittance is sufficiently reduced in the region overlapping with the common electrode CE. This is because an electric field does not leak outside the pixel from the position of the common electrode CE positioned above the gate line G and the source line S, and an undesired lateral electric field does not occur between adjacent pixels. For this reason, the liquid crystal molecules LM in the region overlapping the common electrode CE maintain the initial alignment state as in the OFF state (or during black display). Therefore, even when the color of the color filter CF is different between adjacent pixels, it is possible to suppress the occurrence of color mixing, and it is possible to suppress a decrease in color reproducibility and a decrease in contrast ratio.

  Further, when misalignment between the array substrate AR and the counter substrate CT occurs, there may be a difference in the inter-electrode distance between the common electrode CE on both sides of the drain electrode WD. However, since such misalignment occurs in common for all the pixels PX, there is no difference in the electric field distribution among the pixels PX, and the influence on the display of the image is extremely small. In addition, even if a misalignment occurs between the array substrate AR and the counter substrate CT, it is possible to suppress undesired electric field leakage to adjacent pixels. For this reason, even when the color of the color filter CF is different between adjacent pixels, it is possible to suppress the occurrence of color mixing, and it is possible to suppress a decrease in color reproducibility and a decrease in contrast ratio. .

  Further, when one pixel PX is viewed in the XY plane, the drain electrode WD is disposed on the array substrate AR inside the common electrode CE disposed on the counter substrate CT. In other words, the drain electrode WD is surrounded by the common electrode CE in one pixel PX. By arranging in this way, there is a start point and an end point of the electric lines of force within one pixel, and the electric lines of force of the own pixel do not leak to adjacent pixels. For this reason, for example, the electric field applied to the liquid crystal layer LQ between the pixels PX adjacent in the first direction X is not affected by each other. Accordingly, the liquid crystal molecules LM of the own pixel do not move due to the influence of the electric field from the adjacent pixel, and deterioration of display quality can be suppressed.

  Further, according to the present embodiment, a plurality of domains can be formed in one pixel. Therefore, the viewing angle can be optically compensated in a plurality of directions, and a wide viewing angle can be achieved. In the example shown in FIG. 3, at least two domains can be formed in one pixel, and further, since the two domains have substantially the same area, further viewing angle compensation can be performed.

  In the above example, the case where the initial alignment direction of the liquid crystal molecules LM is parallel to the first direction X has been described. However, the initial alignment direction of the liquid crystal molecules LM is oblique to the first direction X and the second direction Y. It may be an oblique direction that intersects.

  In the above example, the case where the liquid crystal layer LQ is made of a liquid crystal material having positive (positive type) dielectric anisotropy has been described. However, the liquid crystal layer LQ has a negative dielectric anisotropy (negative). Type) liquid crystal material.

  In the present embodiment, the structure of the pixel PX is not limited to the above example.

  FIG. 6 is a plan view schematically showing another structural example of one pixel PX when the array substrate AR shown in FIG. 1 is viewed from the counter substrate side.

  The structural example shown here is different from the structural example shown in FIG. 2 in that the drain electrode WD is formed in a loop shape.

  That is, the drain electrode WD is connected to one end of each of the second electrode portion D2 and the third electrode portion D3, the second electrode portion D2, and the third electrode portion D3 extending along the first direction X, and is connected to the semiconductor layer. The first electrode part D1, which contacts the SC and extends along the second direction Y, is connected to the other end of each of the second electrode part D2 and the third electrode part D3 and extends along the second direction Y. The fourth electrode portion D4 is provided.

  The first electrode portion D1 is located near the left end portion of the pixel PX, while the fourth electrode portion D4 is located near the right end portion of the pixel PX, that is, on the source line S2 side. It extends linearly along the two directions Y. Such a fourth electrode portion D4 is formed in a strip shape having substantially the same width along the first direction X. The drain electrode WD having such a configuration has a rectangular frame shape.

  The counter substrate CT as shown in FIG. 3 can be combined with the array substrate AR having such a structure example. At this time, the main common electrode CAC is located between the second electrode part D2 and the third electrode part D3.

  In such a structural example, the same effect as the above structural example can be obtained. Further, according to this structural example, since the drain electrode WD is formed in a loop shape, it is possible to improve the redundancy against disconnection of the drain electrode WD. That is, even if a disconnection occurs in a part of the drain electrode WD, the pixel potential is supplied to both the second electrode part D2 and the third electrode part D3 that substantially function as the pixel electrode by another path. It becomes possible. Therefore, even if the electrode width becomes extremely narrow due to the demand for higher definition, it is possible to suppress display quality deterioration such as display failure due to disconnection in the pixel PX.

  FIG. 7 is a plan view schematically showing another structural example of one pixel PX when the array substrate AR shown in FIG. 1 is viewed from the counter substrate side.

  The structure example shown here is different from the structure example shown in FIG. 2 in the structure of the switching element SW. That is, the source electrode WS integrated with the source line S1 extends along the first direction X, and is in contact with the semiconductor layer SC at two locations. The first electrode portion D1 of the drain electrode WD having a function as a pixel electrode includes a contact portion DC extending along the first direction X. The contact portion DC is in contact with the semiconductor layer SC between the source electrodes WS.

  Also in the structural example to which the switching element SW having such a structure is applied, the same effect as the above structural example can be obtained. Needless to say, the structure of the switching element SW described here can be applied even when the loop-shaped drain electrode WD as shown in FIG. 6 is applied.

  Each of the above structural examples corresponds to an example in which the drain electrode WD has a function as a pixel electrode, but the structural example described below corresponds to an example in which the pixel electrode PE is provided separately from the drain electrode WD. To do.

  FIG. 8 is a plan view schematically showing another structure example of one pixel PX when the array substrate AR shown in FIG. 1 is viewed from the counter substrate side.

  The structural example shown here is different from the structural example shown in FIG. 2 in that the shape of the drain electrode WD is different and the pixel electrode PE is provided separately from the drain electrode WD. ing.

  In other words, the drain electrode WD contacts the semiconductor layer SC and extends along the second direction Y. In the example shown here, one end of the drain electrode WD extends to a position overlapping the upper layer of the auxiliary capacitance line C1, and the other end of the drain electrode WD extends to a position overlapping the upper layer of the auxiliary capacitance line C2. Yes.

  The pixel electrode PE is located between the adjacent source line S1 and source line S2, and is electrically connected to the drain electrode WD. The pixel electrode PE is opposed to the auxiliary capacitance line C1 and extends along the first direction X, and the main pixel electrode PA1 faces the auxiliary capacitance line C2 and extends along the first direction X. PA2 is provided. The main pixel electrode PA1 includes a contact portion PC1. The contact portion PC1 is located above one end portion of the drain electrode WD and is electrically connected to the drain electrode WD via the contact hole CH1 and the contact hole CH2. Similarly, the main pixel electrode PA2 includes a contact portion PC2. The contact portion PC2 is located above the other end portion of the drain electrode WD and is electrically connected to the drain electrode WD via the contact hole CH3 and the contact hole CH4. In the illustrated example, the main pixel electrode PA1 is separated from the main pixel electrode PA2, but both are electrically connected to the same drain electrode WD, so that the main pixel electrode PA1 and the main pixel electrode PA2 are the same. A voltage is applied.

  In the main pixel electrode PA1, a portion extending from the contact portion PC1 toward the source line S2 is opposed to the storage capacitor line C1, and is formed in a strip shape having substantially the same width along the second direction Y. In the main pixel electrode PA2, a portion extending from the contact portion PC2 toward the source line S2 is opposed to the auxiliary capacitance line C2, and is formed in a strip shape having substantially the same width along the second direction Y. The auxiliary capacitance line C1 mainly forms a capacitance with the main pixel electrode PA1, and the auxiliary capacitance line C2 mainly forms a capacitance with the main pixel electrode PA2.

  The counter substrate CT as shown in FIG. 3 can be combined with the array substrate AR having such a structure example. At this time, the main common electrode CAC is located between the second electrode portion D2 and the third electrode portion D3, between the main pixel electrode PA1 and the main pixel electrode PA2, or above the gate line G1. Further, the distance along the second direction Y between the main common electrode CAC and the main pixel electrode PA1 is substantially the same as the distance along the second direction Y between the main common electrode CAC and the main pixel electrode PA2. is there.

  FIG. 9 is a cross-sectional view schematically showing a cross-sectional structure of the array substrate AR taken along line E-F in FIG.

  The array substrate AR includes the switching element SW, the auxiliary capacitance line C1, the pixel electrode PE, the first insulating film 11, the second insulating film 12, the third insulating film 13, the first alignment film AL1, and the like in the first insulating substrate 10. ing. 3 that are the same as those shown in FIG. 3 are given the same reference numerals, and detailed descriptions thereof are omitted.

  The gate electrode WG, which is a part of the gate wiring G1, the auxiliary capacitance line C1, and the auxiliary capacitance line C2 (not shown) are formed on the inner surface 10A of the first insulating substrate 10 and covered with the first insulating film 11. The source electrode WS and the drain electrode WD, which are part of the source wiring S1, are in contact with the semiconductor layer SC formed on the first insulating film 11. The drain electrode WD extends on the first insulating film 11 so as to overlap the upper layer of the auxiliary capacitance line C1. Although not shown, the drain electrode WD also extends to a position overlapping the upper layer of the auxiliary capacitance line C2 on the first insulating film 11. The semiconductor layer SC, the source electrode WS, and the drain electrode WD are covered with the second insulating film 12. In the second insulating film 12, a contact hole CH1 penetrating to the drain electrode WD is formed. Although not shown, a contact hole CH3 is also formed in the second insulating film 12.

  The third insulating film 13 is formed on the second insulating film 12. The third insulating film 13 is formed, for example, by depositing an organic material, and planarizes the surface. A contact hole CH2 is formed in the third insulating film 13. The contact hole CH2 is larger in size than the contact hole CH1, and penetrates to the drain electrode WD through the contact hole CH1 and to the second insulating film 12 around the contact hole CH1. Although not shown, a contact hole CH4 is also formed in the third insulating film 13.

  The contact portion PC1 of the main pixel electrode PA1 that is the pixel electrode PE and the contact portion PC2 of the main pixel electrode PA2 (not shown) are formed on the third insulating film 13. That is, the second insulating film 12 and the third insulating film 13 correspond to an interlayer insulating film interposed between the source wiring, the source electrode and the drain electrode, and the pixel electrode PE. The contact portion PC1 is in contact with the drain electrode WD through the contact hole CH1 and the contact hole CH2. The main pixel electrode PA1 is disposed so as to overlap the storage capacitor line C1 with the first insulating film 11, the second insulating film 12, and the third insulating film 13 interposed therebetween. Although not shown, the main pixel electrode PA1 is disposed so as to overlap the storage capacitor line C1 with the first insulating film 11, the second insulating film 12, and the third insulating film 13 interposed therebetween. The pixel electrode PE and the third insulating film 13 are covered with the first alignment film AL1.

  In such a structural example, the same effect as the above structural example can be obtained. Further, according to this structural example, since the pixel electrode PE is formed on the third insulating film 13 for flattening the surface, the influence of the irregularities on the surface of the array substrate AR on the alignment state of the liquid crystal molecules LM can be reduced. In addition, it is possible to suppress an increase in the interelectrode distance between the common electrode CE and the pixel electrode PE on the counter substrate CT side.

  FIG. 10 is a plan view schematically showing another structural example of one pixel PX when the array substrate AR shown in FIG. 1 is viewed from the counter substrate side.

  The structural example shown here is different from the structural example shown in FIG. 8 in that the pixel electrode PE is formed in a loop shape. That is, the pixel electrode PE includes a main pixel electrode PA1, a main pixel electrode PA2, a connection part PD1, and a connection part PD2.

  Both the connection part PD1 and the connection part PD2 are formed in a strip shape extending along the second direction Y and having substantially the same width along the first direction X. In the illustrated example, on the source line S1 side of the pixel PX, the connection portion PD1 connects the main pixel electrode PA1 and the main pixel electrode PA2. On the source line S2 side of the pixel PX, the connection part PD2 connects the main pixel electrode PA1 and the main pixel electrode PA2. The pixel electrode PE having such a configuration has a rectangular frame shape.

  In such a structural example, the same effect as the above structural example can be obtained. Further, according to this structural example, since the pixel electrode PE is formed in a loop shape, it is possible to improve redundancy against disconnection.

  FIG. 11 is a plan view schematically showing another structural example of one pixel PX when the array substrate AR shown in FIG. 1 is viewed from the counter substrate side.

  The structural example shown here differs from the structural example shown in FIG. 8 in the structure of the switching element SW. That is, the source electrode WS integrated with the source line S1 extends along the first direction X, and is in contact with the semiconductor layer SC at two locations. The drain electrode WD includes a contact part DC extending along the first direction X. The contact portion DC is in contact with the semiconductor layer SC between the source electrodes WS.

  Also in the structural example to which the switching element SW having such a structure is applied, the same effect as the above structural example can be obtained. Note that the pixel electrodes PE may be formed in a loop shape, similarly to the structure example shown in FIG.

  FIG. 12 is a plan view schematically showing another structural example of one pixel PX when the array substrate AR shown in FIG. 1 is viewed from the counter substrate side.

  The structural example shown here is different from the structural example shown in FIG. 8 in that the array substrate AR includes a gate shield electrode GS and a source shield electrode SS.

  That is, the gate shield electrode GS is opposed to the gate line G1 (or the gate shield electrode GS is positioned and overlaps the upper layer of the gate line G1). Such a gate shield electrode GS extends linearly along the first direction X and is formed in a strip shape. Note that the width of the gate shield electrode GS along the second direction Y is not necessarily constant. The gate shield electrode GS is electrically connected to the common electrode CE and has the same potential as the common electrode CE.

  The source shield electrode SS is opposed to the source line S1 and the source line S2, respectively (or the source shield electrode SS is positioned on and overlaps the source line S1 and the source line S2). Such a source shield electrode SS extends linearly along the second direction Y and is formed in a strip shape. Note that the width along the first direction X of the source shield electrode SS is not necessarily constant. The source shield electrode SS is electrically connected to the common electrode CE and has the same potential as the common electrode CE. In the illustrated example, the gate shield electrode GS and the source shield electrode SS are integrally or continuously formed.

  Since the gate shield electrode GS and the source shield electrode SS are formed on the upper surface of the third insulating film 13 which is the same layer as the pixel electrode PE, they are formed using the same material (for example, ITO) as the pixel electrode PE. Is possible.

  In the array substrate AR having such a structure example, when combined with the counter substrate CT shown in FIG. 3, the gate shield electrode GS faces the main common electrode CAC, and the source shield electrode SS becomes the sub common electrode CBL and the sub common electrode. Opposite the electrode CBR.

  According to such a structural example, since the gate shield electrode GS faces the gate line G, an undesired electric field from the gate line G can be shielded. For this reason, it is possible to suppress an undesired bias from being applied to the liquid crystal layer LQ from the gate wiring G, and it is possible to prevent display defects such as burn-in and the liquid crystal molecule alignment defects. It becomes possible to suppress the occurrence of leakage.

  Further, since the source shield wiring SS is opposed to the source wiring S, an undesired electric field from the source wiring S can be shielded. For this reason, it is possible to suppress an undesired bias from being applied to the liquid crystal layer LQ from the source wiring S, and crosstalk (for example, a state in which the pixel PX is set to a pixel potential for displaying black). Thus, when a pixel potential for displaying white is supplied to the source wiring connected to the pixel PX, a display defect such as a phenomenon in which light leaks from a part of the pixel PX and increases in luminance) occurs. Can be suppressed.

  Further, since the gate shield electrode GS and the source shield electrode SS provided in the array substrate AR are electrically connected to each other and are formed in a lattice shape in the array substrate AR, the redundancy can be improved. . Further, since the main common electrode CA and the sub-common electrode CB provided in the counter substrate CT are electrically connected to each other and formed in a lattice shape, the redundancy can be improved. Since the gate shield electrode GS and source shield electrode SS on the array substrate AR side and the main common electrode CA and sub-common electrode CB on the counter substrate CT side are electrically connected to each other, disconnection occurs in part. Even if it does, it becomes possible to supply a common electric potential stably to each pixel PX, and it becomes possible to suppress generating of a display defect.

  Note that the gate shield electrode GS and the source shield electrode SS may also be applied to each of the above structural examples.

  As described above, according to the present embodiment, it is possible to provide a liquid crystal display device capable of reducing cost and suppressing deterioration in display quality.

  In addition, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

LPN ... Liquid crystal display panel AR ... Array substrate CT ... Counter substrate LQ ... Liquid crystal layer WD ... Drain electrode D1 ... First electrode part D2 ... Second electrode part D3 ... Third electrode part D4 ... Fourth electrode part PE ... Pixel electrode PA ... Main pixel electrode PC ... Contact part CE ... Common electrode CA ... Main common electrode CB ... Sub-common electrode G ... Gate wiring C ... Auxiliary capacitance line S ... Source wiring GS ... Gate shield electrode SS ... Source shield electrode

Claims (14)

The first storage capacitor line and the second storage capacitor line that extend along the first direction, and the first storage capacitor line and the second storage capacitor line that are located between the first storage capacitor line and the second storage capacitor line and extend along the first direction. A gate line, a source line extending along a second direction intersecting the first direction, a semiconductor layer, a gate electrode electrically connected to the gate line, a contact with the semiconductor layer and the source A source electrode electrically connected to the wiring, a first electrode part in contact with the semiconductor layer, a second electrode connected to the first electrode part and facing the first auxiliary capacitance line and extending along a first direction A first substrate comprising: an electrode part; and a drain electrode comprising a third electrode part connected to the first electrode part and facing the second auxiliary capacitance line and extending along a first direction;
A second substrate having a common electrode with a main common electrode located on both sides of the second electrode portion and on both sides of the third electrode portion and extending along the first direction; ,
A liquid crystal layer comprising liquid crystal molecules held between the first substrate and the second substrate;
A liquid crystal display device comprising:   The liquid crystal display device according to claim 1, wherein the main common electrode between the second electrode portion and the third electrode portion is located above the gate line.   The liquid crystal display device according to claim 1, wherein the drain electrode is formed in a loop shape. The first storage capacitor line and the second storage capacitor line that extend along the first direction, and the first storage capacitor line and the second storage capacitor line that are located between the first storage capacitor line and the second storage capacitor line and extend along the first direction. A gate line, a source line extending along a second direction intersecting the first direction, a semiconductor layer, a gate electrode electrically connected to the gate line, a contact with the semiconductor layer and the source A source electrode electrically connected to the wiring; a drain electrode in contact with the semiconductor layer; a first electrode electrically connected to the drain electrode and facing the first auxiliary capacitance line and extending along a first direction; A first substrate having a second main pixel electrode electrically connected to the first main pixel electrode and the drain electrode and facing the second auxiliary capacitance line and extending along a first direction; When,
A second electrode having a common electrode including a main common electrode located on both sides of the first main pixel electrode and on both sides of the second main pixel electrode and extending in the first direction; A substrate,
A liquid crystal layer comprising liquid crystal molecules held between the first substrate and the second substrate;
A liquid crystal display device comprising:   5. The liquid crystal display device according to claim 4, wherein the main common electrode between the first main pixel electrode and the second main pixel electrode is located above the gate line.   The liquid crystal display device according to claim 4, wherein the pixel electrode is formed in a loop shape.   The first substrate further includes a gate shield electrode facing the gate wiring and having the same potential as the common electrode, and a source shield electrode facing the source wiring and having the same potential as the common electrode. A liquid crystal display device according to any one of claims 4 to 6.   8. The liquid crystal display device according to claim 1, wherein the gate wiring is positioned approximately in the middle between the first auxiliary capacitance line and the second auxiliary capacitance line. 9. The first storage capacitor line and the second storage capacitor line that extend along the first direction, and the first storage capacitor line and the second storage capacitor line that are located between the first storage capacitor line and the second storage capacitor line and extend along the first direction. A gate electrode electrically connected to the gate wiring, the first auxiliary capacitance line, the second auxiliary capacitance line, the gate wiring, an insulating film covering the gate electrode, and the insulation A semiconductor layer formed on the film and positioned above the gate electrode; a source wiring formed on the insulating film and extending in a second direction intersecting the first direction; and the source on the insulating film A source electrode electrically connected to the wiring and in contact with the semiconductor layer; and a drain electrode formed on the insulating film, the first electrode portion being in contact with the semiconductor layer, connected to the first electrode portion, and Through the insulating film. A second electrode portion extending along the first direction so as to overlap with the auxiliary capacitance line, and connected to the first electrode portion in the first direction so as to overlap with the second auxiliary capacitance line via the insulating film A drain electrode including a third electrode portion extending along the first substrate, and a first substrate including:
A second substrate having a common electrode with a main common electrode located on both sides of the second electrode portion and on both sides of the third electrode portion and extending along the first direction; ,
A liquid crystal layer comprising liquid crystal molecules held between the first substrate and the second substrate;
A liquid crystal display device comprising:   The liquid crystal display device according to claim 9, wherein the drain electrode is formed of the same material as the source electrode. The first storage capacitor line and the second storage capacitor line that extend along the first direction, and the first storage capacitor line and the second storage capacitor line that are located between the first storage capacitor line and the second storage capacitor line and extend along the first direction. A gate electrode electrically connected to the gate wiring, the first auxiliary capacitance line, the second auxiliary capacitance line, the gate wiring, and a first insulating film covering the gate electrode, A semiconductor layer formed on the first insulating film and positioned above the gate electrode; a source wiring formed on the first insulating film and extending in a second direction intersecting the first direction; A source electrode electrically connected to the source wiring on the first insulating film and in contact with the semiconductor layer, a drain electrode formed on the first insulating film and in contact with the semiconductor layer, the semiconductor layer, and the source Wiring, the source electrode, And a second insulating film covering the drain electrode, and a pixel electrode formed on the second insulating film, wherein the first insulating film and the second insulating film are electrically connected to the drain electrode. Through the first insulating film and the second insulating film, which are electrically connected to the first main pixel electrode and the drain electrode extending in the first direction so as to overlap the first auxiliary capacitance line through the first insulating film and the second insulating film A first substrate comprising: a pixel electrode comprising a second main pixel electrode extending along a first direction so as to overlap the second auxiliary capacitance line;
A second substrate having a common electrode with a main common electrode located on both sides of the second electrode portion and on both sides of the third electrode portion and extending along the first direction; ,
A liquid crystal layer comprising liquid crystal molecules held between the first substrate and the second substrate;
A liquid crystal display device comprising:   The first substrate is further formed on the second insulating film so as to face the gate wiring and has a gate shield electrode having the same potential as the common electrode, and is formed on the second insulating film and faces the source wiring. The liquid crystal display device according to claim 11, further comprising a source shield electrode having the same potential as the common electrode.   The liquid crystal display device according to claim 1, wherein the second substrate includes sub-common electrodes that are connected to the main common electrode and extend in the second direction.   14. The pixel according to claim 1, wherein the pixel in which the drain electrode is disposed has a horizontally long shape whose length along the first direction is longer than the length along the second direction. Liquid crystal display device.

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