JP2017161920A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the amount of retreat shift of an inorganic insulating film on an organic insulating film in a through-hole that connects between a pixel electrode and a thin film transistor of a pixel circuit.SOLUTION: A display device includes: a glass substrate SUB; a semiconductor film PS provided above the substrate; a first interlayer insulating film IN1 provided above the semiconductor; a metal film (source electrode) ST which connects to the semiconductor through a first through-hole TH1 formed in the first interlayer insulating film; an organic insulating film PAS formed of a resin material provided above the first insulating film and the metal film; a second interlayer insulating film IN2 formed of an inorganic insulator provided above the organic insulating film; and a pixel electrode PX which connects to the metal film through a second through-hole formed in the organic insulating film and a third through-hole formed in the third insulating film. The second insulating film is provided in contact with the first insulating film and the metal film. The third through-hole provided in the third insulating film has a tapered shape.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a method for manufacturing a liquid crystal display device and a liquid crystal display device.

  In recent liquid crystal display devices, an organic insulating film layer is provided above the thin film transistor included in each pixel circuit, and an inorganic insulating film for protecting the organic insulating film and the like is further provided thereon. The electrode of the thin film transistor and the pixel electrode are connected by a through hole.

  In order to provide the through hole of the liquid crystal display device described above, a step of forming an organic insulating film layer having a hole in the through hole portion, a step of forming an inorganic insulating film layer thereon, a hole in the through hole portion The step of forming the resist and the step of etching the inorganic insulating film are sequentially performed. By the etching process, the inorganic insulating film in the through hole portion is removed, and the pixel electrode and the thin film transistor that are formed thereafter can be electrically connected. In addition, in order to prevent the pixel electrode from being broken, the end of the inorganic insulating film is etched so as to have a forward taper.

  Patent Document 1 discloses a liquid crystal display device in which three layers of a lower inorganic insulating film layer, an organic insulating film layer, and an upper inorganic insulating film layer are provided between a thin film transistor and a pixel electrode in order from the bottom, An example of a method for forming a through hole penetrating these layers is disclosed.

JP 2011-59314 A

  The inorganic insulating film on the upper side of the organic insulating film tends to be weak because the film forming temperature cannot be raised. For this reason, if a forward taper is formed on the upper inorganic insulating film during dry etching, the amount of backward shift caused by etching the inorganic insulating film in the plane direction increases, and for example, through holes are formed in the inorganic insulating film. It will be removed up to the part outside.

  On the other hand, the resolution of a liquid crystal display panel used in a smartphone or the like is increasing, and the distance between the through hole and other components in the pixel circuit tends to be narrowed. For this reason, when the inorganic insulating film is etched over a wide range, other components are affected. For example, when an electrode is formed between an organic insulating film and an inorganic insulating film in the vicinity of a through hole, the electrode and the pixel electrode are short-circuited, and pixel defects are likely to occur.

  The present application has been made in view of the above problems, and its purpose is to perform etching so as to form a forward taper in an inorganic insulating film on an organic insulating film in a through hole connecting a thin film transistor and a pixel electrode of a pixel circuit. However, it is an object of the present invention to provide a technique that makes it possible to reduce the amount of backward shift accompanying the etching.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  (1) Forming an electrode of a thin film transistor on a substrate, forming an organic insulating film having a first hole above the electrode of the thin film transistor, and forming an inorganic insulating film above the organic insulating film A step of forming a resist film having a second hole on a central portion of the first hole, a step of dry etching the inorganic insulating film using the resist film, and removing the resist film And a step of forming a pixel electrode in contact with the upper surface of the etched inorganic insulating film. In the dry etching step, the total flow rate of the dry etching gas mixed with fluorine gas and oxygen (the volume of the chamber) ) × (0.09 to 0.11) per minute, and the ratio of the oxygen in the mixed dry etching gas is 80% or more. Production method.

  (2) In (1), the method further includes a step of forming a counter electrode between the organic insulating film and the inorganic insulating film, wherein an upper surface of the counter electrode is in contact with the inorganic insulating film, and a lower surface of the counter electrode is A method of manufacturing a liquid crystal display device, wherein polarization of liquid crystal is controlled by an electric field generated between the counter electrode and the pixel electrode in contact with the organic insulating film.

  (3) The method for manufacturing a liquid crystal display device according to (1) or (2), wherein the electrode of the thin film transistor is a metal electrically connected to an upper surface of a semiconductor film included in the thin film transistor.

  (4) a thin film transistor including a semiconductor film and an electrode film that is overlying the semiconductor film and electrically connected to the semiconductor film; and a first thin film that is overlying the electrode film and overlaps the electrode film in plan view An organic insulating film in which holes are formed, and a second hole that is formed above the organic insulating film and is inside the first hole in a plan view, and has a tapered shape in the second hole. A second inorganic insulating film; a pixel electrode above the second inorganic insulating film and connected to the metal film through the first and second holes; the organic insulating film; and the second And a counter electrode which is formed between the inorganic insulating film and controls polarization of liquid crystal by an electric field generated between the pixel electrode and the pixel electrode.

  According to the present invention, the amount of backward shift of the inorganic insulating film on the organic insulating film can be reduced in the through hole connecting the thin film transistor and the pixel electrode of the pixel circuit.

It is a circuit diagram which shows an example of the equivalent circuit of the liquid crystal display device concerning embodiment of this invention. It is a fragmentary top view which shows the pixel circuit on the array substrate concerning embodiment of this invention. FIG. 3 is a cross-sectional view taken along the line III-III of the pixel circuit shown in FIG. 2. FIG. 4 is a cross-sectional view taken along the line IV-IV of the pixel circuit shown in FIG. 2. It is sectional drawing which shows the array substrate after photoresist formation. It is sectional drawing which shows the array substrate in the middle of an etching process. It is sectional drawing which shows the array substrate at the time of completion | finish of an etching process. It is sectional drawing which shows the comparative example of a pixel circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Of the constituent elements that appear, those having the same function are given the same reference numerals, and the description thereof is omitted. Hereinafter, an example in which the present invention is applied to an IPS liquid crystal display device will be described.

  A liquid crystal display device according to an embodiment of the present invention includes an array substrate, a filter substrate facing the array substrate and provided with a color filter, a liquid crystal material sealed in a region sandwiched between these substrates, an array And a backlight that emits light from the outside of the substrate.

  FIG. 1 is a circuit diagram illustrating an example of an equivalent circuit of the liquid crystal display device according to the first embodiment. A plurality of gate signal lines GL, a plurality of video signal lines DL, a plurality of pixel electrodes PX, a plurality of common electrodes CT, a plurality of thin film transistors TR, a video signal line drive circuit XDV, a gate scanning circuit YDV, and the like are arranged on the array substrate. Is done. The plurality of gate signal lines GL extend in the horizontal direction side by side in the display area on the array substrate, and the plurality of video signal lines DL extend in the vertical direction side by side in the display area. One end of these video signal lines DL is connected to the video signal line drive circuit XDV, and one end of the gate signal line GL is connected to the gate scanning circuit YDV.

  A portion surrounded by the adjacent gate signal line GL and the adjacent video signal line DL is a pixel circuit. The plurality of pixel circuits are arranged in a matrix. Each pixel circuit includes a thin film transistor TR, a pixel electrode PX, and a common electrode CT. The thin film transistor TR includes a source electrode ST, a drain electrode DT, and a gate electrode GT. The drain electrode DT is a part of the video signal line DL and is electrically connected to the video signal line drive circuit XDV. The source electrode ST is connected to the pixel electrode PX. A common voltage is supplied to the common electrode CT. The common voltage is a constant voltage regardless of the luminance displayed by each pixel circuit, but may be periodically changed every certain time (frame).

  The pixel electrode PX and the common electrode CT constitute a capacitor via a liquid crystal. The gate electrode GT of the thin film transistor TR is a part of the gate signal line GL. When the on-voltage of the scanning pulse is supplied from the gate scanning circuit YDV, the thin-film transistor TR is turned on, and the pixel to which the on-voltage is supplied accordingly. The video signal line drive circuit XDV supplies the potential of the video signal toward the pixel electrode PX toward the circuit. Then, the above-described capacitor stores a potential difference based on the potential of the video signal and the common voltage. The transmittance of the liquid crystal is changed by the electric field generated by this potential difference, and the amount of light transmitted through each pixel circuit is controlled. Note that since the thin film transistor TR has no polarity and the names of the source electrode ST and the drain electrode DT are determined conveniently depending on the direction of voltage, their arrangement and connection destination may be reversed.

  FIG. 2 is a partial plan view showing a pixel circuit on the array substrate according to the embodiment of the present invention. 3 is a cross-sectional view taken along the line III-III of the pixel circuit shown in FIG. 2, and FIG. 4 is a cross-sectional view taken along the line IV-IV of the pixel circuit shown in FIG. The thin film transistor TR has a top gate structure. In the top gate structure, the gate electrode GT is located above the polysilicon semiconductor film PS, and a portion of the semiconductor film PS above the gate electrode GT is a channel.

  On the glass substrate SUB constituting the array substrate, a base film UI is formed, and a semiconductor film PS is formed thereon. The base film UI includes a silicon oxide layer and a silicon nitride layer, and prevents the semiconductor film PS from being contaminated by the composition of the glass substrate SUB. Over the semiconductor film PS, a gate insulating film GI is provided so as to cover the semiconductor film PS. Further, a layer of the gate signal line GL (gate electrode GT) is provided above the gate insulating film GI, and extends in the left-right direction in FIG. A first interlayer insulating film IN1 is provided over the gate signal line GL so as to cover the gate signal line GL, and a layer including the video signal line DL and the source electrode ST is provided thereon. The video signal line DL extends in the vertical direction in FIG. 2, but is slightly inclined from the vertical direction at a portion between the gate signal lines GL. The gate signal line GL, the video signal line DL, and the source electrode ST are metal films such as Al. The first interlayer insulating film IN1 and the gate insulating film GI are inorganic insulating films.

  As shown in FIG. 2, the source electrode ST is located at the center of the adjacent video signal lines DL, and is arranged so that the lower portion thereof overlaps the gate signal line GL below the pixel circuit. Is almost rectangular. In addition, as seen in FIG. 2, the upper two corners of the source electrode ST are cut off obliquely. The first interlayer insulating film IN1 and the gate insulating film GI have a through hole TH1 on the upper side and the center in the left-right direction of the source electrode ST of FIG. The source electrode ST is connected to the upper surface of the end on the source side of the semiconductor film PS through the through hole TH1.

  Referring to FIG. 2, the semiconductor film PS extends downward from a position connected to the through hole TH1, extends to the left after crossing the gate signal line GL, enters the lower layer of the video signal line DL, extends upward, and is again gated. It intersects with the signal line GL. In addition, a through hole TH3 is provided in an intermediate portion of the adjacent gate signal line GL in the first interlayer insulating film IN1 and the gate insulating film GI, and the video signal line DL is connected to the drain of the semiconductor film PS through the through hole TH3. Connected to the upper surface of the side end.

  A portion of the semiconductor film PS that intersects the gate signal line GL serves as a channel region of the thin film transistor TR, and this portion of the gate signal line GL particularly serves as the gate electrode GT of the thin film transistor TR. A light shielding film may be formed below the semiconductor film PS.

  Over the source electrode ST, an organic insulating film PAS layer and a second interlayer insulating film IN2 are formed. Each of the organic insulating film PAS and the second interlayer insulating film IN2 has a hole constituting the through hole TH2. As shown in FIG. 2, the through hole TH2 is located slightly to the right of the center of the source electrode ST and above the gate signal line GL. The organic insulating film PAS is flattened so that the unevenness on the lower side thereof becomes inconspicuous. The second interlayer insulating film IN2 mainly includes silicon nitride (SiN), and the outer peripheral portion of the hole is tapered.

  A layer including the common electrode CT is provided between the layer of the organic insulating film PAS and the layer of the second interlayer insulating film IN2. The common electrode CT is formed in almost the entire region between the adjacent gate signal lines GL in a plan view, but is not formed in the through hole TH2 and its outer edge (a region surrounded by a one-dot chain line in FIG. 2). The second interlayer insulating film IN2 covers at least part of the inner peripheral wall of the through hole TH2 and the common electrode CT.

  The pixel electrode PX is in contact with the upper surface of the source electrode ST below the through hole TH2. Further, the pixel electrode PX is disposed in a region surrounded by the video signal line DL and the gate signal line GL, and the pixel electrode PX has a so-called comb shape. The pixel electrode PX has a plurality of linear regions extending along the video signal line DL, and the plurality of linear regions are connected to other linear regions in the same pixel circuit at both ends. .

  Next, a method for manufacturing the liquid crystal display device described so far will be described. First, a base film UI including a layer of silicon oxide or silicon nitride is formed on the glass substrate SUB. When the base film UI is formed, a semiconductor layer containing polysilicon is stacked and patterned to form the semiconductor film PS. Further, ion doping is performed on the semiconductor film PS. Next, a gate insulating film GI including an inorganic insulator such as silicon oxide is formed on the semiconductor film PS.

  Next, a gate signal line GL (gate electrode GT) made of a metal such as Al is formed on the gate insulating film GI. Over the gate insulating film GI, a layer of the first interlayer insulating film IN1 containing silicon oxide is laminated, and a part of the layer is etched to form the through hole TH1 and the through hole TH3. After the through holes TH1 and TH3 are formed, a metal film made of Al is laminated, and the metal film is patterned to form the source electrode ST and the video signal line DL. In addition, about each layer demonstrated so far, you may change a raw material as needed.

  After the source electrode ST and the like are formed, an organic insulating film PAS having a hole constituting the through hole TH2 is formed above the source electrode ST. The holes in the organic insulating film PAS are formed by applying a photosensitive resin material on the array substrate and exposing the photosensitive resin material.

  A common electrode CT is formed by laminating a conductive film layer made of ITO (Indium Tin Oxide) on the organic insulating film PAS and patterning it. Further, a silicon nitride layer (hereinafter referred to as “etching target layer”) formed at a temperature lower than the heat resistant temperature of the organic insulating film PAS is formed thereon by a CVD apparatus. The temperature for forming the etching target layer is lower than the temperature for forming the inorganic insulating film below the organic insulating film PAS. Although the thickness of the etching target layer is 120 nanometers, the thickness may be different.

  Next, the etching target layer is etched to form a hole constituting the through hole TH2. Hereinafter, this process will be described.

  First, a photoresist PR (resist film) is formed in preparation for etching. In the step of forming the photoresist PR, first, a photosensitive resin material is applied. This photosensitive resin material contains about 80 to 90% of propylene glycol monomethyl ether acetate as a solvent and 10% or more of a photosensitive novolak resin derivative. Moreover, this photosensitive resin material contains 1 to 10% of benzyl alcohol, and the concentration of the naphthoquinonediazide derivative is 5% or less. Next, in order to remove the solvent, the array substrate is dried and a part thereof is exposed. As a result, a photoresist PR having a hole is formed at a position corresponding to the center of the through hole TH2.

  When the photoresist PR is formed, a step of etching the etching target layer using the photoresist PR is performed. In the etching process, first, an array substrate is placed in a chamber CB of an etching apparatus that performs dry etching. FIG. 5A is a cross-sectional view showing the array substrate disposed in the chamber CB after the photoresist PR is formed. There is an upper electrode UE in the upper part of the chamber CB, and a lower electrode LE in the lower part. The array substrate is placed on the lower electrode LE.

  FIG. 5B is a cross-sectional view showing the array substrate during the etching process. When the array substrate is disposed in the chamber CB, the etching apparatus flows a mixed dry etching gas from the upper electrode UE toward the lower electrode LE to form the through hole TH2. This mixed dry etching gas is a mixture of a fluorine-based gas and oxygen, and the proportion of oxygen in the mixed dry etching gas is 80% or more. In the process of flowing the mixed dry etching gas, the total flow rate of the mixed dry etching gas is set to (volume of the chamber CB) × (0.09 to 0.11) per minute. FIG. 5C is a cross-sectional view showing the array substrate at the end of the etching process.

  During this etching, the photoresist PR in the through-hole TH2 portion tends to recede due to oxygen. Thereby, a forward taper can be formed in the second interlayer insulating film IN2. More specifically, a forward taper can be formed if the oxygen concentration is 80% or more, but it is particularly preferable that the taper is 85% to 90%. If it exceeds 95%, it is difficult to control how etching proceeds, and if it is less than 80%, it becomes difficult to form a forward taper.

  Furthermore, as described above, the total flow rate of the mixed dry etching gas per minute needs to be in the range of 0.09 to 0.11 times the volume of the chamber CB. When the total flow rate of the mixed etching gas is less than the above-mentioned minimum value, the etching speed of the etching target layer is remarkably slowed, and the throughput is lowered. On the other hand, when the total flow rate is larger than the above-described maximum value, the etching speed in the lateral direction is increased with respect to the etching speed downward. Therefore, in the latter case, the structure of the surrounding pixel circuit (here, the common electrode CT) is adversely affected and the yield is reduced.

  When the through hole TH2 is formed, a step of removing the photoresist PR is performed. Then, the pixel electrode PX in contact with the source electrode ST on the lower surface of the through hole TH2 is formed. The pixel electrode PX is made of ITO and overlaps with the common electrode CT at a part away from the through hole TH2 by a certain amount or more when viewed in plan.

  When the pixel electrode PX is formed, an alignment film is formed thereon, and a color filter substrate is disposed so as to correspond to the array substrate. Then, liquid crystal is filled between the color filter substrate and the array substrate, and a circuit such as a flexible substrate and other optical members are arranged on the array substrate to complete a liquid crystal display panel.

  FIG. 6 is a cross-sectional view showing a comparative example of the pixel circuit included in the array substrate. In the example of FIG. 6, although the interlayer insulating film INB and the interlayer insulating film INC are dry etched at a time to form the through hole TH2, the above-described conditions are not used for the etching. In order to form a taper without depending on the receding of the photoresist PR, the receding layer is provided with a thickness of about 30 nm on the upper side of the interlayer insulating film INC. The receding layer is easier to etch than the underlying layer, thereby forming a taper.

  When such an etching method is used, there arises a problem that the interlayer insulating film INC is etched in the lateral direction by the etching. As a result, even if the diameter of the bottom of the hole penetrating the source electrode ST is d1, the interlayer insulating film INC in a range wider than the range of the through hole TH2 (diameter is d2) is scraped. There is a case where a portion covering the common electrode CT is lost. In such a case, a short-circuit portion SH where the pixel electrode PX and the common electrode CT are in contact with each other occurs, and the pixel cannot be displayed.

  In the cross-sectional view shown in FIG. 6, unlike the cross-sectional views shown in FIGS. 3 and 4, the interlayer insulating film INA corresponding to the first interlayer insulating film IN1 and the interlayer insulating film INC corresponding to the second interlayer insulating film IN2 are used. In addition, the interlayer insulating film INB is included between the layer including the source electrode ST and the layer of the organic insulating film PAS. By the etching method, the bottom of the through hole TH2 is securely connected to the source electrode ST. The problem that the range in which the interlayer insulating film INC is removed becomes wider when trying to penetrate is caused even if the interlayer insulating film INB does not exist.

  On the other hand, in the array substrate according to the embodiment of the present invention, the range in which the second interlayer insulating film IN2 is cut is smaller than that in FIG. 6, and is within the range of the through hole TH2. Thereby, even if the common electrode CT is placed near the through hole TH2 as compared with the comparative example, the occurrence of a short circuit can be prevented. As a result, not only the yield is improved, but also restrictions on the design of the pixel circuit are relaxed, and the pixel circuit can be easily reduced in size and resolution.

  Although the embodiment of the present invention has been described so far, the present invention is not limited to the above-described configuration. For example, the present invention may be applied to a liquid crystal display device of another method such as a TN method or a VA method instead of the IPS method. This is because a structure for connecting the above-described thin film transistor TR and the pixel electrode PX is also provided.

CT common electrode, DL video signal line, GL gate signal line, PX pixel electrode, TR thin film transistor, XDV video signal line drive circuit, YDV gate scanning circuit, DT drain electrode, GI gate insulating film, GT gate electrode, IN1 first Interlayer insulation film, IN2
Second interlayer insulating film, PAS organic insulating film, PS semiconductor film, ST source electrode, SUB
Glass substrate, TH1, TH2, TH3 through hole, UI underlayer, CB chamber, LE lower electrode, UE upper electrode, PR photoresist, INA, INB, INC interlayer insulating film, SH short-circuited portion.

Claims (6)

A substrate,
A semiconductor provided above the substrate;
A first insulating film provided above the semiconductor;
A metal film provided above the first insulating film and connected to the semiconductor through a first through hole formed in the first insulating film;
A second insulating film made of a resin material provided above the first insulating film and the metal film;
A third insulating film made of an inorganic insulator provided above the second insulating film;
A pixel electrode connected to the metal film via a second through hole formed in the second insulating film and a third through hole formed in the third insulating film;
The second insulating film is provided in contact with the first insulating film and the metal film,
The display device, wherein the third through hole provided in the third insulating film has a tapered shape.   2. The width of a portion where the second through hole contacts the metal in the first cross section of the substrate is larger than a width where the third through hole contacts the metal film. The display device described in 1.   In the second cross section of the substrate, the width where the third insulating film and the metal film are in contact with each other on one side of the third through hole is such that the third insulating film and the metal film on the other side are in contact with each other. The display device according to claim 1, wherein the display device is larger than a contact width. The substrate is provided with a gate signal line for controlling conduction of the semiconductor,
The display device according to claim 3, wherein the other side is a side close to the gate signal line. A common electrode is provided between the second insulating film and the third insulating film,
5. The display device according to claim 1, wherein the common electrode extends to a tapered portion of the second through hole. 6. The display device according to claim 1, wherein the pixel electrode is patterned by etching also in a tapered portion of the second through hole.

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